2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/etherdevice.h>
25 void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt)
27 htt->num_pending_tx--;
28 if (htt->num_pending_tx == htt->max_num_pending_tx - 1)
29 ieee80211_wake_queues(htt->ar->hw);
32 static void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt)
34 spin_lock_bh(&htt->tx_lock);
35 __ath10k_htt_tx_dec_pending(htt);
36 spin_unlock_bh(&htt->tx_lock);
39 static int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt)
43 spin_lock_bh(&htt->tx_lock);
45 if (htt->num_pending_tx >= htt->max_num_pending_tx) {
50 htt->num_pending_tx++;
51 if (htt->num_pending_tx == htt->max_num_pending_tx)
52 ieee80211_stop_queues(htt->ar->hw);
55 spin_unlock_bh(&htt->tx_lock);
59 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt)
61 struct ath10k *ar = htt->ar;
64 lockdep_assert_held(&htt->tx_lock);
66 msdu_id = find_first_zero_bit(htt->used_msdu_ids,
67 htt->max_num_pending_tx);
68 if (msdu_id == htt->max_num_pending_tx)
71 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", msdu_id);
72 __set_bit(msdu_id, htt->used_msdu_ids);
76 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id)
78 struct ath10k *ar = htt->ar;
80 lockdep_assert_held(&htt->tx_lock);
82 if (!test_bit(msdu_id, htt->used_msdu_ids))
83 ath10k_warn(ar, "trying to free unallocated msdu_id %d\n",
86 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx free msdu_id %hu\n", msdu_id);
87 __clear_bit(msdu_id, htt->used_msdu_ids);
90 int ath10k_htt_tx_alloc(struct ath10k_htt *htt)
92 struct ath10k *ar = htt->ar;
94 spin_lock_init(&htt->tx_lock);
96 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, htt->ar->fw_features))
97 htt->max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC;
99 htt->max_num_pending_tx = TARGET_NUM_MSDU_DESC;
101 ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n",
102 htt->max_num_pending_tx);
104 htt->pending_tx = kzalloc(sizeof(*htt->pending_tx) *
105 htt->max_num_pending_tx, GFP_KERNEL);
106 if (!htt->pending_tx)
109 htt->used_msdu_ids = kzalloc(sizeof(unsigned long) *
110 BITS_TO_LONGS(htt->max_num_pending_tx),
112 if (!htt->used_msdu_ids) {
113 kfree(htt->pending_tx);
117 htt->tx_pool = dma_pool_create("ath10k htt tx pool", htt->ar->dev,
118 sizeof(struct ath10k_htt_txbuf), 4, 0);
120 kfree(htt->used_msdu_ids);
121 kfree(htt->pending_tx);
128 static void ath10k_htt_tx_free_pending(struct ath10k_htt *htt)
130 struct ath10k *ar = htt->ar;
131 struct htt_tx_done tx_done = {0};
134 spin_lock_bh(&htt->tx_lock);
135 for (msdu_id = 0; msdu_id < htt->max_num_pending_tx; msdu_id++) {
136 if (!test_bit(msdu_id, htt->used_msdu_ids))
139 ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %hu\n",
143 tx_done.msdu_id = msdu_id;
145 ath10k_txrx_tx_unref(htt, &tx_done);
147 spin_unlock_bh(&htt->tx_lock);
150 void ath10k_htt_tx_free(struct ath10k_htt *htt)
152 ath10k_htt_tx_free_pending(htt);
153 kfree(htt->pending_tx);
154 kfree(htt->used_msdu_ids);
155 dma_pool_destroy(htt->tx_pool);
158 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb)
160 dev_kfree_skb_any(skb);
163 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt)
165 struct ath10k *ar = htt->ar;
171 len += sizeof(cmd->hdr);
172 len += sizeof(cmd->ver_req);
174 skb = ath10k_htc_alloc_skb(ar, len);
179 cmd = (struct htt_cmd *)skb->data;
180 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_VERSION_REQ;
182 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
184 dev_kfree_skb_any(skb);
191 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie)
193 struct ath10k *ar = htt->ar;
194 struct htt_stats_req *req;
199 len += sizeof(cmd->hdr);
200 len += sizeof(cmd->stats_req);
202 skb = ath10k_htc_alloc_skb(ar, len);
207 cmd = (struct htt_cmd *)skb->data;
208 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_STATS_REQ;
210 req = &cmd->stats_req;
212 memset(req, 0, sizeof(*req));
214 /* currently we support only max 8 bit masks so no need to worry
215 * about endian support */
216 req->upload_types[0] = mask;
217 req->reset_types[0] = mask;
218 req->stat_type = HTT_STATS_REQ_CFG_STAT_TYPE_INVALID;
219 req->cookie_lsb = cpu_to_le32(cookie & 0xffffffff);
220 req->cookie_msb = cpu_to_le32((cookie & 0xffffffff00000000ULL) >> 32);
222 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
224 ath10k_warn(ar, "failed to send htt type stats request: %d",
226 dev_kfree_skb_any(skb);
233 int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt)
235 struct ath10k *ar = htt->ar;
238 struct htt_rx_ring_setup_ring *ring;
239 const int num_rx_ring = 1;
246 * the HW expects the buffer to be an integral number of 4-byte
249 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4));
250 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0);
252 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup.hdr)
253 + (sizeof(*ring) * num_rx_ring);
254 skb = ath10k_htc_alloc_skb(ar, len);
260 cmd = (struct htt_cmd *)skb->data;
261 ring = &cmd->rx_setup.rings[0];
263 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG;
264 cmd->rx_setup.hdr.num_rings = 1;
266 /* FIXME: do we need all of this? */
268 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR;
269 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD;
270 flags |= HTT_RX_RING_FLAGS_PPDU_START;
271 flags |= HTT_RX_RING_FLAGS_PPDU_END;
272 flags |= HTT_RX_RING_FLAGS_MPDU_START;
273 flags |= HTT_RX_RING_FLAGS_MPDU_END;
274 flags |= HTT_RX_RING_FLAGS_MSDU_START;
275 flags |= HTT_RX_RING_FLAGS_MSDU_END;
276 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION;
277 flags |= HTT_RX_RING_FLAGS_FRAG_INFO;
278 flags |= HTT_RX_RING_FLAGS_UNICAST_RX;
279 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX;
280 flags |= HTT_RX_RING_FLAGS_CTRL_RX;
281 flags |= HTT_RX_RING_FLAGS_MGMT_RX;
282 flags |= HTT_RX_RING_FLAGS_NULL_RX;
283 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX;
285 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr);
287 ring->fw_idx_shadow_reg_paddr =
288 __cpu_to_le32(htt->rx_ring.alloc_idx.paddr);
289 ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr);
290 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size);
291 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE);
292 ring->flags = __cpu_to_le16(flags);
293 ring->fw_idx_init_val = __cpu_to_le16(fw_idx);
295 #define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4)
297 ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status));
298 ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload));
299 ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start));
300 ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end));
301 ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start));
302 ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end));
303 ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start));
304 ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end));
305 ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention));
306 ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info));
310 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
312 dev_kfree_skb_any(skb);
319 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,
320 u8 max_subfrms_ampdu,
321 u8 max_subfrms_amsdu)
323 struct ath10k *ar = htt->ar;
324 struct htt_aggr_conf *aggr_conf;
330 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */
332 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64)
335 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31)
338 len = sizeof(cmd->hdr);
339 len += sizeof(cmd->aggr_conf);
341 skb = ath10k_htc_alloc_skb(ar, len);
346 cmd = (struct htt_cmd *)skb->data;
347 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG;
349 aggr_conf = &cmd->aggr_conf;
350 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu;
351 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu;
353 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d",
354 aggr_conf->max_num_amsdu_subframes,
355 aggr_conf->max_num_ampdu_subframes);
357 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
359 dev_kfree_skb_any(skb);
366 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
368 struct ath10k *ar = htt->ar;
369 struct device *dev = ar->dev;
370 struct sk_buff *txdesc = NULL;
372 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
373 u8 vdev_id = skb_cb->vdev_id;
378 res = ath10k_htt_tx_inc_pending(htt);
382 len += sizeof(cmd->hdr);
383 len += sizeof(cmd->mgmt_tx);
385 spin_lock_bh(&htt->tx_lock);
386 res = ath10k_htt_tx_alloc_msdu_id(htt);
388 spin_unlock_bh(&htt->tx_lock);
392 htt->pending_tx[msdu_id] = msdu;
393 spin_unlock_bh(&htt->tx_lock);
395 txdesc = ath10k_htc_alloc_skb(ar, len);
398 goto err_free_msdu_id;
401 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
403 res = dma_mapping_error(dev, skb_cb->paddr);
405 goto err_free_txdesc;
407 skb_put(txdesc, len);
408 cmd = (struct htt_cmd *)txdesc->data;
409 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_MGMT_TX;
410 cmd->mgmt_tx.msdu_paddr = __cpu_to_le32(ATH10K_SKB_CB(msdu)->paddr);
411 cmd->mgmt_tx.len = __cpu_to_le32(msdu->len);
412 cmd->mgmt_tx.desc_id = __cpu_to_le32(msdu_id);
413 cmd->mgmt_tx.vdev_id = __cpu_to_le32(vdev_id);
414 memcpy(cmd->mgmt_tx.hdr, msdu->data,
415 min_t(int, msdu->len, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN));
417 skb_cb->htt.txbuf = NULL;
419 res = ath10k_htc_send(&htt->ar->htc, htt->eid, txdesc);
426 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
428 dev_kfree_skb_any(txdesc);
430 spin_lock_bh(&htt->tx_lock);
431 htt->pending_tx[msdu_id] = NULL;
432 ath10k_htt_tx_free_msdu_id(htt, msdu_id);
433 spin_unlock_bh(&htt->tx_lock);
435 ath10k_htt_tx_dec_pending(htt);
440 int ath10k_htt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
442 struct ath10k *ar = htt->ar;
443 struct device *dev = ar->dev;
444 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
445 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
446 struct ath10k_hif_sg_item sg_items[2];
447 struct htt_data_tx_desc_frag *frags;
448 u8 vdev_id = skb_cb->vdev_id;
449 u8 tid = skb_cb->htt.tid;
453 u16 msdu_id, flags1 = 0;
458 res = ath10k_htt_tx_inc_pending(htt);
462 spin_lock_bh(&htt->tx_lock);
463 res = ath10k_htt_tx_alloc_msdu_id(htt);
465 spin_unlock_bh(&htt->tx_lock);
469 htt->pending_tx[msdu_id] = msdu;
470 spin_unlock_bh(&htt->tx_lock);
472 prefetch_len = min(htt->prefetch_len, msdu->len);
473 prefetch_len = roundup(prefetch_len, 4);
475 /* Since HTT 3.0 there is no separate mgmt tx command. However in case
476 * of mgmt tx using TX_FRM there is not tx fragment list. Instead of tx
477 * fragment list host driver specifies directly frame pointer. */
478 use_frags = htt->target_version_major < 3 ||
479 !ieee80211_is_mgmt(hdr->frame_control);
481 skb_cb->htt.txbuf = dma_pool_alloc(htt->tx_pool, GFP_ATOMIC,
483 if (!skb_cb->htt.txbuf)
484 goto err_free_msdu_id;
485 skb_cb->htt.txbuf_paddr = paddr;
487 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
489 res = dma_mapping_error(dev, skb_cb->paddr);
493 if (likely(use_frags)) {
494 frags = skb_cb->htt.txbuf->frags;
496 frags[0].paddr = __cpu_to_le32(skb_cb->paddr);
497 frags[0].len = __cpu_to_le32(msdu->len);
501 flags0 |= SM(ATH10K_HW_TXRX_NATIVE_WIFI,
502 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
504 frags_paddr = skb_cb->htt.txbuf_paddr;
506 flags0 |= SM(ATH10K_HW_TXRX_MGMT,
507 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
509 frags_paddr = skb_cb->paddr;
512 /* Normally all commands go through HTC which manages tx credits for
513 * each endpoint and notifies when tx is completed.
515 * HTT endpoint is creditless so there's no need to care about HTC
516 * flags. In that case it is trivial to fill the HTC header here.
518 * MSDU transmission is considered completed upon HTT event. This
519 * implies no relevant resources can be freed until after the event is
520 * received. That's why HTC tx completion handler itself is ignored by
521 * setting NULL to transfer_context for all sg items.
523 * There is simply no point in pushing HTT TX_FRM through HTC tx path
524 * as it's a waste of resources. By bypassing HTC it is possible to
525 * avoid extra memory allocations, compress data structures and thus
526 * improve performance. */
528 skb_cb->htt.txbuf->htc_hdr.eid = htt->eid;
529 skb_cb->htt.txbuf->htc_hdr.len = __cpu_to_le16(
530 sizeof(skb_cb->htt.txbuf->cmd_hdr) +
531 sizeof(skb_cb->htt.txbuf->cmd_tx) +
533 skb_cb->htt.txbuf->htc_hdr.flags = 0;
535 if (!ieee80211_has_protected(hdr->frame_control))
536 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT;
538 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
540 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID);
541 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID);
542 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD;
543 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD;
545 /* Prevent firmware from sending up tx inspection requests. There's
546 * nothing ath10k can do with frames requested for inspection so force
547 * it to simply rely a regular tx completion with discard status.
549 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED;
551 skb_cb->htt.txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM;
552 skb_cb->htt.txbuf->cmd_tx.flags0 = flags0;
553 skb_cb->htt.txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1);
554 skb_cb->htt.txbuf->cmd_tx.len = __cpu_to_le16(msdu->len);
555 skb_cb->htt.txbuf->cmd_tx.id = __cpu_to_le16(msdu_id);
556 skb_cb->htt.txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr);
557 skb_cb->htt.txbuf->cmd_tx.peerid = __cpu_to_le32(HTT_INVALID_PEERID);
559 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid);
560 ath10k_dbg(ar, ATH10K_DBG_HTT,
561 "htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %08x, msdu_paddr %08x vdev %hhu tid %hhu\n",
562 flags0, flags1, msdu->len, msdu_id, frags_paddr,
563 (u32)skb_cb->paddr, vdev_id, tid);
564 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ",
565 msdu->data, msdu->len);
566 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len);
567 trace_ath10k_tx_payload(ar, msdu->data, msdu->len);
569 sg_items[0].transfer_id = 0;
570 sg_items[0].transfer_context = NULL;
571 sg_items[0].vaddr = &skb_cb->htt.txbuf->htc_hdr;
572 sg_items[0].paddr = skb_cb->htt.txbuf_paddr +
573 sizeof(skb_cb->htt.txbuf->frags);
574 sg_items[0].len = sizeof(skb_cb->htt.txbuf->htc_hdr) +
575 sizeof(skb_cb->htt.txbuf->cmd_hdr) +
576 sizeof(skb_cb->htt.txbuf->cmd_tx);
578 sg_items[1].transfer_id = 0;
579 sg_items[1].transfer_context = NULL;
580 sg_items[1].vaddr = msdu->data;
581 sg_items[1].paddr = skb_cb->paddr;
582 sg_items[1].len = prefetch_len;
584 res = ath10k_hif_tx_sg(htt->ar,
585 htt->ar->htc.endpoint[htt->eid].ul_pipe_id,
586 sg_items, ARRAY_SIZE(sg_items));
593 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
595 dma_pool_free(htt->tx_pool,
597 skb_cb->htt.txbuf_paddr);
599 spin_lock_bh(&htt->tx_lock);
600 htt->pending_tx[msdu_id] = NULL;
601 ath10k_htt_tx_free_msdu_id(htt, msdu_id);
602 spin_unlock_bh(&htt->tx_lock);
604 ath10k_htt_tx_dec_pending(htt);