2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include "targaddrs.h"
23 /* QCA988X 1.0 definitions (unsupported) */
24 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0
26 /* QCA988X 2.0 definitions */
27 #define QCA988X_HW_2_0_VERSION 0x4100016c
28 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2
29 #define QCA988X_HW_2_0_FW_DIR "ath10k/QCA988X/hw2.0"
30 #define QCA988X_HW_2_0_FW_FILE "firmware.bin"
31 #define QCA988X_HW_2_0_OTP_FILE "otp.bin"
32 #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin"
33 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234
35 /* Known pecularities:
36 * - current FW doesn't support raw rx mode (last tested v599)
37 * - current FW dumps upon raw tx mode (last tested v599)
38 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
39 * - raw have FCS, nwifi doesn't
40 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
41 * param, llc/snap) are aligned to 4byte boundaries each */
42 enum ath10k_hw_txrx_mode {
43 ATH10K_HW_TXRX_RAW = 0,
44 ATH10K_HW_TXRX_NATIVE_WIFI = 1,
45 ATH10K_HW_TXRX_ETHERNET = 2,
47 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */
48 ATH10K_HW_TXRX_MGMT = 3,
51 enum ath10k_mcast2ucast_mode {
52 ATH10K_MCAST2UCAST_DISABLED = 0,
53 ATH10K_MCAST2UCAST_ENABLED = 1,
56 /* Target specific defines for MAIN firmware */
57 #define TARGET_NUM_VDEVS 8
58 #define TARGET_NUM_PEER_AST 2
59 #define TARGET_NUM_WDS_ENTRIES 32
60 #define TARGET_DMA_BURST_SIZE 0
61 #define TARGET_MAC_AGGR_DELIM 0
62 #define TARGET_AST_SKID_LIMIT 16
63 #define TARGET_NUM_PEERS 16
64 #define TARGET_NUM_OFFLOAD_PEERS 0
65 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0
66 #define TARGET_NUM_PEER_KEYS 2
67 #define TARGET_NUM_TIDS (2 * ((TARGET_NUM_PEERS) + (TARGET_NUM_VDEVS)))
68 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
69 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
70 #define TARGET_RX_TIMEOUT_LO_PRI 100
71 #define TARGET_RX_TIMEOUT_HI_PRI 40
73 /* Native Wifi decap mode is used to align IP frames to 4-byte boundaries and
74 * avoid a very expensive re-alignment in mac80211. */
75 #define TARGET_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI
77 #define TARGET_SCAN_MAX_PENDING_REQS 4
78 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3
79 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3
80 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8
81 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3
82 #define TARGET_NUM_MCAST_GROUPS 0
83 #define TARGET_NUM_MCAST_TABLE_ELEMS 0
84 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED
85 #define TARGET_TX_DBG_LOG_SIZE 1024
86 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
87 #define TARGET_VOW_CONFIG 0
88 #define TARGET_NUM_MSDU_DESC (1024 + 400)
89 #define TARGET_MAX_FRAG_ENTRIES 0
91 /* Target specific defines for 10.X firmware */
92 #define TARGET_10X_NUM_VDEVS 16
93 #define TARGET_10X_NUM_PEER_AST 2
94 #define TARGET_10X_NUM_WDS_ENTRIES 32
95 #define TARGET_10X_DMA_BURST_SIZE 0
96 #define TARGET_10X_MAC_AGGR_DELIM 0
97 #define TARGET_10X_AST_SKID_LIMIT 16
98 #define TARGET_10X_NUM_PEERS (128 + (TARGET_10X_NUM_VDEVS))
99 #define TARGET_10X_NUM_OFFLOAD_PEERS 0
100 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0
101 #define TARGET_10X_NUM_PEER_KEYS 2
102 #define TARGET_10X_NUM_TIDS 256
103 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
104 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
105 #define TARGET_10X_RX_TIMEOUT_LO_PRI 100
106 #define TARGET_10X_RX_TIMEOUT_HI_PRI 40
107 #define TARGET_10X_RX_DECAP_MODE ATH10K_HW_TXRX_ETHERNET
108 #define TARGET_10X_SCAN_MAX_PENDING_REQS 4
109 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2
110 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2
111 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8
112 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3
113 #define TARGET_10X_NUM_MCAST_GROUPS 0
114 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0
115 #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED
116 #define TARGET_10X_TX_DBG_LOG_SIZE 1024
117 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
118 #define TARGET_10X_VOW_CONFIG 0
119 #define TARGET_10X_NUM_MSDU_DESC (1024 + 400)
120 #define TARGET_10X_MAX_FRAG_ENTRIES 0
122 /* Number of Copy Engines supported */
126 * Total number of PCIe MSI interrupts requested for all interrupt sources.
127 * PCIe standard forces this to be a power of 2.
128 * Some Host OS's limit MSI requests that can be granted to 8
129 * so for now we abide by this limit and avoid requesting more
132 #define MSI_NUM_REQUEST_LOG2 3
133 #define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2)
136 * Granted MSIs are assigned as follows:
137 * Firmware uses the first
138 * Remaining MSIs, if any, are used by Copy Engines
139 * This mapping is known to both Target firmware and Host software.
140 * It may be changed as long as Host and Target are kept in sync.
142 /* MSI for firmware (errors, etc.) */
143 #define MSI_ASSIGN_FW 0
145 /* MSIs for Copy Engines */
146 #define MSI_ASSIGN_CE_INITIAL 1
147 #define MSI_ASSIGN_CE_MAX 7
150 #define RTC_STATE_V_ON 3
152 #define RTC_STATE_COLD_RESET_MASK 0x00000400
153 #define RTC_STATE_V_LSB 0
154 #define RTC_STATE_V_MASK 0x00000007
155 #define RTC_STATE_ADDRESS 0x0000
156 #define PCIE_SOC_WAKE_V_MASK 0x00000001
157 #define PCIE_SOC_WAKE_ADDRESS 0x0004
158 #define PCIE_SOC_WAKE_RESET 0x00000000
159 #define SOC_GLOBAL_RESET_ADDRESS 0x0008
161 #define RTC_SOC_BASE_ADDRESS 0x00004000
162 #define RTC_WMAC_BASE_ADDRESS 0x00005000
163 #define MAC_COEX_BASE_ADDRESS 0x00006000
164 #define BT_COEX_BASE_ADDRESS 0x00007000
165 #define SOC_PCIE_BASE_ADDRESS 0x00008000
166 #define SOC_CORE_BASE_ADDRESS 0x00009000
167 #define WLAN_UART_BASE_ADDRESS 0x0000c000
168 #define WLAN_SI_BASE_ADDRESS 0x00010000
169 #define WLAN_GPIO_BASE_ADDRESS 0x00014000
170 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
171 #define WLAN_MAC_BASE_ADDRESS 0x00020000
172 #define EFUSE_BASE_ADDRESS 0x00030000
173 #define FPGA_REG_BASE_ADDRESS 0x00039000
174 #define WLAN_UART2_BASE_ADDRESS 0x00054c00
175 #define CE_WRAPPER_BASE_ADDRESS 0x00057000
176 #define CE0_BASE_ADDRESS 0x00057400
177 #define CE1_BASE_ADDRESS 0x00057800
178 #define CE2_BASE_ADDRESS 0x00057c00
179 #define CE3_BASE_ADDRESS 0x00058000
180 #define CE4_BASE_ADDRESS 0x00058400
181 #define CE5_BASE_ADDRESS 0x00058800
182 #define CE6_BASE_ADDRESS 0x00058c00
183 #define CE7_BASE_ADDRESS 0x00059000
184 #define DBI_BASE_ADDRESS 0x00060000
185 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000
186 #define PCIE_LOCAL_BASE_ADDRESS 0x00080000
188 #define SOC_RESET_CONTROL_OFFSET 0x00000000
189 #define SOC_RESET_CONTROL_SI0_RST_MASK 0x00000001
190 #define SOC_CPU_CLOCK_OFFSET 0x00000020
191 #define SOC_CPU_CLOCK_STANDARD_LSB 0
192 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003
193 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028
194 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
195 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4
196 #define SOC_LPO_CAL_OFFSET 0x000000e0
197 #define SOC_LPO_CAL_ENABLE_LSB 20
198 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000
200 #define SOC_CHIP_ID_ADDRESS 0x000000ec
201 #define SOC_CHIP_ID_REV_LSB 8
202 #define SOC_CHIP_ID_REV_MASK 0x00000f00
204 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008
205 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004
206 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0
207 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001
209 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028
210 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800
211 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c
212 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800
213 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050
214 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054
215 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058
216 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c
218 #define CLOCK_GPIO_OFFSET 0xffffffff
219 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0
220 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0
222 #define SI_CONFIG_OFFSET 0x00000000
223 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18
224 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
225 #define SI_CONFIG_I2C_LSB 16
226 #define SI_CONFIG_I2C_MASK 0x00010000
227 #define SI_CONFIG_POS_SAMPLE_LSB 7
228 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
229 #define SI_CONFIG_INACTIVE_DATA_LSB 5
230 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
231 #define SI_CONFIG_INACTIVE_CLK_LSB 4
232 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
233 #define SI_CONFIG_DIVIDER_LSB 0
234 #define SI_CONFIG_DIVIDER_MASK 0x0000000f
235 #define SI_CS_OFFSET 0x00000004
236 #define SI_CS_DONE_ERR_MASK 0x00000400
237 #define SI_CS_DONE_INT_MASK 0x00000200
238 #define SI_CS_START_LSB 8
239 #define SI_CS_START_MASK 0x00000100
240 #define SI_CS_RX_CNT_LSB 4
241 #define SI_CS_RX_CNT_MASK 0x000000f0
242 #define SI_CS_TX_CNT_LSB 0
243 #define SI_CS_TX_CNT_MASK 0x0000000f
245 #define SI_TX_DATA0_OFFSET 0x00000008
246 #define SI_TX_DATA1_OFFSET 0x0000000c
247 #define SI_RX_DATA0_OFFSET 0x00000010
248 #define SI_RX_DATA1_OFFSET 0x00000014
250 #define CORE_CTRL_CPU_INTR_MASK 0x00002000
251 #define CORE_CTRL_ADDRESS 0x0000
252 #define PCIE_INTR_ENABLE_ADDRESS 0x0008
253 #define PCIE_INTR_CLR_ADDRESS 0x0014
254 #define SCRATCH_3_ADDRESS 0x0030
256 /* Firmware indications to the Host via SCRATCH_3 register. */
257 #define FW_INDICATOR_ADDRESS (SOC_CORE_BASE_ADDRESS + SCRATCH_3_ADDRESS)
258 #define FW_IND_EVENT_PENDING 1
259 #define FW_IND_INITIALIZED 2
261 /* HOST_REG interrupt from firmware */
262 #define PCIE_INTR_FIRMWARE_MASK 0x00000400
263 #define PCIE_INTR_CE_MASK_ALL 0x0007f800
265 #define DRAM_BASE_ADDRESS 0x00400000
269 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
270 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
271 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET
272 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET
273 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK
274 #define RESET_CONTROL_MBOX_RST_MASK MISSING
275 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK
276 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS
277 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS
278 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS
279 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK
280 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK
281 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS
282 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS
283 #define LOCAL_SCRATCH_OFFSET 0x18
284 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET
285 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET
286 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS
287 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS
288 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS
289 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS
290 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB
291 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK
292 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB
293 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK
294 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS
295 #define MBOX_BASE_ADDRESS MISSING
296 #define INT_STATUS_ENABLE_ERROR_LSB MISSING
297 #define INT_STATUS_ENABLE_ERROR_MASK MISSING
298 #define INT_STATUS_ENABLE_CPU_LSB MISSING
299 #define INT_STATUS_ENABLE_CPU_MASK MISSING
300 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING
301 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING
302 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
303 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
304 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
305 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
306 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
307 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
308 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
309 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
310 #define INT_STATUS_ENABLE_ADDRESS MISSING
311 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
312 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
313 #define HOST_INT_STATUS_ADDRESS MISSING
314 #define CPU_INT_STATUS_ADDRESS MISSING
315 #define ERROR_INT_STATUS_ADDRESS MISSING
316 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING
317 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING
318 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
319 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
320 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
321 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
322 #define COUNT_DEC_ADDRESS MISSING
323 #define HOST_INT_STATUS_CPU_MASK MISSING
324 #define HOST_INT_STATUS_CPU_LSB MISSING
325 #define HOST_INT_STATUS_ERROR_MASK MISSING
326 #define HOST_INT_STATUS_ERROR_LSB MISSING
327 #define HOST_INT_STATUS_COUNTER_MASK MISSING
328 #define HOST_INT_STATUS_COUNTER_LSB MISSING
329 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING
330 #define WINDOW_DATA_ADDRESS MISSING
331 #define WINDOW_READ_ADDR_ADDRESS MISSING
332 #define WINDOW_WRITE_ADDR_ADDRESS MISSING
334 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)