2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include "targaddrs.h"
23 /* Supported FW version */
24 #define SUPPORTED_FW_MAJOR 1
25 #define SUPPORTED_FW_MINOR 0
26 #define SUPPORTED_FW_RELEASE 0
27 #define SUPPORTED_FW_BUILD 636
29 /* QCA988X 2.0 definitions */
30 #define QCA988X_HW_2_0_VERSION 0x4100016c
31 #define QCA988X_HW_2_0_FW_DIR "ath10k/QCA988X/hw2.0"
32 #define QCA988X_HW_2_0_FW_FILE "firmware.bin"
33 #define QCA988X_HW_2_0_OTP_FILE "otp.bin"
34 #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin"
35 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234
37 /* Known pecularities:
38 * - current FW doesn't support raw rx mode (last tested v599)
39 * - current FW dumps upon raw tx mode (last tested v599)
40 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
41 * - raw have FCS, nwifi doesn't
42 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
43 * param, llc/snap) are aligned to 4byte boundaries each */
44 enum ath10k_hw_txrx_mode {
45 ATH10K_HW_TXRX_RAW = 0,
46 ATH10K_HW_TXRX_NATIVE_WIFI = 1,
47 ATH10K_HW_TXRX_ETHERNET = 2,
50 enum ath10k_mcast2ucast_mode {
51 ATH10K_MCAST2UCAST_DISABLED = 0,
52 ATH10K_MCAST2UCAST_ENABLED = 1,
55 #define TARGET_NUM_VDEVS 8
56 #define TARGET_NUM_PEER_AST 2
57 #define TARGET_NUM_WDS_ENTRIES 32
58 #define TARGET_DMA_BURST_SIZE 0
59 #define TARGET_MAC_AGGR_DELIM 0
60 #define TARGET_AST_SKID_LIMIT 16
61 #define TARGET_NUM_PEERS 16
62 #define TARGET_NUM_OFFLOAD_PEERS 0
63 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0
64 #define TARGET_NUM_PEER_KEYS 2
65 #define TARGET_NUM_TIDS (2 * ((TARGET_NUM_PEERS) + (TARGET_NUM_VDEVS)))
66 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
67 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
68 #define TARGET_RX_TIMEOUT_LO_PRI 100
69 #define TARGET_RX_TIMEOUT_HI_PRI 40
70 #define TARGET_RX_DECAP_MODE ATH10K_HW_TXRX_ETHERNET
71 #define TARGET_SCAN_MAX_PENDING_REQS 4
72 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3
73 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3
74 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8
75 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3
76 #define TARGET_NUM_MCAST_GROUPS 0
77 #define TARGET_NUM_MCAST_TABLE_ELEMS 0
78 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED
79 #define TARGET_TX_DBG_LOG_SIZE 1024
80 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
81 #define TARGET_VOW_CONFIG 0
82 #define TARGET_NUM_MSDU_DESC (1024 + 400)
83 #define TARGET_MAX_FRAG_ENTRIES 0
86 /* Number of Copy Engines supported */
90 * Total number of PCIe MSI interrupts requested for all interrupt sources.
91 * PCIe standard forces this to be a power of 2.
92 * Some Host OS's limit MSI requests that can be granted to 8
93 * so for now we abide by this limit and avoid requesting more
96 #define MSI_NUM_REQUEST_LOG2 3
97 #define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2)
100 * Granted MSIs are assigned as follows:
101 * Firmware uses the first
102 * Remaining MSIs, if any, are used by Copy Engines
103 * This mapping is known to both Target firmware and Host software.
104 * It may be changed as long as Host and Target are kept in sync.
106 /* MSI for firmware (errors, etc.) */
107 #define MSI_ASSIGN_FW 0
109 /* MSIs for Copy Engines */
110 #define MSI_ASSIGN_CE_INITIAL 1
111 #define MSI_ASSIGN_CE_MAX 7
114 #define RTC_STATE_V_ON 3
116 #define RTC_STATE_COLD_RESET_MASK 0x00000400
117 #define RTC_STATE_V_LSB 0
118 #define RTC_STATE_V_MASK 0x00000007
119 #define RTC_STATE_ADDRESS 0x0000
120 #define PCIE_SOC_WAKE_V_MASK 0x00000001
121 #define PCIE_SOC_WAKE_ADDRESS 0x0004
122 #define PCIE_SOC_WAKE_RESET 0x00000000
123 #define SOC_GLOBAL_RESET_ADDRESS 0x0008
125 #define RTC_SOC_BASE_ADDRESS 0x00004000
126 #define RTC_WMAC_BASE_ADDRESS 0x00005000
127 #define MAC_COEX_BASE_ADDRESS 0x00006000
128 #define BT_COEX_BASE_ADDRESS 0x00007000
129 #define SOC_PCIE_BASE_ADDRESS 0x00008000
130 #define SOC_CORE_BASE_ADDRESS 0x00009000
131 #define WLAN_UART_BASE_ADDRESS 0x0000c000
132 #define WLAN_SI_BASE_ADDRESS 0x00010000
133 #define WLAN_GPIO_BASE_ADDRESS 0x00014000
134 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
135 #define WLAN_MAC_BASE_ADDRESS 0x00020000
136 #define EFUSE_BASE_ADDRESS 0x00030000
137 #define FPGA_REG_BASE_ADDRESS 0x00039000
138 #define WLAN_UART2_BASE_ADDRESS 0x00054c00
139 #define CE_WRAPPER_BASE_ADDRESS 0x00057000
140 #define CE0_BASE_ADDRESS 0x00057400
141 #define CE1_BASE_ADDRESS 0x00057800
142 #define CE2_BASE_ADDRESS 0x00057c00
143 #define CE3_BASE_ADDRESS 0x00058000
144 #define CE4_BASE_ADDRESS 0x00058400
145 #define CE5_BASE_ADDRESS 0x00058800
146 #define CE6_BASE_ADDRESS 0x00058c00
147 #define CE7_BASE_ADDRESS 0x00059000
148 #define DBI_BASE_ADDRESS 0x00060000
149 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000
150 #define PCIE_LOCAL_BASE_ADDRESS 0x00080000
152 #define SOC_RESET_CONTROL_OFFSET 0x00000000
153 #define SOC_RESET_CONTROL_SI0_RST_MASK 0x00000001
154 #define SOC_CPU_CLOCK_OFFSET 0x00000020
155 #define SOC_CPU_CLOCK_STANDARD_LSB 0
156 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003
157 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028
158 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
159 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4
160 #define SOC_LPO_CAL_OFFSET 0x000000e0
161 #define SOC_LPO_CAL_ENABLE_LSB 20
162 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000
164 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008
165 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004
166 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0
167 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001
169 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028
170 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800
171 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c
172 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800
173 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050
174 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054
175 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058
176 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c
178 #define CLOCK_GPIO_OFFSET 0xffffffff
179 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0
180 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0
182 #define SI_CONFIG_OFFSET 0x00000000
183 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18
184 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
185 #define SI_CONFIG_I2C_LSB 16
186 #define SI_CONFIG_I2C_MASK 0x00010000
187 #define SI_CONFIG_POS_SAMPLE_LSB 7
188 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
189 #define SI_CONFIG_INACTIVE_DATA_LSB 5
190 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
191 #define SI_CONFIG_INACTIVE_CLK_LSB 4
192 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
193 #define SI_CONFIG_DIVIDER_LSB 0
194 #define SI_CONFIG_DIVIDER_MASK 0x0000000f
195 #define SI_CS_OFFSET 0x00000004
196 #define SI_CS_DONE_ERR_MASK 0x00000400
197 #define SI_CS_DONE_INT_MASK 0x00000200
198 #define SI_CS_START_LSB 8
199 #define SI_CS_START_MASK 0x00000100
200 #define SI_CS_RX_CNT_LSB 4
201 #define SI_CS_RX_CNT_MASK 0x000000f0
202 #define SI_CS_TX_CNT_LSB 0
203 #define SI_CS_TX_CNT_MASK 0x0000000f
205 #define SI_TX_DATA0_OFFSET 0x00000008
206 #define SI_TX_DATA1_OFFSET 0x0000000c
207 #define SI_RX_DATA0_OFFSET 0x00000010
208 #define SI_RX_DATA1_OFFSET 0x00000014
210 #define CORE_CTRL_CPU_INTR_MASK 0x00002000
211 #define CORE_CTRL_ADDRESS 0x0000
212 #define PCIE_INTR_ENABLE_ADDRESS 0x0008
213 #define PCIE_INTR_CLR_ADDRESS 0x0014
214 #define SCRATCH_3_ADDRESS 0x0030
216 /* Firmware indications to the Host via SCRATCH_3 register. */
217 #define FW_INDICATOR_ADDRESS (SOC_CORE_BASE_ADDRESS + SCRATCH_3_ADDRESS)
218 #define FW_IND_EVENT_PENDING 1
219 #define FW_IND_INITIALIZED 2
221 /* HOST_REG interrupt from firmware */
222 #define PCIE_INTR_FIRMWARE_MASK 0x00000400
223 #define PCIE_INTR_CE_MASK_ALL 0x0007f800
225 #define DRAM_BASE_ADDRESS 0x00400000
229 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
230 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
231 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET
232 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET
233 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK
234 #define RESET_CONTROL_MBOX_RST_MASK MISSING
235 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK
236 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS
237 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS
238 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS
239 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK
240 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK
241 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS
242 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS
243 #define LOCAL_SCRATCH_OFFSET 0x18
244 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET
245 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET
246 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS
247 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS
248 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS
249 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS
250 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB
251 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK
252 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB
253 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK
254 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS
255 #define MBOX_BASE_ADDRESS MISSING
256 #define INT_STATUS_ENABLE_ERROR_LSB MISSING
257 #define INT_STATUS_ENABLE_ERROR_MASK MISSING
258 #define INT_STATUS_ENABLE_CPU_LSB MISSING
259 #define INT_STATUS_ENABLE_CPU_MASK MISSING
260 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING
261 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING
262 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
263 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
264 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
265 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
266 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
267 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
268 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
269 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
270 #define INT_STATUS_ENABLE_ADDRESS MISSING
271 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
272 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
273 #define HOST_INT_STATUS_ADDRESS MISSING
274 #define CPU_INT_STATUS_ADDRESS MISSING
275 #define ERROR_INT_STATUS_ADDRESS MISSING
276 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING
277 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING
278 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
279 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
280 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
281 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
282 #define COUNT_DEC_ADDRESS MISSING
283 #define HOST_INT_STATUS_CPU_MASK MISSING
284 #define HOST_INT_STATUS_CPU_LSB MISSING
285 #define HOST_INT_STATUS_ERROR_MASK MISSING
286 #define HOST_INT_STATUS_ERROR_LSB MISSING
287 #define HOST_INT_STATUS_COUNTER_MASK MISSING
288 #define HOST_INT_STATUS_COUNTER_LSB MISSING
289 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING
290 #define WINDOW_DATA_ADDRESS MISSING
291 #define WINDOW_READ_ADDR_ADDRESS MISSING
292 #define WINDOW_WRITE_ADDR_ADDRESS MISSING
294 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)