2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/pci.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
26 #include "targaddrs.h"
35 static unsigned int ath10k_target_ps;
36 module_param(ath10k_target_ps, uint, 0644);
37 MODULE_PARM_DESC(ath10k_target_ps, "Enable ath10k Target (SoC) PS option");
39 #define QCA988X_2_0_DEVICE_ID (0x003c)
41 static DEFINE_PCI_DEVICE_TABLE(ath10k_pci_id_table) = {
42 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
46 static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
49 static void ath10k_pci_process_ce(struct ath10k *ar);
50 static int ath10k_pci_post_rx(struct ath10k *ar);
51 static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info,
53 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info);
54 static void ath10k_pci_stop_ce(struct ath10k *ar);
55 static void ath10k_pci_device_reset(struct ath10k *ar);
56 static int ath10k_pci_reset_target(struct ath10k *ar);
57 static int ath10k_pci_start_intr(struct ath10k *ar);
58 static void ath10k_pci_stop_intr(struct ath10k *ar);
60 static const struct ce_attr host_ce_config_wlan[] = {
61 /* CE0: host->target HTC control and raw streams */
63 .flags = CE_ATTR_FLAGS,
69 /* CE1: target->host HTT + HTC control */
71 .flags = CE_ATTR_FLAGS,
77 /* CE2: target->host WMI */
79 .flags = CE_ATTR_FLAGS,
85 /* CE3: host->target WMI */
87 .flags = CE_ATTR_FLAGS,
93 /* CE4: host->target HTT */
95 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
96 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
103 .flags = CE_ATTR_FLAGS,
109 /* CE6: target autonomous hif_memcpy */
111 .flags = CE_ATTR_FLAGS,
117 /* CE7: ce_diag, the Diagnostic Window */
119 .flags = CE_ATTR_FLAGS,
121 .src_sz_max = DIAG_TRANSFER_LIMIT,
126 /* Target firmware's Copy Engine configuration. */
127 static const struct ce_pipe_config target_ce_config_wlan[] = {
128 /* CE0: host->target HTC control and raw streams */
131 .pipedir = PIPEDIR_OUT,
134 .flags = CE_ATTR_FLAGS,
138 /* CE1: target->host HTT + HTC control */
141 .pipedir = PIPEDIR_IN,
144 .flags = CE_ATTR_FLAGS,
148 /* CE2: target->host WMI */
151 .pipedir = PIPEDIR_IN,
154 .flags = CE_ATTR_FLAGS,
158 /* CE3: host->target WMI */
161 .pipedir = PIPEDIR_OUT,
164 .flags = CE_ATTR_FLAGS,
168 /* CE4: host->target HTT */
171 .pipedir = PIPEDIR_OUT,
174 .flags = CE_ATTR_FLAGS,
178 /* NB: 50% of src nentries, since tx has 2 frags */
183 .pipedir = PIPEDIR_OUT,
186 .flags = CE_ATTR_FLAGS,
190 /* CE6: Reserved for target autonomous hif_memcpy */
193 .pipedir = PIPEDIR_INOUT,
196 .flags = CE_ATTR_FLAGS,
200 /* CE7 used only by Host */
204 * Diagnostic read/write access is provided for startup/config/debug usage.
205 * Caller must guarantee proper alignment, when applicable, and single user
208 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
211 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
214 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
217 struct ath10k_ce_pipe *ce_diag;
218 /* Host buffer address in CE space */
220 dma_addr_t ce_data_base = 0;
221 void *data_buf = NULL;
225 * This code cannot handle reads to non-memory space. Redirect to the
226 * register read fn but preserve the multi word read capability of
229 if (address < DRAM_BASE_ADDRESS) {
230 if (!IS_ALIGNED(address, 4) ||
231 !IS_ALIGNED((unsigned long)data, 4))
234 while ((nbytes >= 4) && ((ret = ath10k_pci_diag_read_access(
235 ar, address, (u32 *)data)) == 0)) {
236 nbytes -= sizeof(u32);
237 address += sizeof(u32);
243 ce_diag = ar_pci->ce_diag;
246 * Allocate a temporary bounce buffer to hold caller's data
247 * to be DMA'ed from Target. This guarantees
248 * 1) 4-byte alignment
249 * 2) Buffer in DMA-able space
251 orig_nbytes = nbytes;
252 data_buf = (unsigned char *)pci_alloc_consistent(ar_pci->pdev,
260 memset(data_buf, 0, orig_nbytes);
262 remaining_bytes = orig_nbytes;
263 ce_data = ce_data_base;
264 while (remaining_bytes) {
265 nbytes = min_t(unsigned int, remaining_bytes,
266 DIAG_TRANSFER_LIMIT);
268 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, ce_data);
272 /* Request CE to send from Target(!) address to Host buffer */
274 * The address supplied by the caller is in the
275 * Target CPU virtual address space.
277 * In order to use this address with the diagnostic CE,
278 * convert it from Target CPU virtual address space
279 * to CE address space
282 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem,
284 ath10k_pci_sleep(ar);
286 ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0,
292 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
296 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
302 if (nbytes != completed_nbytes) {
307 if (buf != (u32) address) {
313 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
318 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
324 if (nbytes != completed_nbytes) {
329 if (buf != ce_data) {
334 remaining_bytes -= nbytes;
341 /* Copy data from allocated DMA buf to caller's buf */
342 WARN_ON_ONCE(orig_nbytes & 3);
343 for (i = 0; i < orig_nbytes / sizeof(__le32); i++) {
345 __le32_to_cpu(((__le32 *)data_buf)[i]);
348 ath10k_dbg(ATH10K_DBG_PCI, "%s failure (0x%x)\n",
352 pci_free_consistent(ar_pci->pdev, orig_nbytes,
353 data_buf, ce_data_base);
358 /* Read 4-byte aligned data from Target memory or register */
359 static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
362 /* Assume range doesn't cross this boundary */
363 if (address >= DRAM_BASE_ADDRESS)
364 return ath10k_pci_diag_read_mem(ar, address, data, sizeof(u32));
367 *data = ath10k_pci_read32(ar, address);
368 ath10k_pci_sleep(ar);
372 static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
373 const void *data, int nbytes)
375 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
378 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
381 struct ath10k_ce_pipe *ce_diag;
382 void *data_buf = NULL;
383 u32 ce_data; /* Host buffer address in CE space */
384 dma_addr_t ce_data_base = 0;
387 ce_diag = ar_pci->ce_diag;
390 * Allocate a temporary bounce buffer to hold caller's data
391 * to be DMA'ed to Target. This guarantees
392 * 1) 4-byte alignment
393 * 2) Buffer in DMA-able space
395 orig_nbytes = nbytes;
396 data_buf = (unsigned char *)pci_alloc_consistent(ar_pci->pdev,
404 /* Copy caller's data to allocated DMA buf */
405 WARN_ON_ONCE(orig_nbytes & 3);
406 for (i = 0; i < orig_nbytes / sizeof(__le32); i++)
407 ((__le32 *)data_buf)[i] = __cpu_to_le32(((u32 *)data)[i]);
410 * The address supplied by the caller is in the
411 * Target CPU virtual address space.
413 * In order to use this address with the diagnostic CE,
415 * Target CPU virtual address space
420 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, address);
421 ath10k_pci_sleep(ar);
423 remaining_bytes = orig_nbytes;
424 ce_data = ce_data_base;
425 while (remaining_bytes) {
426 /* FIXME: check cast */
427 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
429 /* Set up to receive directly into Target(!) address */
430 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, address);
435 * Request CE to send caller-supplied data that
436 * was copied to bounce buffer to Target(!) address.
438 ret = ath10k_ce_send(ce_diag, NULL, (u32) ce_data,
444 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
449 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
455 if (nbytes != completed_nbytes) {
460 if (buf != ce_data) {
466 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
471 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
477 if (nbytes != completed_nbytes) {
482 if (buf != address) {
487 remaining_bytes -= nbytes;
494 pci_free_consistent(ar_pci->pdev, orig_nbytes, data_buf,
499 ath10k_dbg(ATH10K_DBG_PCI, "%s failure (0x%x)\n", __func__,
505 /* Write 4B data to Target memory or register */
506 static int ath10k_pci_diag_write_access(struct ath10k *ar, u32 address,
509 /* Assume range doesn't cross this boundary */
510 if (address >= DRAM_BASE_ADDRESS)
511 return ath10k_pci_diag_write_mem(ar, address, &data,
515 ath10k_pci_write32(ar, address, data);
516 ath10k_pci_sleep(ar);
520 static bool ath10k_pci_target_is_awake(struct ath10k *ar)
522 void __iomem *mem = ath10k_pci_priv(ar)->mem;
524 val = ioread32(mem + PCIE_LOCAL_BASE_ADDRESS +
526 return (RTC_STATE_V_GET(val) == RTC_STATE_V_ON);
529 static void ath10k_pci_wait(struct ath10k *ar)
533 while (n-- && !ath10k_pci_target_is_awake(ar))
537 ath10k_warn("Unable to wakeup target\n");
540 void ath10k_do_pci_wake(struct ath10k *ar)
542 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
543 void __iomem *pci_addr = ar_pci->mem;
547 if (atomic_read(&ar_pci->keep_awake_count) == 0) {
549 iowrite32(PCIE_SOC_WAKE_V_MASK,
550 pci_addr + PCIE_LOCAL_BASE_ADDRESS +
551 PCIE_SOC_WAKE_ADDRESS);
553 atomic_inc(&ar_pci->keep_awake_count);
555 if (ar_pci->verified_awake)
559 if (ath10k_pci_target_is_awake(ar)) {
560 ar_pci->verified_awake = true;
564 if (tot_delay > PCIE_WAKE_TIMEOUT) {
565 ath10k_warn("target takes too long to wake up (awake count %d)\n",
566 atomic_read(&ar_pci->keep_awake_count));
571 tot_delay += curr_delay;
578 void ath10k_do_pci_sleep(struct ath10k *ar)
580 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
581 void __iomem *pci_addr = ar_pci->mem;
583 if (atomic_dec_and_test(&ar_pci->keep_awake_count)) {
585 ar_pci->verified_awake = false;
586 iowrite32(PCIE_SOC_WAKE_RESET,
587 pci_addr + PCIE_LOCAL_BASE_ADDRESS +
588 PCIE_SOC_WAKE_ADDRESS);
593 * FIXME: Handle OOM properly.
596 struct ath10k_pci_compl *get_free_compl(struct ath10k_pci_pipe *pipe_info)
598 struct ath10k_pci_compl *compl = NULL;
600 spin_lock_bh(&pipe_info->pipe_lock);
601 if (list_empty(&pipe_info->compl_free)) {
602 ath10k_warn("Completion buffers are full\n");
605 compl = list_first_entry(&pipe_info->compl_free,
606 struct ath10k_pci_compl, list);
607 list_del(&compl->list);
609 spin_unlock_bh(&pipe_info->pipe_lock);
613 /* Called by lower (CE) layer when a send to Target completes. */
614 static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe *ce_state,
615 void *transfer_context,
618 unsigned int transfer_id)
620 struct ath10k *ar = ce_state->ar;
621 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
622 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
623 struct ath10k_pci_compl *compl;
624 bool process = false;
628 * For the send completion of an item in sendlist, just
629 * increment num_sends_allowed. The upper layer callback will
630 * be triggered when last fragment is done with send.
632 if (transfer_context == CE_SENDLIST_ITEM_CTXT) {
633 spin_lock_bh(&pipe_info->pipe_lock);
634 pipe_info->num_sends_allowed++;
635 spin_unlock_bh(&pipe_info->pipe_lock);
639 compl = get_free_compl(pipe_info);
643 compl->state = ATH10K_PCI_COMPL_SEND;
644 compl->ce_state = ce_state;
645 compl->pipe_info = pipe_info;
646 compl->skb = transfer_context;
647 compl->nbytes = nbytes;
648 compl->transfer_id = transfer_id;
652 * Add the completion to the processing queue.
654 spin_lock_bh(&ar_pci->compl_lock);
655 list_add_tail(&compl->list, &ar_pci->compl_process);
656 spin_unlock_bh(&ar_pci->compl_lock);
659 } while (ath10k_ce_completed_send_next(ce_state,
665 * If only some of the items within a sendlist have completed,
666 * don't invoke completion processing until the entire sendlist
672 ath10k_pci_process_ce(ar);
675 /* Called by lower (CE) layer when data is received from the Target. */
676 static void ath10k_pci_ce_recv_data(struct ath10k_ce_pipe *ce_state,
677 void *transfer_context, u32 ce_data,
679 unsigned int transfer_id,
682 struct ath10k *ar = ce_state->ar;
683 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
684 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
685 struct ath10k_pci_compl *compl;
689 compl = get_free_compl(pipe_info);
693 compl->state = ATH10K_PCI_COMPL_RECV;
694 compl->ce_state = ce_state;
695 compl->pipe_info = pipe_info;
696 compl->skb = transfer_context;
697 compl->nbytes = nbytes;
698 compl->transfer_id = transfer_id;
699 compl->flags = flags;
701 skb = transfer_context;
702 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
703 skb->len + skb_tailroom(skb),
706 * Add the completion to the processing queue.
708 spin_lock_bh(&ar_pci->compl_lock);
709 list_add_tail(&compl->list, &ar_pci->compl_process);
710 spin_unlock_bh(&ar_pci->compl_lock);
712 } while (ath10k_ce_completed_recv_next(ce_state,
718 ath10k_pci_process_ce(ar);
721 /* Send the first nbytes bytes of the buffer */
722 static int ath10k_pci_hif_send_head(struct ath10k *ar, u8 pipe_id,
723 unsigned int transfer_id,
724 unsigned int bytes, struct sk_buff *nbuf)
726 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(nbuf);
727 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
728 struct ath10k_pci_pipe *pipe_info = &(ar_pci->pipe_info[pipe_id]);
729 struct ath10k_ce_pipe *ce_hdl = pipe_info->ce_hdl;
730 struct ce_sendlist sendlist;
735 memset(&sendlist, 0, sizeof(struct ce_sendlist));
737 len = min(bytes, nbuf->len);
741 ath10k_warn("skb not aligned to 4-byte boundary (%d)\n", len);
743 ath10k_dbg(ATH10K_DBG_PCI,
744 "pci send data vaddr %p paddr 0x%llx len %d as %d bytes\n",
745 nbuf->data, (unsigned long long) skb_cb->paddr,
747 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL,
749 nbuf->data, nbuf->len);
751 ath10k_ce_sendlist_buf_add(&sendlist, skb_cb->paddr, len, flags);
753 /* Make sure we have resources to handle this request */
754 spin_lock_bh(&pipe_info->pipe_lock);
755 if (!pipe_info->num_sends_allowed) {
756 ath10k_warn("Pipe: %d is full\n", pipe_id);
757 spin_unlock_bh(&pipe_info->pipe_lock);
760 pipe_info->num_sends_allowed--;
761 spin_unlock_bh(&pipe_info->pipe_lock);
763 ret = ath10k_ce_sendlist_send(ce_hdl, nbuf, &sendlist, transfer_id);
765 ath10k_warn("CE send failed: %p\n", nbuf);
770 static u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
772 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
773 struct ath10k_pci_pipe *pipe_info = &(ar_pci->pipe_info[pipe]);
776 spin_lock_bh(&pipe_info->pipe_lock);
777 ret = pipe_info->num_sends_allowed;
778 spin_unlock_bh(&pipe_info->pipe_lock);
783 static void ath10k_pci_hif_dump_area(struct ath10k *ar)
785 u32 reg_dump_area = 0;
786 u32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
791 ath10k_err("firmware crashed!\n");
792 ath10k_err("hardware name %s version 0x%x\n",
793 ar->hw_params.name, ar->target_version);
794 ath10k_err("firmware version: %u.%u.%u.%u\n", ar->fw_version_major,
795 ar->fw_version_minor, ar->fw_version_release,
796 ar->fw_version_build);
798 host_addr = host_interest_item_address(HI_ITEM(hi_failure_state));
799 if (ath10k_pci_diag_read_mem(ar, host_addr,
800 ®_dump_area, sizeof(u32)) != 0) {
801 ath10k_warn("could not read hi_failure_state\n");
805 ath10k_err("target register Dump Location: 0x%08X\n", reg_dump_area);
807 ret = ath10k_pci_diag_read_mem(ar, reg_dump_area,
809 REG_DUMP_COUNT_QCA988X * sizeof(u32));
811 ath10k_err("could not dump FW Dump Area\n");
815 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
817 ath10k_err("target Register Dump\n");
818 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
819 ath10k_err("[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
822 reg_dump_values[i + 1],
823 reg_dump_values[i + 2],
824 reg_dump_values[i + 3]);
826 ieee80211_queue_work(ar->hw, &ar->restart_work);
829 static void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
835 * Decide whether to actually poll for completions, or just
836 * wait for a later chance.
837 * If there seem to be plenty of resources left, then just wait
838 * since checking involves reading a CE register, which is a
839 * relatively expensive operation.
841 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
844 * If at least 50% of the total resources are still available,
845 * don't bother checking again yet.
847 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
850 ath10k_ce_per_engine_service(ar, pipe);
853 static void ath10k_pci_hif_set_callbacks(struct ath10k *ar,
854 struct ath10k_hif_cb *callbacks)
856 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
858 ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
860 memcpy(&ar_pci->msg_callbacks_current, callbacks,
861 sizeof(ar_pci->msg_callbacks_current));
864 static int ath10k_pci_start_ce(struct ath10k *ar)
866 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
867 struct ath10k_ce_pipe *ce_diag = ar_pci->ce_diag;
868 const struct ce_attr *attr;
869 struct ath10k_pci_pipe *pipe_info;
870 struct ath10k_pci_compl *compl;
871 int i, pipe_num, completions, disable_interrupts;
873 spin_lock_init(&ar_pci->compl_lock);
874 INIT_LIST_HEAD(&ar_pci->compl_process);
876 for (pipe_num = 0; pipe_num < ar_pci->ce_count; pipe_num++) {
877 pipe_info = &ar_pci->pipe_info[pipe_num];
879 spin_lock_init(&pipe_info->pipe_lock);
880 INIT_LIST_HEAD(&pipe_info->compl_free);
882 /* Handle Diagnostic CE specially */
883 if (pipe_info->ce_hdl == ce_diag)
886 attr = &host_ce_config_wlan[pipe_num];
889 if (attr->src_nentries) {
890 disable_interrupts = attr->flags & CE_ATTR_DIS_INTR;
891 ath10k_ce_send_cb_register(pipe_info->ce_hdl,
892 ath10k_pci_ce_send_done,
894 completions += attr->src_nentries;
895 pipe_info->num_sends_allowed = attr->src_nentries - 1;
898 if (attr->dest_nentries) {
899 ath10k_ce_recv_cb_register(pipe_info->ce_hdl,
900 ath10k_pci_ce_recv_data);
901 completions += attr->dest_nentries;
904 if (completions == 0)
907 for (i = 0; i < completions; i++) {
908 compl = kmalloc(sizeof(*compl), GFP_KERNEL);
910 ath10k_warn("No memory for completion state\n");
911 ath10k_pci_stop_ce(ar);
915 compl->state = ATH10K_PCI_COMPL_FREE;
916 list_add_tail(&compl->list, &pipe_info->compl_free);
923 static void ath10k_pci_stop_ce(struct ath10k *ar)
925 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
926 struct ath10k_pci_compl *compl;
930 ath10k_ce_disable_interrupts(ar);
932 /* Cancel the pending tasklet */
933 tasklet_kill(&ar_pci->intr_tq);
935 for (i = 0; i < CE_COUNT; i++)
936 tasklet_kill(&ar_pci->pipe_info[i].intr);
938 /* Mark pending completions as aborted, so that upper layers free up
939 * their associated resources */
940 spin_lock_bh(&ar_pci->compl_lock);
941 list_for_each_entry(compl, &ar_pci->compl_process, list) {
943 ATH10K_SKB_CB(skb)->is_aborted = true;
945 spin_unlock_bh(&ar_pci->compl_lock);
948 static void ath10k_pci_cleanup_ce(struct ath10k *ar)
950 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
951 struct ath10k_pci_compl *compl, *tmp;
952 struct ath10k_pci_pipe *pipe_info;
953 struct sk_buff *netbuf;
956 /* Free pending completions. */
957 spin_lock_bh(&ar_pci->compl_lock);
958 if (!list_empty(&ar_pci->compl_process))
959 ath10k_warn("pending completions still present! possible memory leaks.\n");
961 list_for_each_entry_safe(compl, tmp, &ar_pci->compl_process, list) {
962 list_del(&compl->list);
964 dev_kfree_skb_any(netbuf);
967 spin_unlock_bh(&ar_pci->compl_lock);
969 /* Free unused completions for each pipe. */
970 for (pipe_num = 0; pipe_num < ar_pci->ce_count; pipe_num++) {
971 pipe_info = &ar_pci->pipe_info[pipe_num];
973 spin_lock_bh(&pipe_info->pipe_lock);
974 list_for_each_entry_safe(compl, tmp,
975 &pipe_info->compl_free, list) {
976 list_del(&compl->list);
979 spin_unlock_bh(&pipe_info->pipe_lock);
983 static void ath10k_pci_process_ce(struct ath10k *ar)
985 struct ath10k_pci *ar_pci = ar->hif.priv;
986 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
987 struct ath10k_pci_compl *compl;
990 int ret, send_done = 0;
992 /* Upper layers aren't ready to handle tx/rx completions in parallel so
993 * we must serialize all completion processing. */
995 spin_lock_bh(&ar_pci->compl_lock);
996 if (ar_pci->compl_processing) {
997 spin_unlock_bh(&ar_pci->compl_lock);
1000 ar_pci->compl_processing = true;
1001 spin_unlock_bh(&ar_pci->compl_lock);
1004 spin_lock_bh(&ar_pci->compl_lock);
1005 if (list_empty(&ar_pci->compl_process)) {
1006 spin_unlock_bh(&ar_pci->compl_lock);
1009 compl = list_first_entry(&ar_pci->compl_process,
1010 struct ath10k_pci_compl, list);
1011 list_del(&compl->list);
1012 spin_unlock_bh(&ar_pci->compl_lock);
1014 switch (compl->state) {
1015 case ATH10K_PCI_COMPL_SEND:
1016 cb->tx_completion(ar,
1018 compl->transfer_id);
1021 case ATH10K_PCI_COMPL_RECV:
1022 ret = ath10k_pci_post_rx_pipe(compl->pipe_info, 1);
1024 ath10k_warn("Unable to post recv buffer for pipe: %d\n",
1025 compl->pipe_info->pipe_num);
1030 nbytes = compl->nbytes;
1032 ath10k_dbg(ATH10K_DBG_PCI,
1033 "ath10k_pci_ce_recv_data netbuf=%p nbytes=%d\n",
1035 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL,
1036 "ath10k rx: ", skb->data, nbytes);
1038 if (skb->len + skb_tailroom(skb) >= nbytes) {
1040 skb_put(skb, nbytes);
1041 cb->rx_completion(ar, skb,
1042 compl->pipe_info->pipe_num);
1044 ath10k_warn("rxed more than expected (nbytes %d, max %d)",
1046 skb->len + skb_tailroom(skb));
1049 case ATH10K_PCI_COMPL_FREE:
1050 ath10k_warn("free completion cannot be processed\n");
1053 ath10k_warn("invalid completion state (%d)\n",
1058 compl->state = ATH10K_PCI_COMPL_FREE;
1061 * Add completion back to the pipe's free list.
1063 spin_lock_bh(&compl->pipe_info->pipe_lock);
1064 list_add_tail(&compl->list, &compl->pipe_info->compl_free);
1065 compl->pipe_info->num_sends_allowed += send_done;
1066 spin_unlock_bh(&compl->pipe_info->pipe_lock);
1069 spin_lock_bh(&ar_pci->compl_lock);
1070 ar_pci->compl_processing = false;
1071 spin_unlock_bh(&ar_pci->compl_lock);
1074 /* TODO - temporary mapping while we have too few CE's */
1075 static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar,
1076 u16 service_id, u8 *ul_pipe,
1077 u8 *dl_pipe, int *ul_is_polled,
1082 /* polling for received messages not supported */
1085 switch (service_id) {
1086 case ATH10K_HTC_SVC_ID_HTT_DATA_MSG:
1088 * Host->target HTT gets its own pipe, so it can be polled
1089 * while other pipes are interrupt driven.
1093 * Use the same target->host pipe for HTC ctrl, HTC raw
1099 case ATH10K_HTC_SVC_ID_RSVD_CTRL:
1100 case ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS:
1102 * Note: HTC_RAW_STREAMS_SVC is currently unused, and
1103 * HTC_CTRL_RSVD_SVC could share the same pipe as the
1104 * WMI services. So, if another CE is needed, change
1105 * this to *ul_pipe = 3, which frees up CE 0.
1112 case ATH10K_HTC_SVC_ID_WMI_DATA_BK:
1113 case ATH10K_HTC_SVC_ID_WMI_DATA_BE:
1114 case ATH10K_HTC_SVC_ID_WMI_DATA_VI:
1115 case ATH10K_HTC_SVC_ID_WMI_DATA_VO:
1117 case ATH10K_HTC_SVC_ID_WMI_CONTROL:
1123 /* pipe 6 reserved */
1124 /* pipe 7 reserved */
1131 (host_ce_config_wlan[*ul_pipe].flags & CE_ATTR_DIS_INTR) != 0;
1136 static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1137 u8 *ul_pipe, u8 *dl_pipe)
1139 int ul_is_polled, dl_is_polled;
1141 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1142 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1149 static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info,
1152 struct ath10k *ar = pipe_info->hif_ce_state;
1153 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1154 struct ath10k_ce_pipe *ce_state = pipe_info->ce_hdl;
1155 struct sk_buff *skb;
1159 if (pipe_info->buf_sz == 0)
1162 for (i = 0; i < num; i++) {
1163 skb = dev_alloc_skb(pipe_info->buf_sz);
1165 ath10k_warn("could not allocate skbuff for pipe %d\n",
1171 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
1173 ce_data = dma_map_single(ar->dev, skb->data,
1174 skb->len + skb_tailroom(skb),
1177 if (unlikely(dma_mapping_error(ar->dev, ce_data))) {
1178 ath10k_warn("could not dma map skbuff\n");
1179 dev_kfree_skb_any(skb);
1184 ATH10K_SKB_CB(skb)->paddr = ce_data;
1186 pci_dma_sync_single_for_device(ar_pci->pdev, ce_data,
1188 PCI_DMA_FROMDEVICE);
1190 ret = ath10k_ce_recv_buf_enqueue(ce_state, (void *)skb,
1193 ath10k_warn("could not enqueue to pipe %d (%d)\n",
1202 ath10k_pci_rx_pipe_cleanup(pipe_info);
1206 static int ath10k_pci_post_rx(struct ath10k *ar)
1208 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1209 struct ath10k_pci_pipe *pipe_info;
1210 const struct ce_attr *attr;
1211 int pipe_num, ret = 0;
1213 for (pipe_num = 0; pipe_num < ar_pci->ce_count; pipe_num++) {
1214 pipe_info = &ar_pci->pipe_info[pipe_num];
1215 attr = &host_ce_config_wlan[pipe_num];
1217 if (attr->dest_nentries == 0)
1220 ret = ath10k_pci_post_rx_pipe(pipe_info,
1221 attr->dest_nentries - 1);
1223 ath10k_warn("Unable to replenish recv buffers for pipe: %d\n",
1226 for (; pipe_num >= 0; pipe_num--) {
1227 pipe_info = &ar_pci->pipe_info[pipe_num];
1228 ath10k_pci_rx_pipe_cleanup(pipe_info);
1237 static int ath10k_pci_hif_start(struct ath10k *ar)
1239 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1242 ret = ath10k_pci_start_ce(ar);
1244 ath10k_warn("could not start CE (%d)\n", ret);
1248 /* Post buffers once to start things off. */
1249 ret = ath10k_pci_post_rx(ar);
1251 ath10k_warn("could not post rx pipes (%d)\n", ret);
1255 ar_pci->started = 1;
1259 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
1262 struct ath10k_pci *ar_pci;
1263 struct ath10k_ce_pipe *ce_hdl;
1265 struct sk_buff *netbuf;
1268 buf_sz = pipe_info->buf_sz;
1270 /* Unused Copy Engine */
1274 ar = pipe_info->hif_ce_state;
1275 ar_pci = ath10k_pci_priv(ar);
1277 if (!ar_pci->started)
1280 ce_hdl = pipe_info->ce_hdl;
1282 while (ath10k_ce_revoke_recv_next(ce_hdl, (void **)&netbuf,
1284 dma_unmap_single(ar->dev, ATH10K_SKB_CB(netbuf)->paddr,
1285 netbuf->len + skb_tailroom(netbuf),
1287 dev_kfree_skb_any(netbuf);
1291 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
1294 struct ath10k_pci *ar_pci;
1295 struct ath10k_ce_pipe *ce_hdl;
1296 struct sk_buff *netbuf;
1298 unsigned int nbytes;
1302 buf_sz = pipe_info->buf_sz;
1304 /* Unused Copy Engine */
1308 ar = pipe_info->hif_ce_state;
1309 ar_pci = ath10k_pci_priv(ar);
1311 if (!ar_pci->started)
1314 ce_hdl = pipe_info->ce_hdl;
1316 while (ath10k_ce_cancel_send_next(ce_hdl, (void **)&netbuf,
1317 &ce_data, &nbytes, &id) == 0) {
1318 if (netbuf != CE_SENDLIST_ITEM_CTXT)
1320 * Indicate the completion to higer layer to free
1323 ATH10K_SKB_CB(netbuf)->is_aborted = true;
1324 ar_pci->msg_callbacks_current.tx_completion(ar,
1331 * Cleanup residual buffers for device shutdown:
1332 * buffers that were enqueued for receive
1333 * buffers that were to be sent
1334 * Note: Buffers that had completed but which were
1335 * not yet processed are on a completion queue. They
1336 * are handled when the completion thread shuts down.
1338 static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
1340 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1343 for (pipe_num = 0; pipe_num < ar_pci->ce_count; pipe_num++) {
1344 struct ath10k_pci_pipe *pipe_info;
1346 pipe_info = &ar_pci->pipe_info[pipe_num];
1347 ath10k_pci_rx_pipe_cleanup(pipe_info);
1348 ath10k_pci_tx_pipe_cleanup(pipe_info);
1352 static void ath10k_pci_ce_deinit(struct ath10k *ar)
1354 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1355 struct ath10k_pci_pipe *pipe_info;
1358 for (pipe_num = 0; pipe_num < ar_pci->ce_count; pipe_num++) {
1359 pipe_info = &ar_pci->pipe_info[pipe_num];
1360 if (pipe_info->ce_hdl) {
1361 ath10k_ce_deinit(pipe_info->ce_hdl);
1362 pipe_info->ce_hdl = NULL;
1363 pipe_info->buf_sz = 0;
1368 static void ath10k_pci_disable_irqs(struct ath10k *ar)
1370 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1373 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
1374 disable_irq(ar_pci->pdev->irq + i);
1377 static void ath10k_pci_hif_stop(struct ath10k *ar)
1379 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1381 ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
1383 /* Irqs are never explicitly re-enabled. They are implicitly re-enabled
1384 * by ath10k_pci_start_intr(). */
1385 ath10k_pci_disable_irqs(ar);
1387 ath10k_pci_stop_ce(ar);
1389 /* At this point, asynchronous threads are stopped, the target should
1390 * not DMA nor interrupt. We process the leftovers and then free
1391 * everything else up. */
1393 ath10k_pci_process_ce(ar);
1394 ath10k_pci_cleanup_ce(ar);
1395 ath10k_pci_buffer_cleanup(ar);
1397 ar_pci->started = 0;
1400 static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
1401 void *req, u32 req_len,
1402 void *resp, u32 *resp_len)
1404 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1405 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1406 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1407 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
1408 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
1409 dma_addr_t req_paddr = 0;
1410 dma_addr_t resp_paddr = 0;
1411 struct bmi_xfer xfer = {};
1412 void *treq, *tresp = NULL;
1415 if (resp && !resp_len)
1418 if (resp && resp_len && *resp_len == 0)
1421 treq = kmemdup(req, req_len, GFP_KERNEL);
1425 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
1426 ret = dma_mapping_error(ar->dev, req_paddr);
1430 if (resp && resp_len) {
1431 tresp = kzalloc(*resp_len, GFP_KERNEL);
1437 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
1439 ret = dma_mapping_error(ar->dev, resp_paddr);
1443 xfer.wait_for_resp = true;
1446 ath10k_ce_recv_buf_enqueue(ce_rx, &xfer, resp_paddr);
1449 init_completion(&xfer.done);
1451 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
1455 ret = wait_for_completion_timeout(&xfer.done,
1456 BMI_COMMUNICATION_TIMEOUT_HZ);
1459 unsigned int unused_nbytes;
1460 unsigned int unused_id;
1463 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
1464 &unused_nbytes, &unused_id);
1466 /* non-zero means we did not time out */
1474 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
1475 dma_unmap_single(ar->dev, resp_paddr,
1476 *resp_len, DMA_FROM_DEVICE);
1479 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
1481 if (ret == 0 && resp_len) {
1482 *resp_len = min(*resp_len, xfer.resp_len);
1483 memcpy(resp, tresp, xfer.resp_len);
1492 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state,
1493 void *transfer_context,
1495 unsigned int nbytes,
1496 unsigned int transfer_id)
1498 struct bmi_xfer *xfer = transfer_context;
1500 if (xfer->wait_for_resp)
1503 complete(&xfer->done);
1506 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state,
1507 void *transfer_context,
1509 unsigned int nbytes,
1510 unsigned int transfer_id,
1513 struct bmi_xfer *xfer = transfer_context;
1515 if (!xfer->wait_for_resp) {
1516 ath10k_warn("unexpected: BMI data received; ignoring\n");
1520 xfer->resp_len = nbytes;
1521 complete(&xfer->done);
1525 * Map from service/endpoint to Copy Engine.
1526 * This table is derived from the CE_PCI TABLE, above.
1527 * It is passed to the Target at startup for use by firmware.
1529 static const struct service_to_pipe target_service_to_ce_map_wlan[] = {
1531 ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1532 PIPEDIR_OUT, /* out = UL = host -> target */
1536 ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1537 PIPEDIR_IN, /* in = DL = target -> host */
1541 ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1542 PIPEDIR_OUT, /* out = UL = host -> target */
1546 ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1547 PIPEDIR_IN, /* in = DL = target -> host */
1551 ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1552 PIPEDIR_OUT, /* out = UL = host -> target */
1556 ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1557 PIPEDIR_IN, /* in = DL = target -> host */
1561 ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1562 PIPEDIR_OUT, /* out = UL = host -> target */
1566 ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1567 PIPEDIR_IN, /* in = DL = target -> host */
1571 ATH10K_HTC_SVC_ID_WMI_CONTROL,
1572 PIPEDIR_OUT, /* out = UL = host -> target */
1576 ATH10K_HTC_SVC_ID_WMI_CONTROL,
1577 PIPEDIR_IN, /* in = DL = target -> host */
1581 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1582 PIPEDIR_OUT, /* out = UL = host -> target */
1583 0, /* could be moved to 3 (share with WMI) */
1586 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1587 PIPEDIR_IN, /* in = DL = target -> host */
1591 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS, /* not currently used */
1592 PIPEDIR_OUT, /* out = UL = host -> target */
1596 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS, /* not currently used */
1597 PIPEDIR_IN, /* in = DL = target -> host */
1601 ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1602 PIPEDIR_OUT, /* out = UL = host -> target */
1606 ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1607 PIPEDIR_IN, /* in = DL = target -> host */
1611 /* (Additions here) */
1613 { /* Must be last */
1621 * Send an interrupt to the device to wake up the Target CPU
1622 * so it has an opportunity to notice any changed state.
1624 static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
1629 ret = ath10k_pci_diag_read_access(ar, SOC_CORE_BASE_ADDRESS |
1633 ath10k_warn("Unable to read core ctrl\n");
1637 /* A_INUM_FIRMWARE interrupt to Target CPU */
1638 core_ctrl |= CORE_CTRL_CPU_INTR_MASK;
1640 ret = ath10k_pci_diag_write_access(ar, SOC_CORE_BASE_ADDRESS |
1644 ath10k_warn("Unable to set interrupt mask\n");
1649 static int ath10k_pci_init_config(struct ath10k *ar)
1651 u32 interconnect_targ_addr;
1652 u32 pcie_state_targ_addr = 0;
1653 u32 pipe_cfg_targ_addr = 0;
1654 u32 svc_to_pipe_map = 0;
1655 u32 pcie_config_flags = 0;
1657 u32 ealloc_targ_addr;
1659 u32 flag2_targ_addr;
1662 /* Download to Target the CE Config and the service-to-CE map */
1663 interconnect_targ_addr =
1664 host_interest_item_address(HI_ITEM(hi_interconnect_state));
1666 /* Supply Target-side CE configuration */
1667 ret = ath10k_pci_diag_read_access(ar, interconnect_targ_addr,
1668 &pcie_state_targ_addr);
1670 ath10k_err("Failed to get pcie state addr: %d\n", ret);
1674 if (pcie_state_targ_addr == 0) {
1676 ath10k_err("Invalid pcie state addr\n");
1680 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1681 offsetof(struct pcie_state,
1683 &pipe_cfg_targ_addr);
1685 ath10k_err("Failed to get pipe cfg addr: %d\n", ret);
1689 if (pipe_cfg_targ_addr == 0) {
1691 ath10k_err("Invalid pipe cfg addr\n");
1695 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
1696 target_ce_config_wlan,
1697 sizeof(target_ce_config_wlan));
1700 ath10k_err("Failed to write pipe cfg: %d\n", ret);
1704 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1705 offsetof(struct pcie_state,
1709 ath10k_err("Failed to get svc/pipe map: %d\n", ret);
1713 if (svc_to_pipe_map == 0) {
1715 ath10k_err("Invalid svc_to_pipe map\n");
1719 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
1720 target_service_to_ce_map_wlan,
1721 sizeof(target_service_to_ce_map_wlan));
1723 ath10k_err("Failed to write svc/pipe map: %d\n", ret);
1727 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1728 offsetof(struct pcie_state,
1730 &pcie_config_flags);
1732 ath10k_err("Failed to get pcie config_flags: %d\n", ret);
1736 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
1738 ret = ath10k_pci_diag_write_mem(ar, pcie_state_targ_addr +
1739 offsetof(struct pcie_state, config_flags),
1741 sizeof(pcie_config_flags));
1743 ath10k_err("Failed to write pcie config_flags: %d\n", ret);
1747 /* configure early allocation */
1748 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
1750 ret = ath10k_pci_diag_read_access(ar, ealloc_targ_addr, &ealloc_value);
1752 ath10k_err("Faile to get early alloc val: %d\n", ret);
1756 /* first bank is switched to IRAM */
1757 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
1758 HI_EARLY_ALLOC_MAGIC_MASK);
1759 ealloc_value |= ((1 << HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
1760 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
1762 ret = ath10k_pci_diag_write_access(ar, ealloc_targ_addr, ealloc_value);
1764 ath10k_err("Failed to set early alloc val: %d\n", ret);
1768 /* Tell Target to proceed with initialization */
1769 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
1771 ret = ath10k_pci_diag_read_access(ar, flag2_targ_addr, &flag2_value);
1773 ath10k_err("Failed to get option val: %d\n", ret);
1777 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
1779 ret = ath10k_pci_diag_write_access(ar, flag2_targ_addr, flag2_value);
1781 ath10k_err("Failed to set option val: %d\n", ret);
1790 static int ath10k_pci_ce_init(struct ath10k *ar)
1792 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1793 struct ath10k_pci_pipe *pipe_info;
1794 const struct ce_attr *attr;
1797 for (pipe_num = 0; pipe_num < ar_pci->ce_count; pipe_num++) {
1798 pipe_info = &ar_pci->pipe_info[pipe_num];
1799 pipe_info->pipe_num = pipe_num;
1800 pipe_info->hif_ce_state = ar;
1801 attr = &host_ce_config_wlan[pipe_num];
1803 pipe_info->ce_hdl = ath10k_ce_init(ar, pipe_num, attr);
1804 if (pipe_info->ce_hdl == NULL) {
1805 ath10k_err("Unable to initialize CE for pipe: %d\n",
1808 /* It is safe to call it here. It checks if ce_hdl is
1809 * valid for each pipe */
1810 ath10k_pci_ce_deinit(ar);
1814 if (pipe_num == ar_pci->ce_count - 1) {
1816 * Reserve the ultimate CE for
1817 * diagnostic Window support
1820 ar_pci->pipe_info[ar_pci->ce_count - 1].ce_hdl;
1824 pipe_info->buf_sz = (size_t) (attr->src_sz_max);
1828 * Initially, establish CE completion handlers for use with BMI.
1829 * These are overwritten with generic handlers after we exit BMI phase.
1831 pipe_info = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1832 ath10k_ce_send_cb_register(pipe_info->ce_hdl,
1833 ath10k_pci_bmi_send_done, 0);
1835 pipe_info = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1836 ath10k_ce_recv_cb_register(pipe_info->ce_hdl,
1837 ath10k_pci_bmi_recv_data);
1842 static void ath10k_pci_fw_interrupt_handler(struct ath10k *ar)
1844 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1845 u32 fw_indicator_address, fw_indicator;
1847 ath10k_pci_wake(ar);
1849 fw_indicator_address = ar_pci->fw_indicator_address;
1850 fw_indicator = ath10k_pci_read32(ar, fw_indicator_address);
1852 if (fw_indicator & FW_IND_EVENT_PENDING) {
1853 /* ACK: clear Target-side pending event */
1854 ath10k_pci_write32(ar, fw_indicator_address,
1855 fw_indicator & ~FW_IND_EVENT_PENDING);
1857 if (ar_pci->started) {
1858 ath10k_pci_hif_dump_area(ar);
1861 * Probable Target failure before we're prepared
1862 * to handle it. Generally unexpected.
1864 ath10k_warn("early firmware event indicated\n");
1868 ath10k_pci_sleep(ar);
1871 static int ath10k_pci_hif_power_up(struct ath10k *ar)
1873 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1876 ret = ath10k_pci_start_intr(ar);
1878 ath10k_err("could not start interrupt handling (%d)\n", ret);
1883 * Bring the target up cleanly.
1885 * The target may be in an undefined state with an AUX-powered Target
1886 * and a Host in WoW mode. If the Host crashes, loses power, or is
1887 * restarted (without unloading the driver) then the Target is left
1888 * (aux) powered and running. On a subsequent driver load, the Target
1889 * is in an unexpected state. We try to catch that here in order to
1890 * reset the Target and retry the probe.
1892 ath10k_pci_device_reset(ar);
1894 ret = ath10k_pci_reset_target(ar);
1898 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
1899 /* Force AWAKE forever */
1900 ath10k_do_pci_wake(ar);
1902 ret = ath10k_pci_ce_init(ar);
1906 ret = ath10k_pci_init_config(ar);
1910 ret = ath10k_pci_wake_target_cpu(ar);
1912 ath10k_err("could not wake up target CPU (%d)\n", ret);
1919 ath10k_pci_ce_deinit(ar);
1921 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
1922 ath10k_do_pci_sleep(ar);
1924 ath10k_pci_stop_intr(ar);
1929 static void ath10k_pci_hif_power_down(struct ath10k *ar)
1931 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1933 ath10k_pci_stop_intr(ar);
1935 ath10k_pci_ce_deinit(ar);
1936 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
1937 ath10k_do_pci_sleep(ar);
1942 #define ATH10K_PCI_PM_CONTROL 0x44
1944 static int ath10k_pci_hif_suspend(struct ath10k *ar)
1946 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1947 struct pci_dev *pdev = ar_pci->pdev;
1950 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
1952 if ((val & 0x000000ff) != 0x3) {
1953 pci_save_state(pdev);
1954 pci_disable_device(pdev);
1955 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
1956 (val & 0xffffff00) | 0x03);
1962 static int ath10k_pci_hif_resume(struct ath10k *ar)
1964 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1965 struct pci_dev *pdev = ar_pci->pdev;
1968 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
1970 if ((val & 0x000000ff) != 0) {
1971 pci_restore_state(pdev);
1972 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
1975 * Suspend/Resume resets the PCI configuration space,
1976 * so we have to re-disable the RETRY_TIMEOUT register (0x41)
1977 * to keep PCI Tx retries from interfering with C3 CPU state
1979 pci_read_config_dword(pdev, 0x40, &val);
1981 if ((val & 0x0000ff00) != 0)
1982 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
1989 static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
1990 .send_head = ath10k_pci_hif_send_head,
1991 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
1992 .start = ath10k_pci_hif_start,
1993 .stop = ath10k_pci_hif_stop,
1994 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
1995 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
1996 .send_complete_check = ath10k_pci_hif_send_complete_check,
1997 .set_callbacks = ath10k_pci_hif_set_callbacks,
1998 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
1999 .power_up = ath10k_pci_hif_power_up,
2000 .power_down = ath10k_pci_hif_power_down,
2002 .suspend = ath10k_pci_hif_suspend,
2003 .resume = ath10k_pci_hif_resume,
2007 static void ath10k_pci_ce_tasklet(unsigned long ptr)
2009 struct ath10k_pci_pipe *pipe = (struct ath10k_pci_pipe *)ptr;
2010 struct ath10k_pci *ar_pci = pipe->ar_pci;
2012 ath10k_ce_per_engine_service(ar_pci->ar, pipe->pipe_num);
2015 static void ath10k_msi_err_tasklet(unsigned long data)
2017 struct ath10k *ar = (struct ath10k *)data;
2019 ath10k_pci_fw_interrupt_handler(ar);
2023 * Handler for a per-engine interrupt on a PARTICULAR CE.
2024 * This is used in cases where each CE has a private MSI interrupt.
2026 static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg)
2028 struct ath10k *ar = arg;
2029 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2030 int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL;
2032 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) {
2033 ath10k_warn("unexpected/invalid irq %d ce_id %d\n", irq, ce_id);
2038 * NOTE: We are able to derive ce_id from irq because we
2039 * use a one-to-one mapping for CE's 0..5.
2040 * CE's 6 & 7 do not use interrupts at all.
2042 * This mapping must be kept in sync with the mapping
2045 tasklet_schedule(&ar_pci->pipe_info[ce_id].intr);
2049 static irqreturn_t ath10k_pci_msi_fw_handler(int irq, void *arg)
2051 struct ath10k *ar = arg;
2052 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2054 tasklet_schedule(&ar_pci->msi_fw_err);
2059 * Top-level interrupt handler for all PCI interrupts from a Target.
2060 * When a block of MSI interrupts is allocated, this top-level handler
2061 * is not used; instead, we directly call the correct sub-handler.
2063 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
2065 struct ath10k *ar = arg;
2066 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2068 if (ar_pci->num_msi_intrs == 0) {
2070 * IMPORTANT: INTR_CLR regiser has to be set after
2071 * INTR_ENABLE is set to 0, otherwise interrupt can not be
2074 iowrite32(0, ar_pci->mem +
2075 (SOC_CORE_BASE_ADDRESS |
2076 PCIE_INTR_ENABLE_ADDRESS));
2077 iowrite32(PCIE_INTR_FIRMWARE_MASK |
2078 PCIE_INTR_CE_MASK_ALL,
2079 ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2080 PCIE_INTR_CLR_ADDRESS));
2082 * IMPORTANT: this extra read transaction is required to
2083 * flush the posted write buffer.
2085 (void) ioread32(ar_pci->mem +
2086 (SOC_CORE_BASE_ADDRESS |
2087 PCIE_INTR_ENABLE_ADDRESS));
2090 tasklet_schedule(&ar_pci->intr_tq);
2095 static void ath10k_pci_tasklet(unsigned long data)
2097 struct ath10k *ar = (struct ath10k *)data;
2098 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2100 ath10k_pci_fw_interrupt_handler(ar); /* FIXME: Handle FW error */
2101 ath10k_ce_per_engine_service_any(ar);
2103 if (ar_pci->num_msi_intrs == 0) {
2104 /* Enable Legacy PCI line interrupts */
2105 iowrite32(PCIE_INTR_FIRMWARE_MASK |
2106 PCIE_INTR_CE_MASK_ALL,
2107 ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2108 PCIE_INTR_ENABLE_ADDRESS));
2110 * IMPORTANT: this extra read transaction is required to
2111 * flush the posted write buffer
2113 (void) ioread32(ar_pci->mem +
2114 (SOC_CORE_BASE_ADDRESS |
2115 PCIE_INTR_ENABLE_ADDRESS));
2119 static int ath10k_pci_start_intr_msix(struct ath10k *ar, int num)
2121 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2125 ret = pci_enable_msi_block(ar_pci->pdev, num);
2129 ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW,
2130 ath10k_pci_msi_fw_handler,
2131 IRQF_SHARED, "ath10k_pci", ar);
2133 ath10k_warn("request_irq(%d) failed %d\n",
2134 ar_pci->pdev->irq + MSI_ASSIGN_FW, ret);
2136 pci_disable_msi(ar_pci->pdev);
2140 for (i = MSI_ASSIGN_CE_INITIAL; i <= MSI_ASSIGN_CE_MAX; i++) {
2141 ret = request_irq(ar_pci->pdev->irq + i,
2142 ath10k_pci_per_engine_handler,
2143 IRQF_SHARED, "ath10k_pci", ar);
2145 ath10k_warn("request_irq(%d) failed %d\n",
2146 ar_pci->pdev->irq + i, ret);
2148 for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--)
2149 free_irq(ar_pci->pdev->irq + i, ar);
2151 free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar);
2152 pci_disable_msi(ar_pci->pdev);
2157 ath10k_info("MSI-X interrupt handling (%d intrs)\n", num);
2161 static int ath10k_pci_start_intr_msi(struct ath10k *ar)
2163 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2166 ret = pci_enable_msi(ar_pci->pdev);
2170 ret = request_irq(ar_pci->pdev->irq,
2171 ath10k_pci_interrupt_handler,
2172 IRQF_SHARED, "ath10k_pci", ar);
2174 pci_disable_msi(ar_pci->pdev);
2178 ath10k_info("MSI interrupt handling\n");
2182 static int ath10k_pci_start_intr_legacy(struct ath10k *ar)
2184 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2187 ret = request_irq(ar_pci->pdev->irq,
2188 ath10k_pci_interrupt_handler,
2189 IRQF_SHARED, "ath10k_pci", ar);
2194 * Make sure to wake the Target before enabling Legacy
2197 iowrite32(PCIE_SOC_WAKE_V_MASK,
2198 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
2199 PCIE_SOC_WAKE_ADDRESS);
2201 ath10k_pci_wait(ar);
2204 * A potential race occurs here: The CORE_BASE write
2205 * depends on target correctly decoding AXI address but
2206 * host won't know when target writes BAR to CORE_CTRL.
2207 * This write might get lost if target has NOT written BAR.
2208 * For now, fix the race by repeating the write in below
2209 * synchronization checking.
2211 iowrite32(PCIE_INTR_FIRMWARE_MASK |
2212 PCIE_INTR_CE_MASK_ALL,
2213 ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2214 PCIE_INTR_ENABLE_ADDRESS));
2215 iowrite32(PCIE_SOC_WAKE_RESET,
2216 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
2217 PCIE_SOC_WAKE_ADDRESS);
2219 ath10k_info("legacy interrupt handling\n");
2223 static int ath10k_pci_start_intr(struct ath10k *ar)
2225 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2226 int num = MSI_NUM_REQUEST;
2230 tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long) ar);
2231 tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
2232 (unsigned long) ar);
2234 for (i = 0; i < CE_COUNT; i++) {
2235 ar_pci->pipe_info[i].ar_pci = ar_pci;
2236 tasklet_init(&ar_pci->pipe_info[i].intr,
2237 ath10k_pci_ce_tasklet,
2238 (unsigned long)&ar_pci->pipe_info[i]);
2241 if (!test_bit(ATH10K_PCI_FEATURE_MSI_X, ar_pci->features))
2245 ret = ath10k_pci_start_intr_msix(ar, num);
2249 ath10k_warn("MSI-X didn't succeed (%d), trying MSI\n", ret);
2254 ret = ath10k_pci_start_intr_msi(ar);
2258 ath10k_warn("MSI didn't succeed (%d), trying legacy INTR\n",
2263 ret = ath10k_pci_start_intr_legacy(ar);
2266 ar_pci->num_msi_intrs = num;
2267 ar_pci->ce_count = CE_COUNT;
2271 static void ath10k_pci_stop_intr(struct ath10k *ar)
2273 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2276 /* There's at least one interrupt irregardless whether its legacy INTR
2277 * or MSI or MSI-X */
2278 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
2279 free_irq(ar_pci->pdev->irq + i, ar);
2281 if (ar_pci->num_msi_intrs > 0)
2282 pci_disable_msi(ar_pci->pdev);
2285 static int ath10k_pci_reset_target(struct ath10k *ar)
2287 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2288 int wait_limit = 300; /* 3 sec */
2290 /* Wait for Target to finish initialization before we proceed. */
2291 iowrite32(PCIE_SOC_WAKE_V_MASK,
2292 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
2293 PCIE_SOC_WAKE_ADDRESS);
2295 ath10k_pci_wait(ar);
2297 while (wait_limit-- &&
2298 !(ioread32(ar_pci->mem + FW_INDICATOR_ADDRESS) &
2299 FW_IND_INITIALIZED)) {
2300 if (ar_pci->num_msi_intrs == 0)
2301 /* Fix potential race by repeating CORE_BASE writes */
2302 iowrite32(PCIE_INTR_FIRMWARE_MASK |
2303 PCIE_INTR_CE_MASK_ALL,
2304 ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2305 PCIE_INTR_ENABLE_ADDRESS));
2309 if (wait_limit < 0) {
2310 ath10k_err("Target stalled\n");
2311 iowrite32(PCIE_SOC_WAKE_RESET,
2312 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
2313 PCIE_SOC_WAKE_ADDRESS);
2317 iowrite32(PCIE_SOC_WAKE_RESET,
2318 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
2319 PCIE_SOC_WAKE_ADDRESS);
2324 static void ath10k_pci_device_reset(struct ath10k *ar)
2326 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2327 void __iomem *mem = ar_pci->mem;
2331 if (!SOC_GLOBAL_RESET_ADDRESS)
2337 ath10k_pci_reg_write32(mem, PCIE_SOC_WAKE_ADDRESS,
2338 PCIE_SOC_WAKE_V_MASK);
2339 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2340 if (ath10k_pci_target_is_awake(ar))
2345 /* Put Target, including PCIe, into RESET. */
2346 val = ath10k_pci_reg_read32(mem, SOC_GLOBAL_RESET_ADDRESS);
2348 ath10k_pci_reg_write32(mem, SOC_GLOBAL_RESET_ADDRESS, val);
2350 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2351 if (ath10k_pci_reg_read32(mem, RTC_STATE_ADDRESS) &
2352 RTC_STATE_COLD_RESET_MASK)
2357 /* Pull Target, including PCIe, out of RESET. */
2359 ath10k_pci_reg_write32(mem, SOC_GLOBAL_RESET_ADDRESS, val);
2361 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2362 if (!(ath10k_pci_reg_read32(mem, RTC_STATE_ADDRESS) &
2363 RTC_STATE_COLD_RESET_MASK))
2368 ath10k_pci_reg_write32(mem, PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_RESET);
2371 static void ath10k_pci_dump_features(struct ath10k_pci *ar_pci)
2375 for (i = 0; i < ATH10K_PCI_FEATURE_COUNT; i++) {
2376 if (!test_bit(i, ar_pci->features))
2380 case ATH10K_PCI_FEATURE_MSI_X:
2381 ath10k_dbg(ATH10K_DBG_PCI, "device supports MSI-X\n");
2383 case ATH10K_PCI_FEATURE_SOC_POWER_SAVE:
2384 ath10k_dbg(ATH10K_DBG_PCI, "QCA98XX SoC power save enabled\n");
2390 static int ath10k_pci_probe(struct pci_dev *pdev,
2391 const struct pci_device_id *pci_dev)
2396 struct ath10k_pci *ar_pci;
2399 ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
2401 ar_pci = kzalloc(sizeof(*ar_pci), GFP_KERNEL);
2405 ar_pci->pdev = pdev;
2406 ar_pci->dev = &pdev->dev;
2408 switch (pci_dev->device) {
2409 case QCA988X_2_0_DEVICE_ID:
2410 set_bit(ATH10K_PCI_FEATURE_MSI_X, ar_pci->features);
2414 ath10k_err("Unkown device ID: %d\n", pci_dev->device);
2418 if (ath10k_target_ps)
2419 set_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features);
2421 ath10k_pci_dump_features(ar_pci);
2423 ar = ath10k_core_create(ar_pci, ar_pci->dev, &ath10k_pci_hif_ops);
2425 ath10k_err("ath10k_core_create failed!\n");
2431 ar_pci->fw_indicator_address = FW_INDICATOR_ADDRESS;
2432 atomic_set(&ar_pci->keep_awake_count, 0);
2434 pci_set_drvdata(pdev, ar);
2437 * Without any knowledge of the Host, the Target may have been reset or
2438 * power cycled and its Config Space may no longer reflect the PCI
2439 * address space that was assigned earlier by the PCI infrastructure.
2442 ret = pci_assign_resource(pdev, BAR_NUM);
2444 ath10k_err("cannot assign PCI space: %d\n", ret);
2448 ret = pci_enable_device(pdev);
2450 ath10k_err("cannot enable PCI device: %d\n", ret);
2454 /* Request MMIO resources */
2455 ret = pci_request_region(pdev, BAR_NUM, "ath");
2457 ath10k_err("PCI MMIO reservation error: %d\n", ret);
2462 * Target structures have a limit of 32 bit DMA pointers.
2463 * DMA pointers can be wider than 32 bits by default on some systems.
2465 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2467 ath10k_err("32-bit DMA not available: %d\n", ret);
2471 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2473 ath10k_err("cannot enable 32-bit consistent DMA\n");
2477 /* Set bus master bit in PCI_COMMAND to enable DMA */
2478 pci_set_master(pdev);
2481 * Temporary FIX: disable ASPM
2482 * Will be removed after the OTP is programmed
2484 pci_read_config_dword(pdev, 0x80, &lcr_val);
2485 pci_write_config_dword(pdev, 0x80, (lcr_val & 0xffffff00));
2487 /* Arrange for access to Target SoC registers. */
2488 mem = pci_iomap(pdev, BAR_NUM, 0);
2490 ath10k_err("PCI iomap error\n");
2497 spin_lock_init(&ar_pci->ce_lock);
2499 ret = ath10k_core_register(ar);
2501 ath10k_err("could not register driver core (%d)\n", ret);
2508 pci_iounmap(pdev, mem);
2510 pci_clear_master(pdev);
2512 pci_release_region(pdev, BAR_NUM);
2514 pci_disable_device(pdev);
2516 pci_set_drvdata(pdev, NULL);
2517 ath10k_core_destroy(ar);
2519 /* call HIF PCI free here */
2525 static void ath10k_pci_remove(struct pci_dev *pdev)
2527 struct ath10k *ar = pci_get_drvdata(pdev);
2528 struct ath10k_pci *ar_pci;
2530 ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
2535 ar_pci = ath10k_pci_priv(ar);
2540 tasklet_kill(&ar_pci->msi_fw_err);
2542 ath10k_core_unregister(ar);
2544 pci_set_drvdata(pdev, NULL);
2545 pci_iounmap(pdev, ar_pci->mem);
2546 pci_release_region(pdev, BAR_NUM);
2547 pci_clear_master(pdev);
2548 pci_disable_device(pdev);
2550 ath10k_core_destroy(ar);
2554 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
2556 static struct pci_driver ath10k_pci_driver = {
2557 .name = "ath10k_pci",
2558 .id_table = ath10k_pci_id_table,
2559 .probe = ath10k_pci_probe,
2560 .remove = ath10k_pci_remove,
2563 static int __init ath10k_pci_init(void)
2567 ret = pci_register_driver(&ath10k_pci_driver);
2569 ath10k_err("pci_register_driver failed [%d]\n", ret);
2573 module_init(ath10k_pci_init);
2575 static void __exit ath10k_pci_exit(void)
2577 pci_unregister_driver(&ath10k_pci_driver);
2580 module_exit(ath10k_pci_exit);
2582 MODULE_AUTHOR("Qualcomm Atheros");
2583 MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
2584 MODULE_LICENSE("Dual BSD/GPL");
2585 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_FILE);
2586 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_OTP_FILE);
2587 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);