drivers/net/wireless/ath/ath10k/pci.c

   1 /*
   2  * Copyright (c) 2005-2011 Atheros Communications Inc.
   3  * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  */
  17
  18 #include <linux/pci.h>
  19 #include <linux/module.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/spinlock.h>
  22
  23 #include "core.h"
  24 #include "debug.h"
  25
  26 #include "targaddrs.h"
  27 #include "bmi.h"
  28
  29 #include "hif.h"
  30 #include "htc.h"
  31
  32 #include "ce.h"
  33 #include "pci.h"
  34
  35 static unsigned int ath10k_target_ps;
  36 module_param(ath10k_target_ps, uint, 0644);
  37 MODULE_PARM_DESC(ath10k_target_ps, "Enable ath10k Target (SoC) PS option");
  38
  39 #define QCA988X_2_0_DEVICE_ID   (0x003c)
  40
  41 static DEFINE_PCI_DEVICE_TABLE(ath10k_pci_id_table) = {
  42         { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
  43         {0}
  44 };
  45
  46 static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
  47                                        u32 *data);
  48
  49 static void ath10k_pci_process_ce(struct ath10k *ar);
  50 static int ath10k_pci_post_rx(struct ath10k *ar);
  51 static int ath10k_pci_post_rx_pipe(struct hif_ce_pipe_info *pipe_info,
  52                                              int num);
  53 static void ath10k_pci_rx_pipe_cleanup(struct hif_ce_pipe_info *pipe_info);
  54 static void ath10k_pci_stop_ce(struct ath10k *ar);
  55 static void ath10k_pci_device_reset(struct ath10k *ar);
  56 static int ath10k_pci_reset_target(struct ath10k *ar);
  57 static int ath10k_pci_start_intr(struct ath10k *ar);
  58 static void ath10k_pci_stop_intr(struct ath10k *ar);
  59
  60 static const struct ce_attr host_ce_config_wlan[] = {
  61         /* host->target HTC control and raw streams */
  62         { /* CE0 */ CE_ATTR_FLAGS, 0, 16, 256, 0, NULL,},
  63         /* could be moved to share CE3 */
  64         /* target->host HTT + HTC control */
  65         { /* CE1 */ CE_ATTR_FLAGS, 0, 0, 512, 512, NULL,},
  66         /* target->host WMI */
  67         { /* CE2 */ CE_ATTR_FLAGS, 0, 0, 2048, 32, NULL,},
  68         /* host->target WMI */
  69         { /* CE3 */ CE_ATTR_FLAGS, 0, 32, 2048, 0, NULL,},
  70         /* host->target HTT */
  71         { /* CE4 */ CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 0,
  72                     CE_HTT_H2T_MSG_SRC_NENTRIES, 256, 0, NULL,},
  73         /* unused */
  74         { /* CE5 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
  75         /* Target autonomous hif_memcpy */
  76         { /* CE6 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
  77         /* ce_diag, the Diagnostic Window */
  78         { /* CE7 */ CE_ATTR_FLAGS, 0, 2, DIAG_TRANSFER_LIMIT, 2, NULL,},
  79 };
  80
  81 /* Target firmware's Copy Engine configuration. */
  82 static const struct ce_pipe_config target_ce_config_wlan[] = {
  83         /* host->target HTC control and raw streams */
  84         { /* CE0 */ 0, PIPEDIR_OUT, 32, 256, CE_ATTR_FLAGS, 0,},
  85         /* target->host HTT + HTC control */
  86         { /* CE1 */ 1, PIPEDIR_IN, 32, 512, CE_ATTR_FLAGS, 0,},
  87         /* target->host WMI */
  88         { /* CE2 */ 2, PIPEDIR_IN, 32, 2048, CE_ATTR_FLAGS, 0,},
  89         /* host->target WMI */
  90         { /* CE3 */ 3, PIPEDIR_OUT, 32, 2048, CE_ATTR_FLAGS, 0,},
  91         /* host->target HTT */
  92         { /* CE4 */ 4, PIPEDIR_OUT, 256, 256, CE_ATTR_FLAGS, 0,},
  93         /* NB: 50% of src nentries, since tx has 2 frags */
  94         /* unused */
  95         { /* CE5 */ 5, PIPEDIR_OUT, 32, 2048, CE_ATTR_FLAGS, 0,},
  96         /* Reserved for target autonomous hif_memcpy */
  97         { /* CE6 */ 6, PIPEDIR_INOUT, 32, 4096, CE_ATTR_FLAGS, 0,},
  98         /* CE7 used only by Host */
  99 };
 100
 101 /*
 102  * Diagnostic read/write access is provided for startup/config/debug usage.
 103  * Caller must guarantee proper alignment, when applicable, and single user
 104  * at any moment.
 105  */
 106 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
 107                                     int nbytes)
 108 {
 109         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 110         int ret = 0;
 111         u32 buf;
 112         unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
 113         unsigned int id;
 114         unsigned int flags;
 115         struct ce_state *ce_diag;
 116         /* Host buffer address in CE space */
 117         u32 ce_data;
 118         dma_addr_t ce_data_base = 0;
 119         void *data_buf = NULL;
 120         int i;
 121
 122         /*
 123          * This code cannot handle reads to non-memory space. Redirect to the
 124          * register read fn but preserve the multi word read capability of
 125          * this fn
 126          */
 127         if (address < DRAM_BASE_ADDRESS) {
 128                 if (!IS_ALIGNED(address, 4) ||
 129                     !IS_ALIGNED((unsigned long)data, 4))
 130                         return -EIO;
 131
 132                 while ((nbytes >= 4) &&  ((ret = ath10k_pci_diag_read_access(
 133                                            ar, address, (u32 *)data)) == 0)) {
 134                         nbytes -= sizeof(u32);
 135                         address += sizeof(u32);
 136                         data += sizeof(u32);
 137                 }
 138                 return ret;
 139         }
 140
 141         ce_diag = ar_pci->ce_diag;
 142
 143         /*
 144          * Allocate a temporary bounce buffer to hold caller's data
 145          * to be DMA'ed from Target. This guarantees
 146          *   1) 4-byte alignment
 147          *   2) Buffer in DMA-able space
 148          */
 149         orig_nbytes = nbytes;
 150         data_buf = (unsigned char *)pci_alloc_consistent(ar_pci->pdev,
 151                                                          orig_nbytes,
 152                                                          &ce_data_base);
 153
 154         if (!data_buf) {
 155                 ret = -ENOMEM;
 156                 goto done;
 157         }
 158         memset(data_buf, 0, orig_nbytes);
 159
 160         remaining_bytes = orig_nbytes;
 161         ce_data = ce_data_base;
 162         while (remaining_bytes) {
 163                 nbytes = min_t(unsigned int, remaining_bytes,
 164                                DIAG_TRANSFER_LIMIT);
 165
 166                 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, ce_data);
 167                 if (ret != 0)
 168                         goto done;
 169
 170                 /* Request CE to send from Target(!) address to Host buffer */
 171                 /*
 172                  * The address supplied by the caller is in the
 173                  * Target CPU virtual address space.
 174                  *
 175                  * In order to use this address with the diagnostic CE,
 176                  * convert it from Target CPU virtual address space
 177                  * to CE address space
 178                  */
 179                 ath10k_pci_wake(ar);
 180                 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem,
 181                                                      address);
 182                 ath10k_pci_sleep(ar);
 183
 184                 ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0,
 185                                  0);
 186                 if (ret)
 187                         goto done;
 188
 189                 i = 0;
 190                 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
 191                                                      &completed_nbytes,
 192                                                      &id) != 0) {
 193                         mdelay(1);
 194                         if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
 195                                 ret = -EBUSY;
 196                                 goto done;
 197                         }
 198                 }
 199
 200                 if (nbytes != completed_nbytes) {
 201                         ret = -EIO;
 202                         goto done;
 203                 }
 204
 205                 if (buf != (u32) address) {
 206                         ret = -EIO;
 207                         goto done;
 208                 }
 209
 210                 i = 0;
 211                 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
 212                                                      &completed_nbytes,
 213                                                      &id, &flags) != 0) {
 214                         mdelay(1);
 215
 216                         if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
 217                                 ret = -EBUSY;
 218                                 goto done;
 219                         }
 220                 }
 221
 222                 if (nbytes != completed_nbytes) {
 223                         ret = -EIO;
 224                         goto done;
 225                 }
 226
 227                 if (buf != ce_data) {
 228                         ret = -EIO;
 229                         goto done;
 230                 }
 231
 232                 remaining_bytes -= nbytes;
 233                 address += nbytes;
 234                 ce_data += nbytes;
 235         }
 236
 237 done:
 238         if (ret == 0) {
 239                 /* Copy data from allocated DMA buf to caller's buf */
 240                 WARN_ON_ONCE(orig_nbytes & 3);
 241                 for (i = 0; i < orig_nbytes / sizeof(__le32); i++) {
 242                         ((u32 *)data)[i] =
 243                                 __le32_to_cpu(((__le32 *)data_buf)[i]);
 244                 }
 245         } else
 246                 ath10k_dbg(ATH10K_DBG_PCI, "%s failure (0x%x)\n",
 247                            __func__, address);
 248
 249         if (data_buf)
 250                 pci_free_consistent(ar_pci->pdev, orig_nbytes,
 251                                     data_buf, ce_data_base);
 252
 253         return ret;
 254 }
 255
 256 /* Read 4-byte aligned data from Target memory or register */
 257 static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
 258                                        u32 *data)
 259 {
 260         /* Assume range doesn't cross this boundary */
 261         if (address >= DRAM_BASE_ADDRESS)
 262                 return ath10k_pci_diag_read_mem(ar, address, data, sizeof(u32));
 263
 264         ath10k_pci_wake(ar);
 265         *data = ath10k_pci_read32(ar, address);
 266         ath10k_pci_sleep(ar);
 267         return 0;
 268 }
 269
 270 static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
 271                                      const void *data, int nbytes)
 272 {
 273         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 274         int ret = 0;
 275         u32 buf;
 276         unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
 277         unsigned int id;
 278         unsigned int flags;
 279         struct ce_state *ce_diag;
 280         void *data_buf = NULL;
 281         u32 ce_data;    /* Host buffer address in CE space */
 282         dma_addr_t ce_data_base = 0;
 283         int i;
 284
 285         ce_diag = ar_pci->ce_diag;
 286
 287         /*
 288          * Allocate a temporary bounce buffer to hold caller's data
 289          * to be DMA'ed to Target. This guarantees
 290          *   1) 4-byte alignment
 291          *   2) Buffer in DMA-able space
 292          */
 293         orig_nbytes = nbytes;
 294         data_buf = (unsigned char *)pci_alloc_consistent(ar_pci->pdev,
 295                                                          orig_nbytes,
 296                                                          &ce_data_base);
 297         if (!data_buf) {
 298                 ret = -ENOMEM;
 299                 goto done;
 300         }
 301
 302         /* Copy caller's data to allocated DMA buf */
 303         WARN_ON_ONCE(orig_nbytes & 3);
 304         for (i = 0; i < orig_nbytes / sizeof(__le32); i++)
 305                 ((__le32 *)data_buf)[i] = __cpu_to_le32(((u32 *)data)[i]);
 306
 307         /*
 308          * The address supplied by the caller is in the
 309          * Target CPU virtual address space.
 310          *
 311          * In order to use this address with the diagnostic CE,
 312          * convert it from
 313          *    Target CPU virtual address space
 314          * to
 315          *    CE address space
 316          */
 317         ath10k_pci_wake(ar);
 318         address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, address);
 319         ath10k_pci_sleep(ar);
 320
 321         remaining_bytes = orig_nbytes;
 322         ce_data = ce_data_base;
 323         while (remaining_bytes) {
 324                 /* FIXME: check cast */
 325                 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
 326
 327                 /* Set up to receive directly into Target(!) address */
 328                 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, address);
 329                 if (ret != 0)
 330                         goto done;
 331
 332                 /*
 333                  * Request CE to send caller-supplied data that
 334                  * was copied to bounce buffer to Target(!) address.
 335                  */
 336                 ret = ath10k_ce_send(ce_diag, NULL, (u32) ce_data,
 337                                      nbytes, 0, 0);
 338                 if (ret != 0)
 339                         goto done;
 340
 341                 i = 0;
 342                 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
 343                                                      &completed_nbytes,
 344                                                      &id) != 0) {
 345                         mdelay(1);
 346
 347                         if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
 348                                 ret = -EBUSY;
 349                                 goto done;
 350                         }
 351                 }
 352
 353                 if (nbytes != completed_nbytes) {
 354                         ret = -EIO;
 355                         goto done;
 356                 }
 357
 358                 if (buf != ce_data) {
 359                         ret = -EIO;
 360                         goto done;
 361                 }
 362
 363                 i = 0;
 364                 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
 365                                                      &completed_nbytes,
 366                                                      &id, &flags) != 0) {
 367                         mdelay(1);
 368
 369                         if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
 370                                 ret = -EBUSY;
 371                                 goto done;
 372                         }
 373                 }
 374
 375                 if (nbytes != completed_nbytes) {
 376                         ret = -EIO;
 377                         goto done;
 378                 }
 379
 380                 if (buf != address) {
 381                         ret = -EIO;
 382                         goto done;
 383                 }
 384
 385                 remaining_bytes -= nbytes;
 386                 address += nbytes;
 387                 ce_data += nbytes;
 388         }
 389
 390 done:
 391         if (data_buf) {
 392                 pci_free_consistent(ar_pci->pdev, orig_nbytes, data_buf,
 393                                     ce_data_base);
 394         }
 395
 396         if (ret != 0)
 397                 ath10k_dbg(ATH10K_DBG_PCI, "%s failure (0x%x)\n", __func__,
 398                            address);
 399
 400         return ret;
 401 }
 402
 403 /* Write 4B data to Target memory or register */
 404 static int ath10k_pci_diag_write_access(struct ath10k *ar, u32 address,
 405                                         u32 data)
 406 {
 407         /* Assume range doesn't cross this boundary */
 408         if (address >= DRAM_BASE_ADDRESS)
 409                 return ath10k_pci_diag_write_mem(ar, address, &data,
 410                                                  sizeof(u32));
 411
 412         ath10k_pci_wake(ar);
 413         ath10k_pci_write32(ar, address, data);
 414         ath10k_pci_sleep(ar);
 415         return 0;
 416 }
 417
 418 static bool ath10k_pci_target_is_awake(struct ath10k *ar)
 419 {
 420         void __iomem *mem = ath10k_pci_priv(ar)->mem;
 421         u32 val;
 422         val = ioread32(mem + PCIE_LOCAL_BASE_ADDRESS +
 423                        RTC_STATE_ADDRESS);
 424         return (RTC_STATE_V_GET(val) == RTC_STATE_V_ON);
 425 }
 426
 427 static void ath10k_pci_wait(struct ath10k *ar)
 428 {
 429         int n = 100;
 430
 431         while (n-- && !ath10k_pci_target_is_awake(ar))
 432                 msleep(10);
 433
 434         if (n < 0)
 435                 ath10k_warn("Unable to wakeup target\n");
 436 }
 437
 438 void ath10k_do_pci_wake(struct ath10k *ar)
 439 {
 440         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 441         void __iomem *pci_addr = ar_pci->mem;
 442         int tot_delay = 0;
 443         int curr_delay = 5;
 444
 445         if (atomic_read(&ar_pci->keep_awake_count) == 0) {
 446                 /* Force AWAKE */
 447                 iowrite32(PCIE_SOC_WAKE_V_MASK,
 448                           pci_addr + PCIE_LOCAL_BASE_ADDRESS +
 449                           PCIE_SOC_WAKE_ADDRESS);
 450         }
 451         atomic_inc(&ar_pci->keep_awake_count);
 452
 453         if (ar_pci->verified_awake)
 454                 return;
 455
 456         for (;;) {
 457                 if (ath10k_pci_target_is_awake(ar)) {
 458                         ar_pci->verified_awake = true;
 459                         break;
 460                 }
 461
 462                 if (tot_delay > PCIE_WAKE_TIMEOUT) {
 463                         ath10k_warn("target takes too long to wake up (awake count %d)\n",
 464                                     atomic_read(&ar_pci->keep_awake_count));
 465                         break;
 466                 }
 467
 468                 udelay(curr_delay);
 469                 tot_delay += curr_delay;
 470
 471                 if (curr_delay < 50)
 472                         curr_delay += 5;
 473         }
 474 }
 475
 476 void ath10k_do_pci_sleep(struct ath10k *ar)
 477 {
 478         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 479         void __iomem *pci_addr = ar_pci->mem;
 480
 481         if (atomic_dec_and_test(&ar_pci->keep_awake_count)) {
 482                 /* Allow sleep */
 483                 ar_pci->verified_awake = false;
 484                 iowrite32(PCIE_SOC_WAKE_RESET,
 485                           pci_addr + PCIE_LOCAL_BASE_ADDRESS +
 486                           PCIE_SOC_WAKE_ADDRESS);
 487         }
 488 }
 489
 490 /*
 491  * FIXME: Handle OOM properly.
 492  */
 493 static inline
 494 struct ath10k_pci_compl *get_free_compl(struct hif_ce_pipe_info *pipe_info)
 495 {
 496         struct ath10k_pci_compl *compl = NULL;
 497
 498         spin_lock_bh(&pipe_info->pipe_lock);
 499         if (list_empty(&pipe_info->compl_free)) {
 500                 ath10k_warn("Completion buffers are full\n");
 501                 goto exit;
 502         }
 503         compl = list_first_entry(&pipe_info->compl_free,
 504                                  struct ath10k_pci_compl, list);
 505         list_del(&compl->list);
 506 exit:
 507         spin_unlock_bh(&pipe_info->pipe_lock);
 508         return compl;
 509 }
 510
 511 /* Called by lower (CE) layer when a send to Target completes. */
 512 static void ath10k_pci_ce_send_done(struct ce_state *ce_state,
 513                                     void *transfer_context,
 514                                     u32 ce_data,
 515                                     unsigned int nbytes,
 516                                     unsigned int transfer_id)
 517 {
 518         struct ath10k *ar = ce_state->ar;
 519         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 520         struct hif_ce_pipe_info *pipe_info =  &ar_pci->pipe_info[ce_state->id];
 521         struct ath10k_pci_compl *compl;
 522         bool process = false;
 523
 524         do {
 525                 /*
 526                  * For the send completion of an item in sendlist, just
 527                  * increment num_sends_allowed. The upper layer callback will
 528                  * be triggered when last fragment is done with send.
 529                  */
 530                 if (transfer_context == CE_SENDLIST_ITEM_CTXT) {
 531                         spin_lock_bh(&pipe_info->pipe_lock);
 532                         pipe_info->num_sends_allowed++;
 533                         spin_unlock_bh(&pipe_info->pipe_lock);
 534                         continue;
 535                 }
 536
 537                 compl = get_free_compl(pipe_info);
 538                 if (!compl)
 539                         break;
 540
 541                 compl->send_or_recv = HIF_CE_COMPLETE_SEND;
 542                 compl->ce_state = ce_state;
 543                 compl->pipe_info = pipe_info;
 544                 compl->transfer_context = transfer_context;
 545                 compl->nbytes = nbytes;
 546                 compl->transfer_id = transfer_id;
 547                 compl->flags = 0;
 548
 549                 /*
 550                  * Add the completion to the processing queue.
 551                  */
 552                 spin_lock_bh(&ar_pci->compl_lock);
 553                 list_add_tail(&compl->list, &ar_pci->compl_process);
 554                 spin_unlock_bh(&ar_pci->compl_lock);
 555
 556                 process = true;
 557         } while (ath10k_ce_completed_send_next(ce_state,
 558                                                            &transfer_context,
 559                                                            &ce_data, &nbytes,
 560                                                            &transfer_id) == 0);
 561
 562         /*
 563          * If only some of the items within a sendlist have completed,
 564          * don't invoke completion processing until the entire sendlist
 565          * has been sent.
 566          */
 567         if (!process)
 568                 return;
 569
 570         ath10k_pci_process_ce(ar);
 571 }
 572
 573 /* Called by lower (CE) layer when data is received from the Target. */
 574 static void ath10k_pci_ce_recv_data(struct ce_state *ce_state,
 575                                     void *transfer_context, u32 ce_data,
 576                                     unsigned int nbytes,
 577                                     unsigned int transfer_id,
 578                                     unsigned int flags)
 579 {
 580         struct ath10k *ar = ce_state->ar;
 581         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 582         struct hif_ce_pipe_info *pipe_info =  &ar_pci->pipe_info[ce_state->id];
 583         struct ath10k_pci_compl *compl;
 584         struct sk_buff *skb;
 585
 586         do {
 587                 compl = get_free_compl(pipe_info);
 588                 if (!compl)
 589                         break;
 590
 591                 compl->send_or_recv = HIF_CE_COMPLETE_RECV;
 592                 compl->ce_state = ce_state;
 593                 compl->pipe_info = pipe_info;
 594                 compl->transfer_context = transfer_context;
 595                 compl->nbytes = nbytes;
 596                 compl->transfer_id = transfer_id;
 597                 compl->flags = flags;
 598
 599                 skb = transfer_context;
 600                 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
 601                                  skb->len + skb_tailroom(skb),
 602                                  DMA_FROM_DEVICE);
 603                 /*
 604                  * Add the completion to the processing queue.
 605                  */
 606                 spin_lock_bh(&ar_pci->compl_lock);
 607                 list_add_tail(&compl->list, &ar_pci->compl_process);
 608                 spin_unlock_bh(&ar_pci->compl_lock);
 609
 610         } while (ath10k_ce_completed_recv_next(ce_state,
 611                                                            &transfer_context,
 612                                                            &ce_data, &nbytes,
 613                                                            &transfer_id,
 614                                                            &flags) == 0);
 615
 616         ath10k_pci_process_ce(ar);
 617 }
 618
 619 /* Send the first nbytes bytes of the buffer */
 620 static int ath10k_pci_hif_send_head(struct ath10k *ar, u8 pipe_id,
 621                                     unsigned int transfer_id,
 622                                     unsigned int bytes, struct sk_buff *nbuf)
 623 {
 624         struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(nbuf);
 625         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 626         struct hif_ce_pipe_info *pipe_info = &(ar_pci->pipe_info[pipe_id]);
 627         struct ce_state *ce_hdl = pipe_info->ce_hdl;
 628         struct ce_sendlist sendlist;
 629         unsigned int len;
 630         u32 flags = 0;
 631         int ret;
 632
 633         memset(&sendlist, 0, sizeof(struct ce_sendlist));
 634
 635         len = min(bytes, nbuf->len);
 636         bytes -= len;
 637
 638         if (len & 3)
 639                 ath10k_warn("skb not aligned to 4-byte boundary (%d)\n", len);
 640
 641         ath10k_dbg(ATH10K_DBG_PCI,
 642                    "pci send data vaddr %p paddr 0x%llx len %d as %d bytes\n",
 643                    nbuf->data, (unsigned long long) skb_cb->paddr,
 644                    nbuf->len, len);
 645         ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL,
 646                         "ath10k tx: data: ",
 647                         nbuf->data, nbuf->len);
 648
 649         ath10k_ce_sendlist_buf_add(&sendlist, skb_cb->paddr, len, flags);
 650
 651         /* Make sure we have resources to handle this request */
 652         spin_lock_bh(&pipe_info->pipe_lock);
 653         if (!pipe_info->num_sends_allowed) {
 654                 ath10k_warn("Pipe: %d is full\n", pipe_id);
 655                 spin_unlock_bh(&pipe_info->pipe_lock);
 656                 return -ENOSR;
 657         }
 658         pipe_info->num_sends_allowed--;
 659         spin_unlock_bh(&pipe_info->pipe_lock);
 660
 661         ret = ath10k_ce_sendlist_send(ce_hdl, nbuf, &sendlist, transfer_id);
 662         if (ret)
 663                 ath10k_warn("CE send failed: %p\n", nbuf);
 664
 665         return ret;
 666 }
 667
 668 static u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
 669 {
 670         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 671         struct hif_ce_pipe_info *pipe_info = &(ar_pci->pipe_info[pipe]);
 672         int ret;
 673
 674         spin_lock_bh(&pipe_info->pipe_lock);
 675         ret = pipe_info->num_sends_allowed;
 676         spin_unlock_bh(&pipe_info->pipe_lock);
 677
 678         return ret;
 679 }
 680
 681 static void ath10k_pci_hif_dump_area(struct ath10k *ar)
 682 {
 683         u32 reg_dump_area = 0;
 684         u32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
 685         u32 host_addr;
 686         int ret;
 687         u32 i;
 688
 689         ath10k_err("firmware crashed!\n");
 690         ath10k_err("hardware name %s version 0x%x\n",
 691                    ar->hw_params.name, ar->target_version);
 692         ath10k_err("firmware version: %u.%u.%u.%u\n", ar->fw_version_major,
 693                    ar->fw_version_minor, ar->fw_version_release,
 694                    ar->fw_version_build);
 695
 696         host_addr = host_interest_item_address(HI_ITEM(hi_failure_state));
 697         if (ath10k_pci_diag_read_mem(ar, host_addr,
 698                                      &reg_dump_area, sizeof(u32)) != 0) {
 699                 ath10k_warn("could not read hi_failure_state\n");
 700                 return;
 701         }
 702
 703         ath10k_err("target register Dump Location: 0x%08X\n", reg_dump_area);
 704
 705         ret = ath10k_pci_diag_read_mem(ar, reg_dump_area,
 706                                        &reg_dump_values[0],
 707                                        REG_DUMP_COUNT_QCA988X * sizeof(u32));
 708         if (ret != 0) {
 709                 ath10k_err("could not dump FW Dump Area\n");
 710                 return;
 711         }
 712
 713         BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
 714
 715         ath10k_err("target Register Dump\n");
 716         for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
 717                 ath10k_err("[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
 718                            i,
 719                            reg_dump_values[i],
 720                            reg_dump_values[i + 1],
 721                            reg_dump_values[i + 2],
 722                            reg_dump_values[i + 3]);
 723
 724         ieee80211_queue_work(ar->hw, &ar->restart_work);
 725 }
 726
 727 static void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
 728                                                int force)
 729 {
 730         if (!force) {
 731                 int resources;
 732                 /*
 733                  * Decide whether to actually poll for completions, or just
 734                  * wait for a later chance.
 735                  * If there seem to be plenty of resources left, then just wait
 736                  * since checking involves reading a CE register, which is a
 737                  * relatively expensive operation.
 738                  */
 739                 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
 740
 741                 /*
 742                  * If at least 50% of the total resources are still available,
 743                  * don't bother checking again yet.
 744                  */
 745                 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
 746                         return;
 747         }
 748         ath10k_ce_per_engine_service(ar, pipe);
 749 }
 750
 751 static void ath10k_pci_hif_set_callbacks(struct ath10k *ar,
 752                                          struct ath10k_hif_cb *callbacks)
 753 {
 754         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 755
 756         ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
 757
 758         memcpy(&ar_pci->msg_callbacks_current, callbacks,
 759                sizeof(ar_pci->msg_callbacks_current));
 760 }
 761
 762 static int ath10k_pci_start_ce(struct ath10k *ar)
 763 {
 764         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 765         struct ce_state *ce_diag = ar_pci->ce_diag;
 766         const struct ce_attr *attr;
 767         struct hif_ce_pipe_info *pipe_info;
 768         struct ath10k_pci_compl *compl;
 769         int i, pipe_num, completions, disable_interrupts;
 770
 771         spin_lock_init(&ar_pci->compl_lock);
 772         INIT_LIST_HEAD(&ar_pci->compl_process);
 773
 774         for (pipe_num = 0; pipe_num < ar_pci->ce_count; pipe_num++) {
 775                 pipe_info = &ar_pci->pipe_info[pipe_num];
 776
 777                 spin_lock_init(&pipe_info->pipe_lock);
 778                 INIT_LIST_HEAD(&pipe_info->compl_free);
 779
 780                 /* Handle Diagnostic CE specially */
 781                 if (pipe_info->ce_hdl == ce_diag)
 782                         continue;
 783
 784                 attr = &host_ce_config_wlan[pipe_num];
 785                 completions = 0;
 786
 787                 if (attr->src_nentries) {
 788                         disable_interrupts = attr->flags & CE_ATTR_DIS_INTR;
 789                         ath10k_ce_send_cb_register(pipe_info->ce_hdl,
 790                                                    ath10k_pci_ce_send_done,
 791                                                    disable_interrupts);
 792                         completions += attr->src_nentries;
 793                         pipe_info->num_sends_allowed = attr->src_nentries - 1;
 794                 }
 795
 796                 if (attr->dest_nentries) {
 797                         ath10k_ce_recv_cb_register(pipe_info->ce_hdl,
 798                                                    ath10k_pci_ce_recv_data);
 799                         completions += attr->dest_nentries;
 800                 }
 801
 802                 if (completions == 0)
 803                         continue;
 804
 805                 for (i = 0; i < completions; i++) {
 806                         compl = kmalloc(sizeof(*compl), GFP_KERNEL);
 807                         if (!compl) {
 808                                 ath10k_warn("No memory for completion state\n");
 809                                 ath10k_pci_stop_ce(ar);
 810                                 return -ENOMEM;
 811                         }
 812
 813                         compl->send_or_recv = HIF_CE_COMPLETE_FREE;
 814                         list_add_tail(&compl->list, &pipe_info->compl_free);
 815                 }
 816         }
 817
 818         return 0;
 819 }
 820
 821 static void ath10k_pci_stop_ce(struct ath10k *ar)
 822 {
 823         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 824         struct ath10k_pci_compl *compl;
 825         struct sk_buff *skb;
 826         int i;
 827
 828         ath10k_ce_disable_interrupts(ar);
 829
 830         /* Cancel the pending tasklet */
 831         tasklet_kill(&ar_pci->intr_tq);
 832
 833         for (i = 0; i < CE_COUNT; i++)
 834                 tasklet_kill(&ar_pci->pipe_info[i].intr);
 835
 836         /* Mark pending completions as aborted, so that upper layers free up
 837          * their associated resources */
 838         spin_lock_bh(&ar_pci->compl_lock);
 839         list_for_each_entry(compl, &ar_pci->compl_process, list) {
 840                 skb = (struct sk_buff *)compl->transfer_context;
 841                 ATH10K_SKB_CB(skb)->is_aborted = true;
 842         }
 843         spin_unlock_bh(&ar_pci->compl_lock);
 844 }
 845
 846 static void ath10k_pci_cleanup_ce(struct ath10k *ar)
 847 {
 848         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 849         struct ath10k_pci_compl *compl, *tmp;
 850         struct hif_ce_pipe_info *pipe_info;
 851         struct sk_buff *netbuf;
 852         int pipe_num;
 853
 854         /* Free pending completions. */
 855         spin_lock_bh(&ar_pci->compl_lock);
 856         if (!list_empty(&ar_pci->compl_process))
 857                 ath10k_warn("pending completions still present! possible memory leaks.\n");
 858
 859         list_for_each_entry_safe(compl, tmp, &ar_pci->compl_process, list) {
 860                 list_del(&compl->list);
 861                 netbuf = (struct sk_buff *)compl->transfer_context;
 862                 dev_kfree_skb_any(netbuf);
 863                 kfree(compl);
 864         }
 865         spin_unlock_bh(&ar_pci->compl_lock);
 866
 867         /* Free unused completions for each pipe. */
 868         for (pipe_num = 0; pipe_num < ar_pci->ce_count; pipe_num++) {
 869                 pipe_info = &ar_pci->pipe_info[pipe_num];
 870
 871                 spin_lock_bh(&pipe_info->pipe_lock);
 872                 list_for_each_entry_safe(compl, tmp,
 873                                          &pipe_info->compl_free, list) {
 874                         list_del(&compl->list);
 875                         kfree(compl);
 876                 }
 877                 spin_unlock_bh(&pipe_info->pipe_lock);
 878         }
 879 }
 880
 881 static void ath10k_pci_process_ce(struct ath10k *ar)
 882 {
 883         struct ath10k_pci *ar_pci = ar->hif.priv;
 884         struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
 885         struct ath10k_pci_compl *compl;
 886         struct sk_buff *skb;
 887         unsigned int nbytes;
 888         int ret, send_done = 0;
 889
 890         /* Upper layers aren't ready to handle tx/rx completions in parallel so
 891          * we must serialize all completion processing. */
 892
 893         spin_lock_bh(&ar_pci->compl_lock);
 894         if (ar_pci->compl_processing) {
 895                 spin_unlock_bh(&ar_pci->compl_lock);
 896                 return;
 897         }
 898         ar_pci->compl_processing = true;
 899         spin_unlock_bh(&ar_pci->compl_lock);
 900
 901         for (;;) {
 902                 spin_lock_bh(&ar_pci->compl_lock);
 903                 if (list_empty(&ar_pci->compl_process)) {
 904                         spin_unlock_bh(&ar_pci->compl_lock);
 905                         break;
 906                 }
 907                 compl = list_first_entry(&ar_pci->compl_process,
 908                                          struct ath10k_pci_compl, list);
 909                 list_del(&compl->list);
 910                 spin_unlock_bh(&ar_pci->compl_lock);
 911
 912                 if (compl->send_or_recv == HIF_CE_COMPLETE_SEND) {
 913                         cb->tx_completion(ar,
 914                                           compl->transfer_context,
 915                                           compl->transfer_id);
 916                         send_done = 1;
 917                 } else {
 918                         ret = ath10k_pci_post_rx_pipe(compl->pipe_info, 1);
 919                         if (ret) {
 920                                 ath10k_warn("Unable to post recv buffer for pipe: %d\n",
 921                                             compl->pipe_info->pipe_num);
 922                                 break;
 923                         }
 924
 925                         skb = (struct sk_buff *)compl->transfer_context;
 926                         nbytes = compl->nbytes;
 927
 928                         ath10k_dbg(ATH10K_DBG_PCI,
 929                                    "ath10k_pci_ce_recv_data netbuf=%p  nbytes=%d\n",
 930                                    skb, nbytes);
 931                         ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL,
 932                                         "ath10k rx: ", skb->data, nbytes);
 933
 934                         if (skb->len + skb_tailroom(skb) >= nbytes) {
 935                                 skb_trim(skb, 0);
 936                                 skb_put(skb, nbytes);
 937                                 cb->rx_completion(ar, skb,
 938                                                   compl->pipe_info->pipe_num);
 939                         } else {
 940                                 ath10k_warn("rxed more than expected (nbytes %d, max %d)",
 941                                             nbytes,
 942                                             skb->len + skb_tailroom(skb));
 943                         }
 944                 }
 945
 946                 compl->send_or_recv = HIF_CE_COMPLETE_FREE;
 947
 948                 /*
 949                  * Add completion back to the pipe's free list.
 950                  */
 951                 spin_lock_bh(&compl->pipe_info->pipe_lock);
 952                 list_add_tail(&compl->list, &compl->pipe_info->compl_free);
 953                 compl->pipe_info->num_sends_allowed += send_done;
 954                 spin_unlock_bh(&compl->pipe_info->pipe_lock);
 955         }
 956
 957         spin_lock_bh(&ar_pci->compl_lock);
 958         ar_pci->compl_processing = false;
 959         spin_unlock_bh(&ar_pci->compl_lock);
 960 }
 961
 962 /* TODO - temporary mapping while we have too few CE's */
 963 static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar,
 964                                               u16 service_id, u8 *ul_pipe,
 965                                               u8 *dl_pipe, int *ul_is_polled,
 966                                               int *dl_is_polled)
 967 {
 968         int ret = 0;
 969
 970         /* polling for received messages not supported */
 971         *dl_is_polled = 0;
 972
 973         switch (service_id) {
 974         case ATH10K_HTC_SVC_ID_HTT_DATA_MSG:
 975                 /*
 976                  * Host->target HTT gets its own pipe, so it can be polled
 977                  * while other pipes are interrupt driven.
 978                  */
 979                 *ul_pipe = 4;
 980                 /*
 981                  * Use the same target->host pipe for HTC ctrl, HTC raw
 982                  * streams, and HTT.
 983                  */
 984                 *dl_pipe = 1;
 985                 break;
 986
 987         case ATH10K_HTC_SVC_ID_RSVD_CTRL:
 988         case ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS:
 989                 /*
 990                  * Note: HTC_RAW_STREAMS_SVC is currently unused, and
 991                  * HTC_CTRL_RSVD_SVC could share the same pipe as the
 992                  * WMI services.  So, if another CE is needed, change
 993                  * this to *ul_pipe = 3, which frees up CE 0.
 994                  */
 995                 /* *ul_pipe = 3; */
 996                 *ul_pipe = 0;
 997                 *dl_pipe = 1;
 998                 break;
 999
1000         case ATH10K_HTC_SVC_ID_WMI_DATA_BK:
1001         case ATH10K_HTC_SVC_ID_WMI_DATA_BE:
1002         case ATH10K_HTC_SVC_ID_WMI_DATA_VI:
1003         case ATH10K_HTC_SVC_ID_WMI_DATA_VO:
1004
1005         case ATH10K_HTC_SVC_ID_WMI_CONTROL:
1006                 *ul_pipe = 3;
1007                 *dl_pipe = 2;
1008                 break;
1009
1010                 /* pipe 5 unused   */
1011                 /* pipe 6 reserved */
1012                 /* pipe 7 reserved */
1013
1014         default:
1015                 ret = -1;
1016                 break;
1017         }
1018         *ul_is_polled =
1019                 (host_ce_config_wlan[*ul_pipe].flags & CE_ATTR_DIS_INTR) != 0;
1020
1021         return ret;
1022 }
1023
1024 static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1025                                                 u8 *ul_pipe, u8 *dl_pipe)
1026 {
1027         int ul_is_polled, dl_is_polled;
1028
1029         (void)ath10k_pci_hif_map_service_to_pipe(ar,
1030                                                  ATH10K_HTC_SVC_ID_RSVD_CTRL,
1031                                                  ul_pipe,
1032                                                  dl_pipe,
1033                                                  &ul_is_polled,
1034                                                  &dl_is_polled);
1035 }
1036
1037 static int ath10k_pci_post_rx_pipe(struct hif_ce_pipe_info *pipe_info,
1038                                    int num)
1039 {
1040         struct ath10k *ar = pipe_info->hif_ce_state;
1041         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1042         struct ce_state *ce_state = pipe_info->ce_hdl;
1043         struct sk_buff *skb;
1044         dma_addr_t ce_data;
1045         int i, ret = 0;
1046
1047         if (pipe_info->buf_sz == 0)
1048                 return 0;
1049
1050         for (i = 0; i < num; i++) {
1051                 skb = dev_alloc_skb(pipe_info->buf_sz);
1052                 if (!skb) {
1053                         ath10k_warn("could not allocate skbuff for pipe %d\n",
1054                                     num);
1055                         ret = -ENOMEM;
1056                         goto err;
1057                 }
1058
1059                 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
1060
1061                 ce_data = dma_map_single(ar->dev, skb->data,
1062                                          skb->len + skb_tailroom(skb),
1063                                          DMA_FROM_DEVICE);
1064
1065                 if (unlikely(dma_mapping_error(ar->dev, ce_data))) {
1066                         ath10k_warn("could not dma map skbuff\n");
1067                         dev_kfree_skb_any(skb);
1068                         ret = -EIO;
1069                         goto err;
1070                 }
1071
1072                 ATH10K_SKB_CB(skb)->paddr = ce_data;
1073
1074                 pci_dma_sync_single_for_device(ar_pci->pdev, ce_data,
1075                                                pipe_info->buf_sz,
1076                                                PCI_DMA_FROMDEVICE);
1077
1078                 ret = ath10k_ce_recv_buf_enqueue(ce_state, (void *)skb,
1079                                                  ce_data);
1080                 if (ret) {
1081                         ath10k_warn("could not enqueue to pipe %d (%d)\n",
1082                                     num, ret);
1083                         goto err;
1084                 }
1085         }
1086
1087         return ret;
1088
1089 err:
1090         ath10k_pci_rx_pipe_cleanup(pipe_info);
1091         return ret;
1092 }
1093
1094 static int ath10k_pci_post_rx(struct ath10k *ar)
1095 {
1096         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1097         struct hif_ce_pipe_info *pipe_info;
1098         const struct ce_attr *attr;
1099         int pipe_num, ret = 0;
1100
1101         for (pipe_num = 0; pipe_num < ar_pci->ce_count; pipe_num++) {
1102                 pipe_info = &ar_pci->pipe_info[pipe_num];
1103                 attr = &host_ce_config_wlan[pipe_num];
1104
1105                 if (attr->dest_nentries == 0)
1106                         continue;
1107
1108                 ret = ath10k_pci_post_rx_pipe(pipe_info,
1109                                               attr->dest_nentries - 1);
1110                 if (ret) {
1111                         ath10k_warn("Unable to replenish recv buffers for pipe: %d\n",
1112                                     pipe_num);
1113
1114                         for (; pipe_num >= 0; pipe_num--) {
1115                                 pipe_info = &ar_pci->pipe_info[pipe_num];
1116                                 ath10k_pci_rx_pipe_cleanup(pipe_info);
1117                         }
1118                         return ret;
1119                 }
1120         }
1121
1122         return 0;
1123 }
1124
1125 static int ath10k_pci_hif_start(struct ath10k *ar)
1126 {
1127         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1128         int ret;
1129
1130         ret = ath10k_pci_start_ce(ar);
1131         if (ret) {
1132                 ath10k_warn("could not start CE (%d)\n", ret);
1133                 return ret;
1134         }
1135
1136         /* Post buffers once to start things off. */
1137         ret = ath10k_pci_post_rx(ar);
1138         if (ret) {
1139                 ath10k_warn("could not post rx pipes (%d)\n", ret);
1140                 return ret;
1141         }
1142
1143         ar_pci->started = 1;
1144         return 0;
1145 }
1146
1147 static void ath10k_pci_rx_pipe_cleanup(struct hif_ce_pipe_info *pipe_info)
1148 {
1149         struct ath10k *ar;
1150         struct ath10k_pci *ar_pci;
1151         struct ce_state *ce_hdl;
1152         u32 buf_sz;
1153         struct sk_buff *netbuf;
1154         u32 ce_data;
1155
1156         buf_sz = pipe_info->buf_sz;
1157
1158         /* Unused Copy Engine */
1159         if (buf_sz == 0)
1160                 return;
1161
1162         ar = pipe_info->hif_ce_state;
1163         ar_pci = ath10k_pci_priv(ar);
1164
1165         if (!ar_pci->started)
1166                 return;
1167
1168         ce_hdl = pipe_info->ce_hdl;
1169
1170         while (ath10k_ce_revoke_recv_next(ce_hdl, (void **)&netbuf,
1171                                           &ce_data) == 0) {
1172                 dma_unmap_single(ar->dev, ATH10K_SKB_CB(netbuf)->paddr,
1173                                  netbuf->len + skb_tailroom(netbuf),
1174                                  DMA_FROM_DEVICE);
1175                 dev_kfree_skb_any(netbuf);
1176         }
1177 }
1178
1179 static void ath10k_pci_tx_pipe_cleanup(struct hif_ce_pipe_info *pipe_info)
1180 {
1181         struct ath10k *ar;
1182         struct ath10k_pci *ar_pci;
1183         struct ce_state *ce_hdl;
1184         struct sk_buff *netbuf;
1185         u32 ce_data;
1186         unsigned int nbytes;
1187         unsigned int id;
1188         u32 buf_sz;
1189
1190         buf_sz = pipe_info->buf_sz;
1191
1192         /* Unused Copy Engine */
1193         if (buf_sz == 0)
1194                 return;
1195
1196         ar = pipe_info->hif_ce_state;
1197         ar_pci = ath10k_pci_priv(ar);
1198
1199         if (!ar_pci->started)
1200                 return;
1201
1202         ce_hdl = pipe_info->ce_hdl;
1203
1204         while (ath10k_ce_cancel_send_next(ce_hdl, (void **)&netbuf,
1205                                           &ce_data, &nbytes, &id) == 0) {
1206                 if (netbuf != CE_SENDLIST_ITEM_CTXT)
1207                         /*
1208                          * Indicate the completion to higer layer to free
1209                          * the buffer
1210                          */
1211                         ATH10K_SKB_CB(netbuf)->is_aborted = true;
1212                         ar_pci->msg_callbacks_current.tx_completion(ar,
1213                                                                     netbuf,
1214                                                                     id);
1215         }
1216 }
1217
1218 /*
1219  * Cleanup residual buffers for device shutdown:
1220  *    buffers that were enqueued for receive
1221  *    buffers that were to be sent
1222  * Note: Buffers that had completed but which were
1223  * not yet processed are on a completion queue. They
1224  * are handled when the completion thread shuts down.
1225  */
1226 static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
1227 {
1228         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1229         int pipe_num;
1230
1231         for (pipe_num = 0; pipe_num < ar_pci->ce_count; pipe_num++) {
1232                 struct hif_ce_pipe_info *pipe_info;
1233
1234                 pipe_info = &ar_pci->pipe_info[pipe_num];
1235                 ath10k_pci_rx_pipe_cleanup(pipe_info);
1236                 ath10k_pci_tx_pipe_cleanup(pipe_info);
1237         }
1238 }
1239
1240 static void ath10k_pci_ce_deinit(struct ath10k *ar)
1241 {
1242         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1243         struct hif_ce_pipe_info *pipe_info;
1244         int pipe_num;
1245
1246         for (pipe_num = 0; pipe_num < ar_pci->ce_count; pipe_num++) {
1247                 pipe_info = &ar_pci->pipe_info[pipe_num];
1248                 if (pipe_info->ce_hdl) {
1249                         ath10k_ce_deinit(pipe_info->ce_hdl);
1250                         pipe_info->ce_hdl = NULL;
1251                         pipe_info->buf_sz = 0;
1252                 }
1253         }
1254 }
1255
1256 static void ath10k_pci_disable_irqs(struct ath10k *ar)
1257 {
1258         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1259         int i;
1260
1261         for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
1262                 disable_irq(ar_pci->pdev->irq + i);
1263 }
1264
1265 static void ath10k_pci_hif_stop(struct ath10k *ar)
1266 {
1267         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1268
1269         ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
1270
1271         /* Irqs are never explicitly re-enabled. They are implicitly re-enabled
1272          * by ath10k_pci_start_intr(). */
1273         ath10k_pci_disable_irqs(ar);
1274
1275         ath10k_pci_stop_ce(ar);
1276
1277         /* At this point, asynchronous threads are stopped, the target should
1278          * not DMA nor interrupt. We process the leftovers and then free
1279          * everything else up. */
1280
1281         ath10k_pci_process_ce(ar);
1282         ath10k_pci_cleanup_ce(ar);
1283         ath10k_pci_buffer_cleanup(ar);
1284
1285         ar_pci->started = 0;
1286 }
1287
1288 static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
1289                                            void *req, u32 req_len,
1290                                            void *resp, u32 *resp_len)
1291 {
1292         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1293         struct ce_state *ce_tx = ar_pci->pipe_info[BMI_CE_NUM_TO_TARG].ce_hdl;
1294         struct ce_state *ce_rx = ar_pci->pipe_info[BMI_CE_NUM_TO_HOST].ce_hdl;
1295         dma_addr_t req_paddr = 0;
1296         dma_addr_t resp_paddr = 0;
1297         struct bmi_xfer xfer = {};
1298         void *treq, *tresp = NULL;
1299         int ret = 0;
1300
1301         if (resp && !resp_len)
1302                 return -EINVAL;
1303
1304         if (resp && resp_len && *resp_len == 0)
1305                 return -EINVAL;
1306
1307         treq = kmemdup(req, req_len, GFP_KERNEL);
1308         if (!treq)
1309                 return -ENOMEM;
1310
1311         req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
1312         ret = dma_mapping_error(ar->dev, req_paddr);
1313         if (ret)
1314                 goto err_dma;
1315
1316         if (resp && resp_len) {
1317                 tresp = kzalloc(*resp_len, GFP_KERNEL);
1318                 if (!tresp) {
1319                         ret = -ENOMEM;
1320                         goto err_req;
1321                 }
1322
1323                 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
1324                                             DMA_FROM_DEVICE);
1325                 ret = dma_mapping_error(ar->dev, resp_paddr);
1326                 if (ret)
1327                         goto err_req;
1328
1329                 xfer.wait_for_resp = true;
1330                 xfer.resp_len = 0;
1331
1332                 ath10k_ce_recv_buf_enqueue(ce_rx, &xfer, resp_paddr);
1333         }
1334
1335         init_completion(&xfer.done);
1336
1337         ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
1338         if (ret)
1339                 goto err_resp;
1340
1341         ret = wait_for_completion_timeout(&xfer.done,
1342                                           BMI_COMMUNICATION_TIMEOUT_HZ);
1343         if (ret <= 0) {
1344                 u32 unused_buffer;
1345                 unsigned int unused_nbytes;
1346                 unsigned int unused_id;
1347
1348                 ret = -ETIMEDOUT;
1349                 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
1350                                            &unused_nbytes, &unused_id);
1351         } else {
1352                 /* non-zero means we did not time out */
1353                 ret = 0;
1354         }
1355
1356 err_resp:
1357         if (resp) {
1358                 u32 unused_buffer;
1359
1360                 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
1361                 dma_unmap_single(ar->dev, resp_paddr,
1362                                  *resp_len, DMA_FROM_DEVICE);
1363         }
1364 err_req:
1365         dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
1366
1367         if (ret == 0 && resp_len) {
1368                 *resp_len = min(*resp_len, xfer.resp_len);
1369                 memcpy(resp, tresp, xfer.resp_len);
1370         }
1371 err_dma:
1372         kfree(treq);
1373         kfree(tresp);
1374
1375         return ret;
1376 }
1377
1378 static void ath10k_pci_bmi_send_done(struct ce_state *ce_state,
1379                                      void *transfer_context,
1380                                      u32 data,
1381                                      unsigned int nbytes,
1382                                      unsigned int transfer_id)
1383 {
1384         struct bmi_xfer *xfer = transfer_context;
1385
1386         if (xfer->wait_for_resp)
1387                 return;
1388
1389         complete(&xfer->done);
1390 }
1391
1392 static void ath10k_pci_bmi_recv_data(struct ce_state *ce_state,
1393                                      void *transfer_context,
1394                                      u32 data,
1395                                      unsigned int nbytes,
1396                                      unsigned int transfer_id,
1397                                      unsigned int flags)
1398 {
1399         struct bmi_xfer *xfer = transfer_context;
1400
1401         if (!xfer->wait_for_resp) {
1402                 ath10k_warn("unexpected: BMI data received; ignoring\n");
1403                 return;
1404         }
1405
1406         xfer->resp_len = nbytes;
1407         complete(&xfer->done);
1408 }
1409
1410 /*
1411  * Map from service/endpoint to Copy Engine.
1412  * This table is derived from the CE_PCI TABLE, above.
1413  * It is passed to the Target at startup for use by firmware.
1414  */
1415 static const struct service_to_pipe target_service_to_ce_map_wlan[] = {
1416         {
1417                  ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1418                  PIPEDIR_OUT,           /* out = UL = host -> target */
1419                  3,
1420         },
1421         {
1422                  ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1423                  PIPEDIR_IN,            /* in = DL = target -> host */
1424                  2,
1425         },
1426         {
1427                  ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1428                  PIPEDIR_OUT,           /* out = UL = host -> target */
1429                  3,
1430         },
1431         {
1432                  ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1433                  PIPEDIR_IN,            /* in = DL = target -> host */
1434                  2,
1435         },
1436         {
1437                  ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1438                  PIPEDIR_OUT,           /* out = UL = host -> target */
1439                  3,
1440         },
1441         {
1442                  ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1443                  PIPEDIR_IN,            /* in = DL = target -> host */
1444                  2,
1445         },
1446         {
1447                  ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1448                  PIPEDIR_OUT,           /* out = UL = host -> target */
1449                  3,
1450         },
1451         {
1452                  ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1453                  PIPEDIR_IN,            /* in = DL = target -> host */
1454                  2,
1455         },
1456         {
1457                  ATH10K_HTC_SVC_ID_WMI_CONTROL,
1458                  PIPEDIR_OUT,           /* out = UL = host -> target */
1459                  3,
1460         },
1461         {
1462                  ATH10K_HTC_SVC_ID_WMI_CONTROL,
1463                  PIPEDIR_IN,            /* in = DL = target -> host */
1464                  2,
1465         },
1466         {
1467                  ATH10K_HTC_SVC_ID_RSVD_CTRL,
1468                  PIPEDIR_OUT,           /* out = UL = host -> target */
1469                  0,             /* could be moved to 3 (share with WMI) */
1470         },
1471         {
1472                  ATH10K_HTC_SVC_ID_RSVD_CTRL,
1473                  PIPEDIR_IN,            /* in = DL = target -> host */
1474                  1,
1475         },
1476         {
1477                  ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS,    /* not currently used */
1478                  PIPEDIR_OUT,           /* out = UL = host -> target */
1479                  0,
1480         },
1481         {
1482                  ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS,    /* not currently used */
1483                  PIPEDIR_IN,            /* in = DL = target -> host */
1484                  1,
1485         },
1486         {
1487                  ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1488                  PIPEDIR_OUT,           /* out = UL = host -> target */
1489                  4,
1490         },
1491         {
1492                  ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1493                  PIPEDIR_IN,            /* in = DL = target -> host */
1494                  1,
1495         },
1496
1497         /* (Additions here) */
1498
1499         {                               /* Must be last */
1500                  0,
1501                  0,
1502                  0,
1503         },
1504 };
1505
1506 /*
1507  * Send an interrupt to the device to wake up the Target CPU
1508  * so it has an opportunity to notice any changed state.
1509  */
1510 static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
1511 {
1512         int ret;
1513         u32 core_ctrl;
1514
1515         ret = ath10k_pci_diag_read_access(ar, SOC_CORE_BASE_ADDRESS |
1516                                               CORE_CTRL_ADDRESS,
1517                                           &core_ctrl);
1518         if (ret) {
1519                 ath10k_warn("Unable to read core ctrl\n");
1520                 return ret;
1521         }
1522
1523         /* A_INUM_FIRMWARE interrupt to Target CPU */
1524         core_ctrl |= CORE_CTRL_CPU_INTR_MASK;
1525
1526         ret = ath10k_pci_diag_write_access(ar, SOC_CORE_BASE_ADDRESS |
1527                                                CORE_CTRL_ADDRESS,
1528                                            core_ctrl);
1529         if (ret)
1530                 ath10k_warn("Unable to set interrupt mask\n");
1531
1532         return ret;
1533 }
1534
1535 static int ath10k_pci_init_config(struct ath10k *ar)
1536 {
1537         u32 interconnect_targ_addr;
1538         u32 pcie_state_targ_addr = 0;
1539         u32 pipe_cfg_targ_addr = 0;
1540         u32 svc_to_pipe_map = 0;
1541         u32 pcie_config_flags = 0;
1542         u32 ealloc_value;
1543         u32 ealloc_targ_addr;
1544         u32 flag2_value;
1545         u32 flag2_targ_addr;
1546         int ret = 0;
1547
1548         /* Download to Target the CE Config and the service-to-CE map */
1549         interconnect_targ_addr =
1550                 host_interest_item_address(HI_ITEM(hi_interconnect_state));
1551
1552         /* Supply Target-side CE configuration */
1553         ret = ath10k_pci_diag_read_access(ar, interconnect_targ_addr,
1554                                           &pcie_state_targ_addr);
1555         if (ret != 0) {
1556                 ath10k_err("Failed to get pcie state addr: %d\n", ret);
1557                 return ret;
1558         }
1559
1560         if (pcie_state_targ_addr == 0) {
1561                 ret = -EIO;
1562                 ath10k_err("Invalid pcie state addr\n");
1563                 return ret;
1564         }
1565
1566         ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1567                                           offsetof(struct pcie_state,
1568                                                    pipe_cfg_addr),
1569                                           &pipe_cfg_targ_addr);
1570         if (ret != 0) {
1571                 ath10k_err("Failed to get pipe cfg addr: %d\n", ret);
1572                 return ret;
1573         }
1574
1575         if (pipe_cfg_targ_addr == 0) {
1576                 ret = -EIO;
1577                 ath10k_err("Invalid pipe cfg addr\n");
1578                 return ret;
1579         }
1580
1581         ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
1582                                  target_ce_config_wlan,
1583                                  sizeof(target_ce_config_wlan));
1584
1585         if (ret != 0) {
1586                 ath10k_err("Failed to write pipe cfg: %d\n", ret);
1587                 return ret;
1588         }
1589
1590         ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1591                                           offsetof(struct pcie_state,
1592                                                    svc_to_pipe_map),
1593                                           &svc_to_pipe_map);
1594         if (ret != 0) {
1595                 ath10k_err("Failed to get svc/pipe map: %d\n", ret);
1596                 return ret;
1597         }
1598
1599         if (svc_to_pipe_map == 0) {
1600                 ret = -EIO;
1601                 ath10k_err("Invalid svc_to_pipe map\n");
1602                 return ret;
1603         }
1604
1605         ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
1606                                  target_service_to_ce_map_wlan,
1607                                  sizeof(target_service_to_ce_map_wlan));
1608         if (ret != 0) {
1609                 ath10k_err("Failed to write svc/pipe map: %d\n", ret);
1610                 return ret;
1611         }
1612
1613         ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1614                                           offsetof(struct pcie_state,
1615                                                    config_flags),
1616                                           &pcie_config_flags);
1617         if (ret != 0) {
1618                 ath10k_err("Failed to get pcie config_flags: %d\n", ret);
1619                 return ret;
1620         }
1621
1622         pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
1623
1624         ret = ath10k_pci_diag_write_mem(ar, pcie_state_targ_addr +
1625                                  offsetof(struct pcie_state, config_flags),
1626                                  &pcie_config_flags,
1627                                  sizeof(pcie_config_flags));
1628         if (ret != 0) {
1629                 ath10k_err("Failed to write pcie config_flags: %d\n", ret);
1630                 return ret;
1631         }
1632
1633         /* configure early allocation */
1634         ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
1635
1636         ret = ath10k_pci_diag_read_access(ar, ealloc_targ_addr, &ealloc_value);
1637         if (ret != 0) {
1638                 ath10k_err("Faile to get early alloc val: %d\n", ret);
1639                 return ret;
1640         }
1641
1642         /* first bank is switched to IRAM */
1643         ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
1644                          HI_EARLY_ALLOC_MAGIC_MASK);
1645         ealloc_value |= ((1 << HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
1646                          HI_EARLY_ALLOC_IRAM_BANKS_MASK);
1647
1648         ret = ath10k_pci_diag_write_access(ar, ealloc_targ_addr, ealloc_value);
1649         if (ret != 0) {
1650                 ath10k_err("Failed to set early alloc val: %d\n", ret);
1651                 return ret;
1652         }
1653
1654         /* Tell Target to proceed with initialization */
1655         flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
1656
1657         ret = ath10k_pci_diag_read_access(ar, flag2_targ_addr, &flag2_value);
1658         if (ret != 0) {
1659                 ath10k_err("Failed to get option val: %d\n", ret);
1660                 return ret;
1661         }
1662
1663         flag2_value |= HI_OPTION_EARLY_CFG_DONE;
1664
1665         ret = ath10k_pci_diag_write_access(ar, flag2_targ_addr, flag2_value);
1666         if (ret != 0) {
1667                 ath10k_err("Failed to set option val: %d\n", ret);
1668                 return ret;
1669         }
1670
1671         return 0;
1672 }
1673
1674
1675
1676 static int ath10k_pci_ce_init(struct ath10k *ar)
1677 {
1678         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1679         struct hif_ce_pipe_info *pipe_info;
1680         const struct ce_attr *attr;
1681         int pipe_num;
1682
1683         for (pipe_num = 0; pipe_num < ar_pci->ce_count; pipe_num++) {
1684                 pipe_info = &ar_pci->pipe_info[pipe_num];
1685                 pipe_info->pipe_num = pipe_num;
1686                 pipe_info->hif_ce_state = ar;
1687                 attr = &host_ce_config_wlan[pipe_num];
1688
1689                 pipe_info->ce_hdl = ath10k_ce_init(ar, pipe_num, attr);
1690                 if (pipe_info->ce_hdl == NULL) {
1691                         ath10k_err("Unable to initialize CE for pipe: %d\n",
1692                                    pipe_num);
1693
1694                         /* It is safe to call it here. It checks if ce_hdl is
1695                          * valid for each pipe */
1696                         ath10k_pci_ce_deinit(ar);
1697                         return -1;
1698                 }
1699
1700                 if (pipe_num == ar_pci->ce_count - 1) {
1701                         /*
1702                          * Reserve the ultimate CE for
1703                          * diagnostic Window support
1704                          */
1705                         ar_pci->ce_diag =
1706                         ar_pci->pipe_info[ar_pci->ce_count - 1].ce_hdl;
1707                         continue;
1708                 }
1709
1710                 pipe_info->buf_sz = (size_t) (attr->src_sz_max);
1711         }
1712
1713         /*
1714          * Initially, establish CE completion handlers for use with BMI.
1715          * These are overwritten with generic handlers after we exit BMI phase.
1716          */
1717         pipe_info = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1718         ath10k_ce_send_cb_register(pipe_info->ce_hdl,
1719                                    ath10k_pci_bmi_send_done, 0);
1720
1721         pipe_info = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1722         ath10k_ce_recv_cb_register(pipe_info->ce_hdl,
1723                                    ath10k_pci_bmi_recv_data);
1724
1725         return 0;
1726 }
1727
1728 static void ath10k_pci_fw_interrupt_handler(struct ath10k *ar)
1729 {
1730         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1731         u32 fw_indicator_address, fw_indicator;
1732
1733         ath10k_pci_wake(ar);
1734
1735         fw_indicator_address = ar_pci->fw_indicator_address;
1736         fw_indicator = ath10k_pci_read32(ar, fw_indicator_address);
1737
1738         if (fw_indicator & FW_IND_EVENT_PENDING) {
1739                 /* ACK: clear Target-side pending event */
1740                 ath10k_pci_write32(ar, fw_indicator_address,
1741                                    fw_indicator & ~FW_IND_EVENT_PENDING);
1742
1743                 if (ar_pci->started) {
1744                         ath10k_pci_hif_dump_area(ar);
1745                 } else {
1746                         /*
1747                          * Probable Target failure before we're prepared
1748                          * to handle it.  Generally unexpected.
1749                          */
1750                         ath10k_warn("early firmware event indicated\n");
1751                 }
1752         }
1753
1754         ath10k_pci_sleep(ar);
1755 }
1756
1757 static int ath10k_pci_hif_power_up(struct ath10k *ar)
1758 {
1759         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1760         int ret;
1761
1762         ret = ath10k_pci_start_intr(ar);
1763         if (ret) {
1764                 ath10k_err("could not start interrupt handling (%d)\n", ret);
1765                 goto err;
1766         }
1767
1768         /*
1769          * Bring the target up cleanly.
1770          *
1771          * The target may be in an undefined state with an AUX-powered Target
1772          * and a Host in WoW mode. If the Host crashes, loses power, or is
1773          * restarted (without unloading the driver) then the Target is left
1774          * (aux) powered and running. On a subsequent driver load, the Target
1775          * is in an unexpected state. We try to catch that here in order to
1776          * reset the Target and retry the probe.
1777          */
1778         ath10k_pci_device_reset(ar);
1779
1780         ret = ath10k_pci_reset_target(ar);
1781         if (ret)
1782                 goto err_irq;
1783
1784         if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
1785                 /* Force AWAKE forever */
1786                 ath10k_do_pci_wake(ar);
1787
1788         ret = ath10k_pci_ce_init(ar);
1789         if (ret)
1790                 goto err_ps;
1791
1792         ret = ath10k_pci_init_config(ar);
1793         if (ret)
1794                 goto err_ce;
1795
1796         ret = ath10k_pci_wake_target_cpu(ar);
1797         if (ret) {
1798                 ath10k_err("could not wake up target CPU (%d)\n", ret);
1799                 goto err_ce;
1800         }
1801
1802         return 0;
1803
1804 err_ce:
1805         ath10k_pci_ce_deinit(ar);
1806 err_ps:
1807         if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
1808                 ath10k_do_pci_sleep(ar);
1809 err_irq:
1810         ath10k_pci_stop_intr(ar);
1811 err:
1812         return ret;
1813 }
1814
1815 static void ath10k_pci_hif_power_down(struct ath10k *ar)
1816 {
1817         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1818
1819         ath10k_pci_stop_intr(ar);
1820
1821         ath10k_pci_ce_deinit(ar);
1822         if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
1823                 ath10k_do_pci_sleep(ar);
1824 }
1825
1826 #ifdef CONFIG_PM
1827
1828 #define ATH10K_PCI_PM_CONTROL 0x44
1829
1830 static int ath10k_pci_hif_suspend(struct ath10k *ar)
1831 {
1832         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1833         struct pci_dev *pdev = ar_pci->pdev;
1834         u32 val;
1835
1836         pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
1837
1838         if ((val & 0x000000ff) != 0x3) {
1839                 pci_save_state(pdev);
1840                 pci_disable_device(pdev);
1841                 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
1842                                        (val & 0xffffff00) | 0x03);
1843         }
1844
1845         return 0;
1846 }
1847
1848 static int ath10k_pci_hif_resume(struct ath10k *ar)
1849 {
1850         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1851         struct pci_dev *pdev = ar_pci->pdev;
1852         u32 val;
1853
1854         pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
1855
1856         if ((val & 0x000000ff) != 0) {
1857                 pci_restore_state(pdev);
1858                 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
1859                                        val & 0xffffff00);
1860                 /*
1861                  * Suspend/Resume resets the PCI configuration space,
1862                  * so we have to re-disable the RETRY_TIMEOUT register (0x41)
1863                  * to keep PCI Tx retries from interfering with C3 CPU state
1864                  */
1865                 pci_read_config_dword(pdev, 0x40, &val);
1866
1867                 if ((val & 0x0000ff00) != 0)
1868                         pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
1869         }
1870
1871         return 0;
1872 }
1873 #endif
1874
1875 static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
1876         .send_head              = ath10k_pci_hif_send_head,
1877         .exchange_bmi_msg       = ath10k_pci_hif_exchange_bmi_msg,
1878         .start                  = ath10k_pci_hif_start,
1879         .stop                   = ath10k_pci_hif_stop,
1880         .map_service_to_pipe    = ath10k_pci_hif_map_service_to_pipe,
1881         .get_default_pipe       = ath10k_pci_hif_get_default_pipe,
1882         .send_complete_check    = ath10k_pci_hif_send_complete_check,
1883         .set_callbacks          = ath10k_pci_hif_set_callbacks,
1884         .get_free_queue_number  = ath10k_pci_hif_get_free_queue_number,
1885         .power_up               = ath10k_pci_hif_power_up,
1886         .power_down             = ath10k_pci_hif_power_down,
1887 #ifdef CONFIG_PM
1888         .suspend                = ath10k_pci_hif_suspend,
1889         .resume                 = ath10k_pci_hif_resume,
1890 #endif
1891 };
1892
1893 static void ath10k_pci_ce_tasklet(unsigned long ptr)
1894 {
1895         struct hif_ce_pipe_info *pipe = (struct hif_ce_pipe_info *)ptr;
1896         struct ath10k_pci *ar_pci = pipe->ar_pci;
1897
1898         ath10k_ce_per_engine_service(ar_pci->ar, pipe->pipe_num);
1899 }
1900
1901 static void ath10k_msi_err_tasklet(unsigned long data)
1902 {
1903         struct ath10k *ar = (struct ath10k *)data;
1904
1905         ath10k_pci_fw_interrupt_handler(ar);
1906 }
1907
1908 /*
1909  * Handler for a per-engine interrupt on a PARTICULAR CE.
1910  * This is used in cases where each CE has a private MSI interrupt.
1911  */
1912 static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg)
1913 {
1914         struct ath10k *ar = arg;
1915         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1916         int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL;
1917
1918         if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) {
1919                 ath10k_warn("unexpected/invalid irq %d ce_id %d\n", irq, ce_id);
1920                 return IRQ_HANDLED;
1921         }
1922
1923         /*
1924          * NOTE: We are able to derive ce_id from irq because we
1925          * use a one-to-one mapping for CE's 0..5.
1926          * CE's 6 & 7 do not use interrupts at all.
1927          *
1928          * This mapping must be kept in sync with the mapping
1929          * used by firmware.
1930          */
1931         tasklet_schedule(&ar_pci->pipe_info[ce_id].intr);
1932         return IRQ_HANDLED;
1933 }
1934
1935 static irqreturn_t ath10k_pci_msi_fw_handler(int irq, void *arg)
1936 {
1937         struct ath10k *ar = arg;
1938         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1939
1940         tasklet_schedule(&ar_pci->msi_fw_err);
1941         return IRQ_HANDLED;
1942 }
1943
1944 /*
1945  * Top-level interrupt handler for all PCI interrupts from a Target.
1946  * When a block of MSI interrupts is allocated, this top-level handler
1947  * is not used; instead, we directly call the correct sub-handler.
1948  */
1949 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
1950 {
1951         struct ath10k *ar = arg;
1952         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1953
1954         if (ar_pci->num_msi_intrs == 0) {
1955                 /*
1956                  * IMPORTANT: INTR_CLR regiser has to be set after
1957                  * INTR_ENABLE is set to 0, otherwise interrupt can not be
1958                  * really cleared.
1959                  */
1960                 iowrite32(0, ar_pci->mem +
1961                           (SOC_CORE_BASE_ADDRESS |
1962                            PCIE_INTR_ENABLE_ADDRESS));
1963                 iowrite32(PCIE_INTR_FIRMWARE_MASK |
1964                           PCIE_INTR_CE_MASK_ALL,
1965                           ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
1966                                          PCIE_INTR_CLR_ADDRESS));
1967                 /*
1968                  * IMPORTANT: this extra read transaction is required to
1969                  * flush the posted write buffer.
1970                  */
1971                 (void) ioread32(ar_pci->mem +
1972                                 (SOC_CORE_BASE_ADDRESS |
1973                                  PCIE_INTR_ENABLE_ADDRESS));
1974         }
1975
1976         tasklet_schedule(&ar_pci->intr_tq);
1977
1978         return IRQ_HANDLED;
1979 }
1980
1981 static void ath10k_pci_tasklet(unsigned long data)
1982 {
1983         struct ath10k *ar = (struct ath10k *)data;
1984         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1985
1986         ath10k_pci_fw_interrupt_handler(ar); /* FIXME: Handle FW error */
1987         ath10k_ce_per_engine_service_any(ar);
1988
1989         if (ar_pci->num_msi_intrs == 0) {
1990                 /* Enable Legacy PCI line interrupts */
1991                 iowrite32(PCIE_INTR_FIRMWARE_MASK |
1992                           PCIE_INTR_CE_MASK_ALL,
1993                           ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
1994                                          PCIE_INTR_ENABLE_ADDRESS));
1995                 /*
1996                  * IMPORTANT: this extra read transaction is required to
1997                  * flush the posted write buffer
1998                  */
1999                 (void) ioread32(ar_pci->mem +
2000                                 (SOC_CORE_BASE_ADDRESS |
2001                                  PCIE_INTR_ENABLE_ADDRESS));
2002         }
2003 }
2004
2005 static int ath10k_pci_start_intr_msix(struct ath10k *ar, int num)
2006 {
2007         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2008         int ret;
2009         int i;
2010
2011         ret = pci_enable_msi_block(ar_pci->pdev, num);
2012         if (ret)
2013                 return ret;
2014
2015         ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW,
2016                           ath10k_pci_msi_fw_handler,
2017                           IRQF_SHARED, "ath10k_pci", ar);
2018         if (ret) {
2019                 ath10k_warn("request_irq(%d) failed %d\n",
2020                             ar_pci->pdev->irq + MSI_ASSIGN_FW, ret);
2021
2022                 pci_disable_msi(ar_pci->pdev);
2023                 return ret;
2024         }
2025
2026         for (i = MSI_ASSIGN_CE_INITIAL; i <= MSI_ASSIGN_CE_MAX; i++) {
2027                 ret = request_irq(ar_pci->pdev->irq + i,
2028                                   ath10k_pci_per_engine_handler,
2029                                   IRQF_SHARED, "ath10k_pci", ar);
2030                 if (ret) {
2031                         ath10k_warn("request_irq(%d) failed %d\n",
2032                                     ar_pci->pdev->irq + i, ret);
2033
2034                         for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--)
2035                                 free_irq(ar_pci->pdev->irq + i, ar);
2036
2037                         free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar);
2038                         pci_disable_msi(ar_pci->pdev);
2039                         return ret;
2040                 }
2041         }
2042
2043         ath10k_info("MSI-X interrupt handling (%d intrs)\n", num);
2044         return 0;
2045 }
2046
2047 static int ath10k_pci_start_intr_msi(struct ath10k *ar)
2048 {
2049         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2050         int ret;
2051
2052         ret = pci_enable_msi(ar_pci->pdev);
2053         if (ret < 0)
2054                 return ret;
2055
2056         ret = request_irq(ar_pci->pdev->irq,
2057                           ath10k_pci_interrupt_handler,
2058                           IRQF_SHARED, "ath10k_pci", ar);
2059         if (ret < 0) {
2060                 pci_disable_msi(ar_pci->pdev);
2061                 return ret;
2062         }
2063
2064         ath10k_info("MSI interrupt handling\n");
2065         return 0;
2066 }
2067
2068 static int ath10k_pci_start_intr_legacy(struct ath10k *ar)
2069 {
2070         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2071         int ret;
2072
2073         ret = request_irq(ar_pci->pdev->irq,
2074                           ath10k_pci_interrupt_handler,
2075                           IRQF_SHARED, "ath10k_pci", ar);
2076         if (ret < 0)
2077                 return ret;
2078
2079         /*
2080          * Make sure to wake the Target before enabling Legacy
2081          * Interrupt.
2082          */
2083         iowrite32(PCIE_SOC_WAKE_V_MASK,
2084                   ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
2085                   PCIE_SOC_WAKE_ADDRESS);
2086
2087         ath10k_pci_wait(ar);
2088
2089         /*
2090          * A potential race occurs here: The CORE_BASE write
2091          * depends on target correctly decoding AXI address but
2092          * host won't know when target writes BAR to CORE_CTRL.
2093          * This write might get lost if target has NOT written BAR.
2094          * For now, fix the race by repeating the write in below
2095          * synchronization checking.
2096          */
2097         iowrite32(PCIE_INTR_FIRMWARE_MASK |
2098                   PCIE_INTR_CE_MASK_ALL,
2099                   ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2100                                  PCIE_INTR_ENABLE_ADDRESS));
2101         iowrite32(PCIE_SOC_WAKE_RESET,
2102                   ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
2103                   PCIE_SOC_WAKE_ADDRESS);
2104
2105         ath10k_info("legacy interrupt handling\n");
2106         return 0;
2107 }
2108
2109 static int ath10k_pci_start_intr(struct ath10k *ar)
2110 {
2111         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2112         int num = MSI_NUM_REQUEST;
2113         int ret;
2114         int i;
2115
2116         tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long) ar);
2117         tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
2118                      (unsigned long) ar);
2119
2120         for (i = 0; i < CE_COUNT; i++) {
2121                 ar_pci->pipe_info[i].ar_pci = ar_pci;
2122                 tasklet_init(&ar_pci->pipe_info[i].intr,
2123                              ath10k_pci_ce_tasklet,
2124                              (unsigned long)&ar_pci->pipe_info[i]);
2125         }
2126
2127         if (!test_bit(ATH10K_PCI_FEATURE_MSI_X, ar_pci->features))
2128                 num = 1;
2129
2130         if (num > 1) {
2131                 ret = ath10k_pci_start_intr_msix(ar, num);
2132                 if (ret == 0)
2133                         goto exit;
2134
2135                 ath10k_warn("MSI-X didn't succeed (%d), trying MSI\n", ret);
2136                 num = 1;
2137         }
2138
2139         if (num == 1) {
2140                 ret = ath10k_pci_start_intr_msi(ar);
2141                 if (ret == 0)
2142                         goto exit;
2143
2144                 ath10k_warn("MSI didn't succeed (%d), trying legacy INTR\n",
2145                             ret);
2146                 num = 0;
2147         }
2148
2149         ret = ath10k_pci_start_intr_legacy(ar);
2150
2151 exit:
2152         ar_pci->num_msi_intrs = num;
2153         ar_pci->ce_count = CE_COUNT;
2154         return ret;
2155 }
2156
2157 static void ath10k_pci_stop_intr(struct ath10k *ar)
2158 {
2159         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2160         int i;
2161
2162         /* There's at least one interrupt irregardless whether its legacy INTR
2163          * or MSI or MSI-X */
2164         for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
2165                 free_irq(ar_pci->pdev->irq + i, ar);
2166
2167         if (ar_pci->num_msi_intrs > 0)
2168                 pci_disable_msi(ar_pci->pdev);
2169 }
2170
2171 static int ath10k_pci_reset_target(struct ath10k *ar)
2172 {
2173         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2174         int wait_limit = 300; /* 3 sec */
2175
2176         /* Wait for Target to finish initialization before we proceed. */
2177         iowrite32(PCIE_SOC_WAKE_V_MASK,
2178                   ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
2179                   PCIE_SOC_WAKE_ADDRESS);
2180
2181         ath10k_pci_wait(ar);
2182
2183         while (wait_limit-- &&
2184                !(ioread32(ar_pci->mem + FW_INDICATOR_ADDRESS) &
2185                  FW_IND_INITIALIZED)) {
2186                 if (ar_pci->num_msi_intrs == 0)
2187                         /* Fix potential race by repeating CORE_BASE writes */
2188                         iowrite32(PCIE_INTR_FIRMWARE_MASK |
2189                                   PCIE_INTR_CE_MASK_ALL,
2190                                   ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2191                                                  PCIE_INTR_ENABLE_ADDRESS));
2192                 mdelay(10);
2193         }
2194
2195         if (wait_limit < 0) {
2196                 ath10k_err("Target stalled\n");
2197                 iowrite32(PCIE_SOC_WAKE_RESET,
2198                           ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
2199                           PCIE_SOC_WAKE_ADDRESS);
2200                 return -EIO;
2201         }
2202
2203         iowrite32(PCIE_SOC_WAKE_RESET,
2204                   ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
2205                   PCIE_SOC_WAKE_ADDRESS);
2206
2207         return 0;
2208 }
2209
2210 static void ath10k_pci_device_reset(struct ath10k *ar)
2211 {
2212         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2213         void __iomem *mem = ar_pci->mem;
2214         int i;
2215         u32 val;
2216
2217         if (!SOC_GLOBAL_RESET_ADDRESS)
2218                 return;
2219
2220         if (!mem)
2221                 return;
2222
2223         ath10k_pci_reg_write32(mem, PCIE_SOC_WAKE_ADDRESS,
2224                                PCIE_SOC_WAKE_V_MASK);
2225         for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2226                 if (ath10k_pci_target_is_awake(ar))
2227                         break;
2228                 msleep(1);
2229         }
2230
2231         /* Put Target, including PCIe, into RESET. */
2232         val = ath10k_pci_reg_read32(mem, SOC_GLOBAL_RESET_ADDRESS);
2233         val |= 1;
2234         ath10k_pci_reg_write32(mem, SOC_GLOBAL_RESET_ADDRESS, val);
2235
2236         for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2237                 if (ath10k_pci_reg_read32(mem, RTC_STATE_ADDRESS) &
2238                                           RTC_STATE_COLD_RESET_MASK)
2239                         break;
2240                 msleep(1);
2241         }
2242
2243         /* Pull Target, including PCIe, out of RESET. */
2244         val &= ~1;
2245         ath10k_pci_reg_write32(mem, SOC_GLOBAL_RESET_ADDRESS, val);
2246
2247         for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2248                 if (!(ath10k_pci_reg_read32(mem, RTC_STATE_ADDRESS) &
2249                                             RTC_STATE_COLD_RESET_MASK))
2250                         break;
2251                 msleep(1);
2252         }
2253
2254         ath10k_pci_reg_write32(mem, PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_RESET);
2255 }
2256
2257 static void ath10k_pci_dump_features(struct ath10k_pci *ar_pci)
2258 {
2259         int i;
2260
2261         for (i = 0; i < ATH10K_PCI_FEATURE_COUNT; i++) {
2262                 if (!test_bit(i, ar_pci->features))
2263                         continue;
2264
2265                 switch (i) {
2266                 case ATH10K_PCI_FEATURE_MSI_X:
2267                         ath10k_dbg(ATH10K_DBG_PCI, "device supports MSI-X\n");
2268                         break;
2269                 case ATH10K_PCI_FEATURE_SOC_POWER_SAVE:
2270                         ath10k_dbg(ATH10K_DBG_PCI, "QCA98XX SoC power save enabled\n");
2271                         break;
2272                 }
2273         }
2274 }
2275
2276 static int ath10k_pci_probe(struct pci_dev *pdev,
2277                             const struct pci_device_id *pci_dev)
2278 {
2279         void __iomem *mem;
2280         int ret = 0;
2281         struct ath10k *ar;
2282         struct ath10k_pci *ar_pci;
2283         u32 lcr_val;
2284
2285         ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
2286
2287         ar_pci = kzalloc(sizeof(*ar_pci), GFP_KERNEL);
2288         if (ar_pci == NULL)
2289                 return -ENOMEM;
2290
2291         ar_pci->pdev = pdev;
2292         ar_pci->dev = &pdev->dev;
2293
2294         switch (pci_dev->device) {
2295         case QCA988X_2_0_DEVICE_ID:
2296                 set_bit(ATH10K_PCI_FEATURE_MSI_X, ar_pci->features);
2297                 break;
2298         default:
2299                 ret = -ENODEV;
2300                 ath10k_err("Unkown device ID: %d\n", pci_dev->device);
2301                 goto err_ar_pci;
2302         }
2303
2304         if (ath10k_target_ps)
2305                 set_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features);
2306
2307         ath10k_pci_dump_features(ar_pci);
2308
2309         ar = ath10k_core_create(ar_pci, ar_pci->dev, &ath10k_pci_hif_ops);
2310         if (!ar) {
2311                 ath10k_err("ath10k_core_create failed!\n");
2312                 ret = -EINVAL;
2313                 goto err_ar_pci;
2314         }
2315
2316         ar_pci->ar = ar;
2317         ar_pci->fw_indicator_address = FW_INDICATOR_ADDRESS;
2318         atomic_set(&ar_pci->keep_awake_count, 0);
2319
2320         pci_set_drvdata(pdev, ar);
2321
2322         /*
2323          * Without any knowledge of the Host, the Target may have been reset or
2324          * power cycled and its Config Space may no longer reflect the PCI
2325          * address space that was assigned earlier by the PCI infrastructure.
2326          * Refresh it now.
2327          */
2328         ret = pci_assign_resource(pdev, BAR_NUM);
2329         if (ret) {
2330                 ath10k_err("cannot assign PCI space: %d\n", ret);
2331                 goto err_ar;
2332         }
2333
2334         ret = pci_enable_device(pdev);
2335         if (ret) {
2336                 ath10k_err("cannot enable PCI device: %d\n", ret);
2337                 goto err_ar;
2338         }
2339
2340         /* Request MMIO resources */
2341         ret = pci_request_region(pdev, BAR_NUM, "ath");
2342         if (ret) {
2343                 ath10k_err("PCI MMIO reservation error: %d\n", ret);
2344                 goto err_device;
2345         }
2346
2347         /*
2348          * Target structures have a limit of 32 bit DMA pointers.
2349          * DMA pointers can be wider than 32 bits by default on some systems.
2350          */
2351         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2352         if (ret) {
2353                 ath10k_err("32-bit DMA not available: %d\n", ret);
2354                 goto err_region;
2355         }
2356
2357         ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2358         if (ret) {
2359                 ath10k_err("cannot enable 32-bit consistent DMA\n");
2360                 goto err_region;
2361         }
2362
2363         /* Set bus master bit in PCI_COMMAND to enable DMA */
2364         pci_set_master(pdev);
2365
2366         /*
2367          * Temporary FIX: disable ASPM
2368          * Will be removed after the OTP is programmed
2369          */
2370         pci_read_config_dword(pdev, 0x80, &lcr_val);
2371         pci_write_config_dword(pdev, 0x80, (lcr_val & 0xffffff00));
2372
2373         /* Arrange for access to Target SoC registers. */
2374         mem = pci_iomap(pdev, BAR_NUM, 0);
2375         if (!mem) {
2376                 ath10k_err("PCI iomap error\n");
2377                 ret = -EIO;
2378                 goto err_master;
2379         }
2380
2381         ar_pci->mem = mem;
2382
2383         spin_lock_init(&ar_pci->ce_lock);
2384
2385         ar_pci->cacheline_sz = dma_get_cache_alignment();
2386
2387         ret = ath10k_core_register(ar);
2388         if (ret) {
2389                 ath10k_err("could not register driver core (%d)\n", ret);
2390                 goto err_iomap;
2391         }
2392
2393         return 0;
2394
2395 err_iomap:
2396         pci_iounmap(pdev, mem);
2397 err_master:
2398         pci_clear_master(pdev);
2399 err_region:
2400         pci_release_region(pdev, BAR_NUM);
2401 err_device:
2402         pci_disable_device(pdev);
2403 err_ar:
2404         pci_set_drvdata(pdev, NULL);
2405         ath10k_core_destroy(ar);
2406 err_ar_pci:
2407         /* call HIF PCI free here */
2408         kfree(ar_pci);
2409
2410         return ret;
2411 }
2412
2413 static void ath10k_pci_remove(struct pci_dev *pdev)
2414 {
2415         struct ath10k *ar = pci_get_drvdata(pdev);
2416         struct ath10k_pci *ar_pci;
2417
2418         ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
2419
2420         if (!ar)
2421                 return;
2422
2423         ar_pci = ath10k_pci_priv(ar);
2424
2425         if (!ar_pci)
2426                 return;
2427
2428         tasklet_kill(&ar_pci->msi_fw_err);
2429
2430         ath10k_core_unregister(ar);
2431
2432         pci_set_drvdata(pdev, NULL);
2433         pci_iounmap(pdev, ar_pci->mem);
2434         pci_release_region(pdev, BAR_NUM);
2435         pci_clear_master(pdev);
2436         pci_disable_device(pdev);
2437
2438         ath10k_core_destroy(ar);
2439         kfree(ar_pci);
2440 }
2441
2442 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
2443
2444 static struct pci_driver ath10k_pci_driver = {
2445         .name = "ath10k_pci",
2446         .id_table = ath10k_pci_id_table,
2447         .probe = ath10k_pci_probe,
2448         .remove = ath10k_pci_remove,
2449 };
2450
2451 static int __init ath10k_pci_init(void)
2452 {
2453         int ret;
2454
2455         ret = pci_register_driver(&ath10k_pci_driver);
2456         if (ret)
2457                 ath10k_err("pci_register_driver failed [%d]\n", ret);
2458
2459         return ret;
2460 }
2461 module_init(ath10k_pci_init);
2462
2463 static void __exit ath10k_pci_exit(void)
2464 {
2465         pci_unregister_driver(&ath10k_pci_driver);
2466 }
2467
2468 module_exit(ath10k_pci_exit);
2469
2470 MODULE_AUTHOR("Qualcomm Atheros");
2471 MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
2472 MODULE_LICENSE("Dual BSD/GPL");
2473 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_FILE);
2474 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_OTP_FILE);
2475 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);