drivers/net/wireless/ath/ath10k/pci.c

   1 /*
   2  * Copyright (c) 2005-2011 Atheros Communications Inc.
   3  * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  */
  17
  18 #include <linux/pci.h>
  19 #include <linux/module.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/spinlock.h>
  22
  23 #include "core.h"
  24 #include "debug.h"
  25
  26 #include "targaddrs.h"
  27 #include "bmi.h"
  28
  29 #include "hif.h"
  30 #include "htc.h"
  31
  32 #include "ce.h"
  33 #include "pci.h"
  34
  35 static unsigned int ath10k_target_ps;
  36 module_param(ath10k_target_ps, uint, 0644);
  37 MODULE_PARM_DESC(ath10k_target_ps, "Enable ath10k Target (SoC) PS option");
  38
  39 #define QCA988X_2_0_DEVICE_ID   (0x003c)
  40
  41 static DEFINE_PCI_DEVICE_TABLE(ath10k_pci_id_table) = {
  42         { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
  43         {0}
  44 };
  45
  46 static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
  47                                        u32 *data);
  48
  49 static void ath10k_pci_process_ce(struct ath10k *ar);
  50 static int ath10k_pci_post_rx(struct ath10k *ar);
  51 static int ath10k_pci_post_rx_pipe(struct hif_ce_pipe_info *pipe_info,
  52                                              int num);
  53 static void ath10k_pci_rx_pipe_cleanup(struct hif_ce_pipe_info *pipe_info);
  54 static void ath10k_pci_stop_ce(struct ath10k *ar);
  55 static void ath10k_pci_device_reset(struct ath10k *ar);
  56 static int ath10k_pci_reset_target(struct ath10k *ar);
  57 static int ath10k_pci_start_intr(struct ath10k *ar);
  58 static void ath10k_pci_stop_intr(struct ath10k *ar);
  59
  60 static const struct ce_attr host_ce_config_wlan[] = {
  61         /* host->target HTC control and raw streams */
  62         { /* CE0 */ CE_ATTR_FLAGS, 0, 16, 256, 0, NULL,},
  63         /* could be moved to share CE3 */
  64         /* target->host HTT + HTC control */
  65         { /* CE1 */ CE_ATTR_FLAGS, 0, 0, 512, 512, NULL,},
  66         /* target->host WMI */
  67         { /* CE2 */ CE_ATTR_FLAGS, 0, 0, 2048, 32, NULL,},
  68         /* host->target WMI */
  69         { /* CE3 */ CE_ATTR_FLAGS, 0, 32, 2048, 0, NULL,},
  70         /* host->target HTT */
  71         { /* CE4 */ CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 0,
  72                     CE_HTT_H2T_MSG_SRC_NENTRIES, 256, 0, NULL,},
  73         /* unused */
  74         { /* CE5 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
  75         /* Target autonomous hif_memcpy */
  76         { /* CE6 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
  77         /* ce_diag, the Diagnostic Window */
  78         { /* CE7 */ CE_ATTR_FLAGS, 0, 2, DIAG_TRANSFER_LIMIT, 2, NULL,},
  79 };
  80
  81 /* Target firmware's Copy Engine configuration. */
  82 static const struct ce_pipe_config target_ce_config_wlan[] = {
  83         /* host->target HTC control and raw streams */
  84         { /* CE0 */ 0, PIPEDIR_OUT, 32, 256, CE_ATTR_FLAGS, 0,},
  85         /* target->host HTT + HTC control */
  86         { /* CE1 */ 1, PIPEDIR_IN, 32, 512, CE_ATTR_FLAGS, 0,},
  87         /* target->host WMI */
  88         { /* CE2 */ 2, PIPEDIR_IN, 32, 2048, CE_ATTR_FLAGS, 0,},
  89         /* host->target WMI */
  90         { /* CE3 */ 3, PIPEDIR_OUT, 32, 2048, CE_ATTR_FLAGS, 0,},
  91         /* host->target HTT */
  92         { /* CE4 */ 4, PIPEDIR_OUT, 256, 256, CE_ATTR_FLAGS, 0,},
  93         /* NB: 50% of src nentries, since tx has 2 frags */
  94         /* unused */
  95         { /* CE5 */ 5, PIPEDIR_OUT, 32, 2048, CE_ATTR_FLAGS, 0,},
  96         /* Reserved for target autonomous hif_memcpy */
  97         { /* CE6 */ 6, PIPEDIR_INOUT, 32, 4096, CE_ATTR_FLAGS, 0,},
  98         /* CE7 used only by Host */
  99 };
 100
 101 /*
 102  * Diagnostic read/write access is provided for startup/config/debug usage.
 103  * Caller must guarantee proper alignment, when applicable, and single user
 104  * at any moment.
 105  */
 106 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
 107                                     int nbytes)
 108 {
 109         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 110         int ret = 0;
 111         u32 buf;
 112         unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
 113         unsigned int id;
 114         unsigned int flags;
 115         struct ce_state *ce_diag;
 116         /* Host buffer address in CE space */
 117         u32 ce_data;
 118         dma_addr_t ce_data_base = 0;
 119         void *data_buf = NULL;
 120         int i;
 121
 122         /*
 123          * This code cannot handle reads to non-memory space. Redirect to the
 124          * register read fn but preserve the multi word read capability of
 125          * this fn
 126          */
 127         if (address < DRAM_BASE_ADDRESS) {
 128                 if (!IS_ALIGNED(address, 4) ||
 129                     !IS_ALIGNED((unsigned long)data, 4))
 130                         return -EIO;
 131
 132                 while ((nbytes >= 4) &&  ((ret = ath10k_pci_diag_read_access(
 133                                            ar, address, (u32 *)data)) == 0)) {
 134                         nbytes -= sizeof(u32);
 135                         address += sizeof(u32);
 136                         data += sizeof(u32);
 137                 }
 138                 return ret;
 139         }
 140
 141         ce_diag = ar_pci->ce_diag;
 142
 143         /*
 144          * Allocate a temporary bounce buffer to hold caller's data
 145          * to be DMA'ed from Target. This guarantees
 146          *   1) 4-byte alignment
 147          *   2) Buffer in DMA-able space
 148          */
 149         orig_nbytes = nbytes;
 150         data_buf = (unsigned char *)pci_alloc_consistent(ar_pci->pdev,
 151                                                          orig_nbytes,
 152                                                          &ce_data_base);
 153
 154         if (!data_buf) {
 155                 ret = -ENOMEM;
 156                 goto done;
 157         }
 158         memset(data_buf, 0, orig_nbytes);
 159
 160         remaining_bytes = orig_nbytes;
 161         ce_data = ce_data_base;
 162         while (remaining_bytes) {
 163                 nbytes = min_t(unsigned int, remaining_bytes,
 164                                DIAG_TRANSFER_LIMIT);
 165
 166                 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, ce_data);
 167                 if (ret != 0)
 168                         goto done;
 169
 170                 /* Request CE to send from Target(!) address to Host buffer */
 171                 /*
 172                  * The address supplied by the caller is in the
 173                  * Target CPU virtual address space.
 174                  *
 175                  * In order to use this address with the diagnostic CE,
 176                  * convert it from Target CPU virtual address space
 177                  * to CE address space
 178                  */
 179                 ath10k_pci_wake(ar);
 180                 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem,
 181                                                      address);
 182                 ath10k_pci_sleep(ar);
 183
 184                 ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0,
 185                                  0);
 186                 if (ret)
 187                         goto done;
 188
 189                 i = 0;
 190                 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
 191                                                      &completed_nbytes,
 192                                                      &id) != 0) {
 193                         mdelay(1);
 194                         if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
 195                                 ret = -EBUSY;
 196                                 goto done;
 197                         }
 198                 }
 199
 200                 if (nbytes != completed_nbytes) {
 201                         ret = -EIO;
 202                         goto done;
 203                 }
 204
 205                 if (buf != (u32) address) {
 206                         ret = -EIO;
 207                         goto done;
 208                 }
 209
 210                 i = 0;
 211                 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
 212                                                      &completed_nbytes,
 213                                                      &id, &flags) != 0) {
 214                         mdelay(1);
 215
 216                         if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
 217                                 ret = -EBUSY;
 218                                 goto done;
 219                         }
 220                 }
 221
 222                 if (nbytes != completed_nbytes) {
 223                         ret = -EIO;
 224                         goto done;
 225                 }
 226
 227                 if (buf != ce_data) {
 228                         ret = -EIO;
 229                         goto done;
 230                 }
 231
 232                 remaining_bytes -= nbytes;
 233                 address += nbytes;
 234                 ce_data += nbytes;
 235         }
 236
 237 done:
 238         if (ret == 0) {
 239                 /* Copy data from allocated DMA buf to caller's buf */
 240                 WARN_ON_ONCE(orig_nbytes & 3);
 241                 for (i = 0; i < orig_nbytes / sizeof(__le32); i++) {
 242                         ((u32 *)data)[i] =
 243                                 __le32_to_cpu(((__le32 *)data_buf)[i]);
 244                 }
 245         } else
 246                 ath10k_dbg(ATH10K_DBG_PCI, "%s failure (0x%x)\n",
 247                            __func__, address);
 248
 249         if (data_buf)
 250                 pci_free_consistent(ar_pci->pdev, orig_nbytes,
 251                                     data_buf, ce_data_base);
 252
 253         return ret;
 254 }
 255
 256 /* Read 4-byte aligned data from Target memory or register */
 257 static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
 258                                        u32 *data)
 259 {
 260         /* Assume range doesn't cross this boundary */
 261         if (address >= DRAM_BASE_ADDRESS)
 262                 return ath10k_pci_diag_read_mem(ar, address, data, sizeof(u32));
 263
 264         ath10k_pci_wake(ar);
 265         *data = ath10k_pci_read32(ar, address);
 266         ath10k_pci_sleep(ar);
 267         return 0;
 268 }
 269
 270 static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
 271                                      const void *data, int nbytes)
 272 {
 273         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 274         int ret = 0;
 275         u32 buf;
 276         unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
 277         unsigned int id;
 278         unsigned int flags;
 279         struct ce_state *ce_diag;
 280         void *data_buf = NULL;
 281         u32 ce_data;    /* Host buffer address in CE space */
 282         dma_addr_t ce_data_base = 0;
 283         int i;
 284
 285         ce_diag = ar_pci->ce_diag;
 286
 287         /*
 288          * Allocate a temporary bounce buffer to hold caller's data
 289          * to be DMA'ed to Target. This guarantees
 290          *   1) 4-byte alignment
 291          *   2) Buffer in DMA-able space
 292          */
 293         orig_nbytes = nbytes;
 294         data_buf = (unsigned char *)pci_alloc_consistent(ar_pci->pdev,
 295                                                          orig_nbytes,
 296                                                          &ce_data_base);
 297         if (!data_buf) {
 298                 ret = -ENOMEM;
 299                 goto done;
 300         }
 301
 302         /* Copy caller's data to allocated DMA buf */
 303         WARN_ON_ONCE(orig_nbytes & 3);
 304         for (i = 0; i < orig_nbytes / sizeof(__le32); i++)
 305                 ((__le32 *)data_buf)[i] = __cpu_to_le32(((u32 *)data)[i]);
 306
 307         /*
 308          * The address supplied by the caller is in the
 309          * Target CPU virtual address space.
 310          *
 311          * In order to use this address with the diagnostic CE,
 312          * convert it from
 313          *    Target CPU virtual address space
 314          * to
 315          *    CE address space
 316          */
 317         ath10k_pci_wake(ar);
 318         address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, address);
 319         ath10k_pci_sleep(ar);
 320
 321         remaining_bytes = orig_nbytes;
 322         ce_data = ce_data_base;
 323         while (remaining_bytes) {
 324                 /* FIXME: check cast */
 325                 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
 326
 327                 /* Set up to receive directly into Target(!) address */
 328                 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, address);
 329                 if (ret != 0)
 330                         goto done;
 331
 332                 /*
 333                  * Request CE to send caller-supplied data that
 334                  * was copied to bounce buffer to Target(!) address.
 335                  */
 336                 ret = ath10k_ce_send(ce_diag, NULL, (u32) ce_data,
 337                                      nbytes, 0, 0);
 338                 if (ret != 0)
 339                         goto done;
 340
 341                 i = 0;
 342                 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
 343                                                      &completed_nbytes,
 344                                                      &id) != 0) {
 345                         mdelay(1);
 346
 347                         if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
 348                                 ret = -EBUSY;
 349                                 goto done;
 350                         }
 351                 }
 352
 353                 if (nbytes != completed_nbytes) {
 354                         ret = -EIO;
 355                         goto done;
 356                 }
 357
 358                 if (buf != ce_data) {
 359                         ret = -EIO;
 360                         goto done;
 361                 }
 362
 363                 i = 0;
 364                 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
 365                                                      &completed_nbytes,
 366                                                      &id, &flags) != 0) {
 367                         mdelay(1);
 368
 369                         if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
 370                                 ret = -EBUSY;
 371                                 goto done;
 372                         }
 373                 }
 374
 375                 if (nbytes != completed_nbytes) {
 376                         ret = -EIO;
 377                         goto done;
 378                 }
 379
 380                 if (buf != address) {
 381                         ret = -EIO;
 382                         goto done;
 383                 }
 384
 385                 remaining_bytes -= nbytes;
 386                 address += nbytes;
 387                 ce_data += nbytes;
 388         }
 389
 390 done:
 391         if (data_buf) {
 392                 pci_free_consistent(ar_pci->pdev, orig_nbytes, data_buf,
 393                                     ce_data_base);
 394         }
 395
 396         if (ret != 0)
 397                 ath10k_dbg(ATH10K_DBG_PCI, "%s failure (0x%x)\n", __func__,
 398                            address);
 399
 400         return ret;
 401 }
 402
 403 /* Write 4B data to Target memory or register */
 404 static int ath10k_pci_diag_write_access(struct ath10k *ar, u32 address,
 405                                         u32 data)
 406 {
 407         /* Assume range doesn't cross this boundary */
 408         if (address >= DRAM_BASE_ADDRESS)
 409                 return ath10k_pci_diag_write_mem(ar, address, &data,
 410                                                  sizeof(u32));
 411
 412         ath10k_pci_wake(ar);
 413         ath10k_pci_write32(ar, address, data);
 414         ath10k_pci_sleep(ar);
 415         return 0;
 416 }
 417
 418 static bool ath10k_pci_target_is_awake(struct ath10k *ar)
 419 {
 420         void __iomem *mem = ath10k_pci_priv(ar)->mem;
 421         u32 val;
 422         val = ioread32(mem + PCIE_LOCAL_BASE_ADDRESS +
 423                        RTC_STATE_ADDRESS);
 424         return (RTC_STATE_V_GET(val) == RTC_STATE_V_ON);
 425 }
 426
 427 static void ath10k_pci_wait(struct ath10k *ar)
 428 {
 429         int n = 100;
 430
 431         while (n-- && !ath10k_pci_target_is_awake(ar))
 432                 msleep(10);
 433
 434         if (n < 0)
 435                 ath10k_warn("Unable to wakeup target\n");
 436 }
 437
 438 void ath10k_do_pci_wake(struct ath10k *ar)
 439 {
 440         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 441         void __iomem *pci_addr = ar_pci->mem;
 442         int tot_delay = 0;
 443         int curr_delay = 5;
 444
 445         if (atomic_read(&ar_pci->keep_awake_count) == 0) {
 446                 /* Force AWAKE */
 447                 iowrite32(PCIE_SOC_WAKE_V_MASK,
 448                           pci_addr + PCIE_LOCAL_BASE_ADDRESS +
 449                           PCIE_SOC_WAKE_ADDRESS);
 450         }
 451         atomic_inc(&ar_pci->keep_awake_count);
 452
 453         if (ar_pci->verified_awake)
 454                 return;
 455
 456         for (;;) {
 457                 if (ath10k_pci_target_is_awake(ar)) {
 458                         ar_pci->verified_awake = true;
 459                         break;
 460                 }
 461
 462                 if (tot_delay > PCIE_WAKE_TIMEOUT) {
 463                         ath10k_warn("target takes too long to wake up (awake count %d)\n",
 464                                     atomic_read(&ar_pci->keep_awake_count));
 465                         break;
 466                 }
 467
 468                 udelay(curr_delay);
 469                 tot_delay += curr_delay;
 470
 471                 if (curr_delay < 50)
 472                         curr_delay += 5;
 473         }
 474 }
 475
 476 void ath10k_do_pci_sleep(struct ath10k *ar)
 477 {
 478         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 479         void __iomem *pci_addr = ar_pci->mem;
 480
 481         if (atomic_dec_and_test(&ar_pci->keep_awake_count)) {
 482                 /* Allow sleep */
 483                 ar_pci->verified_awake = false;
 484                 iowrite32(PCIE_SOC_WAKE_RESET,
 485                           pci_addr + PCIE_LOCAL_BASE_ADDRESS +
 486                           PCIE_SOC_WAKE_ADDRESS);
 487         }
 488 }
 489
 490 /*
 491  * FIXME: Handle OOM properly.
 492  */
 493 static inline
 494 struct ath10k_pci_compl *get_free_compl(struct hif_ce_pipe_info *pipe_info)
 495 {
 496         struct ath10k_pci_compl *compl = NULL;
 497
 498         spin_lock_bh(&pipe_info->pipe_lock);
 499         if (list_empty(&pipe_info->compl_free)) {
 500                 ath10k_warn("Completion buffers are full\n");
 501                 goto exit;
 502         }
 503         compl = list_first_entry(&pipe_info->compl_free,
 504                                  struct ath10k_pci_compl, list);
 505         list_del(&compl->list);
 506 exit:
 507         spin_unlock_bh(&pipe_info->pipe_lock);
 508         return compl;
 509 }
 510
 511 /* Called by lower (CE) layer when a send to Target completes. */
 512 static void ath10k_pci_ce_send_done(struct ce_state *ce_state,
 513                                     void *transfer_context,
 514                                     u32 ce_data,
 515                                     unsigned int nbytes,
 516                                     unsigned int transfer_id)
 517 {
 518         struct ath10k *ar = ce_state->ar;
 519         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 520         struct hif_ce_pipe_info *pipe_info =  &ar_pci->pipe_info[ce_state->id];
 521         struct ath10k_pci_compl *compl;
 522         bool process = false;
 523
 524         do {
 525                 /*
 526                  * For the send completion of an item in sendlist, just
 527                  * increment num_sends_allowed. The upper layer callback will
 528                  * be triggered when last fragment is done with send.
 529                  */
 530                 if (transfer_context == CE_SENDLIST_ITEM_CTXT) {
 531                         spin_lock_bh(&pipe_info->pipe_lock);
 532                         pipe_info->num_sends_allowed++;
 533                         spin_unlock_bh(&pipe_info->pipe_lock);
 534                         continue;
 535                 }
 536
 537                 compl = get_free_compl(pipe_info);
 538                 if (!compl)
 539                         break;
 540
 541                 compl->state = ATH10K_PCI_COMPL_SEND;
 542                 compl->ce_state = ce_state;
 543                 compl->pipe_info = pipe_info;
 544                 compl->transfer_context = transfer_context;
 545                 compl->nbytes = nbytes;
 546                 compl->transfer_id = transfer_id;
 547                 compl->flags = 0;
 548
 549                 /*
 550                  * Add the completion to the processing queue.
 551                  */
 552                 spin_lock_bh(&ar_pci->compl_lock);
 553                 list_add_tail(&compl->list, &ar_pci->compl_process);
 554                 spin_unlock_bh(&ar_pci->compl_lock);
 555
 556                 process = true;
 557         } while (ath10k_ce_completed_send_next(ce_state,
 558                                                            &transfer_context,
 559                                                            &ce_data, &nbytes,
 560                                                            &transfer_id) == 0);
 561
 562         /*
 563          * If only some of the items within a sendlist have completed,
 564          * don't invoke completion processing until the entire sendlist
 565          * has been sent.
 566          */
 567         if (!process)
 568                 return;
 569
 570         ath10k_pci_process_ce(ar);
 571 }
 572
 573 /* Called by lower (CE) layer when data is received from the Target. */
 574 static void ath10k_pci_ce_recv_data(struct ce_state *ce_state,
 575                                     void *transfer_context, u32 ce_data,
 576                                     unsigned int nbytes,
 577                                     unsigned int transfer_id,
 578                                     unsigned int flags)
 579 {
 580         struct ath10k *ar = ce_state->ar;
 581         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 582         struct hif_ce_pipe_info *pipe_info =  &ar_pci->pipe_info[ce_state->id];
 583         struct ath10k_pci_compl *compl;
 584         struct sk_buff *skb;
 585
 586         do {
 587                 compl = get_free_compl(pipe_info);
 588                 if (!compl)
 589                         break;
 590
 591                 compl->state = ATH10K_PCI_COMPL_RECV;
 592                 compl->ce_state = ce_state;
 593                 compl->pipe_info = pipe_info;
 594                 compl->transfer_context = transfer_context;
 595                 compl->nbytes = nbytes;
 596                 compl->transfer_id = transfer_id;
 597                 compl->flags = flags;
 598
 599                 skb = transfer_context;
 600                 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
 601                                  skb->len + skb_tailroom(skb),
 602                                  DMA_FROM_DEVICE);
 603                 /*
 604                  * Add the completion to the processing queue.
 605                  */
 606                 spin_lock_bh(&ar_pci->compl_lock);
 607                 list_add_tail(&compl->list, &ar_pci->compl_process);
 608                 spin_unlock_bh(&ar_pci->compl_lock);
 609
 610         } while (ath10k_ce_completed_recv_next(ce_state,
 611                                                            &transfer_context,
 612                                                            &ce_data, &nbytes,
 613                                                            &transfer_id,
 614                                                            &flags) == 0);
 615
 616         ath10k_pci_process_ce(ar);
 617 }
 618
 619 /* Send the first nbytes bytes of the buffer */
 620 static int ath10k_pci_hif_send_head(struct ath10k *ar, u8 pipe_id,
 621                                     unsigned int transfer_id,
 622                                     unsigned int bytes, struct sk_buff *nbuf)
 623 {
 624         struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(nbuf);
 625         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 626         struct hif_ce_pipe_info *pipe_info = &(ar_pci->pipe_info[pipe_id]);
 627         struct ce_state *ce_hdl = pipe_info->ce_hdl;
 628         struct ce_sendlist sendlist;
 629         unsigned int len;
 630         u32 flags = 0;
 631         int ret;
 632
 633         memset(&sendlist, 0, sizeof(struct ce_sendlist));
 634
 635         len = min(bytes, nbuf->len);
 636         bytes -= len;
 637
 638         if (len & 3)
 639                 ath10k_warn("skb not aligned to 4-byte boundary (%d)\n", len);
 640
 641         ath10k_dbg(ATH10K_DBG_PCI,
 642                    "pci send data vaddr %p paddr 0x%llx len %d as %d bytes\n",
 643                    nbuf->data, (unsigned long long) skb_cb->paddr,
 644                    nbuf->len, len);
 645         ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL,
 646                         "ath10k tx: data: ",
 647                         nbuf->data, nbuf->len);
 648
 649         ath10k_ce_sendlist_buf_add(&sendlist, skb_cb->paddr, len, flags);
 650
 651         /* Make sure we have resources to handle this request */
 652         spin_lock_bh(&pipe_info->pipe_lock);
 653         if (!pipe_info->num_sends_allowed) {
 654                 ath10k_warn("Pipe: %d is full\n", pipe_id);
 655                 spin_unlock_bh(&pipe_info->pipe_lock);
 656                 return -ENOSR;
 657         }
 658         pipe_info->num_sends_allowed--;
 659         spin_unlock_bh(&pipe_info->pipe_lock);
 660
 661         ret = ath10k_ce_sendlist_send(ce_hdl, nbuf, &sendlist, transfer_id);
 662         if (ret)
 663                 ath10k_warn("CE send failed: %p\n", nbuf);
 664
 665         return ret;
 666 }
 667
 668 static u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
 669 {
 670         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 671         struct hif_ce_pipe_info *pipe_info = &(ar_pci->pipe_info[pipe]);
 672         int ret;
 673
 674         spin_lock_bh(&pipe_info->pipe_lock);
 675         ret = pipe_info->num_sends_allowed;
 676         spin_unlock_bh(&pipe_info->pipe_lock);
 677
 678         return ret;
 679 }
 680
 681 static void ath10k_pci_hif_dump_area(struct ath10k *ar)
 682 {
 683         u32 reg_dump_area = 0;
 684         u32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
 685         u32 host_addr;
 686         int ret;
 687         u32 i;
 688
 689         ath10k_err("firmware crashed!\n");
 690         ath10k_err("hardware name %s version 0x%x\n",
 691                    ar->hw_params.name, ar->target_version);
 692         ath10k_err("firmware version: %u.%u.%u.%u\n", ar->fw_version_major,
 693                    ar->fw_version_minor, ar->fw_version_release,
 694                    ar->fw_version_build);
 695
 696         host_addr = host_interest_item_address(HI_ITEM(hi_failure_state));
 697         if (ath10k_pci_diag_read_mem(ar, host_addr,
 698                                      &reg_dump_area, sizeof(u32)) != 0) {
 699                 ath10k_warn("could not read hi_failure_state\n");
 700                 return;
 701         }
 702
 703         ath10k_err("target register Dump Location: 0x%08X\n", reg_dump_area);
 704
 705         ret = ath10k_pci_diag_read_mem(ar, reg_dump_area,
 706                                        &reg_dump_values[0],
 707                                        REG_DUMP_COUNT_QCA988X * sizeof(u32));
 708         if (ret != 0) {
 709                 ath10k_err("could not dump FW Dump Area\n");
 710                 return;
 711         }
 712
 713         BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
 714
 715         ath10k_err("target Register Dump\n");
 716         for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
 717                 ath10k_err("[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
 718                            i,
 719                            reg_dump_values[i],
 720                            reg_dump_values[i + 1],
 721                            reg_dump_values[i + 2],
 722                            reg_dump_values[i + 3]);
 723
 724         ieee80211_queue_work(ar->hw, &ar->restart_work);
 725 }
 726
 727 static void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
 728                                                int force)
 729 {
 730         if (!force) {
 731                 int resources;
 732                 /*
 733                  * Decide whether to actually poll for completions, or just
 734                  * wait for a later chance.
 735                  * If there seem to be plenty of resources left, then just wait
 736                  * since checking involves reading a CE register, which is a
 737                  * relatively expensive operation.
 738                  */
 739                 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
 740
 741                 /*
 742                  * If at least 50% of the total resources are still available,
 743                  * don't bother checking again yet.
 744                  */
 745                 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
 746                         return;
 747         }
 748         ath10k_ce_per_engine_service(ar, pipe);
 749 }
 750
 751 static void ath10k_pci_hif_set_callbacks(struct ath10k *ar,
 752                                          struct ath10k_hif_cb *callbacks)
 753 {
 754         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 755
 756         ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
 757
 758         memcpy(&ar_pci->msg_callbacks_current, callbacks,
 759                sizeof(ar_pci->msg_callbacks_current));
 760 }
 761
 762 static int ath10k_pci_start_ce(struct ath10k *ar)
 763 {
 764         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 765         struct ce_state *ce_diag = ar_pci->ce_diag;
 766         const struct ce_attr *attr;
 767         struct hif_ce_pipe_info *pipe_info;
 768         struct ath10k_pci_compl *compl;
 769         int i, pipe_num, completions, disable_interrupts;
 770
 771         spin_lock_init(&ar_pci->compl_lock);
 772         INIT_LIST_HEAD(&ar_pci->compl_process);
 773
 774         for (pipe_num = 0; pipe_num < ar_pci->ce_count; pipe_num++) {
 775                 pipe_info = &ar_pci->pipe_info[pipe_num];
 776
 777                 spin_lock_init(&pipe_info->pipe_lock);
 778                 INIT_LIST_HEAD(&pipe_info->compl_free);
 779
 780                 /* Handle Diagnostic CE specially */
 781                 if (pipe_info->ce_hdl == ce_diag)
 782                         continue;
 783
 784                 attr = &host_ce_config_wlan[pipe_num];
 785                 completions = 0;
 786
 787                 if (attr->src_nentries) {
 788                         disable_interrupts = attr->flags & CE_ATTR_DIS_INTR;
 789                         ath10k_ce_send_cb_register(pipe_info->ce_hdl,
 790                                                    ath10k_pci_ce_send_done,
 791                                                    disable_interrupts);
 792                         completions += attr->src_nentries;
 793                         pipe_info->num_sends_allowed = attr->src_nentries - 1;
 794                 }
 795
 796                 if (attr->dest_nentries) {
 797                         ath10k_ce_recv_cb_register(pipe_info->ce_hdl,
 798                                                    ath10k_pci_ce_recv_data);
 799                         completions += attr->dest_nentries;
 800                 }
 801
 802                 if (completions == 0)
 803                         continue;
 804
 805                 for (i = 0; i < completions; i++) {
 806                         compl = kmalloc(sizeof(*compl), GFP_KERNEL);
 807                         if (!compl) {
 808                                 ath10k_warn("No memory for completion state\n");
 809                                 ath10k_pci_stop_ce(ar);
 810                                 return -ENOMEM;
 811                         }
 812
 813                         compl->state = ATH10K_PCI_COMPL_FREE;
 814                         list_add_tail(&compl->list, &pipe_info->compl_free);
 815                 }
 816         }
 817
 818         return 0;
 819 }
 820
 821 static void ath10k_pci_stop_ce(struct ath10k *ar)
 822 {
 823         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 824         struct ath10k_pci_compl *compl;
 825         struct sk_buff *skb;
 826         int i;
 827
 828         ath10k_ce_disable_interrupts(ar);
 829
 830         /* Cancel the pending tasklet */
 831         tasklet_kill(&ar_pci->intr_tq);
 832
 833         for (i = 0; i < CE_COUNT; i++)
 834                 tasklet_kill(&ar_pci->pipe_info[i].intr);
 835
 836         /* Mark pending completions as aborted, so that upper layers free up
 837          * their associated resources */
 838         spin_lock_bh(&ar_pci->compl_lock);
 839         list_for_each_entry(compl, &ar_pci->compl_process, list) {
 840                 skb = (struct sk_buff *)compl->transfer_context;
 841                 ATH10K_SKB_CB(skb)->is_aborted = true;
 842         }
 843         spin_unlock_bh(&ar_pci->compl_lock);
 844 }
 845
 846 static void ath10k_pci_cleanup_ce(struct ath10k *ar)
 847 {
 848         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 849         struct ath10k_pci_compl *compl, *tmp;
 850         struct hif_ce_pipe_info *pipe_info;
 851         struct sk_buff *netbuf;
 852         int pipe_num;
 853
 854         /* Free pending completions. */
 855         spin_lock_bh(&ar_pci->compl_lock);
 856         if (!list_empty(&ar_pci->compl_process))
 857                 ath10k_warn("pending completions still present! possible memory leaks.\n");
 858
 859         list_for_each_entry_safe(compl, tmp, &ar_pci->compl_process, list) {
 860                 list_del(&compl->list);
 861                 netbuf = (struct sk_buff *)compl->transfer_context;
 862                 dev_kfree_skb_any(netbuf);
 863                 kfree(compl);
 864         }
 865         spin_unlock_bh(&ar_pci->compl_lock);
 866
 867         /* Free unused completions for each pipe. */
 868         for (pipe_num = 0; pipe_num < ar_pci->ce_count; pipe_num++) {
 869                 pipe_info = &ar_pci->pipe_info[pipe_num];
 870
 871                 spin_lock_bh(&pipe_info->pipe_lock);
 872                 list_for_each_entry_safe(compl, tmp,
 873                                          &pipe_info->compl_free, list) {
 874                         list_del(&compl->list);
 875                         kfree(compl);
 876                 }
 877                 spin_unlock_bh(&pipe_info->pipe_lock);
 878         }
 879 }
 880
 881 static void ath10k_pci_process_ce(struct ath10k *ar)
 882 {
 883         struct ath10k_pci *ar_pci = ar->hif.priv;
 884         struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
 885         struct ath10k_pci_compl *compl;
 886         struct sk_buff *skb;
 887         unsigned int nbytes;
 888         int ret, send_done = 0;
 889
 890         /* Upper layers aren't ready to handle tx/rx completions in parallel so
 891          * we must serialize all completion processing. */
 892
 893         spin_lock_bh(&ar_pci->compl_lock);
 894         if (ar_pci->compl_processing) {
 895                 spin_unlock_bh(&ar_pci->compl_lock);
 896                 return;
 897         }
 898         ar_pci->compl_processing = true;
 899         spin_unlock_bh(&ar_pci->compl_lock);
 900
 901         for (;;) {
 902                 spin_lock_bh(&ar_pci->compl_lock);
 903                 if (list_empty(&ar_pci->compl_process)) {
 904                         spin_unlock_bh(&ar_pci->compl_lock);
 905                         break;
 906                 }
 907                 compl = list_first_entry(&ar_pci->compl_process,
 908                                          struct ath10k_pci_compl, list);
 909                 list_del(&compl->list);
 910                 spin_unlock_bh(&ar_pci->compl_lock);
 911
 912                 switch (compl->state) {
 913                 case ATH10K_PCI_COMPL_SEND:
 914                         cb->tx_completion(ar,
 915                                           compl->transfer_context,
 916                                           compl->transfer_id);
 917                         send_done = 1;
 918                         break;
 919                 case ATH10K_PCI_COMPL_RECV:
 920                         ret = ath10k_pci_post_rx_pipe(compl->pipe_info, 1);
 921                         if (ret) {
 922                                 ath10k_warn("Unable to post recv buffer for pipe: %d\n",
 923                                             compl->pipe_info->pipe_num);
 924                                 break;
 925                         }
 926
 927                         skb = (struct sk_buff *)compl->transfer_context;
 928                         nbytes = compl->nbytes;
 929
 930                         ath10k_dbg(ATH10K_DBG_PCI,
 931                                    "ath10k_pci_ce_recv_data netbuf=%p  nbytes=%d\n",
 932                                    skb, nbytes);
 933                         ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL,
 934                                         "ath10k rx: ", skb->data, nbytes);
 935
 936                         if (skb->len + skb_tailroom(skb) >= nbytes) {
 937                                 skb_trim(skb, 0);
 938                                 skb_put(skb, nbytes);
 939                                 cb->rx_completion(ar, skb,
 940                                                   compl->pipe_info->pipe_num);
 941                         } else {
 942                                 ath10k_warn("rxed more than expected (nbytes %d, max %d)",
 943                                             nbytes,
 944                                             skb->len + skb_tailroom(skb));
 945                         }
 946                         break;
 947                 case ATH10K_PCI_COMPL_FREE:
 948                         ath10k_warn("free completion cannot be processed\n");
 949                         break;
 950                 default:
 951                         ath10k_warn("invalid completion state (%d)\n",
 952                                     compl->state);
 953                         break;
 954                 }
 955
 956                 compl->state = ATH10K_PCI_COMPL_FREE;
 957
 958                 /*
 959                  * Add completion back to the pipe's free list.
 960                  */
 961                 spin_lock_bh(&compl->pipe_info->pipe_lock);
 962                 list_add_tail(&compl->list, &compl->pipe_info->compl_free);
 963                 compl->pipe_info->num_sends_allowed += send_done;
 964                 spin_unlock_bh(&compl->pipe_info->pipe_lock);
 965         }
 966
 967         spin_lock_bh(&ar_pci->compl_lock);
 968         ar_pci->compl_processing = false;
 969         spin_unlock_bh(&ar_pci->compl_lock);
 970 }
 971
 972 /* TODO - temporary mapping while we have too few CE's */
 973 static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar,
 974                                               u16 service_id, u8 *ul_pipe,
 975                                               u8 *dl_pipe, int *ul_is_polled,
 976                                               int *dl_is_polled)
 977 {
 978         int ret = 0;
 979
 980         /* polling for received messages not supported */
 981         *dl_is_polled = 0;
 982
 983         switch (service_id) {
 984         case ATH10K_HTC_SVC_ID_HTT_DATA_MSG:
 985                 /*
 986                  * Host->target HTT gets its own pipe, so it can be polled
 987                  * while other pipes are interrupt driven.
 988                  */
 989                 *ul_pipe = 4;
 990                 /*
 991                  * Use the same target->host pipe for HTC ctrl, HTC raw
 992                  * streams, and HTT.
 993                  */
 994                 *dl_pipe = 1;
 995                 break;
 996
 997         case ATH10K_HTC_SVC_ID_RSVD_CTRL:
 998         case ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS:
 999                 /*
1000                  * Note: HTC_RAW_STREAMS_SVC is currently unused, and
1001                  * HTC_CTRL_RSVD_SVC could share the same pipe as the
1002                  * WMI services.  So, if another CE is needed, change
1003                  * this to *ul_pipe = 3, which frees up CE 0.
1004                  */
1005                 /* *ul_pipe = 3; */
1006                 *ul_pipe = 0;
1007                 *dl_pipe = 1;
1008                 break;
1009
1010         case ATH10K_HTC_SVC_ID_WMI_DATA_BK:
1011         case ATH10K_HTC_SVC_ID_WMI_DATA_BE:
1012         case ATH10K_HTC_SVC_ID_WMI_DATA_VI:
1013         case ATH10K_HTC_SVC_ID_WMI_DATA_VO:
1014
1015         case ATH10K_HTC_SVC_ID_WMI_CONTROL:
1016                 *ul_pipe = 3;
1017                 *dl_pipe = 2;
1018                 break;
1019
1020                 /* pipe 5 unused   */
1021                 /* pipe 6 reserved */
1022                 /* pipe 7 reserved */
1023
1024         default:
1025                 ret = -1;
1026                 break;
1027         }
1028         *ul_is_polled =
1029                 (host_ce_config_wlan[*ul_pipe].flags & CE_ATTR_DIS_INTR) != 0;
1030
1031         return ret;
1032 }
1033
1034 static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1035                                                 u8 *ul_pipe, u8 *dl_pipe)
1036 {
1037         int ul_is_polled, dl_is_polled;
1038
1039         (void)ath10k_pci_hif_map_service_to_pipe(ar,
1040                                                  ATH10K_HTC_SVC_ID_RSVD_CTRL,
1041                                                  ul_pipe,
1042                                                  dl_pipe,
1043                                                  &ul_is_polled,
1044                                                  &dl_is_polled);
1045 }
1046
1047 static int ath10k_pci_post_rx_pipe(struct hif_ce_pipe_info *pipe_info,
1048                                    int num)
1049 {
1050         struct ath10k *ar = pipe_info->hif_ce_state;
1051         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1052         struct ce_state *ce_state = pipe_info->ce_hdl;
1053         struct sk_buff *skb;
1054         dma_addr_t ce_data;
1055         int i, ret = 0;
1056
1057         if (pipe_info->buf_sz == 0)
1058                 return 0;
1059
1060         for (i = 0; i < num; i++) {
1061                 skb = dev_alloc_skb(pipe_info->buf_sz);
1062                 if (!skb) {
1063                         ath10k_warn("could not allocate skbuff for pipe %d\n",
1064                                     num);
1065                         ret = -ENOMEM;
1066                         goto err;
1067                 }
1068
1069                 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
1070
1071                 ce_data = dma_map_single(ar->dev, skb->data,
1072                                          skb->len + skb_tailroom(skb),
1073                                          DMA_FROM_DEVICE);
1074
1075                 if (unlikely(dma_mapping_error(ar->dev, ce_data))) {
1076                         ath10k_warn("could not dma map skbuff\n");
1077                         dev_kfree_skb_any(skb);
1078                         ret = -EIO;
1079                         goto err;
1080                 }
1081
1082                 ATH10K_SKB_CB(skb)->paddr = ce_data;
1083
1084                 pci_dma_sync_single_for_device(ar_pci->pdev, ce_data,
1085                                                pipe_info->buf_sz,
1086                                                PCI_DMA_FROMDEVICE);
1087
1088                 ret = ath10k_ce_recv_buf_enqueue(ce_state, (void *)skb,
1089                                                  ce_data);
1090                 if (ret) {
1091                         ath10k_warn("could not enqueue to pipe %d (%d)\n",
1092                                     num, ret);
1093                         goto err;
1094                 }
1095         }
1096
1097         return ret;
1098
1099 err:
1100         ath10k_pci_rx_pipe_cleanup(pipe_info);
1101         return ret;
1102 }
1103
1104 static int ath10k_pci_post_rx(struct ath10k *ar)
1105 {
1106         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1107         struct hif_ce_pipe_info *pipe_info;
1108         const struct ce_attr *attr;
1109         int pipe_num, ret = 0;
1110
1111         for (pipe_num = 0; pipe_num < ar_pci->ce_count; pipe_num++) {
1112                 pipe_info = &ar_pci->pipe_info[pipe_num];
1113                 attr = &host_ce_config_wlan[pipe_num];
1114
1115                 if (attr->dest_nentries == 0)
1116                         continue;
1117
1118                 ret = ath10k_pci_post_rx_pipe(pipe_info,
1119                                               attr->dest_nentries - 1);
1120                 if (ret) {
1121                         ath10k_warn("Unable to replenish recv buffers for pipe: %d\n",
1122                                     pipe_num);
1123
1124                         for (; pipe_num >= 0; pipe_num--) {
1125                                 pipe_info = &ar_pci->pipe_info[pipe_num];
1126                                 ath10k_pci_rx_pipe_cleanup(pipe_info);
1127                         }
1128                         return ret;
1129                 }
1130         }
1131
1132         return 0;
1133 }
1134
1135 static int ath10k_pci_hif_start(struct ath10k *ar)
1136 {
1137         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1138         int ret;
1139
1140         ret = ath10k_pci_start_ce(ar);
1141         if (ret) {
1142                 ath10k_warn("could not start CE (%d)\n", ret);
1143                 return ret;
1144         }
1145
1146         /* Post buffers once to start things off. */
1147         ret = ath10k_pci_post_rx(ar);
1148         if (ret) {
1149                 ath10k_warn("could not post rx pipes (%d)\n", ret);
1150                 return ret;
1151         }
1152
1153         ar_pci->started = 1;
1154         return 0;
1155 }
1156
1157 static void ath10k_pci_rx_pipe_cleanup(struct hif_ce_pipe_info *pipe_info)
1158 {
1159         struct ath10k *ar;
1160         struct ath10k_pci *ar_pci;
1161         struct ce_state *ce_hdl;
1162         u32 buf_sz;
1163         struct sk_buff *netbuf;
1164         u32 ce_data;
1165
1166         buf_sz = pipe_info->buf_sz;
1167
1168         /* Unused Copy Engine */
1169         if (buf_sz == 0)
1170                 return;
1171
1172         ar = pipe_info->hif_ce_state;
1173         ar_pci = ath10k_pci_priv(ar);
1174
1175         if (!ar_pci->started)
1176                 return;
1177
1178         ce_hdl = pipe_info->ce_hdl;
1179
1180         while (ath10k_ce_revoke_recv_next(ce_hdl, (void **)&netbuf,
1181                                           &ce_data) == 0) {
1182                 dma_unmap_single(ar->dev, ATH10K_SKB_CB(netbuf)->paddr,
1183                                  netbuf->len + skb_tailroom(netbuf),
1184                                  DMA_FROM_DEVICE);
1185                 dev_kfree_skb_any(netbuf);
1186         }
1187 }
1188
1189 static void ath10k_pci_tx_pipe_cleanup(struct hif_ce_pipe_info *pipe_info)
1190 {
1191         struct ath10k *ar;
1192         struct ath10k_pci *ar_pci;
1193         struct ce_state *ce_hdl;
1194         struct sk_buff *netbuf;
1195         u32 ce_data;
1196         unsigned int nbytes;
1197         unsigned int id;
1198         u32 buf_sz;
1199
1200         buf_sz = pipe_info->buf_sz;
1201
1202         /* Unused Copy Engine */
1203         if (buf_sz == 0)
1204                 return;
1205
1206         ar = pipe_info->hif_ce_state;
1207         ar_pci = ath10k_pci_priv(ar);
1208
1209         if (!ar_pci->started)
1210                 return;
1211
1212         ce_hdl = pipe_info->ce_hdl;
1213
1214         while (ath10k_ce_cancel_send_next(ce_hdl, (void **)&netbuf,
1215                                           &ce_data, &nbytes, &id) == 0) {
1216                 if (netbuf != CE_SENDLIST_ITEM_CTXT)
1217                         /*
1218                          * Indicate the completion to higer layer to free
1219                          * the buffer
1220                          */
1221                         ATH10K_SKB_CB(netbuf)->is_aborted = true;
1222                         ar_pci->msg_callbacks_current.tx_completion(ar,
1223                                                                     netbuf,
1224                                                                     id);
1225         }
1226 }
1227
1228 /*
1229  * Cleanup residual buffers for device shutdown:
1230  *    buffers that were enqueued for receive
1231  *    buffers that were to be sent
1232  * Note: Buffers that had completed but which were
1233  * not yet processed are on a completion queue. They
1234  * are handled when the completion thread shuts down.
1235  */
1236 static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
1237 {
1238         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1239         int pipe_num;
1240
1241         for (pipe_num = 0; pipe_num < ar_pci->ce_count; pipe_num++) {
1242                 struct hif_ce_pipe_info *pipe_info;
1243
1244                 pipe_info = &ar_pci->pipe_info[pipe_num];
1245                 ath10k_pci_rx_pipe_cleanup(pipe_info);
1246                 ath10k_pci_tx_pipe_cleanup(pipe_info);
1247         }
1248 }
1249
1250 static void ath10k_pci_ce_deinit(struct ath10k *ar)
1251 {
1252         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1253         struct hif_ce_pipe_info *pipe_info;
1254         int pipe_num;
1255
1256         for (pipe_num = 0; pipe_num < ar_pci->ce_count; pipe_num++) {
1257                 pipe_info = &ar_pci->pipe_info[pipe_num];
1258                 if (pipe_info->ce_hdl) {
1259                         ath10k_ce_deinit(pipe_info->ce_hdl);
1260                         pipe_info->ce_hdl = NULL;
1261                         pipe_info->buf_sz = 0;
1262                 }
1263         }
1264 }
1265
1266 static void ath10k_pci_disable_irqs(struct ath10k *ar)
1267 {
1268         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1269         int i;
1270
1271         for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
1272                 disable_irq(ar_pci->pdev->irq + i);
1273 }
1274
1275 static void ath10k_pci_hif_stop(struct ath10k *ar)
1276 {
1277         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1278
1279         ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
1280
1281         /* Irqs are never explicitly re-enabled. They are implicitly re-enabled
1282          * by ath10k_pci_start_intr(). */
1283         ath10k_pci_disable_irqs(ar);
1284
1285         ath10k_pci_stop_ce(ar);
1286
1287         /* At this point, asynchronous threads are stopped, the target should
1288          * not DMA nor interrupt. We process the leftovers and then free
1289          * everything else up. */
1290
1291         ath10k_pci_process_ce(ar);
1292         ath10k_pci_cleanup_ce(ar);
1293         ath10k_pci_buffer_cleanup(ar);
1294
1295         ar_pci->started = 0;
1296 }
1297
1298 static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
1299                                            void *req, u32 req_len,
1300                                            void *resp, u32 *resp_len)
1301 {
1302         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1303         struct ce_state *ce_tx = ar_pci->pipe_info[BMI_CE_NUM_TO_TARG].ce_hdl;
1304         struct ce_state *ce_rx = ar_pci->pipe_info[BMI_CE_NUM_TO_HOST].ce_hdl;
1305         dma_addr_t req_paddr = 0;
1306         dma_addr_t resp_paddr = 0;
1307         struct bmi_xfer xfer = {};
1308         void *treq, *tresp = NULL;
1309         int ret = 0;
1310
1311         if (resp && !resp_len)
1312                 return -EINVAL;
1313
1314         if (resp && resp_len && *resp_len == 0)
1315                 return -EINVAL;
1316
1317         treq = kmemdup(req, req_len, GFP_KERNEL);
1318         if (!treq)
1319                 return -ENOMEM;
1320
1321         req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
1322         ret = dma_mapping_error(ar->dev, req_paddr);
1323         if (ret)
1324                 goto err_dma;
1325
1326         if (resp && resp_len) {
1327                 tresp = kzalloc(*resp_len, GFP_KERNEL);
1328                 if (!tresp) {
1329                         ret = -ENOMEM;
1330                         goto err_req;
1331                 }
1332
1333                 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
1334                                             DMA_FROM_DEVICE);
1335                 ret = dma_mapping_error(ar->dev, resp_paddr);
1336                 if (ret)
1337                         goto err_req;
1338
1339                 xfer.wait_for_resp = true;
1340                 xfer.resp_len = 0;
1341
1342                 ath10k_ce_recv_buf_enqueue(ce_rx, &xfer, resp_paddr);
1343         }
1344
1345         init_completion(&xfer.done);
1346
1347         ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
1348         if (ret)
1349                 goto err_resp;
1350
1351         ret = wait_for_completion_timeout(&xfer.done,
1352                                           BMI_COMMUNICATION_TIMEOUT_HZ);
1353         if (ret <= 0) {
1354                 u32 unused_buffer;
1355                 unsigned int unused_nbytes;
1356                 unsigned int unused_id;
1357
1358                 ret = -ETIMEDOUT;
1359                 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
1360                                            &unused_nbytes, &unused_id);
1361         } else {
1362                 /* non-zero means we did not time out */
1363                 ret = 0;
1364         }
1365
1366 err_resp:
1367         if (resp) {
1368                 u32 unused_buffer;
1369
1370                 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
1371                 dma_unmap_single(ar->dev, resp_paddr,
1372                                  *resp_len, DMA_FROM_DEVICE);
1373         }
1374 err_req:
1375         dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
1376
1377         if (ret == 0 && resp_len) {
1378                 *resp_len = min(*resp_len, xfer.resp_len);
1379                 memcpy(resp, tresp, xfer.resp_len);
1380         }
1381 err_dma:
1382         kfree(treq);
1383         kfree(tresp);
1384
1385         return ret;
1386 }
1387
1388 static void ath10k_pci_bmi_send_done(struct ce_state *ce_state,
1389                                      void *transfer_context,
1390                                      u32 data,
1391                                      unsigned int nbytes,
1392                                      unsigned int transfer_id)
1393 {
1394         struct bmi_xfer *xfer = transfer_context;
1395
1396         if (xfer->wait_for_resp)
1397                 return;
1398
1399         complete(&xfer->done);
1400 }
1401
1402 static void ath10k_pci_bmi_recv_data(struct ce_state *ce_state,
1403                                      void *transfer_context,
1404                                      u32 data,
1405                                      unsigned int nbytes,
1406                                      unsigned int transfer_id,
1407                                      unsigned int flags)
1408 {
1409         struct bmi_xfer *xfer = transfer_context;
1410
1411         if (!xfer->wait_for_resp) {
1412                 ath10k_warn("unexpected: BMI data received; ignoring\n");
1413                 return;
1414         }
1415
1416         xfer->resp_len = nbytes;
1417         complete(&xfer->done);
1418 }
1419
1420 /*
1421  * Map from service/endpoint to Copy Engine.
1422  * This table is derived from the CE_PCI TABLE, above.
1423  * It is passed to the Target at startup for use by firmware.
1424  */
1425 static const struct service_to_pipe target_service_to_ce_map_wlan[] = {
1426         {
1427                  ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1428                  PIPEDIR_OUT,           /* out = UL = host -> target */
1429                  3,
1430         },
1431         {
1432                  ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1433                  PIPEDIR_IN,            /* in = DL = target -> host */
1434                  2,
1435         },
1436         {
1437                  ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1438                  PIPEDIR_OUT,           /* out = UL = host -> target */
1439                  3,
1440         },
1441         {
1442                  ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1443                  PIPEDIR_IN,            /* in = DL = target -> host */
1444                  2,
1445         },
1446         {
1447                  ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1448                  PIPEDIR_OUT,           /* out = UL = host -> target */
1449                  3,
1450         },
1451         {
1452                  ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1453                  PIPEDIR_IN,            /* in = DL = target -> host */
1454                  2,
1455         },
1456         {
1457                  ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1458                  PIPEDIR_OUT,           /* out = UL = host -> target */
1459                  3,
1460         },
1461         {
1462                  ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1463                  PIPEDIR_IN,            /* in = DL = target -> host */
1464                  2,
1465         },
1466         {
1467                  ATH10K_HTC_SVC_ID_WMI_CONTROL,
1468                  PIPEDIR_OUT,           /* out = UL = host -> target */
1469                  3,
1470         },
1471         {
1472                  ATH10K_HTC_SVC_ID_WMI_CONTROL,
1473                  PIPEDIR_IN,            /* in = DL = target -> host */
1474                  2,
1475         },
1476         {
1477                  ATH10K_HTC_SVC_ID_RSVD_CTRL,
1478                  PIPEDIR_OUT,           /* out = UL = host -> target */
1479                  0,             /* could be moved to 3 (share with WMI) */
1480         },
1481         {
1482                  ATH10K_HTC_SVC_ID_RSVD_CTRL,
1483                  PIPEDIR_IN,            /* in = DL = target -> host */
1484                  1,
1485         },
1486         {
1487                  ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS,    /* not currently used */
1488                  PIPEDIR_OUT,           /* out = UL = host -> target */
1489                  0,
1490         },
1491         {
1492                  ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS,    /* not currently used */
1493                  PIPEDIR_IN,            /* in = DL = target -> host */
1494                  1,
1495         },
1496         {
1497                  ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1498                  PIPEDIR_OUT,           /* out = UL = host -> target */
1499                  4,
1500         },
1501         {
1502                  ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1503                  PIPEDIR_IN,            /* in = DL = target -> host */
1504                  1,
1505         },
1506
1507         /* (Additions here) */
1508
1509         {                               /* Must be last */
1510                  0,
1511                  0,
1512                  0,
1513         },
1514 };
1515
1516 /*
1517  * Send an interrupt to the device to wake up the Target CPU
1518  * so it has an opportunity to notice any changed state.
1519  */
1520 static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
1521 {
1522         int ret;
1523         u32 core_ctrl;
1524
1525         ret = ath10k_pci_diag_read_access(ar, SOC_CORE_BASE_ADDRESS |
1526                                               CORE_CTRL_ADDRESS,
1527                                           &core_ctrl);
1528         if (ret) {
1529                 ath10k_warn("Unable to read core ctrl\n");
1530                 return ret;
1531         }
1532
1533         /* A_INUM_FIRMWARE interrupt to Target CPU */
1534         core_ctrl |= CORE_CTRL_CPU_INTR_MASK;
1535
1536         ret = ath10k_pci_diag_write_access(ar, SOC_CORE_BASE_ADDRESS |
1537                                                CORE_CTRL_ADDRESS,
1538                                            core_ctrl);
1539         if (ret)
1540                 ath10k_warn("Unable to set interrupt mask\n");
1541
1542         return ret;
1543 }
1544
1545 static int ath10k_pci_init_config(struct ath10k *ar)
1546 {
1547         u32 interconnect_targ_addr;
1548         u32 pcie_state_targ_addr = 0;
1549         u32 pipe_cfg_targ_addr = 0;
1550         u32 svc_to_pipe_map = 0;
1551         u32 pcie_config_flags = 0;
1552         u32 ealloc_value;
1553         u32 ealloc_targ_addr;
1554         u32 flag2_value;
1555         u32 flag2_targ_addr;
1556         int ret = 0;
1557
1558         /* Download to Target the CE Config and the service-to-CE map */
1559         interconnect_targ_addr =
1560                 host_interest_item_address(HI_ITEM(hi_interconnect_state));
1561
1562         /* Supply Target-side CE configuration */
1563         ret = ath10k_pci_diag_read_access(ar, interconnect_targ_addr,
1564                                           &pcie_state_targ_addr);
1565         if (ret != 0) {
1566                 ath10k_err("Failed to get pcie state addr: %d\n", ret);
1567                 return ret;
1568         }
1569
1570         if (pcie_state_targ_addr == 0) {
1571                 ret = -EIO;
1572                 ath10k_err("Invalid pcie state addr\n");
1573                 return ret;
1574         }
1575
1576         ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1577                                           offsetof(struct pcie_state,
1578                                                    pipe_cfg_addr),
1579                                           &pipe_cfg_targ_addr);
1580         if (ret != 0) {
1581                 ath10k_err("Failed to get pipe cfg addr: %d\n", ret);
1582                 return ret;
1583         }
1584
1585         if (pipe_cfg_targ_addr == 0) {
1586                 ret = -EIO;
1587                 ath10k_err("Invalid pipe cfg addr\n");
1588                 return ret;
1589         }
1590
1591         ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
1592                                  target_ce_config_wlan,
1593                                  sizeof(target_ce_config_wlan));
1594
1595         if (ret != 0) {
1596                 ath10k_err("Failed to write pipe cfg: %d\n", ret);
1597                 return ret;
1598         }
1599
1600         ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1601                                           offsetof(struct pcie_state,
1602                                                    svc_to_pipe_map),
1603                                           &svc_to_pipe_map);
1604         if (ret != 0) {
1605                 ath10k_err("Failed to get svc/pipe map: %d\n", ret);
1606                 return ret;
1607         }
1608
1609         if (svc_to_pipe_map == 0) {
1610                 ret = -EIO;
1611                 ath10k_err("Invalid svc_to_pipe map\n");
1612                 return ret;
1613         }
1614
1615         ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
1616                                  target_service_to_ce_map_wlan,
1617                                  sizeof(target_service_to_ce_map_wlan));
1618         if (ret != 0) {
1619                 ath10k_err("Failed to write svc/pipe map: %d\n", ret);
1620                 return ret;
1621         }
1622
1623         ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1624                                           offsetof(struct pcie_state,
1625                                                    config_flags),
1626                                           &pcie_config_flags);
1627         if (ret != 0) {
1628                 ath10k_err("Failed to get pcie config_flags: %d\n", ret);
1629                 return ret;
1630         }
1631
1632         pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
1633
1634         ret = ath10k_pci_diag_write_mem(ar, pcie_state_targ_addr +
1635                                  offsetof(struct pcie_state, config_flags),
1636                                  &pcie_config_flags,
1637                                  sizeof(pcie_config_flags));
1638         if (ret != 0) {
1639                 ath10k_err("Failed to write pcie config_flags: %d\n", ret);
1640                 return ret;
1641         }
1642
1643         /* configure early allocation */
1644         ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
1645
1646         ret = ath10k_pci_diag_read_access(ar, ealloc_targ_addr, &ealloc_value);
1647         if (ret != 0) {
1648                 ath10k_err("Faile to get early alloc val: %d\n", ret);
1649                 return ret;
1650         }
1651
1652         /* first bank is switched to IRAM */
1653         ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
1654                          HI_EARLY_ALLOC_MAGIC_MASK);
1655         ealloc_value |= ((1 << HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
1656                          HI_EARLY_ALLOC_IRAM_BANKS_MASK);
1657
1658         ret = ath10k_pci_diag_write_access(ar, ealloc_targ_addr, ealloc_value);
1659         if (ret != 0) {
1660                 ath10k_err("Failed to set early alloc val: %d\n", ret);
1661                 return ret;
1662         }
1663
1664         /* Tell Target to proceed with initialization */
1665         flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
1666
1667         ret = ath10k_pci_diag_read_access(ar, flag2_targ_addr, &flag2_value);
1668         if (ret != 0) {
1669                 ath10k_err("Failed to get option val: %d\n", ret);
1670                 return ret;
1671         }
1672
1673         flag2_value |= HI_OPTION_EARLY_CFG_DONE;
1674
1675         ret = ath10k_pci_diag_write_access(ar, flag2_targ_addr, flag2_value);
1676         if (ret != 0) {
1677                 ath10k_err("Failed to set option val: %d\n", ret);
1678                 return ret;
1679         }
1680
1681         return 0;
1682 }
1683
1684
1685
1686 static int ath10k_pci_ce_init(struct ath10k *ar)
1687 {
1688         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1689         struct hif_ce_pipe_info *pipe_info;
1690         const struct ce_attr *attr;
1691         int pipe_num;
1692
1693         for (pipe_num = 0; pipe_num < ar_pci->ce_count; pipe_num++) {
1694                 pipe_info = &ar_pci->pipe_info[pipe_num];
1695                 pipe_info->pipe_num = pipe_num;
1696                 pipe_info->hif_ce_state = ar;
1697                 attr = &host_ce_config_wlan[pipe_num];
1698
1699                 pipe_info->ce_hdl = ath10k_ce_init(ar, pipe_num, attr);
1700                 if (pipe_info->ce_hdl == NULL) {
1701                         ath10k_err("Unable to initialize CE for pipe: %d\n",
1702                                    pipe_num);
1703
1704                         /* It is safe to call it here. It checks if ce_hdl is
1705                          * valid for each pipe */
1706                         ath10k_pci_ce_deinit(ar);
1707                         return -1;
1708                 }
1709
1710                 if (pipe_num == ar_pci->ce_count - 1) {
1711                         /*
1712                          * Reserve the ultimate CE for
1713                          * diagnostic Window support
1714                          */
1715                         ar_pci->ce_diag =
1716                         ar_pci->pipe_info[ar_pci->ce_count - 1].ce_hdl;
1717                         continue;
1718                 }
1719
1720                 pipe_info->buf_sz = (size_t) (attr->src_sz_max);
1721         }
1722
1723         /*
1724          * Initially, establish CE completion handlers for use with BMI.
1725          * These are overwritten with generic handlers after we exit BMI phase.
1726          */
1727         pipe_info = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1728         ath10k_ce_send_cb_register(pipe_info->ce_hdl,
1729                                    ath10k_pci_bmi_send_done, 0);
1730
1731         pipe_info = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1732         ath10k_ce_recv_cb_register(pipe_info->ce_hdl,
1733                                    ath10k_pci_bmi_recv_data);
1734
1735         return 0;
1736 }
1737
1738 static void ath10k_pci_fw_interrupt_handler(struct ath10k *ar)
1739 {
1740         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1741         u32 fw_indicator_address, fw_indicator;
1742
1743         ath10k_pci_wake(ar);
1744
1745         fw_indicator_address = ar_pci->fw_indicator_address;
1746         fw_indicator = ath10k_pci_read32(ar, fw_indicator_address);
1747
1748         if (fw_indicator & FW_IND_EVENT_PENDING) {
1749                 /* ACK: clear Target-side pending event */
1750                 ath10k_pci_write32(ar, fw_indicator_address,
1751                                    fw_indicator & ~FW_IND_EVENT_PENDING);
1752
1753                 if (ar_pci->started) {
1754                         ath10k_pci_hif_dump_area(ar);
1755                 } else {
1756                         /*
1757                          * Probable Target failure before we're prepared
1758                          * to handle it.  Generally unexpected.
1759                          */
1760                         ath10k_warn("early firmware event indicated\n");
1761                 }
1762         }
1763
1764         ath10k_pci_sleep(ar);
1765 }
1766
1767 static int ath10k_pci_hif_power_up(struct ath10k *ar)
1768 {
1769         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1770         int ret;
1771
1772         ret = ath10k_pci_start_intr(ar);
1773         if (ret) {
1774                 ath10k_err("could not start interrupt handling (%d)\n", ret);
1775                 goto err;
1776         }
1777
1778         /*
1779          * Bring the target up cleanly.
1780          *
1781          * The target may be in an undefined state with an AUX-powered Target
1782          * and a Host in WoW mode. If the Host crashes, loses power, or is
1783          * restarted (without unloading the driver) then the Target is left
1784          * (aux) powered and running. On a subsequent driver load, the Target
1785          * is in an unexpected state. We try to catch that here in order to
1786          * reset the Target and retry the probe.
1787          */
1788         ath10k_pci_device_reset(ar);
1789
1790         ret = ath10k_pci_reset_target(ar);
1791         if (ret)
1792                 goto err_irq;
1793
1794         if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
1795                 /* Force AWAKE forever */
1796                 ath10k_do_pci_wake(ar);
1797
1798         ret = ath10k_pci_ce_init(ar);
1799         if (ret)
1800                 goto err_ps;
1801
1802         ret = ath10k_pci_init_config(ar);
1803         if (ret)
1804                 goto err_ce;
1805
1806         ret = ath10k_pci_wake_target_cpu(ar);
1807         if (ret) {
1808                 ath10k_err("could not wake up target CPU (%d)\n", ret);
1809                 goto err_ce;
1810         }
1811
1812         return 0;
1813
1814 err_ce:
1815         ath10k_pci_ce_deinit(ar);
1816 err_ps:
1817         if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
1818                 ath10k_do_pci_sleep(ar);
1819 err_irq:
1820         ath10k_pci_stop_intr(ar);
1821 err:
1822         return ret;
1823 }
1824
1825 static void ath10k_pci_hif_power_down(struct ath10k *ar)
1826 {
1827         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1828
1829         ath10k_pci_stop_intr(ar);
1830
1831         ath10k_pci_ce_deinit(ar);
1832         if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
1833                 ath10k_do_pci_sleep(ar);
1834 }
1835
1836 #ifdef CONFIG_PM
1837
1838 #define ATH10K_PCI_PM_CONTROL 0x44
1839
1840 static int ath10k_pci_hif_suspend(struct ath10k *ar)
1841 {
1842         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1843         struct pci_dev *pdev = ar_pci->pdev;
1844         u32 val;
1845
1846         pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
1847
1848         if ((val & 0x000000ff) != 0x3) {
1849                 pci_save_state(pdev);
1850                 pci_disable_device(pdev);
1851                 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
1852                                        (val & 0xffffff00) | 0x03);
1853         }
1854
1855         return 0;
1856 }
1857
1858 static int ath10k_pci_hif_resume(struct ath10k *ar)
1859 {
1860         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1861         struct pci_dev *pdev = ar_pci->pdev;
1862         u32 val;
1863
1864         pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
1865
1866         if ((val & 0x000000ff) != 0) {
1867                 pci_restore_state(pdev);
1868                 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
1869                                        val & 0xffffff00);
1870                 /*
1871                  * Suspend/Resume resets the PCI configuration space,
1872                  * so we have to re-disable the RETRY_TIMEOUT register (0x41)
1873                  * to keep PCI Tx retries from interfering with C3 CPU state
1874                  */
1875                 pci_read_config_dword(pdev, 0x40, &val);
1876
1877                 if ((val & 0x0000ff00) != 0)
1878                         pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
1879         }
1880
1881         return 0;
1882 }
1883 #endif
1884
1885 static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
1886         .send_head              = ath10k_pci_hif_send_head,
1887         .exchange_bmi_msg       = ath10k_pci_hif_exchange_bmi_msg,
1888         .start                  = ath10k_pci_hif_start,
1889         .stop                   = ath10k_pci_hif_stop,
1890         .map_service_to_pipe    = ath10k_pci_hif_map_service_to_pipe,
1891         .get_default_pipe       = ath10k_pci_hif_get_default_pipe,
1892         .send_complete_check    = ath10k_pci_hif_send_complete_check,
1893         .set_callbacks          = ath10k_pci_hif_set_callbacks,
1894         .get_free_queue_number  = ath10k_pci_hif_get_free_queue_number,
1895         .power_up               = ath10k_pci_hif_power_up,
1896         .power_down             = ath10k_pci_hif_power_down,
1897 #ifdef CONFIG_PM
1898         .suspend                = ath10k_pci_hif_suspend,
1899         .resume                 = ath10k_pci_hif_resume,
1900 #endif
1901 };
1902
1903 static void ath10k_pci_ce_tasklet(unsigned long ptr)
1904 {
1905         struct hif_ce_pipe_info *pipe = (struct hif_ce_pipe_info *)ptr;
1906         struct ath10k_pci *ar_pci = pipe->ar_pci;
1907
1908         ath10k_ce_per_engine_service(ar_pci->ar, pipe->pipe_num);
1909 }
1910
1911 static void ath10k_msi_err_tasklet(unsigned long data)
1912 {
1913         struct ath10k *ar = (struct ath10k *)data;
1914
1915         ath10k_pci_fw_interrupt_handler(ar);
1916 }
1917
1918 /*
1919  * Handler for a per-engine interrupt on a PARTICULAR CE.
1920  * This is used in cases where each CE has a private MSI interrupt.
1921  */
1922 static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg)
1923 {
1924         struct ath10k *ar = arg;
1925         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1926         int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL;
1927
1928         if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) {
1929                 ath10k_warn("unexpected/invalid irq %d ce_id %d\n", irq, ce_id);
1930                 return IRQ_HANDLED;
1931         }
1932
1933         /*
1934          * NOTE: We are able to derive ce_id from irq because we
1935          * use a one-to-one mapping for CE's 0..5.
1936          * CE's 6 & 7 do not use interrupts at all.
1937          *
1938          * This mapping must be kept in sync with the mapping
1939          * used by firmware.
1940          */
1941         tasklet_schedule(&ar_pci->pipe_info[ce_id].intr);
1942         return IRQ_HANDLED;
1943 }
1944
1945 static irqreturn_t ath10k_pci_msi_fw_handler(int irq, void *arg)
1946 {
1947         struct ath10k *ar = arg;
1948         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1949
1950         tasklet_schedule(&ar_pci->msi_fw_err);
1951         return IRQ_HANDLED;
1952 }
1953
1954 /*
1955  * Top-level interrupt handler for all PCI interrupts from a Target.
1956  * When a block of MSI interrupts is allocated, this top-level handler
1957  * is not used; instead, we directly call the correct sub-handler.
1958  */
1959 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
1960 {
1961         struct ath10k *ar = arg;
1962         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1963
1964         if (ar_pci->num_msi_intrs == 0) {
1965                 /*
1966                  * IMPORTANT: INTR_CLR regiser has to be set after
1967                  * INTR_ENABLE is set to 0, otherwise interrupt can not be
1968                  * really cleared.
1969                  */
1970                 iowrite32(0, ar_pci->mem +
1971                           (SOC_CORE_BASE_ADDRESS |
1972                            PCIE_INTR_ENABLE_ADDRESS));
1973                 iowrite32(PCIE_INTR_FIRMWARE_MASK |
1974                           PCIE_INTR_CE_MASK_ALL,
1975                           ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
1976                                          PCIE_INTR_CLR_ADDRESS));
1977                 /*
1978                  * IMPORTANT: this extra read transaction is required to
1979                  * flush the posted write buffer.
1980                  */
1981                 (void) ioread32(ar_pci->mem +
1982                                 (SOC_CORE_BASE_ADDRESS |
1983                                  PCIE_INTR_ENABLE_ADDRESS));
1984         }
1985
1986         tasklet_schedule(&ar_pci->intr_tq);
1987
1988         return IRQ_HANDLED;
1989 }
1990
1991 static void ath10k_pci_tasklet(unsigned long data)
1992 {
1993         struct ath10k *ar = (struct ath10k *)data;
1994         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1995
1996         ath10k_pci_fw_interrupt_handler(ar); /* FIXME: Handle FW error */
1997         ath10k_ce_per_engine_service_any(ar);
1998
1999         if (ar_pci->num_msi_intrs == 0) {
2000                 /* Enable Legacy PCI line interrupts */
2001                 iowrite32(PCIE_INTR_FIRMWARE_MASK |
2002                           PCIE_INTR_CE_MASK_ALL,
2003                           ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2004                                          PCIE_INTR_ENABLE_ADDRESS));
2005                 /*
2006                  * IMPORTANT: this extra read transaction is required to
2007                  * flush the posted write buffer
2008                  */
2009                 (void) ioread32(ar_pci->mem +
2010                                 (SOC_CORE_BASE_ADDRESS |
2011                                  PCIE_INTR_ENABLE_ADDRESS));
2012         }
2013 }
2014
2015 static int ath10k_pci_start_intr_msix(struct ath10k *ar, int num)
2016 {
2017         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2018         int ret;
2019         int i;
2020
2021         ret = pci_enable_msi_block(ar_pci->pdev, num);
2022         if (ret)
2023                 return ret;
2024
2025         ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW,
2026                           ath10k_pci_msi_fw_handler,
2027                           IRQF_SHARED, "ath10k_pci", ar);
2028         if (ret) {
2029                 ath10k_warn("request_irq(%d) failed %d\n",
2030                             ar_pci->pdev->irq + MSI_ASSIGN_FW, ret);
2031
2032                 pci_disable_msi(ar_pci->pdev);
2033                 return ret;
2034         }
2035
2036         for (i = MSI_ASSIGN_CE_INITIAL; i <= MSI_ASSIGN_CE_MAX; i++) {
2037                 ret = request_irq(ar_pci->pdev->irq + i,
2038                                   ath10k_pci_per_engine_handler,
2039                                   IRQF_SHARED, "ath10k_pci", ar);
2040                 if (ret) {
2041                         ath10k_warn("request_irq(%d) failed %d\n",
2042                                     ar_pci->pdev->irq + i, ret);
2043
2044                         for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--)
2045                                 free_irq(ar_pci->pdev->irq + i, ar);
2046
2047                         free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar);
2048                         pci_disable_msi(ar_pci->pdev);
2049                         return ret;
2050                 }
2051         }
2052
2053         ath10k_info("MSI-X interrupt handling (%d intrs)\n", num);
2054         return 0;
2055 }
2056
2057 static int ath10k_pci_start_intr_msi(struct ath10k *ar)
2058 {
2059         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2060         int ret;
2061
2062         ret = pci_enable_msi(ar_pci->pdev);
2063         if (ret < 0)
2064                 return ret;
2065
2066         ret = request_irq(ar_pci->pdev->irq,
2067                           ath10k_pci_interrupt_handler,
2068                           IRQF_SHARED, "ath10k_pci", ar);
2069         if (ret < 0) {
2070                 pci_disable_msi(ar_pci->pdev);
2071                 return ret;
2072         }
2073
2074         ath10k_info("MSI interrupt handling\n");
2075         return 0;
2076 }
2077
2078 static int ath10k_pci_start_intr_legacy(struct ath10k *ar)
2079 {
2080         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2081         int ret;
2082
2083         ret = request_irq(ar_pci->pdev->irq,
2084                           ath10k_pci_interrupt_handler,
2085                           IRQF_SHARED, "ath10k_pci", ar);
2086         if (ret < 0)
2087                 return ret;
2088
2089         /*
2090          * Make sure to wake the Target before enabling Legacy
2091          * Interrupt.
2092          */
2093         iowrite32(PCIE_SOC_WAKE_V_MASK,
2094                   ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
2095                   PCIE_SOC_WAKE_ADDRESS);
2096
2097         ath10k_pci_wait(ar);
2098
2099         /*
2100          * A potential race occurs here: The CORE_BASE write
2101          * depends on target correctly decoding AXI address but
2102          * host won't know when target writes BAR to CORE_CTRL.
2103          * This write might get lost if target has NOT written BAR.
2104          * For now, fix the race by repeating the write in below
2105          * synchronization checking.
2106          */
2107         iowrite32(PCIE_INTR_FIRMWARE_MASK |
2108                   PCIE_INTR_CE_MASK_ALL,
2109                   ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2110                                  PCIE_INTR_ENABLE_ADDRESS));
2111         iowrite32(PCIE_SOC_WAKE_RESET,
2112                   ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
2113                   PCIE_SOC_WAKE_ADDRESS);
2114
2115         ath10k_info("legacy interrupt handling\n");
2116         return 0;
2117 }
2118
2119 static int ath10k_pci_start_intr(struct ath10k *ar)
2120 {
2121         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2122         int num = MSI_NUM_REQUEST;
2123         int ret;
2124         int i;
2125
2126         tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long) ar);
2127         tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
2128                      (unsigned long) ar);
2129
2130         for (i = 0; i < CE_COUNT; i++) {
2131                 ar_pci->pipe_info[i].ar_pci = ar_pci;
2132                 tasklet_init(&ar_pci->pipe_info[i].intr,
2133                              ath10k_pci_ce_tasklet,
2134                              (unsigned long)&ar_pci->pipe_info[i]);
2135         }
2136
2137         if (!test_bit(ATH10K_PCI_FEATURE_MSI_X, ar_pci->features))
2138                 num = 1;
2139
2140         if (num > 1) {
2141                 ret = ath10k_pci_start_intr_msix(ar, num);
2142                 if (ret == 0)
2143                         goto exit;
2144
2145                 ath10k_warn("MSI-X didn't succeed (%d), trying MSI\n", ret);
2146                 num = 1;
2147         }
2148
2149         if (num == 1) {
2150                 ret = ath10k_pci_start_intr_msi(ar);
2151                 if (ret == 0)
2152                         goto exit;
2153
2154                 ath10k_warn("MSI didn't succeed (%d), trying legacy INTR\n",
2155                             ret);
2156                 num = 0;
2157         }
2158
2159         ret = ath10k_pci_start_intr_legacy(ar);
2160
2161 exit:
2162         ar_pci->num_msi_intrs = num;
2163         ar_pci->ce_count = CE_COUNT;
2164         return ret;
2165 }
2166
2167 static void ath10k_pci_stop_intr(struct ath10k *ar)
2168 {
2169         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2170         int i;
2171
2172         /* There's at least one interrupt irregardless whether its legacy INTR
2173          * or MSI or MSI-X */
2174         for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
2175                 free_irq(ar_pci->pdev->irq + i, ar);
2176
2177         if (ar_pci->num_msi_intrs > 0)
2178                 pci_disable_msi(ar_pci->pdev);
2179 }
2180
2181 static int ath10k_pci_reset_target(struct ath10k *ar)
2182 {
2183         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2184         int wait_limit = 300; /* 3 sec */
2185
2186         /* Wait for Target to finish initialization before we proceed. */
2187         iowrite32(PCIE_SOC_WAKE_V_MASK,
2188                   ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
2189                   PCIE_SOC_WAKE_ADDRESS);
2190
2191         ath10k_pci_wait(ar);
2192
2193         while (wait_limit-- &&
2194                !(ioread32(ar_pci->mem + FW_INDICATOR_ADDRESS) &
2195                  FW_IND_INITIALIZED)) {
2196                 if (ar_pci->num_msi_intrs == 0)
2197                         /* Fix potential race by repeating CORE_BASE writes */
2198                         iowrite32(PCIE_INTR_FIRMWARE_MASK |
2199                                   PCIE_INTR_CE_MASK_ALL,
2200                                   ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2201                                                  PCIE_INTR_ENABLE_ADDRESS));
2202                 mdelay(10);
2203         }
2204
2205         if (wait_limit < 0) {
2206                 ath10k_err("Target stalled\n");
2207                 iowrite32(PCIE_SOC_WAKE_RESET,
2208                           ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
2209                           PCIE_SOC_WAKE_ADDRESS);
2210                 return -EIO;
2211         }
2212
2213         iowrite32(PCIE_SOC_WAKE_RESET,
2214                   ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
2215                   PCIE_SOC_WAKE_ADDRESS);
2216
2217         return 0;
2218 }
2219
2220 static void ath10k_pci_device_reset(struct ath10k *ar)
2221 {
2222         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2223         void __iomem *mem = ar_pci->mem;
2224         int i;
2225         u32 val;
2226
2227         if (!SOC_GLOBAL_RESET_ADDRESS)
2228                 return;
2229
2230         if (!mem)
2231                 return;
2232
2233         ath10k_pci_reg_write32(mem, PCIE_SOC_WAKE_ADDRESS,
2234                                PCIE_SOC_WAKE_V_MASK);
2235         for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2236                 if (ath10k_pci_target_is_awake(ar))
2237                         break;
2238                 msleep(1);
2239         }
2240
2241         /* Put Target, including PCIe, into RESET. */
2242         val = ath10k_pci_reg_read32(mem, SOC_GLOBAL_RESET_ADDRESS);
2243         val |= 1;
2244         ath10k_pci_reg_write32(mem, SOC_GLOBAL_RESET_ADDRESS, val);
2245
2246         for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2247                 if (ath10k_pci_reg_read32(mem, RTC_STATE_ADDRESS) &
2248                                           RTC_STATE_COLD_RESET_MASK)
2249                         break;
2250                 msleep(1);
2251         }
2252
2253         /* Pull Target, including PCIe, out of RESET. */
2254         val &= ~1;
2255         ath10k_pci_reg_write32(mem, SOC_GLOBAL_RESET_ADDRESS, val);
2256
2257         for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2258                 if (!(ath10k_pci_reg_read32(mem, RTC_STATE_ADDRESS) &
2259                                             RTC_STATE_COLD_RESET_MASK))
2260                         break;
2261                 msleep(1);
2262         }
2263
2264         ath10k_pci_reg_write32(mem, PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_RESET);
2265 }
2266
2267 static void ath10k_pci_dump_features(struct ath10k_pci *ar_pci)
2268 {
2269         int i;
2270
2271         for (i = 0; i < ATH10K_PCI_FEATURE_COUNT; i++) {
2272                 if (!test_bit(i, ar_pci->features))
2273                         continue;
2274
2275                 switch (i) {
2276                 case ATH10K_PCI_FEATURE_MSI_X:
2277                         ath10k_dbg(ATH10K_DBG_PCI, "device supports MSI-X\n");
2278                         break;
2279                 case ATH10K_PCI_FEATURE_SOC_POWER_SAVE:
2280                         ath10k_dbg(ATH10K_DBG_PCI, "QCA98XX SoC power save enabled\n");
2281                         break;
2282                 }
2283         }
2284 }
2285
2286 static int ath10k_pci_probe(struct pci_dev *pdev,
2287                             const struct pci_device_id *pci_dev)
2288 {
2289         void __iomem *mem;
2290         int ret = 0;
2291         struct ath10k *ar;
2292         struct ath10k_pci *ar_pci;
2293         u32 lcr_val;
2294
2295         ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
2296
2297         ar_pci = kzalloc(sizeof(*ar_pci), GFP_KERNEL);
2298         if (ar_pci == NULL)
2299                 return -ENOMEM;
2300
2301         ar_pci->pdev = pdev;
2302         ar_pci->dev = &pdev->dev;
2303
2304         switch (pci_dev->device) {
2305         case QCA988X_2_0_DEVICE_ID:
2306                 set_bit(ATH10K_PCI_FEATURE_MSI_X, ar_pci->features);
2307                 break;
2308         default:
2309                 ret = -ENODEV;
2310                 ath10k_err("Unkown device ID: %d\n", pci_dev->device);
2311                 goto err_ar_pci;
2312         }
2313
2314         if (ath10k_target_ps)
2315                 set_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features);
2316
2317         ath10k_pci_dump_features(ar_pci);
2318
2319         ar = ath10k_core_create(ar_pci, ar_pci->dev, &ath10k_pci_hif_ops);
2320         if (!ar) {
2321                 ath10k_err("ath10k_core_create failed!\n");
2322                 ret = -EINVAL;
2323                 goto err_ar_pci;
2324         }
2325
2326         ar_pci->ar = ar;
2327         ar_pci->fw_indicator_address = FW_INDICATOR_ADDRESS;
2328         atomic_set(&ar_pci->keep_awake_count, 0);
2329
2330         pci_set_drvdata(pdev, ar);
2331
2332         /*
2333          * Without any knowledge of the Host, the Target may have been reset or
2334          * power cycled and its Config Space may no longer reflect the PCI
2335          * address space that was assigned earlier by the PCI infrastructure.
2336          * Refresh it now.
2337          */
2338         ret = pci_assign_resource(pdev, BAR_NUM);
2339         if (ret) {
2340                 ath10k_err("cannot assign PCI space: %d\n", ret);
2341                 goto err_ar;
2342         }
2343
2344         ret = pci_enable_device(pdev);
2345         if (ret) {
2346                 ath10k_err("cannot enable PCI device: %d\n", ret);
2347                 goto err_ar;
2348         }
2349
2350         /* Request MMIO resources */
2351         ret = pci_request_region(pdev, BAR_NUM, "ath");
2352         if (ret) {
2353                 ath10k_err("PCI MMIO reservation error: %d\n", ret);
2354                 goto err_device;
2355         }
2356
2357         /*
2358          * Target structures have a limit of 32 bit DMA pointers.
2359          * DMA pointers can be wider than 32 bits by default on some systems.
2360          */
2361         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2362         if (ret) {
2363                 ath10k_err("32-bit DMA not available: %d\n", ret);
2364                 goto err_region;
2365         }
2366
2367         ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2368         if (ret) {
2369                 ath10k_err("cannot enable 32-bit consistent DMA\n");
2370                 goto err_region;
2371         }
2372
2373         /* Set bus master bit in PCI_COMMAND to enable DMA */
2374         pci_set_master(pdev);
2375
2376         /*
2377          * Temporary FIX: disable ASPM
2378          * Will be removed after the OTP is programmed
2379          */
2380         pci_read_config_dword(pdev, 0x80, &lcr_val);
2381         pci_write_config_dword(pdev, 0x80, (lcr_val & 0xffffff00));
2382
2383         /* Arrange for access to Target SoC registers. */
2384         mem = pci_iomap(pdev, BAR_NUM, 0);
2385         if (!mem) {
2386                 ath10k_err("PCI iomap error\n");
2387                 ret = -EIO;
2388                 goto err_master;
2389         }
2390
2391         ar_pci->mem = mem;
2392
2393         spin_lock_init(&ar_pci->ce_lock);
2394
2395         ar_pci->cacheline_sz = dma_get_cache_alignment();
2396
2397         ret = ath10k_core_register(ar);
2398         if (ret) {
2399                 ath10k_err("could not register driver core (%d)\n", ret);
2400                 goto err_iomap;
2401         }
2402
2403         return 0;
2404
2405 err_iomap:
2406         pci_iounmap(pdev, mem);
2407 err_master:
2408         pci_clear_master(pdev);
2409 err_region:
2410         pci_release_region(pdev, BAR_NUM);
2411 err_device:
2412         pci_disable_device(pdev);
2413 err_ar:
2414         pci_set_drvdata(pdev, NULL);
2415         ath10k_core_destroy(ar);
2416 err_ar_pci:
2417         /* call HIF PCI free here */
2418         kfree(ar_pci);
2419
2420         return ret;
2421 }
2422
2423 static void ath10k_pci_remove(struct pci_dev *pdev)
2424 {
2425         struct ath10k *ar = pci_get_drvdata(pdev);
2426         struct ath10k_pci *ar_pci;
2427
2428         ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
2429
2430         if (!ar)
2431                 return;
2432
2433         ar_pci = ath10k_pci_priv(ar);
2434
2435         if (!ar_pci)
2436                 return;
2437
2438         tasklet_kill(&ar_pci->msi_fw_err);
2439
2440         ath10k_core_unregister(ar);
2441
2442         pci_set_drvdata(pdev, NULL);
2443         pci_iounmap(pdev, ar_pci->mem);
2444         pci_release_region(pdev, BAR_NUM);
2445         pci_clear_master(pdev);
2446         pci_disable_device(pdev);
2447
2448         ath10k_core_destroy(ar);
2449         kfree(ar_pci);
2450 }
2451
2452 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
2453
2454 static struct pci_driver ath10k_pci_driver = {
2455         .name = "ath10k_pci",
2456         .id_table = ath10k_pci_id_table,
2457         .probe = ath10k_pci_probe,
2458         .remove = ath10k_pci_remove,
2459 };
2460
2461 static int __init ath10k_pci_init(void)
2462 {
2463         int ret;
2464
2465         ret = pci_register_driver(&ath10k_pci_driver);
2466         if (ret)
2467                 ath10k_err("pci_register_driver failed [%d]\n", ret);
2468
2469         return ret;
2470 }
2471 module_init(ath10k_pci_init);
2472
2473 static void __exit ath10k_pci_exit(void)
2474 {
2475         pci_unregister_driver(&ath10k_pci_driver);
2476 }
2477
2478 module_exit(ath10k_pci_exit);
2479
2480 MODULE_AUTHOR("Qualcomm Atheros");
2481 MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
2482 MODULE_LICENSE("Dual BSD/GPL");
2483 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_FILE);
2484 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_OTP_FILE);
2485 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);