2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/kernel.h>
18 #include <linux/export.h>
22 struct ani_ofdm_level_entry {
23 int spur_immunity_level;
25 int ofdm_weak_signal_on;
28 /* values here are relative to the INI */
35 * WS: OFDM / CCK Weak Signal detection
36 * MRC-CCK: Maximal Ratio Combining for CCK
39 static const struct ani_ofdm_level_entry ofdm_level_table[] = {
41 { 0, 0, 1 }, /* lvl 0 */
42 { 1, 1, 1 }, /* lvl 1 */
43 { 2, 2, 1 }, /* lvl 2 */
44 { 3, 2, 1 }, /* lvl 3 (default) */
45 { 4, 3, 1 }, /* lvl 4 */
46 { 5, 4, 1 }, /* lvl 5 */
47 { 6, 5, 1 }, /* lvl 6 */
48 { 7, 6, 1 }, /* lvl 7 */
49 { 7, 6, 0 }, /* lvl 8 */
50 { 7, 7, 0 } /* lvl 9 */
52 #define ATH9K_ANI_OFDM_NUM_LEVEL \
53 ARRAY_SIZE(ofdm_level_table)
54 #define ATH9K_ANI_OFDM_MAX_LEVEL \
55 (ATH9K_ANI_OFDM_NUM_LEVEL-1)
56 #define ATH9K_ANI_OFDM_DEF_LEVEL \
57 3 /* default level - matches the INI settings */
60 * MRC (Maximal Ratio Combining) has always been used with multi-antenna ofdm.
61 * With OFDM for single stream you just add up all antenna inputs, you're
62 * only interested in what you get after FFT. Signal aligment is also not
63 * required for OFDM because any phase difference adds up in the frequency
66 * MRC requires extra work for use with CCK. You need to align the antenna
67 * signals from the different antenna before you can add the signals together.
68 * You need aligment of signals as CCK is in time domain, so addition can cancel
69 * your signal completely if phase is 180 degrees (think of adding sine waves).
70 * You also need to remove noise before the addition and this is where ANI
71 * MRC CCK comes into play. One of the antenna inputs may be stronger but
72 * lower SNR, so just adding after alignment can be dangerous.
74 * Regardless of alignment in time, the antenna signals add constructively after
75 * FFT and improve your reception. For more information:
77 * http://en.wikipedia.org/wiki/Maximal-ratio_combining
80 struct ani_cck_level_entry {
85 static const struct ani_cck_level_entry cck_level_table[] = {
89 { 2, 1 }, /* lvl 2 (default) */
94 { 6, 0 }, /* lvl 7 (only for high rssi) */
95 { 7, 0 } /* lvl 8 (only for high rssi) */
98 #define ATH9K_ANI_CCK_NUM_LEVEL \
99 ARRAY_SIZE(cck_level_table)
100 #define ATH9K_ANI_CCK_MAX_LEVEL \
101 (ATH9K_ANI_CCK_NUM_LEVEL-1)
102 #define ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI \
103 (ATH9K_ANI_CCK_NUM_LEVEL-3)
104 #define ATH9K_ANI_CCK_DEF_LEVEL \
105 2 /* default level - matches the INI settings */
107 static void ath9k_hw_update_mibstats(struct ath_hw *ah,
108 struct ath9k_mib_stats *stats)
110 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
111 stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
112 stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
113 stats->rts_good += REG_READ(ah, AR_RTS_OK);
114 stats->beacons += REG_READ(ah, AR_BEACON_CNT);
117 static void ath9k_ani_restart(struct ath_hw *ah)
119 struct ar5416AniState *aniState;
124 aniState = &ah->curchan->ani;
125 aniState->listenTime = 0;
127 ENABLE_REGWRITE_BUFFER(ah);
129 REG_WRITE(ah, AR_PHY_ERR_1, 0);
130 REG_WRITE(ah, AR_PHY_ERR_2, 0);
131 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
132 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
134 REGWRITE_BUFFER_FLUSH(ah);
136 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
138 aniState->ofdmPhyErrCount = 0;
139 aniState->cckPhyErrCount = 0;
142 /* Adjust the OFDM Noise Immunity Level */
143 static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel,
146 struct ar5416AniState *aniState = &ah->curchan->ani;
147 struct ath_common *common = ath9k_hw_common(ah);
148 const struct ani_ofdm_level_entry *entry_ofdm;
149 const struct ani_cck_level_entry *entry_cck;
152 ath_dbg(common, ANI, "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
153 aniState->ofdmNoiseImmunityLevel,
154 immunityLevel, BEACON_RSSI(ah),
155 ATH9K_ANI_RSSI_THR_LOW,
156 ATH9K_ANI_RSSI_THR_HIGH);
159 aniState->ofdmNoiseImmunityLevel = immunityLevel;
161 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
162 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
164 if (aniState->spurImmunityLevel != entry_ofdm->spur_immunity_level)
165 ath9k_hw_ani_control(ah,
166 ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
167 entry_ofdm->spur_immunity_level);
169 if (aniState->firstepLevel != entry_ofdm->fir_step_level &&
170 entry_ofdm->fir_step_level >= entry_cck->fir_step_level)
171 ath9k_hw_ani_control(ah,
172 ATH9K_ANI_FIRSTEP_LEVEL,
173 entry_ofdm->fir_step_level);
175 weak_sig = entry_ofdm->ofdm_weak_signal_on;
176 if (ah->opmode == NL80211_IFTYPE_STATION &&
177 BEACON_RSSI(ah) <= ATH9K_ANI_RSSI_THR_HIGH)
180 if (aniState->ofdmWeakSigDetect != weak_sig)
181 ath9k_hw_ani_control(ah,
182 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
183 entry_ofdm->ofdm_weak_signal_on);
185 if (aniState->ofdmNoiseImmunityLevel >= ATH9K_ANI_OFDM_DEF_LEVEL) {
186 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH;
187 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_ABOVE_INI;
189 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_BELOW_INI;
190 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW;
194 static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
196 struct ar5416AniState *aniState;
201 aniState = &ah->curchan->ani;
203 if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL)
204 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1, false);
208 * Set the ANI settings to match an CCK level.
210 static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel,
213 struct ar5416AniState *aniState = &ah->curchan->ani;
214 struct ath_common *common = ath9k_hw_common(ah);
215 const struct ani_ofdm_level_entry *entry_ofdm;
216 const struct ani_cck_level_entry *entry_cck;
218 ath_dbg(common, ANI, "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
219 aniState->cckNoiseImmunityLevel, immunityLevel,
220 BEACON_RSSI(ah), ATH9K_ANI_RSSI_THR_LOW,
221 ATH9K_ANI_RSSI_THR_HIGH);
223 if (ah->opmode == NL80211_IFTYPE_STATION &&
224 BEACON_RSSI(ah) <= ATH9K_ANI_RSSI_THR_LOW &&
225 immunityLevel > ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI)
226 immunityLevel = ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI;
229 aniState->cckNoiseImmunityLevel = immunityLevel;
231 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
232 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
234 if (aniState->firstepLevel != entry_cck->fir_step_level &&
235 entry_cck->fir_step_level >= entry_ofdm->fir_step_level)
236 ath9k_hw_ani_control(ah,
237 ATH9K_ANI_FIRSTEP_LEVEL,
238 entry_cck->fir_step_level);
240 /* Skip MRC CCK for pre AR9003 families */
241 if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah))
244 if (aniState->mrcCCK != entry_cck->mrc_cck_on)
245 ath9k_hw_ani_control(ah,
247 entry_cck->mrc_cck_on);
250 static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
252 struct ar5416AniState *aniState;
257 aniState = &ah->curchan->ani;
259 if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL)
260 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1,
265 * only lower either OFDM or CCK errors per turn
266 * we lower the other one next time
268 static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
270 struct ar5416AniState *aniState;
272 aniState = &ah->curchan->ani;
274 /* lower OFDM noise immunity */
275 if (aniState->ofdmNoiseImmunityLevel > 0 &&
276 (aniState->ofdmsTurn || aniState->cckNoiseImmunityLevel == 0)) {
277 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel - 1,
282 /* lower CCK noise immunity */
283 if (aniState->cckNoiseImmunityLevel > 0)
284 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1,
289 * Restore the ANI parameters in the HAL and reset the statistics.
290 * This routine should be called for every hardware reset and for
291 * every channel change.
293 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
295 struct ar5416AniState *aniState = &ah->curchan->ani;
296 struct ath9k_channel *chan = ah->curchan;
297 struct ath_common *common = ath9k_hw_common(ah);
298 int ofdm_nil, cck_nil;
303 BUG_ON(aniState == NULL);
304 ah->stats.ast_ani_reset++;
306 /* only allow a subset of functions in AP mode */
307 if (ah->opmode == NL80211_IFTYPE_AP) {
308 if (IS_CHAN_2GHZ(chan)) {
309 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
310 ATH9K_ANI_FIRSTEP_LEVEL);
311 if (AR_SREV_9300_20_OR_LATER(ah))
312 ah->ani_function |= ATH9K_ANI_MRC_CCK;
314 ah->ani_function = 0;
317 /* always allow mode (on/off) to be controlled */
318 ah->ani_function |= ATH9K_ANI_MODE;
320 ofdm_nil = max_t(int, ATH9K_ANI_OFDM_DEF_LEVEL,
321 aniState->ofdmNoiseImmunityLevel);
322 cck_nil = max_t(int, ATH9K_ANI_CCK_DEF_LEVEL,
323 aniState->cckNoiseImmunityLevel);
326 (ah->opmode != NL80211_IFTYPE_STATION &&
327 ah->opmode != NL80211_IFTYPE_ADHOC)) {
329 * If we're scanning or in AP mode, the defaults (ini)
330 * should be in place. For an AP we assume the historical
331 * levels for this channel are probably outdated so start
332 * from defaults instead.
334 if (aniState->ofdmNoiseImmunityLevel !=
335 ATH9K_ANI_OFDM_DEF_LEVEL ||
336 aniState->cckNoiseImmunityLevel !=
337 ATH9K_ANI_CCK_DEF_LEVEL) {
339 "Restore defaults: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
344 aniState->ofdmNoiseImmunityLevel,
345 aniState->cckNoiseImmunityLevel);
347 ofdm_nil = ATH9K_ANI_OFDM_DEF_LEVEL;
348 cck_nil = ATH9K_ANI_CCK_DEF_LEVEL;
352 * restore historical levels for this channel
355 "Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
360 aniState->ofdmNoiseImmunityLevel,
361 aniState->cckNoiseImmunityLevel);
363 ath9k_hw_set_ofdm_nil(ah, ofdm_nil, is_scanning);
364 ath9k_hw_set_cck_nil(ah, cck_nil, is_scanning);
367 * enable phy counters if hw supports or if not, enable phy
368 * interrupts (so we can count each one)
370 ath9k_ani_restart(ah);
372 ENABLE_REGWRITE_BUFFER(ah);
374 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
375 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
377 REGWRITE_BUFFER_FLUSH(ah);
380 static bool ath9k_hw_ani_read_counters(struct ath_hw *ah)
382 struct ath_common *common = ath9k_hw_common(ah);
383 struct ar5416AniState *aniState = &ah->curchan->ani;
384 u32 phyCnt1, phyCnt2;
387 ath_hw_cycle_counters_update(common);
388 listenTime = ath_hw_get_listen_time(common);
390 if (listenTime <= 0) {
391 ah->stats.ast_ani_lneg_or_lzero++;
392 ath9k_ani_restart(ah);
396 aniState->listenTime += listenTime;
398 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
400 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
401 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
403 ah->stats.ast_ani_ofdmerrs += phyCnt1 - aniState->ofdmPhyErrCount;
404 aniState->ofdmPhyErrCount = phyCnt1;
406 ah->stats.ast_ani_cckerrs += phyCnt2 - aniState->cckPhyErrCount;
407 aniState->cckPhyErrCount = phyCnt2;
412 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan)
414 struct ar5416AniState *aniState;
415 struct ath_common *common = ath9k_hw_common(ah);
416 u32 ofdmPhyErrRate, cckPhyErrRate;
421 aniState = &ah->curchan->ani;
422 if (!ath9k_hw_ani_read_counters(ah))
425 ofdmPhyErrRate = aniState->ofdmPhyErrCount * 1000 /
426 aniState->listenTime;
427 cckPhyErrRate = aniState->cckPhyErrCount * 1000 /
428 aniState->listenTime;
431 "listenTime=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n",
432 aniState->listenTime,
433 aniState->ofdmNoiseImmunityLevel,
434 ofdmPhyErrRate, aniState->cckNoiseImmunityLevel,
435 cckPhyErrRate, aniState->ofdmsTurn);
437 if (aniState->listenTime > ah->aniperiod) {
438 if (cckPhyErrRate < ah->config.cck_trig_low &&
439 ofdmPhyErrRate < ah->config.ofdm_trig_low) {
440 ath9k_hw_ani_lower_immunity(ah);
441 aniState->ofdmsTurn = !aniState->ofdmsTurn;
442 } else if (ofdmPhyErrRate > ah->config.ofdm_trig_high) {
443 ath9k_hw_ani_ofdm_err_trigger(ah);
444 aniState->ofdmsTurn = false;
445 } else if (cckPhyErrRate > ah->config.cck_trig_high) {
446 ath9k_hw_ani_cck_err_trigger(ah);
447 aniState->ofdmsTurn = true;
449 ath9k_ani_restart(ah);
452 EXPORT_SYMBOL(ath9k_hw_ani_monitor);
454 void ath9k_enable_mib_counters(struct ath_hw *ah)
456 struct ath_common *common = ath9k_hw_common(ah);
458 ath_dbg(common, ANI, "Enable MIB counters\n");
460 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
462 ENABLE_REGWRITE_BUFFER(ah);
464 REG_WRITE(ah, AR_FILT_OFDM, 0);
465 REG_WRITE(ah, AR_FILT_CCK, 0);
466 REG_WRITE(ah, AR_MIBC,
467 ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
469 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
470 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
472 REGWRITE_BUFFER_FLUSH(ah);
475 /* Freeze the MIB counters, get the stats and then clear them */
476 void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
478 struct ath_common *common = ath9k_hw_common(ah);
480 ath_dbg(common, ANI, "Disable MIB counters\n");
482 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
483 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
484 REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
485 REG_WRITE(ah, AR_FILT_OFDM, 0);
486 REG_WRITE(ah, AR_FILT_CCK, 0);
488 EXPORT_SYMBOL(ath9k_hw_disable_mib_counters);
490 void ath9k_hw_ani_init(struct ath_hw *ah)
492 struct ath_common *common = ath9k_hw_common(ah);
495 ath_dbg(common, ANI, "Initialize ANI\n");
497 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH;
498 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW;
500 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH;
501 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW;
503 for (i = 0; i < ARRAY_SIZE(ah->channels); i++) {
504 struct ath9k_channel *chan = &ah->channels[i];
505 struct ar5416AniState *ani = &chan->ani;
507 ani->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
508 ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
509 ani->mrcCCK = AR_SREV_9300_20_OR_LATER(ah) ? true : false;
510 ani->ofdmsTurn = true;
511 ani->ofdmWeakSigDetect = true;
512 ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL;
513 ani->ofdmNoiseImmunityLevel = ATH9K_ANI_OFDM_DEF_LEVEL;
517 * since we expect some ongoing maintenance on the tables, let's sanity
518 * check here default level should not modify INI setting.
520 ah->aniperiod = ATH9K_ANI_PERIOD;
521 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL;
523 ath9k_ani_restart(ah);
524 ath9k_enable_mib_counters(ah);