drivers/net/wireless/ath/ath9k/ar9003_hw.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9003_mac.h"
  19 #include "ar9003_2p2_initvals.h"
  20 #include "ar9485_initvals.h"
  21 #include "ar9340_initvals.h"
  22 #include "ar9330_1p1_initvals.h"
  23 #include "ar9330_1p2_initvals.h"
  24 #include "ar9580_1p0_initvals.h"
  25 #include "ar9462_2p0_initvals.h"
  26
  27 /* General hardware code for the AR9003 hadware family */
  28
  29 /*
  30  * The AR9003 family uses a new INI format (pre, core, post
  31  * arrays per subsystem). This provides support for the
  32  * AR9003 2.2 chipsets.
  33  */
  34 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
  35 {
  36 #define PCIE_PLL_ON_CREQ_DIS_L1_2P0 \
  37                 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0
  38
  39 #define AR9462_BB_CTX_COEFJ(x)  \
  40                 ar9462_##x##_baseband_core_txfir_coeff_japan_2484
  41
  42 #define AR9462_BBC_TXIFR_COEFFJ \
  43                 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
  44         if (AR_SREV_9330_11(ah)) {
  45                 /* mac */
  46                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
  47                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
  48                                 ar9331_1p1_mac_core,
  49                                 ARRAY_SIZE(ar9331_1p1_mac_core), 2);
  50                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
  51                                 ar9331_1p1_mac_postamble,
  52                                 ARRAY_SIZE(ar9331_1p1_mac_postamble), 5);
  53
  54                 /* bb */
  55                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
  56                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
  57                                 ar9331_1p1_baseband_core,
  58                                 ARRAY_SIZE(ar9331_1p1_baseband_core), 2);
  59                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
  60                                 ar9331_1p1_baseband_postamble,
  61                                 ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5);
  62
  63                 /* radio */
  64                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
  65                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
  66                                 ar9331_1p1_radio_core,
  67                                 ARRAY_SIZE(ar9331_1p1_radio_core), 2);
  68                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
  69
  70                 /* soc */
  71                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
  72                                 ar9331_1p1_soc_preamble,
  73                                 ARRAY_SIZE(ar9331_1p1_soc_preamble), 2);
  74                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
  75                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
  76                                 ar9331_1p1_soc_postamble,
  77                                 ARRAY_SIZE(ar9331_1p1_soc_postamble), 2);
  78
  79                 /* rx/tx gain */
  80                 INIT_INI_ARRAY(&ah->iniModesRxGain,
  81                                 ar9331_common_rx_gain_1p1,
  82                                 ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2);
  83                 INIT_INI_ARRAY(&ah->iniModesTxGain,
  84                         ar9331_modes_lowest_ob_db_tx_gain_1p1,
  85                         ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
  86                         5);
  87
  88                 /* additional clock settings */
  89                 if (ah->is_clk_25mhz)
  90                         INIT_INI_ARRAY(&ah->iniModesAdditional,
  91                                         ar9331_1p1_xtal_25M,
  92                                         ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
  93                 else
  94                         INIT_INI_ARRAY(&ah->iniModesAdditional,
  95                                         ar9331_1p1_xtal_40M,
  96                                         ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
  97         } else if (AR_SREV_9330_12(ah)) {
  98                 /* mac */
  99                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 100                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 101                                 ar9331_1p2_mac_core,
 102                                 ARRAY_SIZE(ar9331_1p2_mac_core), 2);
 103                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 104                                 ar9331_1p2_mac_postamble,
 105                                 ARRAY_SIZE(ar9331_1p2_mac_postamble), 5);
 106
 107                 /* bb */
 108                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 109                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 110                                 ar9331_1p2_baseband_core,
 111                                 ARRAY_SIZE(ar9331_1p2_baseband_core), 2);
 112                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 113                                 ar9331_1p2_baseband_postamble,
 114                                 ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5);
 115
 116                 /* radio */
 117                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 118                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 119                                 ar9331_1p2_radio_core,
 120                                 ARRAY_SIZE(ar9331_1p2_radio_core), 2);
 121                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
 122
 123                 /* soc */
 124                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 125                                 ar9331_1p2_soc_preamble,
 126                                 ARRAY_SIZE(ar9331_1p2_soc_preamble), 2);
 127                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 128                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 129                                 ar9331_1p2_soc_postamble,
 130                                 ARRAY_SIZE(ar9331_1p2_soc_postamble), 2);
 131
 132                 /* rx/tx gain */
 133                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 134                                 ar9331_common_rx_gain_1p2,
 135                                 ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2);
 136                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 137                         ar9331_modes_lowest_ob_db_tx_gain_1p2,
 138                         ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
 139                         5);
 140
 141                 /* additional clock settings */
 142                 if (ah->is_clk_25mhz)
 143                         INIT_INI_ARRAY(&ah->iniModesAdditional,
 144                                         ar9331_1p2_xtal_25M,
 145                                         ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
 146                 else
 147                         INIT_INI_ARRAY(&ah->iniModesAdditional,
 148                                         ar9331_1p2_xtal_40M,
 149                                         ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
 150         } else if (AR_SREV_9340(ah)) {
 151                 /* mac */
 152                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 153                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 154                                 ar9340_1p0_mac_core,
 155                                 ARRAY_SIZE(ar9340_1p0_mac_core), 2);
 156                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 157                                 ar9340_1p0_mac_postamble,
 158                                 ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
 159
 160                 /* bb */
 161                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 162                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 163                                 ar9340_1p0_baseband_core,
 164                                 ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
 165                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 166                                 ar9340_1p0_baseband_postamble,
 167                                 ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
 168
 169                 /* radio */
 170                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 171                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 172                                 ar9340_1p0_radio_core,
 173                                 ARRAY_SIZE(ar9340_1p0_radio_core), 2);
 174                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 175                                 ar9340_1p0_radio_postamble,
 176                                 ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
 177
 178                 /* soc */
 179                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 180                                 ar9340_1p0_soc_preamble,
 181                                 ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
 182                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 183                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 184                                 ar9340_1p0_soc_postamble,
 185                                 ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
 186
 187                 /* rx/tx gain */
 188                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 189                                 ar9340Common_wo_xlna_rx_gain_table_1p0,
 190                                 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
 191                                 5);
 192                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 193                                 ar9340Modes_high_ob_db_tx_gain_table_1p0,
 194                                 ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
 195                                 5);
 196
 197                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 198                                 ar9340Modes_fast_clock_1p0,
 199                                 ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
 200                                 3);
 201
 202                 INIT_INI_ARRAY(&ah->iniModesAdditional_40M,
 203                                 ar9340_1p0_radio_core_40M,
 204                                 ARRAY_SIZE(ar9340_1p0_radio_core_40M),
 205                                 2);
 206         } else if (AR_SREV_9485_11(ah)) {
 207                 /* mac */
 208                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 209                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 210                                 ar9485_1_1_mac_core,
 211                                 ARRAY_SIZE(ar9485_1_1_mac_core), 2);
 212                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 213                                 ar9485_1_1_mac_postamble,
 214                                 ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
 215
 216                 /* bb */
 217                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1,
 218                                 ARRAY_SIZE(ar9485_1_1), 2);
 219                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 220                                 ar9485_1_1_baseband_core,
 221                                 ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
 222                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 223                                 ar9485_1_1_baseband_postamble,
 224                                 ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
 225
 226                 /* radio */
 227                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 228                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 229                                 ar9485_1_1_radio_core,
 230                                 ARRAY_SIZE(ar9485_1_1_radio_core), 2);
 231                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 232                                 ar9485_1_1_radio_postamble,
 233                                 ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
 234
 235                 /* soc */
 236                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 237                                 ar9485_1_1_soc_preamble,
 238                                 ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
 239                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 240                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
 241
 242                 /* rx/tx gain */
 243                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 244                                 ar9485Common_wo_xlna_rx_gain_1_1,
 245                                 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
 246                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 247                                 ar9485_modes_lowest_ob_db_tx_gain_1_1,
 248                                 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
 249                                 5);
 250
 251                 /* Load PCIE SERDES settings from INI */
 252
 253                 /* Awake Setting */
 254
 255                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 256                                 ar9485_1_1_pcie_phy_clkreq_disable_L1,
 257                                 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
 258                                 2);
 259
 260                 /* Sleep Setting */
 261
 262                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 263                                 ar9485_1_1_pcie_phy_clkreq_disable_L1,
 264                                 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
 265                                 2);
 266         } else if (AR_SREV_9462_20(ah)) {
 267
 268                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 269                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core,
 270                                 ARRAY_SIZE(ar9462_2p0_mac_core), 2);
 271                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 272                                 ar9462_2p0_mac_postamble,
 273                                 ARRAY_SIZE(ar9462_2p0_mac_postamble), 5);
 274
 275                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 276                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 277                                 ar9462_2p0_baseband_core,
 278                                 ARRAY_SIZE(ar9462_2p0_baseband_core), 2);
 279                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 280                                 ar9462_2p0_baseband_postamble,
 281                                 ARRAY_SIZE(ar9462_2p0_baseband_postamble), 5);
 282
 283                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 284                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 285                                 ar9462_2p0_radio_core,
 286                                 ARRAY_SIZE(ar9462_2p0_radio_core), 2);
 287                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 288                                 ar9462_2p0_radio_postamble,
 289                                 ARRAY_SIZE(ar9462_2p0_radio_postamble), 5);
 290                 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
 291                                 ar9462_2p0_radio_postamble_sys2ant,
 292                                 ARRAY_SIZE(ar9462_2p0_radio_postamble_sys2ant),
 293                                 5);
 294
 295                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 296                                 ar9462_2p0_soc_preamble,
 297                                 ARRAY_SIZE(ar9462_2p0_soc_preamble), 2);
 298                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 299                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 300                                 ar9462_2p0_soc_postamble,
 301                                 ARRAY_SIZE(ar9462_2p0_soc_postamble), 5);
 302
 303                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 304                                 ar9462_common_rx_gain_table_2p0,
 305                                 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2);
 306
 307                 INIT_INI_ARRAY(&ah->ini_BTCOEX_MAX_TXPWR,
 308                                 ar9462_2p0_BTCOEX_MAX_TXPWR_table,
 309                                 ARRAY_SIZE(ar9462_2p0_BTCOEX_MAX_TXPWR_table),
 310                                 2);
 311
 312                 /* Awake -> Sleep Setting */
 313                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 314                                 PCIE_PLL_ON_CREQ_DIS_L1_2P0,
 315                                 ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
 316                                 2);
 317                 /* Sleep -> Awake Setting */
 318                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 319                                 PCIE_PLL_ON_CREQ_DIS_L1_2P0,
 320                                 ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
 321                                 2);
 322
 323                 /* Fast clock modal settings */
 324                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 325                                 ar9462_modes_fast_clock_2p0,
 326                                 ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3);
 327
 328                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 329                                 AR9462_BB_CTX_COEFJ(2p0),
 330                                 ARRAY_SIZE(AR9462_BB_CTX_COEFJ(2p0)), 2);
 331
 332                 INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
 333                                 ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
 334
 335         } else if (AR_SREV_9580(ah)) {
 336                 /* mac */
 337                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 338                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 339                                 ar9580_1p0_mac_core,
 340                                 ARRAY_SIZE(ar9580_1p0_mac_core), 2);
 341                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 342                                 ar9580_1p0_mac_postamble,
 343                                 ARRAY_SIZE(ar9580_1p0_mac_postamble), 5);
 344
 345                 /* bb */
 346                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 347                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 348                                 ar9580_1p0_baseband_core,
 349                                 ARRAY_SIZE(ar9580_1p0_baseband_core), 2);
 350                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 351                                 ar9580_1p0_baseband_postamble,
 352                                 ARRAY_SIZE(ar9580_1p0_baseband_postamble), 5);
 353
 354                 /* radio */
 355                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 356                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 357                                 ar9580_1p0_radio_core,
 358                                 ARRAY_SIZE(ar9580_1p0_radio_core), 2);
 359                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 360                                 ar9580_1p0_radio_postamble,
 361                                 ARRAY_SIZE(ar9580_1p0_radio_postamble), 5);
 362
 363                 /* soc */
 364                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 365                                 ar9580_1p0_soc_preamble,
 366                                 ARRAY_SIZE(ar9580_1p0_soc_preamble), 2);
 367                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 368                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 369                                 ar9580_1p0_soc_postamble,
 370                                 ARRAY_SIZE(ar9580_1p0_soc_postamble), 5);
 371
 372                 /* rx/tx gain */
 373                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 374                                 ar9580_1p0_rx_gain_table,
 375                                 ARRAY_SIZE(ar9580_1p0_rx_gain_table), 2);
 376                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 377                                 ar9580_1p0_low_ob_db_tx_gain_table,
 378                                 ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
 379                                 5);
 380
 381                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 382                                 ar9580_1p0_modes_fast_clock,
 383                                 ARRAY_SIZE(ar9580_1p0_modes_fast_clock),
 384                                 3);
 385         } else {
 386                 /* mac */
 387                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 388                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 389                                 ar9300_2p2_mac_core,
 390                                 ARRAY_SIZE(ar9300_2p2_mac_core), 2);
 391                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 392                                 ar9300_2p2_mac_postamble,
 393                                 ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
 394
 395                 /* bb */
 396                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 397                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 398                                 ar9300_2p2_baseband_core,
 399                                 ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
 400                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 401                                 ar9300_2p2_baseband_postamble,
 402                                 ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
 403
 404                 /* radio */
 405                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 406                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 407                                 ar9300_2p2_radio_core,
 408                                 ARRAY_SIZE(ar9300_2p2_radio_core), 2);
 409                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 410                                 ar9300_2p2_radio_postamble,
 411                                 ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
 412
 413                 /* soc */
 414                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 415                                 ar9300_2p2_soc_preamble,
 416                                 ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
 417                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 418                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 419                                 ar9300_2p2_soc_postamble,
 420                                 ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
 421
 422                 /* rx/tx gain */
 423                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 424                                 ar9300Common_rx_gain_table_2p2,
 425                                 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
 426                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 427                                 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
 428                                 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
 429                                 5);
 430
 431                 /* Load PCIE SERDES settings from INI */
 432
 433                 /* Awake Setting */
 434
 435                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 436                                 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
 437                                 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
 438                                 2);
 439
 440                 /* Sleep Setting */
 441
 442                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 443                                 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
 444                                 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
 445                                 2);
 446
 447                 /* Fast clock modal settings */
 448                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 449                                 ar9300Modes_fast_clock_2p2,
 450                                 ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
 451                                 3);
 452         }
 453 }
 454
 455 static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
 456 {
 457         if (AR_SREV_9330_12(ah))
 458                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 459                         ar9331_modes_lowest_ob_db_tx_gain_1p2,
 460                         ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
 461                         5);
 462         else if (AR_SREV_9330_11(ah))
 463                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 464                         ar9331_modes_lowest_ob_db_tx_gain_1p1,
 465                         ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
 466                         5);
 467         else if (AR_SREV_9340(ah))
 468                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 469                         ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
 470                         ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
 471                         5);
 472         else if (AR_SREV_9485_11(ah))
 473                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 474                         ar9485_modes_lowest_ob_db_tx_gain_1_1,
 475                         ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
 476                         5);
 477         else if (AR_SREV_9580(ah))
 478                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 479                         ar9580_1p0_lowest_ob_db_tx_gain_table,
 480                         ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
 481                         5);
 482         else if (AR_SREV_9462_20(ah))
 483                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 484                         ar9462_modes_low_ob_db_tx_gain_table_2p0,
 485                         ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_2p0),
 486                         5);
 487         else
 488                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 489                         ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
 490                         ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
 491                         5);
 492 }
 493
 494 static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
 495 {
 496         if (AR_SREV_9330_12(ah))
 497                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 498                         ar9331_modes_high_ob_db_tx_gain_1p2,
 499                         ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2),
 500                         5);
 501         else if (AR_SREV_9330_11(ah))
 502                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 503                         ar9331_modes_high_ob_db_tx_gain_1p1,
 504                         ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1),
 505                         5);
 506         else if (AR_SREV_9340(ah))
 507                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 508                         ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
 509                         ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
 510                         5);
 511         else if (AR_SREV_9485_11(ah))
 512                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 513                         ar9485Modes_high_ob_db_tx_gain_1_1,
 514                         ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
 515                         5);
 516         else if (AR_SREV_9580(ah))
 517                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 518                         ar9580_1p0_high_ob_db_tx_gain_table,
 519                         ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
 520                         5);
 521         else if (AR_SREV_9462_20(ah))
 522                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 523                         ar9462_modes_high_ob_db_tx_gain_table_2p0,
 524                         ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_2p0),
 525                         5);
 526         else
 527                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 528                         ar9300Modes_high_ob_db_tx_gain_table_2p2,
 529                         ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
 530                         5);
 531 }
 532
 533 static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
 534 {
 535         if (AR_SREV_9330_12(ah))
 536                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 537                         ar9331_modes_low_ob_db_tx_gain_1p2,
 538                         ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2),
 539                         5);
 540         else if (AR_SREV_9330_11(ah))
 541                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 542                         ar9331_modes_low_ob_db_tx_gain_1p1,
 543                         ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1),
 544                         5);
 545         else if (AR_SREV_9340(ah))
 546                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 547                         ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
 548                         ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
 549                         5);
 550         else if (AR_SREV_9485_11(ah))
 551                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 552                         ar9485Modes_low_ob_db_tx_gain_1_1,
 553                         ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
 554                         5);
 555         else if (AR_SREV_9580(ah))
 556                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 557                         ar9580_1p0_low_ob_db_tx_gain_table,
 558                         ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
 559                         5);
 560         else
 561                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 562                         ar9300Modes_low_ob_db_tx_gain_table_2p2,
 563                         ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
 564                         5);
 565 }
 566
 567 static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
 568 {
 569         if (AR_SREV_9330_12(ah))
 570                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 571                         ar9331_modes_high_power_tx_gain_1p2,
 572                         ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2),
 573                         5);
 574         else if (AR_SREV_9330_11(ah))
 575                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 576                         ar9331_modes_high_power_tx_gain_1p1,
 577                         ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1),
 578                         5);
 579         else if (AR_SREV_9340(ah))
 580                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 581                         ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
 582                         ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
 583                         5);
 584         else if (AR_SREV_9485_11(ah))
 585                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 586                         ar9485Modes_high_power_tx_gain_1_1,
 587                         ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
 588                         5);
 589         else if (AR_SREV_9580(ah))
 590                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 591                         ar9580_1p0_high_power_tx_gain_table,
 592                         ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table),
 593                         5);
 594         else
 595                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 596                         ar9300Modes_high_power_tx_gain_table_2p2,
 597                         ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
 598                         5);
 599 }
 600
 601 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
 602 {
 603         switch (ar9003_hw_get_tx_gain_idx(ah)) {
 604         case 0:
 605         default:
 606                 ar9003_tx_gain_table_mode0(ah);
 607                 break;
 608         case 1:
 609                 ar9003_tx_gain_table_mode1(ah);
 610                 break;
 611         case 2:
 612                 ar9003_tx_gain_table_mode2(ah);
 613                 break;
 614         case 3:
 615                 ar9003_tx_gain_table_mode3(ah);
 616                 break;
 617         }
 618 }
 619
 620 static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
 621 {
 622         if (AR_SREV_9330_12(ah))
 623                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 624                                 ar9331_common_rx_gain_1p2,
 625                                 ARRAY_SIZE(ar9331_common_rx_gain_1p2),
 626                                 2);
 627         else if (AR_SREV_9330_11(ah))
 628                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 629                                 ar9331_common_rx_gain_1p1,
 630                                 ARRAY_SIZE(ar9331_common_rx_gain_1p1),
 631                                 2);
 632         else if (AR_SREV_9340(ah))
 633                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 634                                 ar9340Common_rx_gain_table_1p0,
 635                                 ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
 636                                 2);
 637         else if (AR_SREV_9485_11(ah))
 638                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 639                                 ar9485Common_wo_xlna_rx_gain_1_1,
 640                                 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
 641                                 2);
 642         else if (AR_SREV_9580(ah))
 643                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 644                                 ar9580_1p0_rx_gain_table,
 645                                 ARRAY_SIZE(ar9580_1p0_rx_gain_table),
 646                                 2);
 647         else if (AR_SREV_9462_20(ah))
 648                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 649                                 ar9462_common_rx_gain_table_2p0,
 650                                 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0),
 651                                 2);
 652         else
 653                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 654                                 ar9300Common_rx_gain_table_2p2,
 655                                 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
 656                                 2);
 657 }
 658
 659 static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
 660 {
 661         if (AR_SREV_9330_12(ah))
 662                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 663                         ar9331_common_wo_xlna_rx_gain_1p2,
 664                         ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2),
 665                         2);
 666         else if (AR_SREV_9330_11(ah))
 667                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 668                         ar9331_common_wo_xlna_rx_gain_1p1,
 669                         ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1),
 670                         2);
 671         else if (AR_SREV_9340(ah))
 672                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 673                         ar9340Common_wo_xlna_rx_gain_table_1p0,
 674                         ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
 675                         2);
 676         else if (AR_SREV_9485_11(ah))
 677                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 678                         ar9485Common_wo_xlna_rx_gain_1_1,
 679                         ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
 680                         2);
 681         else if (AR_SREV_9462_20(ah))
 682                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 683                         ar9462_common_wo_xlna_rx_gain_table_2p0,
 684                         ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
 685                         2);
 686         else if (AR_SREV_9580(ah))
 687                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 688                         ar9580_1p0_wo_xlna_rx_gain_table,
 689                         ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
 690                         2);
 691         else
 692                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 693                         ar9300Common_wo_xlna_rx_gain_table_2p2,
 694                         ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
 695                         2);
 696 }
 697
 698 static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
 699 {
 700         if (AR_SREV_9462_20(ah))
 701                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 702                                ar9462_common_mixed_rx_gain_table_2p0,
 703                                ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);
 704 }
 705
 706 static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
 707 {
 708         switch (ar9003_hw_get_rx_gain_idx(ah)) {
 709         case 0:
 710         default:
 711                 ar9003_rx_gain_table_mode0(ah);
 712                 break;
 713         case 1:
 714                 ar9003_rx_gain_table_mode1(ah);
 715                 break;
 716         case 2:
 717                 ar9003_rx_gain_table_mode2(ah);
 718                 break;
 719         }
 720 }
 721
 722 /* set gain table pointers according to values read from the eeprom */
 723 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
 724 {
 725         ar9003_tx_gain_table_apply(ah);
 726         ar9003_rx_gain_table_apply(ah);
 727 }
 728
 729 /*
 730  * Helper for ASPM support.
 731  *
 732  * Disable PLL when in L0s as well as receiver clock when in L1.
 733  * This power saving option must be enabled through the SerDes.
 734  *
 735  * Programming the SerDes must go through the same 288 bit serial shift
 736  * register as the other analog registers.  Hence the 9 writes.
 737  */
 738 static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
 739                                          bool power_off)
 740 {
 741         /* Nothing to do on restore for 11N */
 742         if (!power_off /* !restore */) {
 743                 /* set bit 19 to allow forcing of pcie core into L1 state */
 744                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 745
 746                 /* Several PCIe massages to ensure proper behaviour */
 747                 if (ah->config.pcie_waen)
 748                         REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
 749                 else
 750                         REG_WRITE(ah, AR_WA, ah->WARegVal);
 751         }
 752
 753         /*
 754          * Configire PCIE after Ini init. SERDES values now come from ini file
 755          * This enables PCIe low power mode.
 756          */
 757         if (ah->config.pcieSerDesWrite) {
 758                 unsigned int i;
 759                 struct ar5416IniArray *array;
 760
 761                 array = power_off ? &ah->iniPcieSerdes :
 762                                     &ah->iniPcieSerdesLowPower;
 763
 764                 for (i = 0; i < array->ia_rows; i++) {
 765                         REG_WRITE(ah,
 766                                   INI_RA(array, i, 0),
 767                                   INI_RA(array, i, 1));
 768                 }
 769         }
 770 }
 771
 772 /* Sets up the AR9003 hardware familiy callbacks */
 773 void ar9003_hw_attach_ops(struct ath_hw *ah)
 774 {
 775         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
 776         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
 777
 778         priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
 779         priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
 780
 781         ops->config_pci_powersave = ar9003_hw_configpcipowersave;
 782
 783         ar9003_hw_attach_phy_ops(ah);
 784         ar9003_hw_attach_calib_ops(ah);
 785         ar9003_hw_attach_mac_ops(ah);
 786 }