drivers/net/wireless/ath/ath9k/ar9003_phy.c

   1 /*
   2  * Copyright (c) 2010-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/export.h>
  18 #include "hw.h"
  19 #include "ar9003_phy.h"
  20
  21 static const int firstep_table[] =
  22 /* level:  0   1   2   3   4   5   6   7   8  */
  23         { -4, -2,  0,  2,  4,  6,  8, 10, 12 }; /* lvl 0-8, default 2 */
  24
  25 static const int cycpwrThr1_table[] =
  26 /* level:  0   1   2   3   4   5   6   7   8  */
  27         { -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */
  28
  29 /*
  30  * register values to turn OFDM weak signal detection OFF
  31  */
  32 static const int m1ThreshLow_off = 127;
  33 static const int m2ThreshLow_off = 127;
  34 static const int m1Thresh_off = 127;
  35 static const int m2Thresh_off = 127;
  36 static const int m2CountThr_off =  31;
  37 static const int m2CountThrLow_off =  63;
  38 static const int m1ThreshLowExt_off = 127;
  39 static const int m2ThreshLowExt_off = 127;
  40 static const int m1ThreshExt_off = 127;
  41 static const int m2ThreshExt_off = 127;
  42
  43 /**
  44  * ar9003_hw_set_channel - set channel on single-chip device
  45  * @ah: atheros hardware structure
  46  * @chan:
  47  *
  48  * This is the function to change channel on single-chip devices, that is
  49  * for AR9300 family of chipsets.
  50  *
  51  * This function takes the channel value in MHz and sets
  52  * hardware channel value. Assumes writes have been enabled to analog bus.
  53  *
  54  * Actual Expression,
  55  *
  56  * For 2GHz channel,
  57  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  58  * (freq_ref = 40MHz)
  59  *
  60  * For 5GHz channel,
  61  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
  62  * (freq_ref = 40MHz/(24>>amodeRefSel))
  63  *
  64  * For 5GHz channels which are 5MHz spaced,
  65  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  66  * (freq_ref = 40MHz)
  67  */
  68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
  69 {
  70         u16 bMode, fracMode = 0, aModeRefSel = 0;
  71         u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
  72         struct chan_centers centers;
  73         int loadSynthChannel;
  74
  75         ath9k_hw_get_channel_centers(ah, chan, &centers);
  76         freq = centers.synth_center;
  77
  78         if (freq < 4800) {     /* 2 GHz, fractional mode */
  79                 if (AR_SREV_9330(ah)) {
  80                         if (ah->is_clk_25mhz)
  81                                 div = 75;
  82                         else
  83                                 div = 120;
  84
  85                         channelSel = (freq * 4) / div;
  86                         chan_frac = (((freq * 4) % div) * 0x20000) / div;
  87                         channelSel = (channelSel << 17) | chan_frac;
  88                 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
  89                         /*
  90                          * freq_ref = 40 / (refdiva >> amoderefsel);
  91                          * where refdiva=1 and amoderefsel=0
  92                          * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
  93                          * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
  94                          */
  95                         channelSel = (freq * 4) / 120;
  96                         chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
  97                         channelSel = (channelSel << 17) | chan_frac;
  98                 } else if (AR_SREV_9340(ah)) {
  99                         if (ah->is_clk_25mhz) {
 100                                 channelSel = (freq * 2) / 75;
 101                                 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
 102                                 channelSel = (channelSel << 17) | chan_frac;
 103                         } else {
 104                                 channelSel = CHANSEL_2G(freq) >> 1;
 105                         }
 106                 } else if (AR_SREV_9550(ah)) {
 107                         if (ah->is_clk_25mhz)
 108                                 div = 75;
 109                         else
 110                                 div = 120;
 111
 112                         channelSel = (freq * 4) / div;
 113                         chan_frac = (((freq * 4) % div) * 0x20000) / div;
 114                         channelSel = (channelSel << 17) | chan_frac;
 115                 } else {
 116                         channelSel = CHANSEL_2G(freq);
 117                 }
 118                 /* Set to 2G mode */
 119                 bMode = 1;
 120         } else {
 121                 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) &&
 122                     ah->is_clk_25mhz) {
 123                         channelSel = freq / 75;
 124                         chan_frac = ((freq % 75) * 0x20000) / 75;
 125                         channelSel = (channelSel << 17) | chan_frac;
 126                 } else {
 127                         channelSel = CHANSEL_5G(freq);
 128                         /* Doubler is ON, so, divide channelSel by 2. */
 129                         channelSel >>= 1;
 130                 }
 131                 /* Set to 5G mode */
 132                 bMode = 0;
 133         }
 134
 135         /* Enable fractional mode for all channels */
 136         fracMode = 1;
 137         aModeRefSel = 0;
 138         loadSynthChannel = 0;
 139
 140         reg32 = (bMode << 29);
 141         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
 142
 143         /* Enable Long shift Select for Synthesizer */
 144         REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
 145                       AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
 146
 147         /* Program Synth. setting */
 148         reg32 = (channelSel << 2) | (fracMode << 30) |
 149                 (aModeRefSel << 28) | (loadSynthChannel << 31);
 150         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 151
 152         /* Toggle Load Synth channel bit */
 153         loadSynthChannel = 1;
 154         reg32 = (channelSel << 2) | (fracMode << 30) |
 155                 (aModeRefSel << 28) | (loadSynthChannel << 31);
 156         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 157
 158         ah->curchan = chan;
 159
 160         return 0;
 161 }
 162
 163 /**
 164  * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
 165  * @ah: atheros hardware structure
 166  * @chan:
 167  *
 168  * For single-chip solutions. Converts to baseband spur frequency given the
 169  * input channel frequency and compute register settings below.
 170  *
 171  * Spur mitigation for MRC CCK
 172  */
 173 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
 174                                             struct ath9k_channel *chan)
 175 {
 176         static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
 177         int cur_bb_spur, negative = 0, cck_spur_freq;
 178         int i;
 179         int range, max_spur_cnts, synth_freq;
 180         u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
 181
 182         /*
 183          * Need to verify range +/- 10 MHz in control channel, otherwise spur
 184          * is out-of-band and can be ignored.
 185          */
 186
 187         if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
 188             AR_SREV_9550(ah)) {
 189                 if (spur_fbin_ptr[0] == 0) /* No spur */
 190                         return;
 191                 max_spur_cnts = 5;
 192                 if (IS_CHAN_HT40(chan)) {
 193                         range = 19;
 194                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 195                                            AR_PHY_GC_DYN2040_PRI_CH) == 0)
 196                                 synth_freq = chan->channel + 10;
 197                         else
 198                                 synth_freq = chan->channel - 10;
 199                 } else {
 200                         range = 10;
 201                         synth_freq = chan->channel;
 202                 }
 203         } else {
 204                 range = AR_SREV_9462(ah) ? 5 : 10;
 205                 max_spur_cnts = 4;
 206                 synth_freq = chan->channel;
 207         }
 208
 209         for (i = 0; i < max_spur_cnts; i++) {
 210                 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
 211                         continue;
 212
 213                 negative = 0;
 214                 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
 215                     AR_SREV_9550(ah))
 216                         cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
 217                                                          IS_CHAN_2GHZ(chan));
 218                 else
 219                         cur_bb_spur = spur_freq[i];
 220
 221                 cur_bb_spur -= synth_freq;
 222                 if (cur_bb_spur < 0) {
 223                         negative = 1;
 224                         cur_bb_spur = -cur_bb_spur;
 225                 }
 226                 if (cur_bb_spur < range) {
 227                         cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
 228
 229                         if (negative == 1)
 230                                 cck_spur_freq = -cck_spur_freq;
 231
 232                         cck_spur_freq = cck_spur_freq & 0xfffff;
 233
 234                         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 235                                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
 236                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 237                                       AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
 238                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 239                                       AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
 240                                       0x2);
 241                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 242                                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
 243                                       0x1);
 244                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 245                                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
 246                                       cck_spur_freq);
 247
 248                         return;
 249                 }
 250         }
 251
 252         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 253                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
 254         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 255                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
 256         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 257                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
 258 }
 259
 260 /* Clean all spur register fields */
 261 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
 262 {
 263         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 264                       AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
 265         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 266                       AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
 267         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 268                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
 269         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 270                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
 271         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 272                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
 273         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 274                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
 275         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 276                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
 277         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 278                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
 279         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 280                       AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
 281
 282         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 283                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
 284         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 285                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
 286         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 287                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
 288         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 289                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
 290         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 291                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
 292         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 293                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
 294         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 295                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
 296         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 297                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
 298         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 299                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
 300         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 301                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
 302 }
 303
 304 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
 305                                 int freq_offset,
 306                                 int spur_freq_sd,
 307                                 int spur_delta_phase,
 308                                 int spur_subchannel_sd,
 309                                 int range,
 310                                 int synth_freq)
 311 {
 312         int mask_index = 0;
 313
 314         /* OFDM Spur mitigation */
 315         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 316                  AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
 317         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 318                       AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
 319         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 320                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
 321         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 322                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
 323         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 324                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
 325
 326         if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
 327                 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 328                               AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
 329
 330         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 331                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
 332         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 333                       AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
 334         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 335                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
 336
 337         if (!AR_SREV_9340(ah) &&
 338             REG_READ_FIELD(ah, AR_PHY_MODE,
 339                            AR_PHY_MODE_DYNAMIC) == 0x1)
 340                 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 341                               AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
 342
 343         mask_index = (freq_offset << 4) / 5;
 344         if (mask_index < 0)
 345                 mask_index = mask_index - 1;
 346
 347         mask_index = mask_index & 0x7f;
 348
 349         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 350                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
 351         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 352                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
 353         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 354                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
 355         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 356                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
 357         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 358                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
 359         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 360                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
 361         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 362                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
 363         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 364                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
 365         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 366                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
 367         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 368                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
 369 }
 370
 371 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
 372                                      int freq_offset)
 373 {
 374         int mask_index = 0;
 375
 376         mask_index = (freq_offset << 4) / 5;
 377         if (mask_index < 0)
 378                 mask_index = mask_index - 1;
 379
 380         mask_index = mask_index & 0x7f;
 381
 382         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 383                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
 384                       mask_index);
 385
 386         /* A == B */
 387         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
 388                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
 389                       mask_index);
 390
 391         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 392                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
 393                       mask_index);
 394         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 395                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
 396         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 397                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
 398
 399         /* A == B */
 400         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
 401                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
 402 }
 403
 404 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
 405                                      struct ath9k_channel *chan,
 406                                      int freq_offset,
 407                                      int range,
 408                                      int synth_freq)
 409 {
 410         int spur_freq_sd = 0;
 411         int spur_subchannel_sd = 0;
 412         int spur_delta_phase = 0;
 413
 414         if (IS_CHAN_HT40(chan)) {
 415                 if (freq_offset < 0) {
 416                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 417                                            AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 418                                 spur_subchannel_sd = 1;
 419                         else
 420                                 spur_subchannel_sd = 0;
 421
 422                         spur_freq_sd = ((freq_offset + 10) << 9) / 11;
 423
 424                 } else {
 425                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 426                             AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 427                                 spur_subchannel_sd = 0;
 428                         else
 429                                 spur_subchannel_sd = 1;
 430
 431                         spur_freq_sd = ((freq_offset - 10) << 9) / 11;
 432
 433                 }
 434
 435                 spur_delta_phase = (freq_offset << 17) / 5;
 436
 437         } else {
 438                 spur_subchannel_sd = 0;
 439                 spur_freq_sd = (freq_offset << 9) /11;
 440                 spur_delta_phase = (freq_offset << 18) / 5;
 441         }
 442
 443         spur_freq_sd = spur_freq_sd & 0x3ff;
 444         spur_delta_phase = spur_delta_phase & 0xfffff;
 445
 446         ar9003_hw_spur_ofdm(ah,
 447                             freq_offset,
 448                             spur_freq_sd,
 449                             spur_delta_phase,
 450                             spur_subchannel_sd,
 451                             range, synth_freq);
 452 }
 453
 454 /* Spur mitigation for OFDM */
 455 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
 456                                          struct ath9k_channel *chan)
 457 {
 458         int synth_freq;
 459         int range = 10;
 460         int freq_offset = 0;
 461         int mode;
 462         u8* spurChansPtr;
 463         unsigned int i;
 464         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 465
 466         if (IS_CHAN_5GHZ(chan)) {
 467                 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
 468                 mode = 0;
 469         }
 470         else {
 471                 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
 472                 mode = 1;
 473         }
 474
 475         if (spurChansPtr[0] == 0)
 476                 return; /* No spur in the mode */
 477
 478         if (IS_CHAN_HT40(chan)) {
 479                 range = 19;
 480                 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 481                                    AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 482                         synth_freq = chan->channel - 10;
 483                 else
 484                         synth_freq = chan->channel + 10;
 485         } else {
 486                 range = 10;
 487                 synth_freq = chan->channel;
 488         }
 489
 490         ar9003_hw_spur_ofdm_clear(ah);
 491
 492         for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
 493                 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
 494                 freq_offset -= synth_freq;
 495                 if (abs(freq_offset) < range) {
 496                         ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
 497                                                  range, synth_freq);
 498
 499                         if (AR_SREV_9565(ah) && (i < 4)) {
 500                                 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
 501                                                                  mode);
 502                                 freq_offset -= synth_freq;
 503                                 if (abs(freq_offset) < range)
 504                                         ar9003_hw_spur_ofdm_9565(ah, freq_offset);
 505                         }
 506
 507                         break;
 508                 }
 509         }
 510 }
 511
 512 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
 513                                     struct ath9k_channel *chan)
 514 {
 515         if (!AR_SREV_9565(ah))
 516                 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
 517         ar9003_hw_spur_mitigate_ofdm(ah, chan);
 518 }
 519
 520 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
 521                                          struct ath9k_channel *chan)
 522 {
 523         u32 pll;
 524
 525         pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
 526
 527         if (chan && IS_CHAN_HALF_RATE(chan))
 528                 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
 529         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 530                 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
 531
 532         pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
 533
 534         return pll;
 535 }
 536
 537 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
 538                                        struct ath9k_channel *chan)
 539 {
 540         u32 phymode;
 541         u32 enableDacFifo = 0;
 542
 543         enableDacFifo =
 544                 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
 545
 546         /* Enable 11n HT, 20 MHz */
 547         phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
 548                   AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
 549
 550         /* Configure baseband for dynamic 20/40 operation */
 551         if (IS_CHAN_HT40(chan)) {
 552                 phymode |= AR_PHY_GC_DYN2040_EN;
 553                 /* Configure control (primary) channel at +-10MHz */
 554                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 555                     (chan->chanmode == CHANNEL_G_HT40PLUS))
 556                         phymode |= AR_PHY_GC_DYN2040_PRI_CH;
 557
 558         }
 559
 560         /* make sure we preserve INI settings */
 561         phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
 562         /* turn off Green Field detection for STA for now */
 563         phymode &= ~AR_PHY_GC_GF_DETECT_EN;
 564
 565         REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
 566
 567         /* Configure MAC for 20/40 operation */
 568         ath9k_hw_set11nmac2040(ah);
 569
 570         /* global transmit timeout (25 TUs default)*/
 571         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
 572         /* carrier sense timeout */
 573         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
 574 }
 575
 576 static void ar9003_hw_init_bb(struct ath_hw *ah,
 577                               struct ath9k_channel *chan)
 578 {
 579         u32 synthDelay;
 580
 581         /*
 582          * Wait for the frequency synth to settle (synth goes on
 583          * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
 584          * Value is in 100ns increments.
 585          */
 586         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 587
 588         /* Activate the PHY (includes baseband activate + synthesizer on) */
 589         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 590         ath9k_hw_synth_delay(ah, chan, synthDelay);
 591 }
 592
 593 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
 594 {
 595         if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
 596                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 597                             AR_PHY_SWAP_ALT_CHAIN);
 598
 599         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
 600         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
 601
 602         if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
 603                 tx = 3;
 604
 605         REG_WRITE(ah, AR_SELFGEN_MASK, tx);
 606 }
 607
 608 /*
 609  * Override INI values with chip specific configuration.
 610  */
 611 static void ar9003_hw_override_ini(struct ath_hw *ah)
 612 {
 613         u32 val;
 614
 615         /*
 616          * Set the RX_ABORT and RX_DIS and clear it only after
 617          * RXE is set for MAC. This prevents frames with
 618          * corrupted descriptor status.
 619          */
 620         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 621
 622         /*
 623          * For AR9280 and above, there is a new feature that allows
 624          * Multicast search based on both MAC Address and Key ID. By default,
 625          * this feature is enabled. But since the driver is not using this
 626          * feature, we switch it off; otherwise multicast search based on
 627          * MAC addr only will fail.
 628          */
 629         val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
 630         REG_WRITE(ah, AR_PCU_MISC_MODE2,
 631                   val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
 632
 633         REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
 634                     AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
 635
 636         if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
 637                 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
 638                           AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
 639
 640                 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
 641                                    AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
 642                         ah->enabled_cals |= TX_IQ_CAL;
 643                 else
 644                         ah->enabled_cals &= ~TX_IQ_CAL;
 645
 646                 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
 647                         ah->enabled_cals |= TX_CL_CAL;
 648                 else
 649                         ah->enabled_cals &= ~TX_CL_CAL;
 650         }
 651 }
 652
 653 static void ar9003_hw_prog_ini(struct ath_hw *ah,
 654                                struct ar5416IniArray *iniArr,
 655                                int column)
 656 {
 657         unsigned int i, regWrites = 0;
 658
 659         /* New INI format: Array may be undefined (pre, core, post arrays) */
 660         if (!iniArr->ia_array)
 661                 return;
 662
 663         /*
 664          * New INI format: Pre, core, and post arrays for a given subsystem
 665          * may be modal (> 2 columns) or non-modal (2 columns). Determine if
 666          * the array is non-modal and force the column to 1.
 667          */
 668         if (column >= iniArr->ia_columns)
 669                 column = 1;
 670
 671         for (i = 0; i < iniArr->ia_rows; i++) {
 672                 u32 reg = INI_RA(iniArr, i, 0);
 673                 u32 val = INI_RA(iniArr, i, column);
 674
 675                 REG_WRITE(ah, reg, val);
 676
 677                 DO_DELAY(regWrites);
 678         }
 679 }
 680
 681 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
 682                                             struct ath9k_channel *chan)
 683 {
 684         int ret;
 685
 686         switch (chan->chanmode) {
 687         case CHANNEL_A:
 688         case CHANNEL_A_HT20:
 689                 if (chan->channel <= 5350)
 690                         ret = 1;
 691                 else if ((chan->channel > 5350) && (chan->channel <= 5600))
 692                         ret = 3;
 693                 else
 694                         ret = 5;
 695                 break;
 696
 697         case CHANNEL_A_HT40PLUS:
 698         case CHANNEL_A_HT40MINUS:
 699                 if (chan->channel <= 5350)
 700                         ret = 2;
 701                 else if ((chan->channel > 5350) && (chan->channel <= 5600))
 702                         ret = 4;
 703                 else
 704                         ret = 6;
 705                 break;
 706
 707         case CHANNEL_G:
 708         case CHANNEL_G_HT20:
 709         case CHANNEL_B:
 710                 ret = 8;
 711                 break;
 712
 713         case CHANNEL_G_HT40PLUS:
 714         case CHANNEL_G_HT40MINUS:
 715                 ret = 7;
 716                 break;
 717
 718         default:
 719                 ret = -EINVAL;
 720         }
 721
 722         return ret;
 723 }
 724
 725 static int ar9003_hw_process_ini(struct ath_hw *ah,
 726                                  struct ath9k_channel *chan)
 727 {
 728         unsigned int regWrites = 0, i;
 729         u32 modesIndex;
 730
 731         switch (chan->chanmode) {
 732         case CHANNEL_A:
 733         case CHANNEL_A_HT20:
 734                 modesIndex = 1;
 735                 break;
 736         case CHANNEL_A_HT40PLUS:
 737         case CHANNEL_A_HT40MINUS:
 738                 modesIndex = 2;
 739                 break;
 740         case CHANNEL_G:
 741         case CHANNEL_G_HT20:
 742         case CHANNEL_B:
 743                 modesIndex = 4;
 744                 break;
 745         case CHANNEL_G_HT40PLUS:
 746         case CHANNEL_G_HT40MINUS:
 747                 modesIndex = 3;
 748                 break;
 749
 750         default:
 751                 return -EINVAL;
 752         }
 753
 754         /*
 755          * SOC, MAC, BB, RADIO initvals.
 756          */
 757         for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
 758                 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
 759                 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
 760                 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
 761                 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
 762                 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah))
 763                         ar9003_hw_prog_ini(ah,
 764                                            &ah->ini_radio_post_sys2ant,
 765                                            modesIndex);
 766         }
 767
 768         /*
 769          * RXGAIN initvals.
 770          */
 771         REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
 772
 773         if (AR_SREV_9462_20_OR_LATER(ah)) {
 774                 /*
 775                  * CUS217 mix LNA mode.
 776                  */
 777                 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
 778                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
 779                                         1, regWrites);
 780                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
 781                                         modesIndex, regWrites);
 782                 }
 783
 784                 /*
 785                  * 5G-XLNA
 786                  */
 787                 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) ||
 788                     (ar9003_hw_get_rx_gain_idx(ah) == 3)) {
 789                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 790                                         modesIndex, regWrites);
 791                 }
 792         }
 793
 794         if (AR_SREV_9550(ah))
 795                 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
 796                                 regWrites);
 797
 798         /*
 799          * TXGAIN initvals.
 800          */
 801         if (AR_SREV_9550(ah)) {
 802                 int modes_txgain_index;
 803
 804                 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
 805                 if (modes_txgain_index < 0)
 806                         return -EINVAL;
 807
 808                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
 809                                 regWrites);
 810         } else {
 811                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
 812         }
 813
 814         /*
 815          * For 5GHz channels requiring Fast Clock, apply
 816          * different modal values.
 817          */
 818         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 819                 REG_WRITE_ARRAY(&ah->iniModesFastClock,
 820                                 modesIndex, regWrites);
 821
 822         /*
 823          * Clock frequency initvals.
 824          */
 825         REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
 826
 827         /*
 828          * JAPAN regulatory.
 829          */
 830         if (chan->channel == 2484)
 831                 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
 832
 833         ah->modes_index = modesIndex;
 834         ar9003_hw_override_ini(ah);
 835         ar9003_hw_set_channel_regs(ah, chan);
 836         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
 837         ath9k_hw_apply_txpower(ah, chan, false);
 838
 839         return 0;
 840 }
 841
 842 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
 843                                  struct ath9k_channel *chan)
 844 {
 845         u32 rfMode = 0;
 846
 847         if (chan == NULL)
 848                 return;
 849
 850         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
 851                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
 852
 853         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 854                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
 855         if (IS_CHAN_QUARTER_RATE(chan))
 856                 rfMode |= AR_PHY_MODE_QUARTER;
 857         if (IS_CHAN_HALF_RATE(chan))
 858                 rfMode |= AR_PHY_MODE_HALF;
 859
 860         if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
 861                 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
 862                               AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
 863
 864         REG_WRITE(ah, AR_PHY_MODE, rfMode);
 865 }
 866
 867 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
 868 {
 869         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
 870 }
 871
 872 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
 873                                       struct ath9k_channel *chan)
 874 {
 875         u32 coef_scaled, ds_coef_exp, ds_coef_man;
 876         u32 clockMhzScaled = 0x64000000;
 877         struct chan_centers centers;
 878
 879         /*
 880          * half and quarter rate can divide the scaled clock by 2 or 4
 881          * scale for selected channel bandwidth
 882          */
 883         if (IS_CHAN_HALF_RATE(chan))
 884                 clockMhzScaled = clockMhzScaled >> 1;
 885         else if (IS_CHAN_QUARTER_RATE(chan))
 886                 clockMhzScaled = clockMhzScaled >> 2;
 887
 888         /*
 889          * ALGO -> coef = 1e8/fcarrier*fclock/40;
 890          * scaled coef to provide precision for this floating calculation
 891          */
 892         ath9k_hw_get_channel_centers(ah, chan, &centers);
 893         coef_scaled = clockMhzScaled / centers.synth_center;
 894
 895         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 896                                       &ds_coef_exp);
 897
 898         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 899                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
 900         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 901                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
 902
 903         /*
 904          * For Short GI,
 905          * scaled coeff is 9/10 that of normal coeff
 906          */
 907         coef_scaled = (9 * coef_scaled) / 10;
 908
 909         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 910                                       &ds_coef_exp);
 911
 912         /* for short gi */
 913         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 914                       AR_PHY_SGI_DSC_MAN, ds_coef_man);
 915         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 916                       AR_PHY_SGI_DSC_EXP, ds_coef_exp);
 917 }
 918
 919 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
 920 {
 921         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
 922         return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
 923                              AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
 924 }
 925
 926 /*
 927  * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
 928  * Read the phy active delay register. Value is in 100ns increments.
 929  */
 930 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
 931 {
 932         u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 933
 934         ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
 935
 936         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 937 }
 938
 939 static bool ar9003_hw_ani_control(struct ath_hw *ah,
 940                                   enum ath9k_ani_cmd cmd, int param)
 941 {
 942         struct ath_common *common = ath9k_hw_common(ah);
 943         struct ath9k_channel *chan = ah->curchan;
 944         struct ar5416AniState *aniState = &ah->ani;
 945         int m1ThreshLow, m2ThreshLow;
 946         int m1Thresh, m2Thresh;
 947         int m2CountThr, m2CountThrLow;
 948         int m1ThreshLowExt, m2ThreshLowExt;
 949         int m1ThreshExt, m2ThreshExt;
 950         s32 value, value2;
 951
 952         switch (cmd & ah->ani_function) {
 953         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
 954                 /*
 955                  * on == 1 means ofdm weak signal detection is ON
 956                  * on == 1 is the default, for less noise immunity
 957                  *
 958                  * on == 0 means ofdm weak signal detection is OFF
 959                  * on == 0 means more noise imm
 960                  */
 961                 u32 on = param ? 1 : 0;
 962
 963                 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
 964                         goto skip_ws_det;
 965
 966                 m1ThreshLow = on ?
 967                         aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
 968                 m2ThreshLow = on ?
 969                         aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
 970                 m1Thresh = on ?
 971                         aniState->iniDef.m1Thresh : m1Thresh_off;
 972                 m2Thresh = on ?
 973                         aniState->iniDef.m2Thresh : m2Thresh_off;
 974                 m2CountThr = on ?
 975                         aniState->iniDef.m2CountThr : m2CountThr_off;
 976                 m2CountThrLow = on ?
 977                         aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
 978                 m1ThreshLowExt = on ?
 979                         aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
 980                 m2ThreshLowExt = on ?
 981                         aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
 982                 m1ThreshExt = on ?
 983                         aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
 984                 m2ThreshExt = on ?
 985                         aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
 986
 987                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 988                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
 989                               m1ThreshLow);
 990                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 991                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
 992                               m2ThreshLow);
 993                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 994                               AR_PHY_SFCORR_M1_THRESH,
 995                               m1Thresh);
 996                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 997                               AR_PHY_SFCORR_M2_THRESH,
 998                               m2Thresh);
 999                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1000                               AR_PHY_SFCORR_M2COUNT_THR,
1001                               m2CountThr);
1002                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1003                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1004                               m2CountThrLow);
1005                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1006                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1007                               m1ThreshLowExt);
1008                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1009                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1010                               m2ThreshLowExt);
1011                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1012                               AR_PHY_SFCORR_EXT_M1_THRESH,
1013                               m1ThreshExt);
1014                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1015                               AR_PHY_SFCORR_EXT_M2_THRESH,
1016                               m2ThreshExt);
1017 skip_ws_det:
1018                 if (on)
1019                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1020                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1021                 else
1022                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1023                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1024
1025                 if (on != aniState->ofdmWeakSigDetect) {
1026                         ath_dbg(common, ANI,
1027                                 "** ch %d: ofdm weak signal: %s=>%s\n",
1028                                 chan->channel,
1029                                 aniState->ofdmWeakSigDetect ?
1030                                 "on" : "off",
1031                                 on ? "on" : "off");
1032                         if (on)
1033                                 ah->stats.ast_ani_ofdmon++;
1034                         else
1035                                 ah->stats.ast_ani_ofdmoff++;
1036                         aniState->ofdmWeakSigDetect = on;
1037                 }
1038                 break;
1039         }
1040         case ATH9K_ANI_FIRSTEP_LEVEL:{
1041                 u32 level = param;
1042
1043                 if (level >= ARRAY_SIZE(firstep_table)) {
1044                         ath_dbg(common, ANI,
1045                                 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1046                                 level, ARRAY_SIZE(firstep_table));
1047                         return false;
1048                 }
1049
1050                 /*
1051                  * make register setting relative to default
1052                  * from INI file & cap value
1053                  */
1054                 value = firstep_table[level] -
1055                         firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1056                         aniState->iniDef.firstep;
1057                 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1058                         value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1059                 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1060                         value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1061                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1062                               AR_PHY_FIND_SIG_FIRSTEP,
1063                               value);
1064                 /*
1065                  * we need to set first step low register too
1066                  * make register setting relative to default
1067                  * from INI file & cap value
1068                  */
1069                 value2 = firstep_table[level] -
1070                          firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1071                          aniState->iniDef.firstepLow;
1072                 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1073                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1074                 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1075                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1076
1077                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1078                               AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
1079
1080                 if (level != aniState->firstepLevel) {
1081                         ath_dbg(common, ANI,
1082                                 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1083                                 chan->channel,
1084                                 aniState->firstepLevel,
1085                                 level,
1086                                 ATH9K_ANI_FIRSTEP_LVL,
1087                                 value,
1088                                 aniState->iniDef.firstep);
1089                         ath_dbg(common, ANI,
1090                                 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1091                                 chan->channel,
1092                                 aniState->firstepLevel,
1093                                 level,
1094                                 ATH9K_ANI_FIRSTEP_LVL,
1095                                 value2,
1096                                 aniState->iniDef.firstepLow);
1097                         if (level > aniState->firstepLevel)
1098                                 ah->stats.ast_ani_stepup++;
1099                         else if (level < aniState->firstepLevel)
1100                                 ah->stats.ast_ani_stepdown++;
1101                         aniState->firstepLevel = level;
1102                 }
1103                 break;
1104         }
1105         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1106                 u32 level = param;
1107
1108                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1109                         ath_dbg(common, ANI,
1110                                 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1111                                 level, ARRAY_SIZE(cycpwrThr1_table));
1112                         return false;
1113                 }
1114                 /*
1115                  * make register setting relative to default
1116                  * from INI file & cap value
1117                  */
1118                 value = cycpwrThr1_table[level] -
1119                         cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1120                         aniState->iniDef.cycpwrThr1;
1121                 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1122                         value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1123                 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1124                         value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1125                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1126                               AR_PHY_TIMING5_CYCPWR_THR1,
1127                               value);
1128
1129                 /*
1130                  * set AR_PHY_EXT_CCA for extension channel
1131                  * make register setting relative to default
1132                  * from INI file & cap value
1133                  */
1134                 value2 = cycpwrThr1_table[level] -
1135                          cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1136                          aniState->iniDef.cycpwrThr1Ext;
1137                 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1138                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1139                 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1140                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1141                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1142                               AR_PHY_EXT_CYCPWR_THR1, value2);
1143
1144                 if (level != aniState->spurImmunityLevel) {
1145                         ath_dbg(common, ANI,
1146                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1147                                 chan->channel,
1148                                 aniState->spurImmunityLevel,
1149                                 level,
1150                                 ATH9K_ANI_SPUR_IMMUNE_LVL,
1151                                 value,
1152                                 aniState->iniDef.cycpwrThr1);
1153                         ath_dbg(common, ANI,
1154                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1155                                 chan->channel,
1156                                 aniState->spurImmunityLevel,
1157                                 level,
1158                                 ATH9K_ANI_SPUR_IMMUNE_LVL,
1159                                 value2,
1160                                 aniState->iniDef.cycpwrThr1Ext);
1161                         if (level > aniState->spurImmunityLevel)
1162                                 ah->stats.ast_ani_spurup++;
1163                         else if (level < aniState->spurImmunityLevel)
1164                                 ah->stats.ast_ani_spurdown++;
1165                         aniState->spurImmunityLevel = level;
1166                 }
1167                 break;
1168         }
1169         case ATH9K_ANI_MRC_CCK:{
1170                 /*
1171                  * is_on == 1 means MRC CCK ON (default, less noise imm)
1172                  * is_on == 0 means MRC CCK is OFF (more noise imm)
1173                  */
1174                 bool is_on = param ? 1 : 0;
1175                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1176                               AR_PHY_MRC_CCK_ENABLE, is_on);
1177                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1178                               AR_PHY_MRC_CCK_MUX_REG, is_on);
1179                 if (is_on != aniState->mrcCCK) {
1180                         ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
1181                                 chan->channel,
1182                                 aniState->mrcCCK ? "on" : "off",
1183                                 is_on ? "on" : "off");
1184                 if (is_on)
1185                         ah->stats.ast_ani_ccklow++;
1186                 else
1187                         ah->stats.ast_ani_cckhigh++;
1188                 aniState->mrcCCK = is_on;
1189                 }
1190         break;
1191         }
1192         case ATH9K_ANI_PRESENT:
1193                 break;
1194         default:
1195                 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1196                 return false;
1197         }
1198
1199         ath_dbg(common, ANI,
1200                 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1201                 aniState->spurImmunityLevel,
1202                 aniState->ofdmWeakSigDetect ? "on" : "off",
1203                 aniState->firstepLevel,
1204                 aniState->mrcCCK ? "on" : "off",
1205                 aniState->listenTime,
1206                 aniState->ofdmPhyErrCount,
1207                 aniState->cckPhyErrCount);
1208         return true;
1209 }
1210
1211 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1212                               int16_t nfarray[NUM_NF_READINGS])
1213 {
1214 #define AR_PHY_CH_MINCCA_PWR    0x1FF00000
1215 #define AR_PHY_CH_MINCCA_PWR_S  20
1216 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1217 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1218
1219         int16_t nf;
1220         int i;
1221
1222         for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1223                 if (ah->rxchainmask & BIT(i)) {
1224                         nf = MS(REG_READ(ah, ah->nf_regs[i]),
1225                                          AR_PHY_CH_MINCCA_PWR);
1226                         nfarray[i] = sign_extend32(nf, 8);
1227
1228                         if (IS_CHAN_HT40(ah->curchan)) {
1229                                 u8 ext_idx = AR9300_MAX_CHAINS + i;
1230
1231                                 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1232                                                  AR_PHY_CH_EXT_MINCCA_PWR);
1233                                 nfarray[ext_idx] = sign_extend32(nf, 8);
1234                         }
1235                 }
1236         }
1237 }
1238
1239 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1240 {
1241         ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1242         ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1243         ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1244         ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1245         ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1246         ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1247
1248         if (AR_SREV_9330(ah))
1249                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1250
1251         if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1252                 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1253                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1254                 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1255                 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1256         }
1257 }
1258
1259 /*
1260  * Initialize the ANI register values with default (ini) values.
1261  * This routine is called during a (full) hardware reset after
1262  * all the registers are initialised from the INI.
1263  */
1264 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1265 {
1266         struct ar5416AniState *aniState;
1267         struct ath_common *common = ath9k_hw_common(ah);
1268         struct ath9k_channel *chan = ah->curchan;
1269         struct ath9k_ani_default *iniDef;
1270         u32 val;
1271
1272         aniState = &ah->ani;
1273         iniDef = &aniState->iniDef;
1274
1275         ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1276                 ah->hw_version.macVersion,
1277                 ah->hw_version.macRev,
1278                 ah->opmode,
1279                 chan->channel,
1280                 chan->channelFlags);
1281
1282         val = REG_READ(ah, AR_PHY_SFCORR);
1283         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1284         iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1285         iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1286
1287         val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1288         iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1289         iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1290         iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1291
1292         val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1293         iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1294         iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1295         iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1296         iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1297         iniDef->firstep = REG_READ_FIELD(ah,
1298                                          AR_PHY_FIND_SIG,
1299                                          AR_PHY_FIND_SIG_FIRSTEP);
1300         iniDef->firstepLow = REG_READ_FIELD(ah,
1301                                             AR_PHY_FIND_SIG_LOW,
1302                                             AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1303         iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1304                                             AR_PHY_TIMING5,
1305                                             AR_PHY_TIMING5_CYCPWR_THR1);
1306         iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1307                                                AR_PHY_EXT_CCA,
1308                                                AR_PHY_EXT_CYCPWR_THR1);
1309
1310         /* these levels just got reset to defaults by the INI */
1311         aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1312         aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1313         aniState->ofdmWeakSigDetect = true;
1314         aniState->mrcCCK = true;
1315 }
1316
1317 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1318                                        struct ath_hw_radar_conf *conf)
1319 {
1320         u32 radar_0 = 0, radar_1 = 0;
1321
1322         if (!conf) {
1323                 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1324                 return;
1325         }
1326
1327         radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1328         radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1329         radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1330         radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1331         radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1332         radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1333
1334         radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1335         radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1336         radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1337         radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1338         radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1339
1340         REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1341         REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1342         if (conf->ext_channel)
1343                 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1344         else
1345                 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1346 }
1347
1348 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1349 {
1350         struct ath_hw_radar_conf *conf = &ah->radar_conf;
1351
1352         conf->fir_power = -28;
1353         conf->radar_rssi = 0;
1354         conf->pulse_height = 10;
1355         conf->pulse_rssi = 24;
1356         conf->pulse_inband = 8;
1357         conf->pulse_maxlen = 255;
1358         conf->pulse_inband_step = 12;
1359         conf->radar_inband = 8;
1360 }
1361
1362 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1363                                            struct ath_hw_antcomb_conf *antconf)
1364 {
1365         u32 regval;
1366
1367         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1368         antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1369                                   AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1370         antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1371                                  AR_PHY_ANT_DIV_ALT_LNACONF_S;
1372         antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1373                                   AR_PHY_ANT_FAST_DIV_BIAS_S;
1374
1375         if (AR_SREV_9330_11(ah)) {
1376                 antconf->lna1_lna2_delta = -9;
1377                 antconf->div_group = 1;
1378         } else if (AR_SREV_9485(ah)) {
1379                 antconf->lna1_lna2_delta = -9;
1380                 antconf->div_group = 2;
1381         } else if (AR_SREV_9565(ah)) {
1382                 antconf->lna1_lna2_delta = -3;
1383                 antconf->div_group = 3;
1384         } else {
1385                 antconf->lna1_lna2_delta = -3;
1386                 antconf->div_group = 0;
1387         }
1388 }
1389
1390 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1391                                    struct ath_hw_antcomb_conf *antconf)
1392 {
1393         u32 regval;
1394
1395         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1396         regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1397                     AR_PHY_ANT_DIV_ALT_LNACONF |
1398                     AR_PHY_ANT_FAST_DIV_BIAS |
1399                     AR_PHY_ANT_DIV_MAIN_GAINTB |
1400                     AR_PHY_ANT_DIV_ALT_GAINTB);
1401         regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1402                    & AR_PHY_ANT_DIV_MAIN_LNACONF);
1403         regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1404                    & AR_PHY_ANT_DIV_ALT_LNACONF);
1405         regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1406                    & AR_PHY_ANT_FAST_DIV_BIAS);
1407         regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1408                    & AR_PHY_ANT_DIV_MAIN_GAINTB);
1409         regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1410                    & AR_PHY_ANT_DIV_ALT_GAINTB);
1411
1412         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1413 }
1414
1415 static void ar9003_hw_antctrl_shared_chain_lnadiv(struct ath_hw *ah,
1416                                                   bool enable)
1417 {
1418         u8 ant_div_ctl1;
1419         u32 regval;
1420
1421         if (!AR_SREV_9565(ah))
1422                 return;
1423
1424         ah->shared_chain_lnadiv = enable;
1425         ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1426
1427         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1428         regval &= (~AR_ANT_DIV_CTRL_ALL);
1429         regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
1430         regval &= ~AR_PHY_ANT_DIV_LNADIV;
1431         regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1432
1433         if (enable)
1434                 regval |= AR_ANT_DIV_ENABLE;
1435
1436         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1437
1438         regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1439         regval &= ~AR_FAST_DIV_ENABLE;
1440         regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1441
1442         if (enable)
1443                 regval |= AR_FAST_DIV_ENABLE;
1444
1445         REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1446
1447         if (enable) {
1448                 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1449                             (1 << AR_PHY_ANT_SW_RX_PROT_S));
1450                 if (ah->curchan && IS_CHAN_2GHZ(ah->curchan))
1451                         REG_SET_BIT(ah, AR_PHY_RESTART,
1452                                     AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1453                 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1454                             AR_BTCOEX_WL_LNADIV_FORCE_ON);
1455         } else {
1456                 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE);
1457                 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1458                             (1 << AR_PHY_ANT_SW_RX_PROT_S));
1459                 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE);
1460                 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1461                             AR_BTCOEX_WL_LNADIV_FORCE_ON);
1462
1463                 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1464                 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1465                         AR_PHY_ANT_DIV_ALT_LNACONF |
1466                         AR_PHY_ANT_DIV_MAIN_GAINTB |
1467                         AR_PHY_ANT_DIV_ALT_GAINTB);
1468                 regval |= (ATH_ANT_DIV_COMB_LNA1 << AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1469                 regval |= (ATH_ANT_DIV_COMB_LNA2 << AR_PHY_ANT_DIV_ALT_LNACONF_S);
1470                 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1471         }
1472 }
1473
1474 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1475                                       struct ath9k_channel *chan,
1476                                       u8 *ini_reloaded)
1477 {
1478         unsigned int regWrites = 0;
1479         u32 modesIndex;
1480
1481         switch (chan->chanmode) {
1482         case CHANNEL_A:
1483         case CHANNEL_A_HT20:
1484                 modesIndex = 1;
1485                 break;
1486         case CHANNEL_A_HT40PLUS:
1487         case CHANNEL_A_HT40MINUS:
1488                 modesIndex = 2;
1489                 break;
1490         case CHANNEL_G:
1491         case CHANNEL_G_HT20:
1492         case CHANNEL_B:
1493                 modesIndex = 4;
1494                 break;
1495         case CHANNEL_G_HT40PLUS:
1496         case CHANNEL_G_HT40MINUS:
1497                 modesIndex = 3;
1498                 break;
1499
1500         default:
1501                 return -EINVAL;
1502         }
1503
1504         if (modesIndex == ah->modes_index) {
1505                 *ini_reloaded = false;
1506                 goto set_rfmode;
1507         }
1508
1509         ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1510         ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1511         ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1512         ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1513
1514         if (AR_SREV_9462_20_OR_LATER(ah))
1515                 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1516                                    modesIndex);
1517
1518         REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1519
1520         if (AR_SREV_9462_20_OR_LATER(ah)) {
1521                 /*
1522                  * CUS217 mix LNA mode.
1523                  */
1524                 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
1525                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
1526                                         1, regWrites);
1527                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
1528                                         modesIndex, regWrites);
1529                 }
1530         }
1531
1532         /*
1533          * For 5GHz channels requiring Fast Clock, apply
1534          * different modal values.
1535          */
1536         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1537                 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1538
1539         if (AR_SREV_9565(ah))
1540                 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1541
1542         /*
1543          * JAPAN regulatory.
1544          */
1545         if (chan->channel == 2484)
1546                 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
1547
1548         ah->modes_index = modesIndex;
1549         *ini_reloaded = true;
1550
1551 set_rfmode:
1552         ar9003_hw_set_rfmode(ah, chan);
1553         return 0;
1554 }
1555
1556 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1557                                            struct ath_spec_scan *param)
1558 {
1559         u8 count;
1560
1561         if (!param->enabled) {
1562                 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1563                             AR_PHY_SPECTRAL_SCAN_ENABLE);
1564                 return;
1565         }
1566
1567         REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1568         REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
1569
1570         /* on AR93xx and newer, count = 0 will make the the chip send
1571          * spectral samples endlessly. Check if this really was intended,
1572          * and fix otherwise.
1573          */
1574         count = param->count;
1575         if (param->endless)
1576                 count = 0;
1577         else if (param->count == 0)
1578                 count = 1;
1579
1580         if (param->short_repeat)
1581                 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1582                             AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1583         else
1584                 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1585                             AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1586
1587         REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1588                       AR_PHY_SPECTRAL_SCAN_COUNT, count);
1589         REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1590                       AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
1591         REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1592                       AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
1593
1594         return;
1595 }
1596
1597 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah)
1598 {
1599         /* Activate spectral scan */
1600         REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1601                     AR_PHY_SPECTRAL_SCAN_ACTIVE);
1602 }
1603
1604 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah)
1605 {
1606         struct ath_common *common = ath9k_hw_common(ah);
1607
1608         /* Poll for spectral scan complete */
1609         if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
1610                            AR_PHY_SPECTRAL_SCAN_ACTIVE,
1611                            0, AH_WAIT_TIMEOUT)) {
1612                 ath_err(common, "spectral scan wait failed\n");
1613                 return;
1614         }
1615 }
1616
1617 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1618 {
1619         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1620         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1621         static const u32 ar9300_cca_regs[6] = {
1622                 AR_PHY_CCA_0,
1623                 AR_PHY_CCA_1,
1624                 AR_PHY_CCA_2,
1625                 AR_PHY_EXT_CCA,
1626                 AR_PHY_EXT_CCA_1,
1627                 AR_PHY_EXT_CCA_2,
1628         };
1629
1630         priv_ops->rf_set_freq = ar9003_hw_set_channel;
1631         priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1632         priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1633         priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1634         priv_ops->init_bb = ar9003_hw_init_bb;
1635         priv_ops->process_ini = ar9003_hw_process_ini;
1636         priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1637         priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1638         priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1639         priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1640         priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1641         priv_ops->ani_control = ar9003_hw_ani_control;
1642         priv_ops->do_getnf = ar9003_hw_do_getnf;
1643         priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1644         priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1645         priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
1646
1647         ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1648         ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1649         ops->antctrl_shared_chain_lnadiv = ar9003_hw_antctrl_shared_chain_lnadiv;
1650         ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
1651         ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
1652         ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;
1653
1654         ar9003_hw_set_nf_limits(ah);
1655         ar9003_hw_set_radar_conf(ah);
1656         memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1657 }
1658
1659 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1660 {
1661         struct ath_common *common = ath9k_hw_common(ah);
1662         u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1663         u32 val, idle_count;
1664
1665         if (!idle_tmo_ms) {
1666                 /* disable IRQ, disable chip-reset for BB panic */
1667                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1668                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1669                           ~(AR_PHY_WATCHDOG_RST_ENABLE |
1670                             AR_PHY_WATCHDOG_IRQ_ENABLE));
1671
1672                 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1673                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1674                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1675                           ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1676                             AR_PHY_WATCHDOG_IDLE_ENABLE));
1677
1678                 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
1679                 return;
1680         }
1681
1682         /* enable IRQ, disable chip-reset for BB watchdog */
1683         val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1684         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1685                   (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1686                   ~AR_PHY_WATCHDOG_RST_ENABLE);
1687
1688         /* bound limit to 10 secs */
1689         if (idle_tmo_ms > 10000)
1690                 idle_tmo_ms = 10000;
1691
1692         /*
1693          * The time unit for watchdog event is 2^15 44/88MHz cycles.
1694          *
1695          * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1696          * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1697          *
1698          * Given we use fast clock now in 5 GHz, these time units should
1699          * be common for both 2 GHz and 5 GHz.
1700          */
1701         idle_count = (100 * idle_tmo_ms) / 74;
1702         if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1703                 idle_count = (100 * idle_tmo_ms) / 37;
1704
1705         /*
1706          * enable watchdog in non-IDLE mode, disable in IDLE mode,
1707          * set idle time-out.
1708          */
1709         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1710                   AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1711                   AR_PHY_WATCHDOG_IDLE_MASK |
1712                   (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1713
1714         ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
1715                 idle_tmo_ms);
1716 }
1717
1718 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1719 {
1720         /*
1721          * we want to avoid printing in ISR context so we save the
1722          * watchdog status to be printed later in bottom half context.
1723          */
1724         ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1725
1726         /*
1727          * the watchdog timer should reset on status read but to be sure
1728          * sure we write 0 to the watchdog status bit.
1729          */
1730         REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1731                   ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1732 }
1733
1734 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1735 {
1736         struct ath_common *common = ath9k_hw_common(ah);
1737         u32 status;
1738
1739         if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1740                 return;
1741
1742         status = ah->bb_watchdog_last_status;
1743         ath_dbg(common, RESET,
1744                 "\n==== BB update: BB status=0x%08x ====\n", status);
1745         ath_dbg(common, RESET,
1746                 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1747                 MS(status, AR_PHY_WATCHDOG_INFO),
1748                 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1749                 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1750                 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1751                 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1752                 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1753                 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1754                 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1755                 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1756
1757         ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1758                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1759                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1760         ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
1761                 REG_READ(ah, AR_PHY_GEN_CTRL));
1762
1763 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1764         if (common->cc_survey.cycles)
1765                 ath_dbg(common, RESET,
1766                         "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1767                         PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1768
1769         ath_dbg(common, RESET, "==== BB update: done ====\n\n");
1770 }
1771 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
1772
1773 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1774 {
1775         u32 val;
1776
1777         /* While receiving unsupported rate frame rx state machine
1778          * gets into a state 0xb and if phy_restart happens in that
1779          * state, BB would go hang. If RXSM is in 0xb state after
1780          * first bb panic, ensure to disable the phy_restart.
1781          */
1782         if (!((MS(ah->bb_watchdog_last_status,
1783                   AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1784             ah->bb_hang_rx_ofdm))
1785                 return;
1786
1787         ah->bb_hang_rx_ofdm = true;
1788         val = REG_READ(ah, AR_PHY_RESTART);
1789         val &= ~AR_PHY_RESTART_ENA;
1790
1791         REG_WRITE(ah, AR_PHY_RESTART, val);
1792 }
1793 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);