drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/slab.h>
  19 #include <asm/unaligned.h>
  20
  21 #include "hw.h"
  22 #include "hw-ops.h"
  23 #include "rc.h"
  24 #include "ar9003_mac.h"
  25
  26 #define ATH9K_CLOCK_RATE_CCK            22
  27 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  28 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  29
  30 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  31
  32 MODULE_AUTHOR("Atheros Communications");
  33 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  34 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  35 MODULE_LICENSE("Dual BSD/GPL");
  36
  37 static int __init ath9k_init(void)
  38 {
  39         return 0;
  40 }
  41 module_init(ath9k_init);
  42
  43 static void __exit ath9k_exit(void)
  44 {
  45         return;
  46 }
  47 module_exit(ath9k_exit);
  48
  49 /* Private hardware callbacks */
  50
  51 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
  52 {
  53         ath9k_hw_private_ops(ah)->init_cal_settings(ah);
  54 }
  55
  56 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
  57 {
  58         ath9k_hw_private_ops(ah)->init_mode_regs(ah);
  59 }
  60
  61 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
  62 {
  63         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
  64
  65         return priv_ops->macversion_supported(ah->hw_version.macVersion);
  66 }
  67
  68 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
  69                                         struct ath9k_channel *chan)
  70 {
  71         return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
  72 }
  73
  74 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
  75 {
  76         if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
  77                 return;
  78
  79         ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
  80 }
  81
  82 /********************/
  83 /* Helper Functions */
  84 /********************/
  85
  86 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  87 {
  88         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  89
  90         if (!ah->curchan) /* should really check for CCK instead */
  91                 return usecs *ATH9K_CLOCK_RATE_CCK;
  92         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  93                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  94         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  95 }
  96
  97 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  98 {
  99         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 100
 101         if (conf_is_ht40(conf))
 102                 return ath9k_hw_mac_clks(ah, usecs) * 2;
 103         else
 104                 return ath9k_hw_mac_clks(ah, usecs);
 105 }
 106
 107 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 108 {
 109         int i;
 110
 111         BUG_ON(timeout < AH_TIME_QUANTUM);
 112
 113         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 114                 if ((REG_READ(ah, reg) & mask) == val)
 115                         return true;
 116
 117                 udelay(AH_TIME_QUANTUM);
 118         }
 119
 120         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
 121                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 122                   timeout, reg, REG_READ(ah, reg), mask, val);
 123
 124         return false;
 125 }
 126 EXPORT_SYMBOL(ath9k_hw_wait);
 127
 128 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 129 {
 130         u32 retval;
 131         int i;
 132
 133         for (i = 0, retval = 0; i < n; i++) {
 134                 retval = (retval << 1) | (val & 1);
 135                 val >>= 1;
 136         }
 137         return retval;
 138 }
 139
 140 bool ath9k_get_channel_edges(struct ath_hw *ah,
 141                              u16 flags, u16 *low,
 142                              u16 *high)
 143 {
 144         struct ath9k_hw_capabilities *pCap = &ah->caps;
 145
 146         if (flags & CHANNEL_5GHZ) {
 147                 *low = pCap->low_5ghz_chan;
 148                 *high = pCap->high_5ghz_chan;
 149                 return true;
 150         }
 151         if ((flags & CHANNEL_2GHZ)) {
 152                 *low = pCap->low_2ghz_chan;
 153                 *high = pCap->high_2ghz_chan;
 154                 return true;
 155         }
 156         return false;
 157 }
 158
 159 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 160                            u8 phy, int kbps,
 161                            u32 frameLen, u16 rateix,
 162                            bool shortPreamble)
 163 {
 164         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 165
 166         if (kbps == 0)
 167                 return 0;
 168
 169         switch (phy) {
 170         case WLAN_RC_PHY_CCK:
 171                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 172                 if (shortPreamble)
 173                         phyTime >>= 1;
 174                 numBits = frameLen << 3;
 175                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 176                 break;
 177         case WLAN_RC_PHY_OFDM:
 178                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 179                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 180                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 181                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 182                         txTime = OFDM_SIFS_TIME_QUARTER
 183                                 + OFDM_PREAMBLE_TIME_QUARTER
 184                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 185                 } else if (ah->curchan &&
 186                            IS_CHAN_HALF_RATE(ah->curchan)) {
 187                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 188                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 189                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 190                         txTime = OFDM_SIFS_TIME_HALF +
 191                                 OFDM_PREAMBLE_TIME_HALF
 192                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 193                 } else {
 194                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 195                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 196                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 197                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 198                                 + (numSymbols * OFDM_SYMBOL_TIME);
 199                 }
 200                 break;
 201         default:
 202                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 203                           "Unknown phy %u (rate ix %u)\n", phy, rateix);
 204                 txTime = 0;
 205                 break;
 206         }
 207
 208         return txTime;
 209 }
 210 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 211
 212 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 213                                   struct ath9k_channel *chan,
 214                                   struct chan_centers *centers)
 215 {
 216         int8_t extoff;
 217
 218         if (!IS_CHAN_HT40(chan)) {
 219                 centers->ctl_center = centers->ext_center =
 220                         centers->synth_center = chan->channel;
 221                 return;
 222         }
 223
 224         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 225             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 226                 centers->synth_center =
 227                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 228                 extoff = 1;
 229         } else {
 230                 centers->synth_center =
 231                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 232                 extoff = -1;
 233         }
 234
 235         centers->ctl_center =
 236                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 237         /* 25 MHz spacing is supported by hw but not on upper layers */
 238         centers->ext_center =
 239                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 240 }
 241
 242 /******************/
 243 /* Chip Revisions */
 244 /******************/
 245
 246 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 247 {
 248         u32 val;
 249
 250         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 251
 252         if (val == 0xFF) {
 253                 val = REG_READ(ah, AR_SREV);
 254                 ah->hw_version.macVersion =
 255                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 256                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 257                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 258         } else {
 259                 if (!AR_SREV_9100(ah))
 260                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 261
 262                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 263
 264                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 265                         ah->is_pciexpress = true;
 266         }
 267 }
 268
 269 /************************************/
 270 /* HW Attach, Detach, Init Routines */
 271 /************************************/
 272
 273 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 274 {
 275         if (AR_SREV_9100(ah))
 276                 return;
 277
 278         ENABLE_REGWRITE_BUFFER(ah);
 279
 280         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 281         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 282         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 283         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 284         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 285         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 286         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 287         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 288         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 289
 290         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 291
 292         REGWRITE_BUFFER_FLUSH(ah);
 293         DISABLE_REGWRITE_BUFFER(ah);
 294 }
 295
 296 /* This should work for all families including legacy */
 297 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 298 {
 299         struct ath_common *common = ath9k_hw_common(ah);
 300         u32 regAddr[2] = { AR_STA_ID0 };
 301         u32 regHold[2];
 302         u32 patternData[4] = { 0x55555555,
 303                                0xaaaaaaaa,
 304                                0x66666666,
 305                                0x99999999 };
 306         int i, j, loop_max;
 307
 308         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 309                 loop_max = 2;
 310                 regAddr[1] = AR_PHY_BASE + (8 << 2);
 311         } else
 312                 loop_max = 1;
 313
 314         for (i = 0; i < loop_max; i++) {
 315                 u32 addr = regAddr[i];
 316                 u32 wrData, rdData;
 317
 318                 regHold[i] = REG_READ(ah, addr);
 319                 for (j = 0; j < 0x100; j++) {
 320                         wrData = (j << 16) | j;
 321                         REG_WRITE(ah, addr, wrData);
 322                         rdData = REG_READ(ah, addr);
 323                         if (rdData != wrData) {
 324                                 ath_print(common, ATH_DBG_FATAL,
 325                                           "address test failed "
 326                                           "addr: 0x%08x - wr:0x%08x != "
 327                                           "rd:0x%08x\n",
 328                                           addr, wrData, rdData);
 329                                 return false;
 330                         }
 331                 }
 332                 for (j = 0; j < 4; j++) {
 333                         wrData = patternData[j];
 334                         REG_WRITE(ah, addr, wrData);
 335                         rdData = REG_READ(ah, addr);
 336                         if (wrData != rdData) {
 337                                 ath_print(common, ATH_DBG_FATAL,
 338                                           "address test failed "
 339                                           "addr: 0x%08x - wr:0x%08x != "
 340                                           "rd:0x%08x\n",
 341                                           addr, wrData, rdData);
 342                                 return false;
 343                         }
 344                 }
 345                 REG_WRITE(ah, regAddr[i], regHold[i]);
 346         }
 347         udelay(100);
 348
 349         return true;
 350 }
 351
 352 static void ath9k_hw_init_config(struct ath_hw *ah)
 353 {
 354         int i;
 355
 356         ah->config.dma_beacon_response_time = 2;
 357         ah->config.sw_beacon_response_time = 10;
 358         ah->config.additional_swba_backoff = 0;
 359         ah->config.ack_6mb = 0x0;
 360         ah->config.cwm_ignore_extcca = 0;
 361         ah->config.pcie_powersave_enable = 0;
 362         ah->config.pcie_clock_req = 0;
 363         ah->config.pcie_waen = 0;
 364         ah->config.analog_shiftreg = 1;
 365         ah->config.ofdm_trig_low = 200;
 366         ah->config.ofdm_trig_high = 500;
 367         ah->config.cck_trig_high = 200;
 368         ah->config.cck_trig_low = 100;
 369
 370         /*
 371          * For now ANI is disabled for AR9003, it is still
 372          * being tested.
 373          */
 374         if (!AR_SREV_9300_20_OR_LATER(ah))
 375                 ah->config.enable_ani = 1;
 376
 377         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 378                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 379                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 380         }
 381
 382         if (ah->hw_version.devid != AR2427_DEVID_PCIE)
 383                 ah->config.ht_enable = 1;
 384         else
 385                 ah->config.ht_enable = 0;
 386
 387         ah->config.rx_intr_mitigation = true;
 388
 389         /*
 390          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 391          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 392          * This means we use it for all AR5416 devices, and the few
 393          * minor PCI AR9280 devices out there.
 394          *
 395          * Serialization is required because these devices do not handle
 396          * well the case of two concurrent reads/writes due to the latency
 397          * involved. During one read/write another read/write can be issued
 398          * on another CPU while the previous read/write may still be working
 399          * on our hardware, if we hit this case the hardware poops in a loop.
 400          * We prevent this by serializing reads and writes.
 401          *
 402          * This issue is not present on PCI-Express devices or pre-AR5416
 403          * devices (legacy, 802.11abg).
 404          */
 405         if (num_possible_cpus() > 1)
 406                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 407 }
 408
 409 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 410 {
 411         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 412
 413         regulatory->country_code = CTRY_DEFAULT;
 414         regulatory->power_limit = MAX_RATE_POWER;
 415         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 416
 417         ah->hw_version.magic = AR5416_MAGIC;
 418         ah->hw_version.subvendorid = 0;
 419
 420         ah->ah_flags = 0;
 421         if (!AR_SREV_9100(ah))
 422                 ah->ah_flags = AH_USE_EEPROM;
 423
 424         ah->atim_window = 0;
 425         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 426         ah->beacon_interval = 100;
 427         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 428         ah->slottime = (u32) -1;
 429         ah->globaltxtimeout = (u32) -1;
 430         ah->power_mode = ATH9K_PM_UNDEFINED;
 431 }
 432
 433 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 434 {
 435         struct ath_common *common = ath9k_hw_common(ah);
 436         u32 sum;
 437         int i;
 438         u16 eeval;
 439         u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
 440
 441         sum = 0;
 442         for (i = 0; i < 3; i++) {
 443                 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
 444                 sum += eeval;
 445                 common->macaddr[2 * i] = eeval >> 8;
 446                 common->macaddr[2 * i + 1] = eeval & 0xff;
 447         }
 448         if (sum == 0 || sum == 0xffff * 3)
 449                 return -EADDRNOTAVAIL;
 450
 451         return 0;
 452 }
 453
 454 static int ath9k_hw_post_init(struct ath_hw *ah)
 455 {
 456         int ecode;
 457
 458         if (!AR_SREV_9271(ah)) {
 459                 if (!ath9k_hw_chip_test(ah))
 460                         return -ENODEV;
 461         }
 462
 463         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 464                 ecode = ar9002_hw_rf_claim(ah);
 465                 if (ecode != 0)
 466                         return ecode;
 467         }
 468
 469         ecode = ath9k_hw_eeprom_init(ah);
 470         if (ecode != 0)
 471                 return ecode;
 472
 473         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 474                   "Eeprom VER: %d, REV: %d\n",
 475                   ah->eep_ops->get_eeprom_ver(ah),
 476                   ah->eep_ops->get_eeprom_rev(ah));
 477
 478         ecode = ath9k_hw_rf_alloc_ext_banks(ah);
 479         if (ecode) {
 480                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 481                           "Failed allocating banks for "
 482                           "external radio\n");
 483                 return ecode;
 484         }
 485
 486         if (!AR_SREV_9100(ah)) {
 487                 ath9k_hw_ani_setup(ah);
 488                 ath9k_hw_ani_init(ah);
 489         }
 490
 491         return 0;
 492 }
 493
 494 static void ath9k_hw_attach_ops(struct ath_hw *ah)
 495 {
 496         if (AR_SREV_9300_20_OR_LATER(ah))
 497                 ar9003_hw_attach_ops(ah);
 498         else
 499                 ar9002_hw_attach_ops(ah);
 500 }
 501
 502 /* Called for all hardware families */
 503 static int __ath9k_hw_init(struct ath_hw *ah)
 504 {
 505         struct ath_common *common = ath9k_hw_common(ah);
 506         int r = 0;
 507
 508         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 509                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 510
 511         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 512                 ath_print(common, ATH_DBG_FATAL,
 513                           "Couldn't reset chip\n");
 514                 return -EIO;
 515         }
 516
 517         ath9k_hw_init_defaults(ah);
 518         ath9k_hw_init_config(ah);
 519
 520         ath9k_hw_attach_ops(ah);
 521
 522         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 523                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 524                 return -EIO;
 525         }
 526
 527         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 528                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 529                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 530                         ah->config.serialize_regmode =
 531                                 SER_REG_MODE_ON;
 532                 } else {
 533                         ah->config.serialize_regmode =
 534                                 SER_REG_MODE_OFF;
 535                 }
 536         }
 537
 538         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 539                 ah->config.serialize_regmode);
 540
 541         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 542                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
 543         else
 544                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 545
 546         if (!ath9k_hw_macversion_supported(ah)) {
 547                 ath_print(common, ATH_DBG_FATAL,
 548                           "Mac Chip Rev 0x%02x.%x is not supported by "
 549                           "this driver\n", ah->hw_version.macVersion,
 550                           ah->hw_version.macRev);
 551                 return -EOPNOTSUPP;
 552         }
 553
 554         if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
 555                 ah->is_pciexpress = false;
 556
 557         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 558         ath9k_hw_init_cal_settings(ah);
 559
 560         ah->ani_function = ATH9K_ANI_ALL;
 561         if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
 562                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 563
 564         ath9k_hw_init_mode_regs(ah);
 565
 566         if (ah->is_pciexpress)
 567                 ath9k_hw_configpcipowersave(ah, 0, 0);
 568         else
 569                 ath9k_hw_disablepcie(ah);
 570
 571         if (!AR_SREV_9300_20_OR_LATER(ah))
 572                 ar9002_hw_cck_chan14_spread(ah);
 573
 574         r = ath9k_hw_post_init(ah);
 575         if (r)
 576                 return r;
 577
 578         ath9k_hw_init_mode_gain_regs(ah);
 579         r = ath9k_hw_fill_cap_info(ah);
 580         if (r)
 581                 return r;
 582
 583         r = ath9k_hw_init_macaddr(ah);
 584         if (r) {
 585                 ath_print(common, ATH_DBG_FATAL,
 586                           "Failed to initialize MAC address\n");
 587                 return r;
 588         }
 589
 590         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 591                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 592         else
 593                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 594
 595         if (AR_SREV_9300_20_OR_LATER(ah))
 596                 ar9003_hw_set_nf_limits(ah);
 597
 598         ath9k_init_nfcal_hist_buffer(ah);
 599
 600         common->state = ATH_HW_INITIALIZED;
 601
 602         return 0;
 603 }
 604
 605 int ath9k_hw_init(struct ath_hw *ah)
 606 {
 607         int ret;
 608         struct ath_common *common = ath9k_hw_common(ah);
 609
 610         /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
 611         switch (ah->hw_version.devid) {
 612         case AR5416_DEVID_PCI:
 613         case AR5416_DEVID_PCIE:
 614         case AR5416_AR9100_DEVID:
 615         case AR9160_DEVID_PCI:
 616         case AR9280_DEVID_PCI:
 617         case AR9280_DEVID_PCIE:
 618         case AR9285_DEVID_PCIE:
 619         case AR9287_DEVID_PCI:
 620         case AR9287_DEVID_PCIE:
 621         case AR2427_DEVID_PCIE:
 622         case AR9300_DEVID_PCIE:
 623                 break;
 624         default:
 625                 if (common->bus_ops->ath_bus_type == ATH_USB)
 626                         break;
 627                 ath_print(common, ATH_DBG_FATAL,
 628                           "Hardware device ID 0x%04x not supported\n",
 629                           ah->hw_version.devid);
 630                 return -EOPNOTSUPP;
 631         }
 632
 633         ret = __ath9k_hw_init(ah);
 634         if (ret) {
 635                 ath_print(common, ATH_DBG_FATAL,
 636                           "Unable to initialize hardware; "
 637                           "initialization status: %d\n", ret);
 638                 return ret;
 639         }
 640
 641         return 0;
 642 }
 643 EXPORT_SYMBOL(ath9k_hw_init);
 644
 645 static void ath9k_hw_init_qos(struct ath_hw *ah)
 646 {
 647         ENABLE_REGWRITE_BUFFER(ah);
 648
 649         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 650         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 651
 652         REG_WRITE(ah, AR_QOS_NO_ACK,
 653                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 654                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 655                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 656
 657         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 658         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 659         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 660         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 661         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 662
 663         REGWRITE_BUFFER_FLUSH(ah);
 664         DISABLE_REGWRITE_BUFFER(ah);
 665 }
 666
 667 static void ath9k_hw_init_pll(struct ath_hw *ah,
 668                               struct ath9k_channel *chan)
 669 {
 670         u32 pll = ath9k_hw_compute_pll_control(ah, chan);
 671
 672         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 673
 674         /* Switch the core clock for ar9271 to 117Mhz */
 675         if (AR_SREV_9271(ah)) {
 676                 udelay(500);
 677                 REG_WRITE(ah, 0x50040, 0x304);
 678         }
 679
 680         udelay(RTC_PLL_SETTLE_DELAY);
 681
 682         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
 683 }
 684
 685 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
 686                                           enum nl80211_iftype opmode)
 687 {
 688         u32 imr_reg = AR_IMR_TXERR |
 689                 AR_IMR_TXURN |
 690                 AR_IMR_RXERR |
 691                 AR_IMR_RXORN |
 692                 AR_IMR_BCNMISC;
 693
 694         if (AR_SREV_9300_20_OR_LATER(ah)) {
 695                 imr_reg |= AR_IMR_RXOK_HP;
 696                 if (ah->config.rx_intr_mitigation)
 697                         imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 698                 else
 699                         imr_reg |= AR_IMR_RXOK_LP;
 700
 701         } else {
 702                 if (ah->config.rx_intr_mitigation)
 703                         imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 704                 else
 705                         imr_reg |= AR_IMR_RXOK;
 706         }
 707
 708         if (ah->config.tx_intr_mitigation)
 709                 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
 710         else
 711                 imr_reg |= AR_IMR_TXOK;
 712
 713         if (opmode == NL80211_IFTYPE_AP)
 714                 imr_reg |= AR_IMR_MIB;
 715
 716         ENABLE_REGWRITE_BUFFER(ah);
 717
 718         REG_WRITE(ah, AR_IMR, imr_reg);
 719         ah->imrs2_reg |= AR_IMR_S2_GTT;
 720         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
 721
 722         if (!AR_SREV_9100(ah)) {
 723                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
 724                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
 725                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
 726         }
 727
 728         REGWRITE_BUFFER_FLUSH(ah);
 729         DISABLE_REGWRITE_BUFFER(ah);
 730
 731         if (AR_SREV_9300_20_OR_LATER(ah)) {
 732                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
 733                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
 734                 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
 735                 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
 736         }
 737 }
 738
 739 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
 740 {
 741         u32 val = ath9k_hw_mac_to_clks(ah, us);
 742         val = min(val, (u32) 0xFFFF);
 743         REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
 744 }
 745
 746 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
 747 {
 748         u32 val = ath9k_hw_mac_to_clks(ah, us);
 749         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
 750         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
 751 }
 752
 753 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
 754 {
 755         u32 val = ath9k_hw_mac_to_clks(ah, us);
 756         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
 757         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
 758 }
 759
 760 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
 761 {
 762         if (tu > 0xFFFF) {
 763                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
 764                           "bad global tx timeout %u\n", tu);
 765                 ah->globaltxtimeout = (u32) -1;
 766                 return false;
 767         } else {
 768                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
 769                 ah->globaltxtimeout = tu;
 770                 return true;
 771         }
 772 }
 773
 774 void ath9k_hw_init_global_settings(struct ath_hw *ah)
 775 {
 776         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 777         int acktimeout;
 778         int slottime;
 779         int sifstime;
 780
 781         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
 782                   ah->misc_mode);
 783
 784         if (ah->misc_mode != 0)
 785                 REG_WRITE(ah, AR_PCU_MISC,
 786                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
 787
 788         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
 789                 sifstime = 16;
 790         else
 791                 sifstime = 10;
 792
 793         /* As defined by IEEE 802.11-2007 17.3.8.6 */
 794         slottime = ah->slottime + 3 * ah->coverage_class;
 795         acktimeout = slottime + sifstime;
 796
 797         /*
 798          * Workaround for early ACK timeouts, add an offset to match the
 799          * initval's 64us ack timeout value.
 800          * This was initially only meant to work around an issue with delayed
 801          * BA frames in some implementations, but it has been found to fix ACK
 802          * timeout issues in other cases as well.
 803          */
 804         if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
 805                 acktimeout += 64 - sifstime - ah->slottime;
 806
 807         ath9k_hw_setslottime(ah, slottime);
 808         ath9k_hw_set_ack_timeout(ah, acktimeout);
 809         ath9k_hw_set_cts_timeout(ah, acktimeout);
 810         if (ah->globaltxtimeout != (u32) -1)
 811                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
 812 }
 813 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
 814
 815 void ath9k_hw_deinit(struct ath_hw *ah)
 816 {
 817         struct ath_common *common = ath9k_hw_common(ah);
 818
 819         if (common->state < ATH_HW_INITIALIZED)
 820                 goto free_hw;
 821
 822         if (!AR_SREV_9100(ah))
 823                 ath9k_hw_ani_disable(ah);
 824
 825         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
 826
 827 free_hw:
 828         ath9k_hw_rf_free_ext_banks(ah);
 829 }
 830 EXPORT_SYMBOL(ath9k_hw_deinit);
 831
 832 /*******/
 833 /* INI */
 834 /*******/
 835
 836 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
 837 {
 838         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
 839
 840         if (IS_CHAN_B(chan))
 841                 ctl |= CTL_11B;
 842         else if (IS_CHAN_G(chan))
 843                 ctl |= CTL_11G;
 844         else
 845                 ctl |= CTL_11A;
 846
 847         return ctl;
 848 }
 849
 850 /****************************************/
 851 /* Reset and Channel Switching Routines */
 852 /****************************************/
 853
 854 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
 855 {
 856         struct ath_common *common = ath9k_hw_common(ah);
 857         u32 regval;
 858
 859         ENABLE_REGWRITE_BUFFER(ah);
 860
 861         /*
 862          * set AHB_MODE not to do cacheline prefetches
 863         */
 864         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 865                 regval = REG_READ(ah, AR_AHB_MODE);
 866                 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
 867         }
 868
 869         /*
 870          * let mac dma reads be in 128 byte chunks
 871          */
 872         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
 873         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
 874
 875         REGWRITE_BUFFER_FLUSH(ah);
 876         DISABLE_REGWRITE_BUFFER(ah);
 877
 878         /*
 879          * Restore TX Trigger Level to its pre-reset value.
 880          * The initial value depends on whether aggregation is enabled, and is
 881          * adjusted whenever underruns are detected.
 882          */
 883         if (!AR_SREV_9300_20_OR_LATER(ah))
 884                 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
 885
 886         ENABLE_REGWRITE_BUFFER(ah);
 887
 888         /*
 889          * let mac dma writes be in 128 byte chunks
 890          */
 891         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
 892         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
 893
 894         /*
 895          * Setup receive FIFO threshold to hold off TX activities
 896          */
 897         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
 898
 899         if (AR_SREV_9300_20_OR_LATER(ah)) {
 900                 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
 901                 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
 902
 903                 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
 904                         ah->caps.rx_status_len);
 905         }
 906
 907         /*
 908          * reduce the number of usable entries in PCU TXBUF to avoid
 909          * wrap around issues.
 910          */
 911         if (AR_SREV_9285(ah)) {
 912                 /* For AR9285 the number of Fifos are reduced to half.
 913                  * So set the usable tx buf size also to half to
 914                  * avoid data/delimiter underruns
 915                  */
 916                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
 917                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
 918         } else if (!AR_SREV_9271(ah)) {
 919                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
 920                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
 921         }
 922
 923         REGWRITE_BUFFER_FLUSH(ah);
 924         DISABLE_REGWRITE_BUFFER(ah);
 925
 926         if (AR_SREV_9300_20_OR_LATER(ah))
 927                 ath9k_hw_reset_txstatus_ring(ah);
 928 }
 929
 930 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
 931 {
 932         u32 val;
 933
 934         val = REG_READ(ah, AR_STA_ID1);
 935         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
 936         switch (opmode) {
 937         case NL80211_IFTYPE_AP:
 938                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
 939                           | AR_STA_ID1_KSRCH_MODE);
 940                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 941                 break;
 942         case NL80211_IFTYPE_ADHOC:
 943         case NL80211_IFTYPE_MESH_POINT:
 944                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
 945                           | AR_STA_ID1_KSRCH_MODE);
 946                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 947                 break;
 948         case NL80211_IFTYPE_STATION:
 949         case NL80211_IFTYPE_MONITOR:
 950                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
 951                 break;
 952         }
 953 }
 954
 955 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
 956                                    u32 *coef_mantissa, u32 *coef_exponent)
 957 {
 958         u32 coef_exp, coef_man;
 959
 960         for (coef_exp = 31; coef_exp > 0; coef_exp--)
 961                 if ((coef_scaled >> coef_exp) & 0x1)
 962                         break;
 963
 964         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
 965
 966         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
 967
 968         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
 969         *coef_exponent = coef_exp - 16;
 970 }
 971
 972 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
 973 {
 974         u32 rst_flags;
 975         u32 tmpReg;
 976
 977         if (AR_SREV_9100(ah)) {
 978                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
 979                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
 980                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
 981                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
 982                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
 983         }
 984
 985         ENABLE_REGWRITE_BUFFER(ah);
 986
 987         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
 988                   AR_RTC_FORCE_WAKE_ON_INT);
 989
 990         if (AR_SREV_9100(ah)) {
 991                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
 992                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
 993         } else {
 994                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
 995                 if (tmpReg &
 996                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
 997                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
 998                         u32 val;
 999                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1000
1001                         val = AR_RC_HOSTIF;
1002                         if (!AR_SREV_9300_20_OR_LATER(ah))
1003                                 val |= AR_RC_AHB;
1004                         REG_WRITE(ah, AR_RC, val);
1005
1006                 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1007                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1008
1009                 rst_flags = AR_RTC_RC_MAC_WARM;
1010                 if (type == ATH9K_RESET_COLD)
1011                         rst_flags |= AR_RTC_RC_MAC_COLD;
1012         }
1013
1014         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1015
1016         REGWRITE_BUFFER_FLUSH(ah);
1017         DISABLE_REGWRITE_BUFFER(ah);
1018
1019         udelay(50);
1020
1021         REG_WRITE(ah, AR_RTC_RC, 0);
1022         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1023                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1024                           "RTC stuck in MAC reset\n");
1025                 return false;
1026         }
1027
1028         if (!AR_SREV_9100(ah))
1029                 REG_WRITE(ah, AR_RC, 0);
1030
1031         if (AR_SREV_9100(ah))
1032                 udelay(50);
1033
1034         return true;
1035 }
1036
1037 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1038 {
1039         ENABLE_REGWRITE_BUFFER(ah);
1040
1041         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1042                   AR_RTC_FORCE_WAKE_ON_INT);
1043
1044         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1045                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1046
1047         REG_WRITE(ah, AR_RTC_RESET, 0);
1048
1049         REGWRITE_BUFFER_FLUSH(ah);
1050         DISABLE_REGWRITE_BUFFER(ah);
1051
1052         if (!AR_SREV_9300_20_OR_LATER(ah))
1053                 udelay(2);
1054
1055         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1056                 REG_WRITE(ah, AR_RC, 0);
1057
1058         REG_WRITE(ah, AR_RTC_RESET, 1);
1059
1060         if (!ath9k_hw_wait(ah,
1061                            AR_RTC_STATUS,
1062                            AR_RTC_STATUS_M,
1063                            AR_RTC_STATUS_ON,
1064                            AH_WAIT_TIMEOUT)) {
1065                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1066                           "RTC not waking up\n");
1067                 return false;
1068         }
1069
1070         ath9k_hw_read_revisions(ah);
1071
1072         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1073 }
1074
1075 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1076 {
1077         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1078                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1079
1080         switch (type) {
1081         case ATH9K_RESET_POWER_ON:
1082                 return ath9k_hw_set_reset_power_on(ah);
1083         case ATH9K_RESET_WARM:
1084         case ATH9K_RESET_COLD:
1085                 return ath9k_hw_set_reset(ah, type);
1086         default:
1087                 return false;
1088         }
1089 }
1090
1091 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1092                                 struct ath9k_channel *chan)
1093 {
1094         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1095                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1096                         return false;
1097         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1098                 return false;
1099
1100         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1101                 return false;
1102
1103         ah->chip_fullsleep = false;
1104         ath9k_hw_init_pll(ah, chan);
1105         ath9k_hw_set_rfmode(ah, chan);
1106
1107         return true;
1108 }
1109
1110 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1111                                     struct ath9k_channel *chan)
1112 {
1113         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1114         struct ath_common *common = ath9k_hw_common(ah);
1115         struct ieee80211_channel *channel = chan->chan;
1116         u32 qnum;
1117         int r;
1118
1119         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1120                 if (ath9k_hw_numtxpending(ah, qnum)) {
1121                         ath_print(common, ATH_DBG_QUEUE,
1122                                   "Transmit frames pending on "
1123                                   "queue %d\n", qnum);
1124                         return false;
1125                 }
1126         }
1127
1128         if (!ath9k_hw_rfbus_req(ah)) {
1129                 ath_print(common, ATH_DBG_FATAL,
1130                           "Could not kill baseband RX\n");
1131                 return false;
1132         }
1133
1134         ath9k_hw_set_channel_regs(ah, chan);
1135
1136         r = ath9k_hw_rf_set_freq(ah, chan);
1137         if (r) {
1138                 ath_print(common, ATH_DBG_FATAL,
1139                           "Failed to set channel\n");
1140                 return false;
1141         }
1142
1143         ah->eep_ops->set_txpower(ah, chan,
1144                              ath9k_regd_get_ctl(regulatory, chan),
1145                              channel->max_antenna_gain * 2,
1146                              channel->max_power * 2,
1147                              min((u32) MAX_RATE_POWER,
1148                              (u32) regulatory->power_limit));
1149
1150         ath9k_hw_rfbus_done(ah);
1151
1152         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1153                 ath9k_hw_set_delta_slope(ah, chan);
1154
1155         ath9k_hw_spur_mitigate_freq(ah, chan);
1156
1157         if (!chan->oneTimeCalsDone)
1158                 chan->oneTimeCalsDone = true;
1159
1160         return true;
1161 }
1162
1163 bool ath9k_hw_check_alive(struct ath_hw *ah)
1164 {
1165         int count = 50;
1166         u32 reg;
1167
1168         if (AR_SREV_9285_10_OR_LATER(ah))
1169                 return true;
1170
1171         do {
1172                 reg = REG_READ(ah, AR_OBS_BUS_1);
1173
1174                 if ((reg & 0x7E7FFFEF) == 0x00702400)
1175                         continue;
1176
1177                 switch (reg & 0x7E000B00) {
1178                 case 0x1E000000:
1179                 case 0x52000B00:
1180                 case 0x18000B00:
1181                         continue;
1182                 default:
1183                         return true;
1184                 }
1185         } while (count-- > 0);
1186
1187         return false;
1188 }
1189 EXPORT_SYMBOL(ath9k_hw_check_alive);
1190
1191 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1192                     bool bChannelChange)
1193 {
1194         struct ath_common *common = ath9k_hw_common(ah);
1195         u32 saveLedState;
1196         struct ath9k_channel *curchan = ah->curchan;
1197         u32 saveDefAntenna;
1198         u32 macStaId1;
1199         u64 tsf = 0;
1200         int i, r;
1201
1202         ah->txchainmask = common->tx_chainmask;
1203         ah->rxchainmask = common->rx_chainmask;
1204
1205         if (!ah->chip_fullsleep) {
1206                 ath9k_hw_abortpcurecv(ah);
1207                 if (!ath9k_hw_stopdmarecv(ah))
1208                         ath_print(common, ATH_DBG_XMIT,
1209                                 "Failed to stop receive dma\n");
1210         }
1211
1212         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1213                 return -EIO;
1214
1215         if (curchan && !ah->chip_fullsleep)
1216                 ath9k_hw_getnf(ah, curchan);
1217
1218         if (bChannelChange &&
1219             (ah->chip_fullsleep != true) &&
1220             (ah->curchan != NULL) &&
1221             (chan->channel != ah->curchan->channel) &&
1222             ((chan->channelFlags & CHANNEL_ALL) ==
1223              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1224              !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1225              IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1226
1227                 if (ath9k_hw_channel_change(ah, chan)) {
1228                         ath9k_hw_loadnf(ah, ah->curchan);
1229                         ath9k_hw_start_nfcal(ah);
1230                         return 0;
1231                 }
1232         }
1233
1234         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1235         if (saveDefAntenna == 0)
1236                 saveDefAntenna = 1;
1237
1238         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1239
1240         /* For chips on which RTC reset is done, save TSF before it gets cleared */
1241         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1242                 tsf = ath9k_hw_gettsf64(ah);
1243
1244         saveLedState = REG_READ(ah, AR_CFG_LED) &
1245                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1246                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1247
1248         ath9k_hw_mark_phy_inactive(ah);
1249
1250         /* Only required on the first reset */
1251         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1252                 REG_WRITE(ah,
1253                           AR9271_RESET_POWER_DOWN_CONTROL,
1254                           AR9271_RADIO_RF_RST);
1255                 udelay(50);
1256         }
1257
1258         if (!ath9k_hw_chip_reset(ah, chan)) {
1259                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1260                 return -EINVAL;
1261         }
1262
1263         /* Only required on the first reset */
1264         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1265                 ah->htc_reset_init = false;
1266                 REG_WRITE(ah,
1267                           AR9271_RESET_POWER_DOWN_CONTROL,
1268                           AR9271_GATE_MAC_CTL);
1269                 udelay(50);
1270         }
1271
1272         /* Restore TSF */
1273         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1274                 ath9k_hw_settsf64(ah, tsf);
1275
1276         if (AR_SREV_9280_10_OR_LATER(ah))
1277                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1278
1279         r = ath9k_hw_process_ini(ah, chan);
1280         if (r)
1281                 return r;
1282
1283         /* Setup MFP options for CCMP */
1284         if (AR_SREV_9280_20_OR_LATER(ah)) {
1285                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1286                  * frames when constructing CCMP AAD. */
1287                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1288                               0xc7ff);
1289                 ah->sw_mgmt_crypto = false;
1290         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1291                 /* Disable hardware crypto for management frames */
1292                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1293                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1294                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1295                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1296                 ah->sw_mgmt_crypto = true;
1297         } else
1298                 ah->sw_mgmt_crypto = true;
1299
1300         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1301                 ath9k_hw_set_delta_slope(ah, chan);
1302
1303         ath9k_hw_spur_mitigate_freq(ah, chan);
1304         ah->eep_ops->set_board_values(ah, chan);
1305
1306         ath9k_hw_set_operating_mode(ah, ah->opmode);
1307
1308         ENABLE_REGWRITE_BUFFER(ah);
1309
1310         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1311         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1312                   | macStaId1
1313                   | AR_STA_ID1_RTS_USE_DEF
1314                   | (ah->config.
1315                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1316                   | ah->sta_id1_defaults);
1317         ath_hw_setbssidmask(common);
1318         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1319         ath9k_hw_write_associd(ah);
1320         REG_WRITE(ah, AR_ISR, ~0);
1321         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1322
1323         REGWRITE_BUFFER_FLUSH(ah);
1324         DISABLE_REGWRITE_BUFFER(ah);
1325
1326         r = ath9k_hw_rf_set_freq(ah, chan);
1327         if (r)
1328                 return r;
1329
1330         ENABLE_REGWRITE_BUFFER(ah);
1331
1332         for (i = 0; i < AR_NUM_DCU; i++)
1333                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1334
1335         REGWRITE_BUFFER_FLUSH(ah);
1336         DISABLE_REGWRITE_BUFFER(ah);
1337
1338         ah->intr_txqs = 0;
1339         for (i = 0; i < ah->caps.total_queues; i++)
1340                 ath9k_hw_resettxqueue(ah, i);
1341
1342         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1343         ath9k_hw_init_qos(ah);
1344
1345         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1346                 ath9k_enable_rfkill(ah);
1347
1348         ath9k_hw_init_global_settings(ah);
1349
1350         if (!AR_SREV_9300_20_OR_LATER(ah)) {
1351                 ar9002_hw_enable_async_fifo(ah);
1352                 ar9002_hw_enable_wep_aggregation(ah);
1353         }
1354
1355         REG_WRITE(ah, AR_STA_ID1,
1356                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1357
1358         ath9k_hw_set_dma(ah);
1359
1360         REG_WRITE(ah, AR_OBS, 8);
1361
1362         if (ah->config.rx_intr_mitigation) {
1363                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1364                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1365         }
1366
1367         if (ah->config.tx_intr_mitigation) {
1368                 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1369                 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1370         }
1371
1372         ath9k_hw_init_bb(ah, chan);
1373
1374         if (!ath9k_hw_init_cal(ah, chan))
1375                 return -EIO;
1376
1377         ENABLE_REGWRITE_BUFFER(ah);
1378
1379         ath9k_hw_restore_chainmask(ah);
1380         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1381
1382         REGWRITE_BUFFER_FLUSH(ah);
1383         DISABLE_REGWRITE_BUFFER(ah);
1384
1385         /*
1386          * For big endian systems turn on swapping for descriptors
1387          */
1388         if (AR_SREV_9100(ah)) {
1389                 u32 mask;
1390                 mask = REG_READ(ah, AR_CFG);
1391                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1392                         ath_print(common, ATH_DBG_RESET,
1393                                 "CFG Byte Swap Set 0x%x\n", mask);
1394                 } else {
1395                         mask =
1396                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1397                         REG_WRITE(ah, AR_CFG, mask);
1398                         ath_print(common, ATH_DBG_RESET,
1399                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1400                 }
1401         } else {
1402                 /* Configure AR9271 target WLAN */
1403                 if (AR_SREV_9271(ah))
1404                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1405 #ifdef __BIG_ENDIAN
1406                 else
1407                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1408 #endif
1409         }
1410
1411         if (ah->btcoex_hw.enabled)
1412                 ath9k_hw_btcoex_enable(ah);
1413
1414         if (AR_SREV_9300_20_OR_LATER(ah)) {
1415                 ath9k_hw_loadnf(ah, curchan);
1416                 ath9k_hw_start_nfcal(ah);
1417         }
1418
1419         return 0;
1420 }
1421 EXPORT_SYMBOL(ath9k_hw_reset);
1422
1423 /************************/
1424 /* Key Cache Management */
1425 /************************/
1426
1427 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1428 {
1429         u32 keyType;
1430
1431         if (entry >= ah->caps.keycache_size) {
1432                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1433                           "keychache entry %u out of range\n", entry);
1434                 return false;
1435         }
1436
1437         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1438
1439         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1440         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1441         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1442         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1443         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1444         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1445         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1446         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1447
1448         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1449                 u16 micentry = entry + 64;
1450
1451                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1452                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1453                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1454                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1455
1456         }
1457
1458         return true;
1459 }
1460 EXPORT_SYMBOL(ath9k_hw_keyreset);
1461
1462 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1463 {
1464         u32 macHi, macLo;
1465
1466         if (entry >= ah->caps.keycache_size) {
1467                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1468                           "keychache entry %u out of range\n", entry);
1469                 return false;
1470         }
1471
1472         if (mac != NULL) {
1473                 macHi = (mac[5] << 8) | mac[4];
1474                 macLo = (mac[3] << 24) |
1475                         (mac[2] << 16) |
1476                         (mac[1] << 8) |
1477                         mac[0];
1478                 macLo >>= 1;
1479                 macLo |= (macHi & 1) << 31;
1480                 macHi >>= 1;
1481         } else {
1482                 macLo = macHi = 0;
1483         }
1484         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1485         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
1486
1487         return true;
1488 }
1489 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1490
1491 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1492                                  const struct ath9k_keyval *k,
1493                                  const u8 *mac)
1494 {
1495         const struct ath9k_hw_capabilities *pCap = &ah->caps;
1496         struct ath_common *common = ath9k_hw_common(ah);
1497         u32 key0, key1, key2, key3, key4;
1498         u32 keyType;
1499
1500         if (entry >= pCap->keycache_size) {
1501                 ath_print(common, ATH_DBG_FATAL,
1502                           "keycache entry %u out of range\n", entry);
1503                 return false;
1504         }
1505
1506         switch (k->kv_type) {
1507         case ATH9K_CIPHER_AES_OCB:
1508                 keyType = AR_KEYTABLE_TYPE_AES;
1509                 break;
1510         case ATH9K_CIPHER_AES_CCM:
1511                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1512                         ath_print(common, ATH_DBG_ANY,
1513                                   "AES-CCM not supported by mac rev 0x%x\n",
1514                                   ah->hw_version.macRev);
1515                         return false;
1516                 }
1517                 keyType = AR_KEYTABLE_TYPE_CCM;
1518                 break;
1519         case ATH9K_CIPHER_TKIP:
1520                 keyType = AR_KEYTABLE_TYPE_TKIP;
1521                 if (ATH9K_IS_MIC_ENABLED(ah)
1522                     && entry + 64 >= pCap->keycache_size) {
1523                         ath_print(common, ATH_DBG_ANY,
1524                                   "entry %u inappropriate for TKIP\n", entry);
1525                         return false;
1526                 }
1527                 break;
1528         case ATH9K_CIPHER_WEP:
1529                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1530                         ath_print(common, ATH_DBG_ANY,
1531                                   "WEP key length %u too small\n", k->kv_len);
1532                         return false;
1533                 }
1534                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1535                         keyType = AR_KEYTABLE_TYPE_40;
1536                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1537                         keyType = AR_KEYTABLE_TYPE_104;
1538                 else
1539                         keyType = AR_KEYTABLE_TYPE_128;
1540                 break;
1541         case ATH9K_CIPHER_CLR:
1542                 keyType = AR_KEYTABLE_TYPE_CLR;
1543                 break;
1544         default:
1545                 ath_print(common, ATH_DBG_FATAL,
1546                           "cipher %u not supported\n", k->kv_type);
1547                 return false;
1548         }
1549
1550         key0 = get_unaligned_le32(k->kv_val + 0);
1551         key1 = get_unaligned_le16(k->kv_val + 4);
1552         key2 = get_unaligned_le32(k->kv_val + 6);
1553         key3 = get_unaligned_le16(k->kv_val + 10);
1554         key4 = get_unaligned_le32(k->kv_val + 12);
1555         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1556                 key4 &= 0xff;
1557
1558         /*
1559          * Note: Key cache registers access special memory area that requires
1560          * two 32-bit writes to actually update the values in the internal
1561          * memory. Consequently, the exact order and pairs used here must be
1562          * maintained.
1563          */
1564
1565         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1566                 u16 micentry = entry + 64;
1567
1568                 /*
1569                  * Write inverted key[47:0] first to avoid Michael MIC errors
1570                  * on frames that could be sent or received at the same time.
1571                  * The correct key will be written in the end once everything
1572                  * else is ready.
1573                  */
1574                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1575                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1576
1577                 /* Write key[95:48] */
1578                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1579                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1580
1581                 /* Write key[127:96] and key type */
1582                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1583                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1584
1585                 /* Write MAC address for the entry */
1586                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1587
1588                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1589                         /*
1590                          * TKIP uses two key cache entries:
1591                          * Michael MIC TX/RX keys in the same key cache entry
1592                          * (idx = main index + 64):
1593                          * key0 [31:0] = RX key [31:0]
1594                          * key1 [15:0] = TX key [31:16]
1595                          * key1 [31:16] = reserved
1596                          * key2 [31:0] = RX key [63:32]
1597                          * key3 [15:0] = TX key [15:0]
1598                          * key3 [31:16] = reserved
1599                          * key4 [31:0] = TX key [63:32]
1600                          */
1601                         u32 mic0, mic1, mic2, mic3, mic4;
1602
1603                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1604                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1605                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1606                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1607                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
1608
1609                         /* Write RX[31:0] and TX[31:16] */
1610                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1611                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1612
1613                         /* Write RX[63:32] and TX[15:0] */
1614                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1615                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1616
1617                         /* Write TX[63:32] and keyType(reserved) */
1618                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1619                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1620                                   AR_KEYTABLE_TYPE_CLR);
1621
1622                 } else {
1623                         /*
1624                          * TKIP uses four key cache entries (two for group
1625                          * keys):
1626                          * Michael MIC TX/RX keys are in different key cache
1627                          * entries (idx = main index + 64 for TX and
1628                          * main index + 32 + 96 for RX):
1629                          * key0 [31:0] = TX/RX MIC key [31:0]
1630                          * key1 [31:0] = reserved
1631                          * key2 [31:0] = TX/RX MIC key [63:32]
1632                          * key3 [31:0] = reserved
1633                          * key4 [31:0] = reserved
1634                          *
1635                          * Upper layer code will call this function separately
1636                          * for TX and RX keys when these registers offsets are
1637                          * used.
1638                          */
1639                         u32 mic0, mic2;
1640
1641                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1642                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1643
1644                         /* Write MIC key[31:0] */
1645                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1646                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1647
1648                         /* Write MIC key[63:32] */
1649                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1650                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1651
1652                         /* Write TX[63:32] and keyType(reserved) */
1653                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1654                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1655                                   AR_KEYTABLE_TYPE_CLR);
1656                 }
1657
1658                 /* MAC address registers are reserved for the MIC entry */
1659                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1660                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1661
1662                 /*
1663                  * Write the correct (un-inverted) key[47:0] last to enable
1664                  * TKIP now that all other registers are set with correct
1665                  * values.
1666                  */
1667                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1668                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1669         } else {
1670                 /* Write key[47:0] */
1671                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1672                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1673
1674                 /* Write key[95:48] */
1675                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1676                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1677
1678                 /* Write key[127:96] and key type */
1679                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1680                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1681
1682                 /* Write MAC address for the entry */
1683                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1684         }
1685
1686         return true;
1687 }
1688 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
1689
1690 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
1691 {
1692         if (entry < ah->caps.keycache_size) {
1693                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1694                 if (val & AR_KEYTABLE_VALID)
1695                         return true;
1696         }
1697         return false;
1698 }
1699 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
1700
1701 /******************************/
1702 /* Power Management (Chipset) */
1703 /******************************/
1704
1705 /*
1706  * Notify Power Mgt is disabled in self-generated frames.
1707  * If requested, force chip to sleep.
1708  */
1709 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1710 {
1711         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1712         if (setChip) {
1713                 /*
1714                  * Clear the RTC force wake bit to allow the
1715                  * mac to go to sleep.
1716                  */
1717                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1718                             AR_RTC_FORCE_WAKE_EN);
1719                 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1720                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1721
1722                 /* Shutdown chip. Active low */
1723                 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1724                         REG_CLR_BIT(ah, (AR_RTC_RESET),
1725                                     AR_RTC_RESET_EN);
1726         }
1727 }
1728
1729 /*
1730  * Notify Power Management is enabled in self-generating
1731  * frames. If request, set power mode of chip to
1732  * auto/normal.  Duration in units of 128us (1/8 TU).
1733  */
1734 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1735 {
1736         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1737         if (setChip) {
1738                 struct ath9k_hw_capabilities *pCap = &ah->caps;
1739
1740                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1741                         /* Set WakeOnInterrupt bit; clear ForceWake bit */
1742                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1743                                   AR_RTC_FORCE_WAKE_ON_INT);
1744                 } else {
1745                         /*
1746                          * Clear the RTC force wake bit to allow the
1747                          * mac to go to sleep.
1748                          */
1749                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1750                                     AR_RTC_FORCE_WAKE_EN);
1751                 }
1752         }
1753 }
1754
1755 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1756 {
1757         u32 val;
1758         int i;
1759
1760         if (setChip) {
1761                 if ((REG_READ(ah, AR_RTC_STATUS) &
1762                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1763                         if (ath9k_hw_set_reset_reg(ah,
1764                                            ATH9K_RESET_POWER_ON) != true) {
1765                                 return false;
1766                         }
1767                         if (!AR_SREV_9300_20_OR_LATER(ah))
1768                                 ath9k_hw_init_pll(ah, NULL);
1769                 }
1770                 if (AR_SREV_9100(ah))
1771                         REG_SET_BIT(ah, AR_RTC_RESET,
1772                                     AR_RTC_RESET_EN);
1773
1774                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1775                             AR_RTC_FORCE_WAKE_EN);
1776                 udelay(50);
1777
1778                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1779                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1780                         if (val == AR_RTC_STATUS_ON)
1781                                 break;
1782                         udelay(50);
1783                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1784                                     AR_RTC_FORCE_WAKE_EN);
1785                 }
1786                 if (i == 0) {
1787                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1788                                   "Failed to wakeup in %uus\n",
1789                                   POWER_UP_TIME / 20);
1790                         return false;
1791                 }
1792         }
1793
1794         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1795
1796         return true;
1797 }
1798
1799 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1800 {
1801         struct ath_common *common = ath9k_hw_common(ah);
1802         int status = true, setChip = true;
1803         static const char *modes[] = {
1804                 "AWAKE",
1805                 "FULL-SLEEP",
1806                 "NETWORK SLEEP",
1807                 "UNDEFINED"
1808         };
1809
1810         if (ah->power_mode == mode)
1811                 return status;
1812
1813         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1814                   modes[ah->power_mode], modes[mode]);
1815
1816         switch (mode) {
1817         case ATH9K_PM_AWAKE:
1818                 status = ath9k_hw_set_power_awake(ah, setChip);
1819                 break;
1820         case ATH9K_PM_FULL_SLEEP:
1821                 ath9k_set_power_sleep(ah, setChip);
1822                 ah->chip_fullsleep = true;
1823                 break;
1824         case ATH9K_PM_NETWORK_SLEEP:
1825                 ath9k_set_power_network_sleep(ah, setChip);
1826                 break;
1827         default:
1828                 ath_print(common, ATH_DBG_FATAL,
1829                           "Unknown power mode %u\n", mode);
1830                 return false;
1831         }
1832         ah->power_mode = mode;
1833
1834         return status;
1835 }
1836 EXPORT_SYMBOL(ath9k_hw_setpower);
1837
1838 /*******************/
1839 /* Beacon Handling */
1840 /*******************/
1841
1842 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1843 {
1844         int flags = 0;
1845
1846         ah->beacon_interval = beacon_period;
1847
1848         ENABLE_REGWRITE_BUFFER(ah);
1849
1850         switch (ah->opmode) {
1851         case NL80211_IFTYPE_STATION:
1852         case NL80211_IFTYPE_MONITOR:
1853                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1854                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1855                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1856                 flags |= AR_TBTT_TIMER_EN;
1857                 break;
1858         case NL80211_IFTYPE_ADHOC:
1859         case NL80211_IFTYPE_MESH_POINT:
1860                 REG_SET_BIT(ah, AR_TXCFG,
1861                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1862                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1863                           TU_TO_USEC(next_beacon +
1864                                      (ah->atim_window ? ah->
1865                                       atim_window : 1)));
1866                 flags |= AR_NDP_TIMER_EN;
1867         case NL80211_IFTYPE_AP:
1868                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1869                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1870                           TU_TO_USEC(next_beacon -
1871                                      ah->config.
1872                                      dma_beacon_response_time));
1873                 REG_WRITE(ah, AR_NEXT_SWBA,
1874                           TU_TO_USEC(next_beacon -
1875                                      ah->config.
1876                                      sw_beacon_response_time));
1877                 flags |=
1878                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1879                 break;
1880         default:
1881                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1882                           "%s: unsupported opmode: %d\n",
1883                           __func__, ah->opmode);
1884                 return;
1885                 break;
1886         }
1887
1888         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1889         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1890         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1891         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1892
1893         REGWRITE_BUFFER_FLUSH(ah);
1894         DISABLE_REGWRITE_BUFFER(ah);
1895
1896         beacon_period &= ~ATH9K_BEACON_ENA;
1897         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1898                 ath9k_hw_reset_tsf(ah);
1899         }
1900
1901         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1902 }
1903 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1904
1905 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1906                                     const struct ath9k_beacon_state *bs)
1907 {
1908         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1909         struct ath9k_hw_capabilities *pCap = &ah->caps;
1910         struct ath_common *common = ath9k_hw_common(ah);
1911
1912         ENABLE_REGWRITE_BUFFER(ah);
1913
1914         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1915
1916         REG_WRITE(ah, AR_BEACON_PERIOD,
1917                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1918         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1919                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1920
1921         REGWRITE_BUFFER_FLUSH(ah);
1922         DISABLE_REGWRITE_BUFFER(ah);
1923
1924         REG_RMW_FIELD(ah, AR_RSSI_THR,
1925                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1926
1927         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1928
1929         if (bs->bs_sleepduration > beaconintval)
1930                 beaconintval = bs->bs_sleepduration;
1931
1932         dtimperiod = bs->bs_dtimperiod;
1933         if (bs->bs_sleepduration > dtimperiod)
1934                 dtimperiod = bs->bs_sleepduration;
1935
1936         if (beaconintval == dtimperiod)
1937                 nextTbtt = bs->bs_nextdtim;
1938         else
1939                 nextTbtt = bs->bs_nexttbtt;
1940
1941         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1942         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1943         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1944         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1945
1946         ENABLE_REGWRITE_BUFFER(ah);
1947
1948         REG_WRITE(ah, AR_NEXT_DTIM,
1949                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1950         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1951
1952         REG_WRITE(ah, AR_SLEEP1,
1953                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1954                   | AR_SLEEP1_ASSUME_DTIM);
1955
1956         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1957                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1958         else
1959                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1960
1961         REG_WRITE(ah, AR_SLEEP2,
1962                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1963
1964         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1965         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1966
1967         REGWRITE_BUFFER_FLUSH(ah);
1968         DISABLE_REGWRITE_BUFFER(ah);
1969
1970         REG_SET_BIT(ah, AR_TIMER_MODE,
1971                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1972                     AR_DTIM_TIMER_EN);
1973
1974         /* TSF Out of Range Threshold */
1975         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1976 }
1977 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1978
1979 /*******************/
1980 /* HW Capabilities */
1981 /*******************/
1982
1983 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1984 {
1985         struct ath9k_hw_capabilities *pCap = &ah->caps;
1986         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1987         struct ath_common *common = ath9k_hw_common(ah);
1988         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1989
1990         u16 capField = 0, eeval;
1991
1992         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1993         regulatory->current_rd = eeval;
1994
1995         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1996         if (AR_SREV_9285_10_OR_LATER(ah))
1997                 eeval |= AR9285_RDEXT_DEFAULT;
1998         regulatory->current_rd_ext = eeval;
1999
2000         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
2001
2002         if (ah->opmode != NL80211_IFTYPE_AP &&
2003             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2004                 if (regulatory->current_rd == 0x64 ||
2005                     regulatory->current_rd == 0x65)
2006                         regulatory->current_rd += 5;
2007                 else if (regulatory->current_rd == 0x41)
2008                         regulatory->current_rd = 0x43;
2009                 ath_print(common, ATH_DBG_REGULATORY,
2010                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
2011         }
2012
2013         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2014         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2015                 ath_print(common, ATH_DBG_FATAL,
2016                           "no band has been marked as supported in EEPROM.\n");
2017                 return -EINVAL;
2018         }
2019
2020         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2021
2022         if (eeval & AR5416_OPFLAGS_11A) {
2023                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2024                 if (ah->config.ht_enable) {
2025                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2026                                 set_bit(ATH9K_MODE_11NA_HT20,
2027                                         pCap->wireless_modes);
2028                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2029                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2030                                         pCap->wireless_modes);
2031                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2032                                         pCap->wireless_modes);
2033                         }
2034                 }
2035         }
2036
2037         if (eeval & AR5416_OPFLAGS_11G) {
2038                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2039                 if (ah->config.ht_enable) {
2040                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2041                                 set_bit(ATH9K_MODE_11NG_HT20,
2042                                         pCap->wireless_modes);
2043                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2044                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2045                                         pCap->wireless_modes);
2046                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2047                                         pCap->wireless_modes);
2048                         }
2049                 }
2050         }
2051
2052         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2053         /*
2054          * For AR9271 we will temporarilly uses the rx chainmax as read from
2055          * the EEPROM.
2056          */
2057         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2058             !(eeval & AR5416_OPFLAGS_11A) &&
2059             !(AR_SREV_9271(ah)))
2060                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2061                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2062         else
2063                 /* Use rx_chainmask from EEPROM. */
2064                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2065
2066         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2067                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2068
2069         pCap->low_2ghz_chan = 2312;
2070         pCap->high_2ghz_chan = 2732;
2071
2072         pCap->low_5ghz_chan = 4920;
2073         pCap->high_5ghz_chan = 6100;
2074
2075         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2076         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2077         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2078
2079         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2080         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2081         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2082
2083         if (ah->config.ht_enable)
2084                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2085         else
2086                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2087
2088         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2089         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2090         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2091         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2092
2093         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2094                 pCap->total_queues =
2095                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2096         else
2097                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2098
2099         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2100                 pCap->keycache_size =
2101                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2102         else
2103                 pCap->keycache_size = AR_KEYTABLE_SIZE;
2104
2105         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2106
2107         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2108                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2109         else
2110                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2111
2112         if (AR_SREV_9271(ah))
2113                 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2114         else if (AR_SREV_9285_10_OR_LATER(ah))
2115                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2116         else if (AR_SREV_9280_10_OR_LATER(ah))
2117                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2118         else
2119                 pCap->num_gpio_pins = AR_NUM_GPIO;
2120
2121         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2122                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2123                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2124         } else {
2125                 pCap->rts_aggr_limit = (8 * 1024);
2126         }
2127
2128         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2129
2130 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2131         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2132         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2133                 ah->rfkill_gpio =
2134                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2135                 ah->rfkill_polarity =
2136                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2137
2138                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2139         }
2140 #endif
2141         if (AR_SREV_9271(ah))
2142                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2143         else
2144                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2145
2146         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2147                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2148         else
2149                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2150
2151         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2152                 pCap->reg_cap =
2153                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2154                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2155                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
2156                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2157         } else {
2158                 pCap->reg_cap =
2159                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2160                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2161         }
2162
2163         /* Advertise midband for AR5416 with FCC midband set in eeprom */
2164         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2165             AR_SREV_5416(ah))
2166                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2167
2168         pCap->num_antcfg_5ghz =
2169                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2170         pCap->num_antcfg_2ghz =
2171                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2172
2173         if (AR_SREV_9280_10_OR_LATER(ah) &&
2174             ath9k_hw_btcoex_supported(ah)) {
2175                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2176                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2177
2178                 if (AR_SREV_9285(ah)) {
2179                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2180                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2181                 } else {
2182                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2183                 }
2184         } else {
2185                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2186         }
2187
2188         if (AR_SREV_9300_20_OR_LATER(ah)) {
2189                 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC;
2190                 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2191                 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2192                 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2193                 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2194                 pCap->txs_len = sizeof(struct ar9003_txs);
2195         } else {
2196                 pCap->tx_desc_len = sizeof(struct ath_desc);
2197         }
2198
2199         if (AR_SREV_9300_20_OR_LATER(ah))
2200                 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2201
2202         return 0;
2203 }
2204
2205 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2206                             u32 capability, u32 *result)
2207 {
2208         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2209         switch (type) {
2210         case ATH9K_CAP_CIPHER:
2211                 switch (capability) {
2212                 case ATH9K_CIPHER_AES_CCM:
2213                 case ATH9K_CIPHER_AES_OCB:
2214                 case ATH9K_CIPHER_TKIP:
2215                 case ATH9K_CIPHER_WEP:
2216                 case ATH9K_CIPHER_MIC:
2217                 case ATH9K_CIPHER_CLR:
2218                         return true;
2219                 default:
2220                         return false;
2221                 }
2222         case ATH9K_CAP_TKIP_MIC:
2223                 switch (capability) {
2224                 case 0:
2225                         return true;
2226                 case 1:
2227                         return (ah->sta_id1_defaults &
2228                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2229                         false;
2230                 }
2231         case ATH9K_CAP_TKIP_SPLIT:
2232                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
2233                         false : true;
2234         case ATH9K_CAP_MCAST_KEYSRCH:
2235                 switch (capability) {
2236                 case 0:
2237                         return true;
2238                 case 1:
2239                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2240                                 return false;
2241                         } else {
2242                                 return (ah->sta_id1_defaults &
2243                                         AR_STA_ID1_MCAST_KSRCH) ? true :
2244                                         false;
2245                         }
2246                 }
2247                 return false;
2248         case ATH9K_CAP_TXPOW:
2249                 switch (capability) {
2250                 case 0:
2251                         return 0;
2252                 case 1:
2253                         *result = regulatory->power_limit;
2254                         return 0;
2255                 case 2:
2256                         *result = regulatory->max_power_level;
2257                         return 0;
2258                 case 3:
2259                         *result = regulatory->tp_scale;
2260                         return 0;
2261                 }
2262                 return false;
2263         case ATH9K_CAP_DS:
2264                 return (AR_SREV_9280_20_OR_LATER(ah) &&
2265                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2266                         ? false : true;
2267         default:
2268                 return false;
2269         }
2270 }
2271 EXPORT_SYMBOL(ath9k_hw_getcapability);
2272
2273 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2274                             u32 capability, u32 setting, int *status)
2275 {
2276         switch (type) {
2277         case ATH9K_CAP_TKIP_MIC:
2278                 if (setting)
2279                         ah->sta_id1_defaults |=
2280                                 AR_STA_ID1_CRPT_MIC_ENABLE;
2281                 else
2282                         ah->sta_id1_defaults &=
2283                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2284                 return true;
2285         case ATH9K_CAP_MCAST_KEYSRCH:
2286                 if (setting)
2287                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
2288                 else
2289                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
2290                 return true;
2291         default:
2292                 return false;
2293         }
2294 }
2295 EXPORT_SYMBOL(ath9k_hw_setcapability);
2296
2297 /****************************/
2298 /* GPIO / RFKILL / Antennae */
2299 /****************************/
2300
2301 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2302                                          u32 gpio, u32 type)
2303 {
2304         int addr;
2305         u32 gpio_shift, tmp;
2306
2307         if (gpio > 11)
2308                 addr = AR_GPIO_OUTPUT_MUX3;
2309         else if (gpio > 5)
2310                 addr = AR_GPIO_OUTPUT_MUX2;
2311         else
2312                 addr = AR_GPIO_OUTPUT_MUX1;
2313
2314         gpio_shift = (gpio % 6) * 5;
2315
2316         if (AR_SREV_9280_20_OR_LATER(ah)
2317             || (addr != AR_GPIO_OUTPUT_MUX1)) {
2318                 REG_RMW(ah, addr, (type << gpio_shift),
2319                         (0x1f << gpio_shift));
2320         } else {
2321                 tmp = REG_READ(ah, addr);
2322                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2323                 tmp &= ~(0x1f << gpio_shift);
2324                 tmp |= (type << gpio_shift);
2325                 REG_WRITE(ah, addr, tmp);
2326         }
2327 }
2328
2329 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2330 {
2331         u32 gpio_shift;
2332
2333         BUG_ON(gpio >= ah->caps.num_gpio_pins);
2334
2335         gpio_shift = gpio << 1;
2336
2337         REG_RMW(ah,
2338                 AR_GPIO_OE_OUT,
2339                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2340                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2341 }
2342 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2343
2344 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2345 {
2346 #define MS_REG_READ(x, y) \
2347         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2348
2349         if (gpio >= ah->caps.num_gpio_pins)
2350                 return 0xffffffff;
2351
2352         if (AR_SREV_9300_20_OR_LATER(ah))
2353                 return MS_REG_READ(AR9300, gpio) != 0;
2354         else if (AR_SREV_9271(ah))
2355                 return MS_REG_READ(AR9271, gpio) != 0;
2356         else if (AR_SREV_9287_10_OR_LATER(ah))
2357                 return MS_REG_READ(AR9287, gpio) != 0;
2358         else if (AR_SREV_9285_10_OR_LATER(ah))
2359                 return MS_REG_READ(AR9285, gpio) != 0;
2360         else if (AR_SREV_9280_10_OR_LATER(ah))
2361                 return MS_REG_READ(AR928X, gpio) != 0;
2362         else
2363                 return MS_REG_READ(AR, gpio) != 0;
2364 }
2365 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2366
2367 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2368                          u32 ah_signal_type)
2369 {
2370         u32 gpio_shift;
2371
2372         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2373
2374         gpio_shift = 2 * gpio;
2375
2376         REG_RMW(ah,
2377                 AR_GPIO_OE_OUT,
2378                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2379                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2380 }
2381 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2382
2383 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2384 {
2385         if (AR_SREV_9271(ah))
2386                 val = ~val;
2387
2388         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2389                 AR_GPIO_BIT(gpio));
2390 }
2391 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2392
2393 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2394 {
2395         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2396 }
2397 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2398
2399 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2400 {
2401         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2402 }
2403 EXPORT_SYMBOL(ath9k_hw_setantenna);
2404
2405 /*********************/
2406 /* General Operation */
2407 /*********************/
2408
2409 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2410 {
2411         u32 bits = REG_READ(ah, AR_RX_FILTER);
2412         u32 phybits = REG_READ(ah, AR_PHY_ERR);
2413
2414         if (phybits & AR_PHY_ERR_RADAR)
2415                 bits |= ATH9K_RX_FILTER_PHYRADAR;
2416         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2417                 bits |= ATH9K_RX_FILTER_PHYERR;
2418
2419         return bits;
2420 }
2421 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2422
2423 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2424 {
2425         u32 phybits;
2426
2427         ENABLE_REGWRITE_BUFFER(ah);
2428
2429         REG_WRITE(ah, AR_RX_FILTER, bits);
2430
2431         phybits = 0;
2432         if (bits & ATH9K_RX_FILTER_PHYRADAR)
2433                 phybits |= AR_PHY_ERR_RADAR;
2434         if (bits & ATH9K_RX_FILTER_PHYERR)
2435                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2436         REG_WRITE(ah, AR_PHY_ERR, phybits);
2437
2438         if (phybits)
2439                 REG_WRITE(ah, AR_RXCFG,
2440                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2441         else
2442                 REG_WRITE(ah, AR_RXCFG,
2443                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2444
2445         REGWRITE_BUFFER_FLUSH(ah);
2446         DISABLE_REGWRITE_BUFFER(ah);
2447 }
2448 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2449
2450 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2451 {
2452         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2453                 return false;
2454
2455         ath9k_hw_init_pll(ah, NULL);
2456         return true;
2457 }
2458 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2459
2460 bool ath9k_hw_disable(struct ath_hw *ah)
2461 {
2462         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2463                 return false;
2464
2465         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2466                 return false;
2467
2468         ath9k_hw_init_pll(ah, NULL);
2469         return true;
2470 }
2471 EXPORT_SYMBOL(ath9k_hw_disable);
2472
2473 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2474 {
2475         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2476         struct ath9k_channel *chan = ah->curchan;
2477         struct ieee80211_channel *channel = chan->chan;
2478
2479         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2480
2481         ah->eep_ops->set_txpower(ah, chan,
2482                                  ath9k_regd_get_ctl(regulatory, chan),
2483                                  channel->max_antenna_gain * 2,
2484                                  channel->max_power * 2,
2485                                  min((u32) MAX_RATE_POWER,
2486                                  (u32) regulatory->power_limit));
2487 }
2488 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2489
2490 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
2491 {
2492         memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
2493 }
2494 EXPORT_SYMBOL(ath9k_hw_setmac);
2495
2496 void ath9k_hw_setopmode(struct ath_hw *ah)
2497 {
2498         ath9k_hw_set_operating_mode(ah, ah->opmode);
2499 }
2500 EXPORT_SYMBOL(ath9k_hw_setopmode);
2501
2502 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2503 {
2504         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2505         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2506 }
2507 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2508
2509 void ath9k_hw_write_associd(struct ath_hw *ah)
2510 {
2511         struct ath_common *common = ath9k_hw_common(ah);
2512
2513         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2514         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2515                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2516 }
2517 EXPORT_SYMBOL(ath9k_hw_write_associd);
2518
2519 #define ATH9K_MAX_TSF_READ 10
2520
2521 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2522 {
2523         u32 tsf_lower, tsf_upper1, tsf_upper2;
2524         int i;
2525
2526         tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2527         for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2528                 tsf_lower = REG_READ(ah, AR_TSF_L32);
2529                 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2530                 if (tsf_upper2 == tsf_upper1)
2531                         break;
2532                 tsf_upper1 = tsf_upper2;
2533         }
2534
2535         WARN_ON( i == ATH9K_MAX_TSF_READ );
2536
2537         return (((u64)tsf_upper1 << 32) | tsf_lower);
2538 }
2539 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2540
2541 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2542 {
2543         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2544         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2545 }
2546 EXPORT_SYMBOL(ath9k_hw_settsf64);
2547
2548 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2549 {
2550         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2551                            AH_TSF_WRITE_TIMEOUT))
2552                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2553                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2554
2555         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2556 }
2557 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2558
2559 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2560 {
2561         if (setting)
2562                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2563         else
2564                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2565 }
2566 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2567
2568 /*
2569  *  Extend 15-bit time stamp from rx descriptor to
2570  *  a full 64-bit TSF using the current h/w TSF.
2571 */
2572 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2573 {
2574         u64 tsf;
2575
2576         tsf = ath9k_hw_gettsf64(ah);
2577         if ((tsf & 0x7fff) < rstamp)
2578                 tsf -= 0x8000;
2579         return (tsf & ~0x7fff) | rstamp;
2580 }
2581 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2582
2583 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2584 {
2585         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2586         u32 macmode;
2587
2588         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2589                 macmode = AR_2040_JOINED_RX_CLEAR;
2590         else
2591                 macmode = 0;
2592
2593         REG_WRITE(ah, AR_2040_MODE, macmode);
2594 }
2595
2596 /* HW Generic timers configuration */
2597
2598 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2599 {
2600         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2601         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2602         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2603         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2604         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2605         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2606         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2607         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2608         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2609         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2610                                 AR_NDP2_TIMER_MODE, 0x0002},
2611         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2612                                 AR_NDP2_TIMER_MODE, 0x0004},
2613         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2614                                 AR_NDP2_TIMER_MODE, 0x0008},
2615         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2616                                 AR_NDP2_TIMER_MODE, 0x0010},
2617         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2618                                 AR_NDP2_TIMER_MODE, 0x0020},
2619         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2620                                 AR_NDP2_TIMER_MODE, 0x0040},
2621         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2622                                 AR_NDP2_TIMER_MODE, 0x0080}
2623 };
2624
2625 /* HW generic timer primitives */
2626
2627 /* compute and clear index of rightmost 1 */
2628 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2629 {
2630         u32 b;
2631
2632         b = *mask;
2633         b &= (0-b);
2634         *mask &= ~b;
2635         b *= debruijn32;
2636         b >>= 27;
2637
2638         return timer_table->gen_timer_index[b];
2639 }
2640
2641 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2642 {
2643         return REG_READ(ah, AR_TSF_L32);
2644 }
2645 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2646
2647 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2648                                           void (*trigger)(void *),
2649                                           void (*overflow)(void *),
2650                                           void *arg,
2651                                           u8 timer_index)
2652 {
2653         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2654         struct ath_gen_timer *timer;
2655
2656         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2657
2658         if (timer == NULL) {
2659                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2660                           "Failed to allocate memory"
2661                           "for hw timer[%d]\n", timer_index);
2662                 return NULL;
2663         }
2664
2665         /* allocate a hardware generic timer slot */
2666         timer_table->timers[timer_index] = timer;
2667         timer->index = timer_index;
2668         timer->trigger = trigger;
2669         timer->overflow = overflow;
2670         timer->arg = arg;
2671
2672         return timer;
2673 }
2674 EXPORT_SYMBOL(ath_gen_timer_alloc);
2675
2676 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2677                               struct ath_gen_timer *timer,
2678                               u32 timer_next,
2679                               u32 timer_period)
2680 {
2681         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2682         u32 tsf;
2683
2684         BUG_ON(!timer_period);
2685
2686         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2687
2688         tsf = ath9k_hw_gettsf32(ah);
2689
2690         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2691                   "curent tsf %x period %x"
2692                   "timer_next %x\n", tsf, timer_period, timer_next);
2693
2694         /*
2695          * Pull timer_next forward if the current TSF already passed it
2696          * because of software latency
2697          */
2698         if (timer_next < tsf)
2699                 timer_next = tsf + timer_period;
2700
2701         /*
2702          * Program generic timer registers
2703          */
2704         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2705                  timer_next);
2706         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2707                   timer_period);
2708         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2709                     gen_tmr_configuration[timer->index].mode_mask);
2710
2711         /* Enable both trigger and thresh interrupt masks */
2712         REG_SET_BIT(ah, AR_IMR_S5,
2713                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2714                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2715 }
2716 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2717
2718 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2719 {
2720         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2721
2722         if ((timer->index < AR_FIRST_NDP_TIMER) ||
2723                 (timer->index >= ATH_MAX_GEN_TIMER)) {
2724                 return;
2725         }
2726
2727         /* Clear generic timer enable bits. */
2728         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2729                         gen_tmr_configuration[timer->index].mode_mask);
2730
2731         /* Disable both trigger and thresh interrupt masks */
2732         REG_CLR_BIT(ah, AR_IMR_S5,
2733                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2734                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2735
2736         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2737 }
2738 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2739
2740 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2741 {
2742         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2743
2744         /* free the hardware generic timer slot */
2745         timer_table->timers[timer->index] = NULL;
2746         kfree(timer);
2747 }
2748 EXPORT_SYMBOL(ath_gen_timer_free);
2749
2750 /*
2751  * Generic Timer Interrupts handling
2752  */
2753 void ath_gen_timer_isr(struct ath_hw *ah)
2754 {
2755         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2756         struct ath_gen_timer *timer;
2757         struct ath_common *common = ath9k_hw_common(ah);
2758         u32 trigger_mask, thresh_mask, index;
2759
2760         /* get hardware generic timer interrupt status */
2761         trigger_mask = ah->intr_gen_timer_trigger;
2762         thresh_mask = ah->intr_gen_timer_thresh;
2763         trigger_mask &= timer_table->timer_mask.val;
2764         thresh_mask &= timer_table->timer_mask.val;
2765
2766         trigger_mask &= ~thresh_mask;
2767
2768         while (thresh_mask) {
2769                 index = rightmost_index(timer_table, &thresh_mask);
2770                 timer = timer_table->timers[index];
2771                 BUG_ON(!timer);
2772                 ath_print(common, ATH_DBG_HWTIMER,
2773                           "TSF overflow for Gen timer %d\n", index);
2774                 timer->overflow(timer->arg);
2775         }
2776
2777         while (trigger_mask) {
2778                 index = rightmost_index(timer_table, &trigger_mask);
2779                 timer = timer_table->timers[index];
2780                 BUG_ON(!timer);
2781                 ath_print(common, ATH_DBG_HWTIMER,
2782                           "Gen timer[%d] trigger\n", index);
2783                 timer->trigger(timer->arg);
2784         }
2785 }
2786 EXPORT_SYMBOL(ath_gen_timer_isr);
2787
2788 /********/
2789 /* HTC  */
2790 /********/
2791
2792 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2793 {
2794         ah->htc_reset_init = true;
2795 }
2796 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2797
2798 static struct {
2799         u32 version;
2800         const char * name;
2801 } ath_mac_bb_names[] = {
2802         /* Devices with external radios */
2803         { AR_SREV_VERSION_5416_PCI,     "5416" },
2804         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2805         { AR_SREV_VERSION_9100,         "9100" },
2806         { AR_SREV_VERSION_9160,         "9160" },
2807         /* Single-chip solutions */
2808         { AR_SREV_VERSION_9280,         "9280" },
2809         { AR_SREV_VERSION_9285,         "9285" },
2810         { AR_SREV_VERSION_9287,         "9287" },
2811         { AR_SREV_VERSION_9271,         "9271" },
2812         { AR_SREV_VERSION_9300,         "9300" },
2813 };
2814
2815 /* For devices with external radios */
2816 static struct {
2817         u16 version;
2818         const char * name;
2819 } ath_rf_names[] = {
2820         { 0,                            "5133" },
2821         { AR_RAD5133_SREV_MAJOR,        "5133" },
2822         { AR_RAD5122_SREV_MAJOR,        "5122" },
2823         { AR_RAD2133_SREV_MAJOR,        "2133" },
2824         { AR_RAD2122_SREV_MAJOR,        "2122" }
2825 };
2826
2827 /*
2828  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2829  */
2830 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2831 {
2832         int i;
2833
2834         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2835                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2836                         return ath_mac_bb_names[i].name;
2837                 }
2838         }
2839
2840         return "????";
2841 }
2842
2843 /*
2844  * Return the RF name. "????" is returned if the RF is unknown.
2845  * Used for devices with external radios.
2846  */
2847 static const char *ath9k_hw_rf_name(u16 rf_version)
2848 {
2849         int i;
2850
2851         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2852                 if (ath_rf_names[i].version == rf_version) {
2853                         return ath_rf_names[i].name;
2854                 }
2855         }
2856
2857         return "????";
2858 }
2859
2860 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2861 {
2862         int used;
2863
2864         /* chipsets >= AR9280 are single-chip */
2865         if (AR_SREV_9280_10_OR_LATER(ah)) {
2866                 used = snprintf(hw_name, len,
2867                                "Atheros AR%s Rev:%x",
2868                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2869                                ah->hw_version.macRev);
2870         }
2871         else {
2872                 used = snprintf(hw_name, len,
2873                                "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2874                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2875                                ah->hw_version.macRev,
2876                                ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2877                                                 AR_RADIO_SREV_MAJOR)),
2878                                ah->hw_version.phyRev);
2879         }
2880
2881         hw_name[used] = '\0';
2882 }
2883 EXPORT_SYMBOL(ath9k_hw_name);