2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/ath9k_platform.h>
22 #include <linux/module.h>
26 static char *dev_info = "ath9k";
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
33 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
34 module_param_named(debug, ath9k_debug, uint, 0);
35 MODULE_PARM_DESC(debug, "Debugging mask");
37 int ath9k_modparam_nohwcrypt;
38 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
39 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
42 module_param_named(blink, led_blink, int, 0444);
43 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
45 static int ath9k_btcoex_enable;
46 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
47 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
49 static int ath9k_enable_diversity;
50 module_param_named(enable_diversity, ath9k_enable_diversity, int, 0444);
51 MODULE_PARM_DESC(enable_diversity, "Enable Antenna diversity for AR9565");
53 bool is_ath9k_unloaded;
54 /* We use the hw_value as an index into our private channel structure */
56 #define CHAN2G(_freq, _idx) { \
57 .band = IEEE80211_BAND_2GHZ, \
58 .center_freq = (_freq), \
63 #define CHAN5G(_freq, _idx) { \
64 .band = IEEE80211_BAND_5GHZ, \
65 .center_freq = (_freq), \
70 /* Some 2 GHz radios are actually tunable on 2312-2732
71 * on 5 MHz steps, we support the channels which we know
72 * we have calibration data for all cards though to make
74 static const struct ieee80211_channel ath9k_2ghz_chantable[] = {
75 CHAN2G(2412, 0), /* Channel 1 */
76 CHAN2G(2417, 1), /* Channel 2 */
77 CHAN2G(2422, 2), /* Channel 3 */
78 CHAN2G(2427, 3), /* Channel 4 */
79 CHAN2G(2432, 4), /* Channel 5 */
80 CHAN2G(2437, 5), /* Channel 6 */
81 CHAN2G(2442, 6), /* Channel 7 */
82 CHAN2G(2447, 7), /* Channel 8 */
83 CHAN2G(2452, 8), /* Channel 9 */
84 CHAN2G(2457, 9), /* Channel 10 */
85 CHAN2G(2462, 10), /* Channel 11 */
86 CHAN2G(2467, 11), /* Channel 12 */
87 CHAN2G(2472, 12), /* Channel 13 */
88 CHAN2G(2484, 13), /* Channel 14 */
91 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
92 * on 5 MHz steps, we support the channels which we know
93 * we have calibration data for all cards though to make
95 static const struct ieee80211_channel ath9k_5ghz_chantable[] = {
96 /* _We_ call this UNII 1 */
97 CHAN5G(5180, 14), /* Channel 36 */
98 CHAN5G(5200, 15), /* Channel 40 */
99 CHAN5G(5220, 16), /* Channel 44 */
100 CHAN5G(5240, 17), /* Channel 48 */
101 /* _We_ call this UNII 2 */
102 CHAN5G(5260, 18), /* Channel 52 */
103 CHAN5G(5280, 19), /* Channel 56 */
104 CHAN5G(5300, 20), /* Channel 60 */
105 CHAN5G(5320, 21), /* Channel 64 */
106 /* _We_ call this "Middle band" */
107 CHAN5G(5500, 22), /* Channel 100 */
108 CHAN5G(5520, 23), /* Channel 104 */
109 CHAN5G(5540, 24), /* Channel 108 */
110 CHAN5G(5560, 25), /* Channel 112 */
111 CHAN5G(5580, 26), /* Channel 116 */
112 CHAN5G(5600, 27), /* Channel 120 */
113 CHAN5G(5620, 28), /* Channel 124 */
114 CHAN5G(5640, 29), /* Channel 128 */
115 CHAN5G(5660, 30), /* Channel 132 */
116 CHAN5G(5680, 31), /* Channel 136 */
117 CHAN5G(5700, 32), /* Channel 140 */
118 /* _We_ call this UNII 3 */
119 CHAN5G(5745, 33), /* Channel 149 */
120 CHAN5G(5765, 34), /* Channel 153 */
121 CHAN5G(5785, 35), /* Channel 157 */
122 CHAN5G(5805, 36), /* Channel 161 */
123 CHAN5G(5825, 37), /* Channel 165 */
126 /* Atheros hardware rate code addition for short premble */
127 #define SHPCHECK(__hw_rate, __flags) \
128 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
130 #define RATE(_bitrate, _hw_rate, _flags) { \
131 .bitrate = (_bitrate), \
133 .hw_value = (_hw_rate), \
134 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
137 static struct ieee80211_rate ath9k_legacy_rates[] = {
139 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
140 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
141 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
152 #ifdef CONFIG_MAC80211_LEDS
153 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
154 { .throughput = 0 * 1024, .blink_time = 334 },
155 { .throughput = 1 * 1024, .blink_time = 260 },
156 { .throughput = 5 * 1024, .blink_time = 220 },
157 { .throughput = 10 * 1024, .blink_time = 190 },
158 { .throughput = 20 * 1024, .blink_time = 170 },
159 { .throughput = 50 * 1024, .blink_time = 150 },
160 { .throughput = 70 * 1024, .blink_time = 130 },
161 { .throughput = 100 * 1024, .blink_time = 110 },
162 { .throughput = 200 * 1024, .blink_time = 80 },
163 { .throughput = 300 * 1024, .blink_time = 50 },
167 static void ath9k_deinit_softc(struct ath_softc *sc);
170 * Read and write, they both share the same lock. We do this to serialize
171 * reads and writes on Atheros 802.11n PCI devices only. This is required
172 * as the FIFO on these devices can only accept sanely 2 requests.
175 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
177 struct ath_hw *ah = (struct ath_hw *) hw_priv;
178 struct ath_common *common = ath9k_hw_common(ah);
179 struct ath_softc *sc = (struct ath_softc *) common->priv;
181 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
183 spin_lock_irqsave(&sc->sc_serial_rw, flags);
184 iowrite32(val, sc->mem + reg_offset);
185 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
187 iowrite32(val, sc->mem + reg_offset);
190 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
192 struct ath_hw *ah = (struct ath_hw *) hw_priv;
193 struct ath_common *common = ath9k_hw_common(ah);
194 struct ath_softc *sc = (struct ath_softc *) common->priv;
197 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
199 spin_lock_irqsave(&sc->sc_serial_rw, flags);
200 val = ioread32(sc->mem + reg_offset);
201 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
203 val = ioread32(sc->mem + reg_offset);
207 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
212 val = ioread32(sc->mem + reg_offset);
215 iowrite32(val, sc->mem + reg_offset);
220 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
222 struct ath_hw *ah = (struct ath_hw *) hw_priv;
223 struct ath_common *common = ath9k_hw_common(ah);
224 struct ath_softc *sc = (struct ath_softc *) common->priv;
225 unsigned long uninitialized_var(flags);
228 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
229 spin_lock_irqsave(&sc->sc_serial_rw, flags);
230 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
231 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
233 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
238 /**************************/
240 /**************************/
242 static void setup_ht_cap(struct ath_softc *sc,
243 struct ieee80211_sta_ht_cap *ht_info)
245 struct ath_hw *ah = sc->sc_ah;
246 struct ath_common *common = ath9k_hw_common(ah);
247 u8 tx_streams, rx_streams;
250 ht_info->ht_supported = true;
251 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
252 IEEE80211_HT_CAP_SM_PS |
253 IEEE80211_HT_CAP_SGI_40 |
254 IEEE80211_HT_CAP_DSSSCCK40;
256 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
257 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
259 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
260 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
262 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
263 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
265 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah))
267 else if (AR_SREV_9462(ah))
269 else if (AR_SREV_9300_20_OR_LATER(ah))
274 if (AR_SREV_9280_20_OR_LATER(ah)) {
275 if (max_streams >= 2)
276 ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
277 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
280 /* set up supported mcs set */
281 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
282 tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams);
283 rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams);
285 ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n",
286 tx_streams, rx_streams);
288 if (tx_streams != rx_streams) {
289 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
290 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
291 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
294 for (i = 0; i < rx_streams; i++)
295 ht_info->mcs.rx_mask[i] = 0xff;
297 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
300 static int ath9k_reg_notifier(struct wiphy *wiphy,
301 struct regulatory_request *request)
303 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
304 struct ath_softc *sc = hw->priv;
305 struct ath_hw *ah = sc->sc_ah;
306 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
309 ret = ath_reg_notifier_apply(wiphy, request, reg);
313 sc->config.txpowlimit = 2 * ah->curchan->chan->max_power;
315 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
316 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
317 ath9k_ps_restore(sc);
324 * This function will allocate both the DMA descriptor structure, and the
325 * buffers it contains. These are used to contain the descriptors used
328 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
329 struct list_head *head, const char *name,
330 int nbuf, int ndesc, bool is_tx)
332 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
335 int i, bsize, error, desc_len;
337 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",
340 INIT_LIST_HEAD(head);
343 desc_len = sc->sc_ah->caps.tx_desc_len;
345 desc_len = sizeof(struct ath_desc);
347 /* ath_desc must be a multiple of DWORDs */
348 if ((desc_len % 4) != 0) {
349 ath_err(common, "ath_desc not DWORD aligned\n");
350 BUG_ON((desc_len % 4) != 0);
355 dd->dd_desc_len = desc_len * nbuf * ndesc;
358 * Need additional DMA memory because we can't use
359 * descriptors that cross the 4K page boundary. Assume
360 * one skipped descriptor per 4K page.
362 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
364 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
367 while (ndesc_skipped) {
368 dma_len = ndesc_skipped * desc_len;
369 dd->dd_desc_len += dma_len;
371 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
375 /* allocate descriptors */
376 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
377 &dd->dd_desc_paddr, GFP_KERNEL);
378 if (dd->dd_desc == NULL) {
382 ds = (u8 *) dd->dd_desc;
383 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
384 name, ds, (u32) dd->dd_desc_len,
385 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
387 /* allocate buffers */
388 bsize = sizeof(struct ath_buf) * nbuf;
389 bf = kzalloc(bsize, GFP_KERNEL);
396 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
398 bf->bf_daddr = DS2PHYS(dd, ds);
400 if (!(sc->sc_ah->caps.hw_caps &
401 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
403 * Skip descriptor addresses which can cause 4KB
404 * boundary crossing (addr + length) with a 32 dword
407 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
408 BUG_ON((caddr_t) bf->bf_desc >=
409 ((caddr_t) dd->dd_desc +
412 ds += (desc_len * ndesc);
414 bf->bf_daddr = DS2PHYS(dd, ds);
417 list_add_tail(&bf->list, head);
421 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
424 memset(dd, 0, sizeof(*dd));
428 static int ath9k_init_queues(struct ath_softc *sc)
432 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
433 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
435 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
438 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
439 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
440 sc->tx.txq_map[i]->mac80211_qnum = i;
441 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH;
446 static int ath9k_init_channels_rates(struct ath_softc *sc)
450 BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) +
451 ARRAY_SIZE(ath9k_5ghz_chantable) !=
454 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
455 channels = kmemdup(ath9k_2ghz_chantable,
456 sizeof(ath9k_2ghz_chantable), GFP_KERNEL);
460 sc->sbands[IEEE80211_BAND_2GHZ].channels = channels;
461 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
462 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
463 ARRAY_SIZE(ath9k_2ghz_chantable);
464 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
465 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
466 ARRAY_SIZE(ath9k_legacy_rates);
469 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
470 channels = kmemdup(ath9k_5ghz_chantable,
471 sizeof(ath9k_5ghz_chantable), GFP_KERNEL);
473 if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
474 kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
478 sc->sbands[IEEE80211_BAND_5GHZ].channels = channels;
479 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
480 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
481 ARRAY_SIZE(ath9k_5ghz_chantable);
482 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
483 ath9k_legacy_rates + 4;
484 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
485 ARRAY_SIZE(ath9k_legacy_rates) - 4;
490 static void ath9k_init_misc(struct ath_softc *sc)
492 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
495 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
497 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
498 sc->config.txpowlimit = ATH_TXPOWER_MAX;
499 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
500 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
502 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
503 sc->beacon.bslot[i] = NULL;
505 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
506 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
509 static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
510 const struct ath_bus_ops *bus_ops)
512 struct ath9k_platform_data *pdata = sc->dev->platform_data;
513 struct ath_hw *ah = NULL;
514 struct ath_common *common;
518 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
523 ah->hw_version.devid = devid;
524 ah->reg_ops.read = ath9k_ioread32;
525 ah->reg_ops.write = ath9k_iowrite32;
526 ah->reg_ops.rmw = ath9k_reg_rmw;
527 atomic_set(&ah->intr_ref_cnt, -1);
530 sc->dfs_detector = dfs_pattern_detector_init(NL80211_DFS_UNSET);
533 ah->ah_flags |= AH_USE_EEPROM;
534 sc->sc_ah->led_pin = -1;
536 sc->sc_ah->gpio_mask = pdata->gpio_mask;
537 sc->sc_ah->gpio_val = pdata->gpio_val;
538 sc->sc_ah->led_pin = pdata->led_pin;
539 ah->is_clk_25mhz = pdata->is_clk_25mhz;
540 ah->get_mac_revision = pdata->get_mac_revision;
541 ah->external_reset = pdata->external_reset;
544 common = ath9k_hw_common(ah);
545 common->ops = &ah->reg_ops;
546 common->bus_ops = bus_ops;
550 common->debug_mask = ath9k_debug;
551 common->btcoex_enabled = ath9k_btcoex_enable == 1;
552 common->disable_ani = false;
555 * Enable Antenna diversity only when BTCOEX is disabled
556 * and the user manually requests the feature.
558 if (!common->btcoex_enabled && ath9k_enable_diversity)
559 common->antenna_diversity = 1;
561 spin_lock_init(&common->cc_lock);
563 spin_lock_init(&sc->sc_serial_rw);
564 spin_lock_init(&sc->sc_pm_lock);
565 mutex_init(&sc->mutex);
566 #ifdef CONFIG_ATH9K_DEBUGFS
567 spin_lock_init(&sc->nodes_lock);
568 INIT_LIST_HEAD(&sc->nodes);
570 #ifdef CONFIG_ATH9K_MAC_DEBUG
571 spin_lock_init(&sc->debug.samp_lock);
573 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
574 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
577 INIT_WORK(&sc->hw_reset_work, ath_reset_work);
578 INIT_WORK(&sc->hw_check_work, ath_hw_check);
579 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
580 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
581 setup_timer(&sc->rx_poll_timer, ath_rx_poll, (unsigned long)sc);
584 * Cache line size is used to size and align various
585 * structures used to communicate with the hardware.
587 ath_read_cachesize(common, &csz);
588 common->cachelsz = csz << 2; /* convert to bytes */
590 /* Initializes the hardware for all supported chipsets */
591 ret = ath9k_hw_init(ah);
595 if (pdata && pdata->macaddr)
596 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN);
598 ret = ath9k_init_queues(sc);
602 ret = ath9k_init_btcoex(sc);
606 ret = ath9k_init_channels_rates(sc);
610 ath9k_cmn_init_crypto(sc->sc_ah);
612 ath_fill_led_pin(sc);
614 if (common->bus_ops->aspm_init)
615 common->bus_ops->aspm_init(common);
620 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
621 if (ATH_TXQ_SETUP(sc, i))
622 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
633 static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
635 struct ieee80211_supported_band *sband;
636 struct ieee80211_channel *chan;
637 struct ath_hw *ah = sc->sc_ah;
640 sband = &sc->sbands[band];
641 for (i = 0; i < sband->n_channels; i++) {
642 chan = &sband->channels[i];
643 ah->curchan = &ah->channels[chan->hw_value];
644 ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20);
645 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
649 static void ath9k_init_txpower_limits(struct ath_softc *sc)
651 struct ath_hw *ah = sc->sc_ah;
652 struct ath9k_channel *curchan = ah->curchan;
654 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
655 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
656 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
657 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
659 ah->curchan = curchan;
662 void ath9k_reload_chainmask_settings(struct ath_softc *sc)
664 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT))
667 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
668 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
669 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
670 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
673 static const struct ieee80211_iface_limit if_limits[] = {
674 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) |
675 BIT(NL80211_IFTYPE_P2P_CLIENT) |
676 BIT(NL80211_IFTYPE_WDS) },
678 #ifdef CONFIG_MAC80211_MESH
679 BIT(NL80211_IFTYPE_MESH_POINT) |
681 BIT(NL80211_IFTYPE_AP) |
682 BIT(NL80211_IFTYPE_P2P_GO) },
685 static const struct ieee80211_iface_combination if_comb = {
687 .n_limits = ARRAY_SIZE(if_limits),
688 .max_interfaces = 2048,
689 .num_different_channels = 1,
690 .beacon_int_infra_match = true,
693 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
695 struct ath_hw *ah = sc->sc_ah;
696 struct ath_common *common = ath9k_hw_common(ah);
698 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
699 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
700 IEEE80211_HW_SIGNAL_DBM |
701 IEEE80211_HW_SUPPORTS_PS |
702 IEEE80211_HW_PS_NULLFUNC_STACK |
703 IEEE80211_HW_SPECTRUM_MGMT |
704 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
706 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
707 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
709 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
710 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
712 hw->wiphy->interface_modes =
713 BIT(NL80211_IFTYPE_P2P_GO) |
714 BIT(NL80211_IFTYPE_P2P_CLIENT) |
715 BIT(NL80211_IFTYPE_AP) |
716 BIT(NL80211_IFTYPE_WDS) |
717 BIT(NL80211_IFTYPE_STATION) |
718 BIT(NL80211_IFTYPE_ADHOC) |
719 BIT(NL80211_IFTYPE_MESH_POINT);
721 hw->wiphy->iface_combinations = &if_comb;
722 hw->wiphy->n_iface_combinations = 1;
724 if (AR_SREV_5416(sc->sc_ah))
725 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
727 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
728 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
729 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
731 #ifdef CONFIG_PM_SLEEP
733 if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
734 device_can_wakeup(sc->dev)) {
736 hw->wiphy->wowlan.flags = WIPHY_WOWLAN_MAGIC_PKT |
737 WIPHY_WOWLAN_DISCONNECT;
738 hw->wiphy->wowlan.n_patterns = MAX_NUM_USER_PATTERN;
739 hw->wiphy->wowlan.pattern_min_len = 1;
740 hw->wiphy->wowlan.pattern_max_len = MAX_PATTERN_SIZE;
744 atomic_set(&sc->wow_sleep_proc_intr, -1);
745 atomic_set(&sc->wow_got_bmiss_intr, -1);
751 hw->channel_change_time = 5000;
752 hw->max_listen_interval = 1;
753 hw->max_rate_tries = 10;
754 hw->sta_data_size = sizeof(struct ath_node);
755 hw->vif_data_size = sizeof(struct ath_vif);
757 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;
758 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;
760 /* single chain devices with rx diversity */
761 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
762 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);
764 sc->ant_rx = hw->wiphy->available_antennas_rx;
765 sc->ant_tx = hw->wiphy->available_antennas_tx;
767 #ifdef CONFIG_ATH9K_RATE_CONTROL
768 hw->rate_control_algorithm = "ath9k_rate_control";
771 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
772 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
773 &sc->sbands[IEEE80211_BAND_2GHZ];
774 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
775 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
776 &sc->sbands[IEEE80211_BAND_5GHZ];
778 ath9k_reload_chainmask_settings(sc);
780 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
783 int ath9k_init_device(u16 devid, struct ath_softc *sc,
784 const struct ath_bus_ops *bus_ops)
786 struct ieee80211_hw *hw = sc->hw;
787 struct ath_common *common;
790 struct ath_regulatory *reg;
792 /* Bring up device */
793 error = ath9k_init_softc(devid, sc, bus_ops);
798 common = ath9k_hw_common(ah);
799 ath9k_set_hw_capab(sc, hw);
801 /* Initialize regulatory */
802 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
807 reg = &common->regulatory;
810 error = ath_tx_init(sc, ATH_TXBUF);
815 error = ath_rx_init(sc, ATH_RXBUF);
819 ath9k_init_txpower_limits(sc);
821 #ifdef CONFIG_MAC80211_LEDS
822 /* must be initialized before ieee80211_register_hw */
823 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
824 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
825 ARRAY_SIZE(ath9k_tpt_blink));
828 /* Register with mac80211 */
829 error = ieee80211_register_hw(hw);
833 error = ath9k_init_debug(ah);
835 ath_err(common, "Unable to create debugfs files\n");
839 /* Handle world regulatory */
840 if (!ath_is_world_regd(reg)) {
841 error = regulatory_hint(hw->wiphy, reg->alpha2);
847 ath_start_rfkill_poll(sc);
852 ieee80211_unregister_hw(hw);
860 ath9k_deinit_softc(sc);
865 /*****************************/
866 /* De-Initialization */
867 /*****************************/
869 static void ath9k_deinit_softc(struct ath_softc *sc)
873 if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
874 kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
876 if (sc->sbands[IEEE80211_BAND_5GHZ].channels)
877 kfree(sc->sbands[IEEE80211_BAND_5GHZ].channels);
879 ath9k_deinit_btcoex(sc);
881 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
882 if (ATH_TXQ_SETUP(sc, i))
883 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
885 ath9k_hw_deinit(sc->sc_ah);
886 if (sc->dfs_detector != NULL)
887 sc->dfs_detector->exit(sc->dfs_detector);
893 void ath9k_deinit_device(struct ath_softc *sc)
895 struct ieee80211_hw *hw = sc->hw;
899 wiphy_rfkill_stop_polling(sc->hw->wiphy);
902 ath9k_ps_restore(sc);
904 ieee80211_unregister_hw(hw);
907 ath9k_deinit_softc(sc);
910 void ath_descdma_cleanup(struct ath_softc *sc,
911 struct ath_descdma *dd,
912 struct list_head *head)
914 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
917 INIT_LIST_HEAD(head);
918 kfree(dd->dd_bufptr);
919 memset(dd, 0, sizeof(*dd));
922 /************************/
924 /************************/
926 static int __init ath9k_init(void)
930 /* Register rate control algorithm */
931 error = ath_rate_control_register();
933 pr_err("Unable to register rate control algorithm: %d\n",
938 error = ath_pci_init();
940 pr_err("No PCI devices found, driver not installed\n");
942 goto err_rate_unregister;
945 error = ath_ahb_init();
957 ath_rate_control_unregister();
961 module_init(ath9k_init);
963 static void __exit ath9k_exit(void)
965 is_ath9k_unloaded = true;
968 ath_rate_control_unregister();
969 pr_info("%s: Driver unloaded\n", dev_info);
971 module_exit(ath9k_exit);