drivers/net/wireless/ath/wil6210/interrupt.c

   1 /*
   2  * Copyright (c) 2012 Qualcomm Atheros, Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/interrupt.h>
  18
  19 #include "wil6210.h"
  20 #include "trace.h"
  21
  22 /**
  23  * Theory of operation:
  24  *
  25  * There is ISR pseudo-cause register,
  26  * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE
  27  * Its bits represents OR'ed bits from 3 real ISR registers:
  28  * TX, RX, and MISC.
  29  *
  30  * Registers may be configured to either "write 1 to clear" or
  31  * "clear on read" mode
  32  *
  33  * When handling interrupt, one have to mask/unmask interrupts for the
  34  * real ISR registers, or hardware may malfunction.
  35  *
  36  */
  37
  38 #define WIL6210_IRQ_DISABLE     (0xFFFFFFFFUL)
  39 #define WIL6210_IMC_RX          BIT_DMA_EP_RX_ICR_RX_DONE
  40 #define WIL6210_IMC_TX          (BIT_DMA_EP_TX_ICR_TX_DONE | \
  41                                 BIT_DMA_EP_TX_ICR_TX_DONE_N(0))
  42 #define WIL6210_IMC_MISC        (ISR_MISC_FW_READY | \
  43                                  ISR_MISC_MBOX_EVT | \
  44                                  ISR_MISC_FW_ERROR)
  45
  46 #define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \
  47                                         BIT_DMA_PSEUDO_CAUSE_TX | \
  48                                         BIT_DMA_PSEUDO_CAUSE_MISC))
  49
  50 #if defined(CONFIG_WIL6210_ISR_COR)
  51 /* configure to Clear-On-Read mode */
  52 #define WIL_ICR_ICC_VALUE       (0xFFFFFFFFUL)
  53
  54 static inline void wil_icr_clear(u32 x, void __iomem *addr)
  55 {
  56 }
  57 #else /* defined(CONFIG_WIL6210_ISR_COR) */
  58 /* configure to Write-1-to-Clear mode */
  59 #define WIL_ICR_ICC_VALUE       (0UL)
  60
  61 static inline void wil_icr_clear(u32 x, void __iomem *addr)
  62 {
  63         iowrite32(x, addr);
  64 }
  65 #endif /* defined(CONFIG_WIL6210_ISR_COR) */
  66
  67 static inline u32 wil_ioread32_and_clear(void __iomem *addr)
  68 {
  69         u32 x = ioread32(addr);
  70
  71         wil_icr_clear(x, addr);
  72
  73         return x;
  74 }
  75
  76 static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
  77 {
  78         iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
  79                   HOSTADDR(RGF_DMA_EP_TX_ICR) +
  80                   offsetof(struct RGF_ICR, IMS));
  81 }
  82
  83 static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
  84 {
  85         iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
  86                   HOSTADDR(RGF_DMA_EP_RX_ICR) +
  87                   offsetof(struct RGF_ICR, IMS));
  88 }
  89
  90 static void wil6210_mask_irq_misc(struct wil6210_priv *wil)
  91 {
  92         iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
  93                   HOSTADDR(RGF_DMA_EP_MISC_ICR) +
  94                   offsetof(struct RGF_ICR, IMS));
  95 }
  96
  97 static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
  98 {
  99         wil_dbg_irq(wil, "%s()\n", __func__);
 100
 101         iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
 102                   HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
 103
 104         clear_bit(wil_status_irqen, &wil->status);
 105 }
 106
 107 void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
 108 {
 109         iowrite32(WIL6210_IMC_TX, wil->csr +
 110                   HOSTADDR(RGF_DMA_EP_TX_ICR) +
 111                   offsetof(struct RGF_ICR, IMC));
 112 }
 113
 114 void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
 115 {
 116         iowrite32(WIL6210_IMC_RX, wil->csr +
 117                   HOSTADDR(RGF_DMA_EP_RX_ICR) +
 118                   offsetof(struct RGF_ICR, IMC));
 119 }
 120
 121 static void wil6210_unmask_irq_misc(struct wil6210_priv *wil)
 122 {
 123         iowrite32(WIL6210_IMC_MISC, wil->csr +
 124                   HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 125                   offsetof(struct RGF_ICR, IMC));
 126 }
 127
 128 static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
 129 {
 130         wil_dbg_irq(wil, "%s()\n", __func__);
 131
 132         set_bit(wil_status_irqen, &wil->status);
 133
 134         iowrite32(WIL6210_IRQ_PSEUDO_MASK, wil->csr +
 135                   HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
 136 }
 137
 138 void wil6210_disable_irq(struct wil6210_priv *wil)
 139 {
 140         wil_dbg_irq(wil, "%s()\n", __func__);
 141
 142         wil6210_mask_irq_tx(wil);
 143         wil6210_mask_irq_rx(wil);
 144         wil6210_mask_irq_misc(wil);
 145         wil6210_mask_irq_pseudo(wil);
 146 }
 147
 148 void wil6210_enable_irq(struct wil6210_priv *wil)
 149 {
 150         wil_dbg_irq(wil, "%s()\n", __func__);
 151
 152         iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
 153                   offsetof(struct RGF_ICR, ICC));
 154         iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
 155                   offsetof(struct RGF_ICR, ICC));
 156         iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 157                   offsetof(struct RGF_ICR, ICC));
 158
 159         wil6210_unmask_irq_pseudo(wil);
 160         wil6210_unmask_irq_tx(wil);
 161         wil6210_unmask_irq_rx(wil);
 162         wil6210_unmask_irq_misc(wil);
 163 }
 164
 165 static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
 166 {
 167         struct wil6210_priv *wil = cookie;
 168         u32 isr = wil_ioread32_and_clear(wil->csr +
 169                                          HOSTADDR(RGF_DMA_EP_RX_ICR) +
 170                                          offsetof(struct RGF_ICR, ICR));
 171
 172         trace_wil6210_irq_rx(isr);
 173         wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
 174
 175         if (!isr) {
 176                 wil_err(wil, "spurious IRQ: RX\n");
 177                 return IRQ_NONE;
 178         }
 179
 180         wil6210_mask_irq_rx(wil);
 181
 182         if (isr & BIT_DMA_EP_RX_ICR_RX_DONE) {
 183                 wil_dbg_irq(wil, "RX done\n");
 184                 isr &= ~BIT_DMA_EP_RX_ICR_RX_DONE;
 185                 wil_dbg_txrx(wil, "NAPI schedule\n");
 186                 napi_schedule(&wil->napi_rx);
 187         }
 188
 189         if (isr)
 190                 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
 191
 192         /* Rx IRQ will be enabled when NAPI processing finished */
 193
 194         return IRQ_HANDLED;
 195 }
 196
 197 static irqreturn_t wil6210_irq_tx(int irq, void *cookie)
 198 {
 199         struct wil6210_priv *wil = cookie;
 200         u32 isr = wil_ioread32_and_clear(wil->csr +
 201                                          HOSTADDR(RGF_DMA_EP_TX_ICR) +
 202                                          offsetof(struct RGF_ICR, ICR));
 203
 204         trace_wil6210_irq_tx(isr);
 205         wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
 206
 207         if (!isr) {
 208                 wil_err(wil, "spurious IRQ: TX\n");
 209                 return IRQ_NONE;
 210         }
 211
 212         wil6210_mask_irq_tx(wil);
 213
 214         if (isr & BIT_DMA_EP_TX_ICR_TX_DONE) {
 215                 wil_dbg_irq(wil, "TX done\n");
 216                 napi_schedule(&wil->napi_tx);
 217                 isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE;
 218                 /* clear also all VRING interrupts */
 219                 isr &= ~(BIT(25) - 1UL);
 220         }
 221
 222         if (isr)
 223                 wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr);
 224
 225         /* Tx IRQ will be enabled when NAPI processing finished */
 226
 227         return IRQ_HANDLED;
 228 }
 229
 230 static void wil_notify_fw_error(struct wil6210_priv *wil)
 231 {
 232         struct device *dev = &wil_to_ndev(wil)->dev;
 233         char *envp[3] = {
 234                 [0] = "SOURCE=wil6210",
 235                 [1] = "EVENT=FW_ERROR",
 236                 [2] = NULL,
 237         };
 238         kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp);
 239 }
 240
 241 static void wil_cache_mbox_regs(struct wil6210_priv *wil)
 242 {
 243         /* make shadow copy of registers that should not change on run time */
 244         wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,
 245                              sizeof(struct wil6210_mbox_ctl));
 246         wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx);
 247         wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx);
 248 }
 249
 250 static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
 251 {
 252         struct wil6210_priv *wil = cookie;
 253         u32 isr = wil_ioread32_and_clear(wil->csr +
 254                                          HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 255                                          offsetof(struct RGF_ICR, ICR));
 256
 257         trace_wil6210_irq_misc(isr);
 258         wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr);
 259
 260         if (!isr) {
 261                 wil_err(wil, "spurious IRQ: MISC\n");
 262                 return IRQ_NONE;
 263         }
 264
 265         wil6210_mask_irq_misc(wil);
 266
 267         if (isr & ISR_MISC_FW_ERROR) {
 268                 wil_err(wil, "Firmware error detected\n");
 269                 clear_bit(wil_status_fwready, &wil->status);
 270                 /*
 271                  * do not clear @isr here - we do 2-nd part in thread
 272                  * there, user space get notified, and it should be done
 273                  * in non-atomic context
 274                  */
 275         }
 276
 277         if (isr & ISR_MISC_FW_READY) {
 278                 wil_dbg_irq(wil, "IRQ: FW ready\n");
 279                 wil_cache_mbox_regs(wil);
 280                 set_bit(wil_status_reset_done, &wil->status);
 281                 /**
 282                  * Actual FW ready indicated by the
 283                  * WMI_FW_READY_EVENTID
 284                  */
 285                 isr &= ~ISR_MISC_FW_READY;
 286         }
 287
 288         wil->isr_misc = isr;
 289
 290         if (isr) {
 291                 return IRQ_WAKE_THREAD;
 292         } else {
 293                 wil6210_unmask_irq_misc(wil);
 294                 return IRQ_HANDLED;
 295         }
 296 }
 297
 298 static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
 299 {
 300         struct wil6210_priv *wil = cookie;
 301         u32 isr = wil->isr_misc;
 302
 303         trace_wil6210_irq_misc_thread(isr);
 304         wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr);
 305
 306         if (isr & ISR_MISC_FW_ERROR) {
 307                 wil_notify_fw_error(wil);
 308                 isr &= ~ISR_MISC_FW_ERROR;
 309         }
 310
 311         if (isr & ISR_MISC_MBOX_EVT) {
 312                 wil_dbg_irq(wil, "MBOX event\n");
 313                 wmi_recv_cmd(wil);
 314                 isr &= ~ISR_MISC_MBOX_EVT;
 315         }
 316
 317         if (isr)
 318                 wil_err(wil, "un-handled MISC ISR bits 0x%08x\n", isr);
 319
 320         wil->isr_misc = 0;
 321
 322         wil6210_unmask_irq_misc(wil);
 323
 324         return IRQ_HANDLED;
 325 }
 326
 327 /**
 328  * thread IRQ handler
 329  */
 330 static irqreturn_t wil6210_thread_irq(int irq, void *cookie)
 331 {
 332         struct wil6210_priv *wil = cookie;
 333
 334         wil_dbg_irq(wil, "Thread IRQ\n");
 335         /* Discover real IRQ cause */
 336         if (wil->isr_misc)
 337                 wil6210_irq_misc_thread(irq, cookie);
 338
 339         wil6210_unmask_irq_pseudo(wil);
 340
 341         return IRQ_HANDLED;
 342 }
 343
 344 /* DEBUG
 345  * There is subtle bug in hardware that causes IRQ to raise when it should be
 346  * masked. It is quite rare and hard to debug.
 347  *
 348  * Catch irq issue if it happens and print all I can.
 349  */
 350 static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
 351 {
 352         if (!test_bit(wil_status_irqen, &wil->status)) {
 353                 u32 icm_rx = wil_ioread32_and_clear(wil->csr +
 354                                 HOSTADDR(RGF_DMA_EP_RX_ICR) +
 355                                 offsetof(struct RGF_ICR, ICM));
 356                 u32 icr_rx = wil_ioread32_and_clear(wil->csr +
 357                                 HOSTADDR(RGF_DMA_EP_RX_ICR) +
 358                                 offsetof(struct RGF_ICR, ICR));
 359                 u32 imv_rx = ioread32(wil->csr +
 360                                 HOSTADDR(RGF_DMA_EP_RX_ICR) +
 361                                 offsetof(struct RGF_ICR, IMV));
 362                 u32 icm_tx = wil_ioread32_and_clear(wil->csr +
 363                                 HOSTADDR(RGF_DMA_EP_TX_ICR) +
 364                                 offsetof(struct RGF_ICR, ICM));
 365                 u32 icr_tx = wil_ioread32_and_clear(wil->csr +
 366                                 HOSTADDR(RGF_DMA_EP_TX_ICR) +
 367                                 offsetof(struct RGF_ICR, ICR));
 368                 u32 imv_tx = ioread32(wil->csr +
 369                                 HOSTADDR(RGF_DMA_EP_TX_ICR) +
 370                                 offsetof(struct RGF_ICR, IMV));
 371                 u32 icm_misc = wil_ioread32_and_clear(wil->csr +
 372                                 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 373                                 offsetof(struct RGF_ICR, ICM));
 374                 u32 icr_misc = wil_ioread32_and_clear(wil->csr +
 375                                 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 376                                 offsetof(struct RGF_ICR, ICR));
 377                 u32 imv_misc = ioread32(wil->csr +
 378                                 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 379                                 offsetof(struct RGF_ICR, IMV));
 380                 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
 381                                 "Rx   icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
 382                                 "Tx   icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
 383                                 "Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n",
 384                                 pseudo_cause,
 385                                 icm_rx, icr_rx, imv_rx,
 386                                 icm_tx, icr_tx, imv_tx,
 387                                 icm_misc, icr_misc, imv_misc);
 388
 389                 return -EINVAL;
 390         }
 391
 392         return 0;
 393 }
 394
 395 static irqreturn_t wil6210_hardirq(int irq, void *cookie)
 396 {
 397         irqreturn_t rc = IRQ_HANDLED;
 398         struct wil6210_priv *wil = cookie;
 399         u32 pseudo_cause = ioread32(wil->csr + HOSTADDR(RGF_DMA_PSEUDO_CAUSE));
 400
 401         /**
 402          * pseudo_cause is Clear-On-Read, no need to ACK
 403          */
 404         if ((pseudo_cause == 0) || ((pseudo_cause & 0xff) == 0xff))
 405                 return IRQ_NONE;
 406
 407         /* FIXME: IRQ mask debug */
 408         if (wil6210_debug_irq_mask(wil, pseudo_cause))
 409                 return IRQ_NONE;
 410
 411         trace_wil6210_irq_pseudo(pseudo_cause);
 412         wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);
 413
 414         wil6210_mask_irq_pseudo(wil);
 415
 416         /* Discover real IRQ cause
 417          * There are 2 possible phases for every IRQ:
 418          * - hard IRQ handler called right here
 419          * - threaded handler called later
 420          *
 421          * Hard IRQ handler reads and clears ISR.
 422          *
 423          * If threaded handler requested, hard IRQ handler
 424          * returns IRQ_WAKE_THREAD and saves ISR register value
 425          * for the threaded handler use.
 426          *
 427          * voting for wake thread - need at least 1 vote
 428          */
 429         if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) &&
 430             (wil6210_irq_rx(irq, cookie) == IRQ_WAKE_THREAD))
 431                 rc = IRQ_WAKE_THREAD;
 432
 433         if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) &&
 434             (wil6210_irq_tx(irq, cookie) == IRQ_WAKE_THREAD))
 435                 rc = IRQ_WAKE_THREAD;
 436
 437         if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) &&
 438             (wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD))
 439                 rc = IRQ_WAKE_THREAD;
 440
 441         /* if thread is requested, it will unmask IRQ */
 442         if (rc != IRQ_WAKE_THREAD)
 443                 wil6210_unmask_irq_pseudo(wil);
 444
 445         return rc;
 446 }
 447
 448 static int wil6210_request_3msi(struct wil6210_priv *wil, int irq)
 449 {
 450         int rc;
 451         /*
 452          * IRQ's are in the following order:
 453          * - Tx
 454          * - Rx
 455          * - Misc
 456          */
 457
 458         rc = request_irq(irq, wil6210_irq_tx, IRQF_SHARED,
 459                          WIL_NAME"_tx", wil);
 460         if (rc)
 461                 return rc;
 462
 463         rc = request_irq(irq + 1, wil6210_irq_rx, IRQF_SHARED,
 464                          WIL_NAME"_rx", wil);
 465         if (rc)
 466                 goto free0;
 467
 468         rc = request_threaded_irq(irq + 2, wil6210_irq_misc,
 469                                   wil6210_irq_misc_thread,
 470                                   IRQF_SHARED, WIL_NAME"_misc", wil);
 471         if (rc)
 472                 goto free1;
 473
 474         return 0;
 475         /* error branch */
 476 free1:
 477         free_irq(irq + 1, wil);
 478 free0:
 479         free_irq(irq, wil);
 480
 481         return rc;
 482 }
 483
 484 int wil6210_init_irq(struct wil6210_priv *wil, int irq)
 485 {
 486         int rc;
 487         if (wil->n_msi == 3)
 488                 rc = wil6210_request_3msi(wil, irq);
 489         else
 490                 rc = request_threaded_irq(irq, wil6210_hardirq,
 491                                           wil6210_thread_irq,
 492                                           wil->n_msi ? 0 : IRQF_SHARED,
 493                                           WIL_NAME, wil);
 494         if (rc)
 495                 return rc;
 496
 497         wil6210_enable_irq(wil);
 498
 499         return 0;
 500 }
 501
 502 void wil6210_fini_irq(struct wil6210_priv *wil, int irq)
 503 {
 504         wil6210_disable_irq(wil);
 505         free_irq(irq, wil);
 506         if (wil->n_msi == 3) {
 507                 free_irq(irq + 1, wil);
 508                 free_irq(irq + 2, wil);
 509         }
 510 }