4 #include <linux/kernel.h>
5 #include <linux/spinlock.h>
6 #include <linux/interrupt.h>
7 #include <linux/hw_random.h>
8 #include <linux/bcma/bcma.h>
9 #include <linux/ssb/ssb.h>
10 #include <linux/completion.h>
11 #include <net/mac80211.h>
18 #include "phy_common.h"
21 #ifdef CONFIG_B43_DEBUG
28 #define B43_MMIO_DMA0_REASON 0x20
29 #define B43_MMIO_DMA0_IRQ_MASK 0x24
30 #define B43_MMIO_DMA1_REASON 0x28
31 #define B43_MMIO_DMA1_IRQ_MASK 0x2C
32 #define B43_MMIO_DMA2_REASON 0x30
33 #define B43_MMIO_DMA2_IRQ_MASK 0x34
34 #define B43_MMIO_DMA3_REASON 0x38
35 #define B43_MMIO_DMA3_IRQ_MASK 0x3C
36 #define B43_MMIO_DMA4_REASON 0x40
37 #define B43_MMIO_DMA4_IRQ_MASK 0x44
38 #define B43_MMIO_DMA5_REASON 0x48
39 #define B43_MMIO_DMA5_IRQ_MASK 0x4C
40 #define B43_MMIO_MACCTL 0x120 /* MAC control */
41 #define B43_MMIO_MACCMD 0x124 /* MAC command */
42 #define B43_MMIO_GEN_IRQ_REASON 0x128
43 #define B43_MMIO_GEN_IRQ_MASK 0x12C
44 #define B43_MMIO_RAM_CONTROL 0x130
45 #define B43_MMIO_RAM_DATA 0x134
46 #define B43_MMIO_PS_STATUS 0x140
47 #define B43_MMIO_RADIO_HWENABLED_HI 0x158
48 #define B43_MMIO_MAC_HW_CAP 0x15C /* MAC capabilities (corerev >= 13) */
49 #define B43_MMIO_SHM_CONTROL 0x160
50 #define B43_MMIO_SHM_DATA 0x164
51 #define B43_MMIO_SHM_DATA_UNALIGNED 0x166
52 #define B43_MMIO_XMITSTAT_0 0x170
53 #define B43_MMIO_XMITSTAT_1 0x174
54 #define B43_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
55 #define B43_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
56 #define B43_MMIO_TSF_CFP_REP 0x188
57 #define B43_MMIO_TSF_CFP_START 0x18C
58 #define B43_MMIO_TSF_CFP_MAXDUR 0x190
61 #define B43_MMIO_DMA32_BASE0 0x200
62 #define B43_MMIO_DMA32_BASE1 0x220
63 #define B43_MMIO_DMA32_BASE2 0x240
64 #define B43_MMIO_DMA32_BASE3 0x260
65 #define B43_MMIO_DMA32_BASE4 0x280
66 #define B43_MMIO_DMA32_BASE5 0x2A0
68 #define B43_MMIO_DMA64_BASE0 0x200
69 #define B43_MMIO_DMA64_BASE1 0x240
70 #define B43_MMIO_DMA64_BASE2 0x280
71 #define B43_MMIO_DMA64_BASE3 0x2C0
72 #define B43_MMIO_DMA64_BASE4 0x300
73 #define B43_MMIO_DMA64_BASE5 0x340
75 /* PIO on core rev < 11 */
76 #define B43_MMIO_PIO_BASE0 0x300
77 #define B43_MMIO_PIO_BASE1 0x310
78 #define B43_MMIO_PIO_BASE2 0x320
79 #define B43_MMIO_PIO_BASE3 0x330
80 #define B43_MMIO_PIO_BASE4 0x340
81 #define B43_MMIO_PIO_BASE5 0x350
82 #define B43_MMIO_PIO_BASE6 0x360
83 #define B43_MMIO_PIO_BASE7 0x370
84 /* PIO on core rev >= 11 */
85 #define B43_MMIO_PIO11_BASE0 0x200
86 #define B43_MMIO_PIO11_BASE1 0x240
87 #define B43_MMIO_PIO11_BASE2 0x280
88 #define B43_MMIO_PIO11_BASE3 0x2C0
89 #define B43_MMIO_PIO11_BASE4 0x300
90 #define B43_MMIO_PIO11_BASE5 0x340
92 #define B43_MMIO_RADIO24_CONTROL 0x3D8 /* core rev >= 24 only */
93 #define B43_MMIO_RADIO24_DATA 0x3DA /* core rev >= 24 only */
94 #define B43_MMIO_PHY_VER 0x3E0
95 #define B43_MMIO_PHY_RADIO 0x3E2
96 #define B43_MMIO_PHY0 0x3E6
97 #define B43_MMIO_ANTENNA 0x3E8
98 #define B43_MMIO_CHANNEL 0x3F0
99 #define B43_MMIO_CHANNEL_EXT 0x3F4
100 #define B43_MMIO_RADIO_CONTROL 0x3F6
101 #define B43_MMIO_RADIO_DATA_HIGH 0x3F8
102 #define B43_MMIO_RADIO_DATA_LOW 0x3FA
103 #define B43_MMIO_PHY_CONTROL 0x3FC
104 #define B43_MMIO_PHY_DATA 0x3FE
105 #define B43_MMIO_MACFILTER_CONTROL 0x420
106 #define B43_MMIO_MACFILTER_DATA 0x422
107 #define B43_MMIO_RCMTA_COUNT 0x43C
108 #define B43_MMIO_PSM_PHY_HDR 0x492
109 #define B43_MMIO_RADIO_HWENABLED_LO 0x49A
110 #define B43_MMIO_GPIO_CONTROL 0x49C
111 #define B43_MMIO_GPIO_MASK 0x49E
112 #define B43_MMIO_TXE0_CTL 0x500
113 #define B43_MMIO_TXE0_AUX 0x502
114 #define B43_MMIO_TXE0_TS_LOC 0x504
115 #define B43_MMIO_TXE0_TIME_OUT 0x506
116 #define B43_MMIO_TXE0_WM_0 0x508
117 #define B43_MMIO_TXE0_WM_1 0x50A
118 #define B43_MMIO_TXE0_PHYCTL 0x50C
119 #define B43_MMIO_TXE0_STATUS 0x50E
120 #define B43_MMIO_TXE0_MMPLCP0 0x510
121 #define B43_MMIO_TXE0_MMPLCP1 0x512
122 #define B43_MMIO_TXE0_PHYCTL1 0x514
123 #define B43_MMIO_XMTFIFODEF 0x520
124 #define B43_MMIO_XMTFIFO_FRAME_CNT 0x522 /* core rev>= 16 only */
125 #define B43_MMIO_XMTFIFO_BYTE_CNT 0x524 /* core rev>= 16 only */
126 #define B43_MMIO_XMTFIFO_HEAD 0x526 /* core rev>= 16 only */
127 #define B43_MMIO_XMTFIFO_RD_PTR 0x528 /* core rev>= 16 only */
128 #define B43_MMIO_XMTFIFO_WR_PTR 0x52A /* core rev>= 16 only */
129 #define B43_MMIO_XMTFIFODEF1 0x52C /* core rev>= 16 only */
130 #define B43_MMIO_XMTFIFOCMD 0x540
131 #define B43_MMIO_XMTFIFOFLUSH 0x542
132 #define B43_MMIO_XMTFIFOTHRESH 0x544
133 #define B43_MMIO_XMTFIFORDY 0x546
134 #define B43_MMIO_XMTFIFOPRIRDY 0x548
135 #define B43_MMIO_XMTFIFORQPRI 0x54A
136 #define B43_MMIO_XMTTPLATETXPTR 0x54C
137 #define B43_MMIO_XMTTPLATEPTR 0x550
138 #define B43_MMIO_SMPL_CLCT_STRPTR 0x552 /* core rev>= 22 only */
139 #define B43_MMIO_SMPL_CLCT_STPPTR 0x554 /* core rev>= 22 only */
140 #define B43_MMIO_SMPL_CLCT_CURPTR 0x556 /* core rev>= 22 only */
141 #define B43_MMIO_XMTTPLATEDATALO 0x560
142 #define B43_MMIO_XMTTPLATEDATAHI 0x562
143 #define B43_MMIO_XMTSEL 0x568
144 #define B43_MMIO_XMTTXCNT 0x56A
145 #define B43_MMIO_XMTTXSHMADDR 0x56C
146 #define B43_MMIO_TSF_CFP_START_LOW 0x604
147 #define B43_MMIO_TSF_CFP_START_HIGH 0x606
148 #define B43_MMIO_TSF_CFP_PRETBTT 0x612
149 #define B43_MMIO_TSF_CLK_FRAC_LOW 0x62E
150 #define B43_MMIO_TSF_CLK_FRAC_HIGH 0x630
151 #define B43_MMIO_TSF_0 0x632 /* core rev < 3 only */
152 #define B43_MMIO_TSF_1 0x634 /* core rev < 3 only */
153 #define B43_MMIO_TSF_2 0x636 /* core rev < 3 only */
154 #define B43_MMIO_TSF_3 0x638 /* core rev < 3 only */
155 #define B43_MMIO_RNG 0x65A
156 #define B43_MMIO_IFSSLOT 0x684 /* Interframe slot time */
157 #define B43_MMIO_IFSCTL 0x688 /* Interframe space control */
158 #define B43_MMIO_IFSSTAT 0x690
159 #define B43_MMIO_IFSMEDBUSYCTL 0x692
160 #define B43_MMIO_IFTXDUR 0x694
161 #define B43_MMIO_IFSCTL_USE_EDCF 0x0004
162 #define B43_MMIO_POWERUP_DELAY 0x6A8
163 #define B43_MMIO_BTCOEX_CTL 0x6B4 /* Bluetooth Coexistence Control */
164 #define B43_MMIO_BTCOEX_STAT 0x6B6 /* Bluetooth Coexistence Status */
165 #define B43_MMIO_BTCOEX_TXCTL 0x6B8 /* Bluetooth Coexistence Transmit Control */
166 #define B43_MMIO_WEPCTL 0x7C0
168 /* SPROM boardflags_lo values */
169 #define B43_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
170 #define B43_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
171 #define B43_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
172 #define B43_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
173 #define B43_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
174 #define B43_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
175 #define B43_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
176 #define B43_BFL_ENETADM 0x0080 /* has ADMtek switch */
177 #define B43_BFL_ENETVLAN 0x0100 /* can do vlan */
178 #define B43_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
179 #define B43_BFL_NOPCI 0x0400 /* leaves PCI floating */
180 #define B43_BFL_FEM 0x0800 /* supports the Front End Module */
181 #define B43_BFL_EXTLNA 0x1000 /* has an external LNA */
182 #define B43_BFL_HGPA 0x2000 /* had high gain PA */
183 #define B43_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
184 #define B43_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
186 /* SPROM boardflags_hi values */
187 #define B43_BFH_NOPA 0x0001 /* has no PA */
188 #define B43_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
189 #define B43_BFH_PAREF 0x0004 /* uses the PARef LDO */
190 #define B43_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared
192 #define B43_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
193 #define B43_BFH_BUCKBOOST 0x0020 /* has buck/booster */
194 #define B43_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna
196 #define B43_BFH_NOCBUCK 0x0080
197 #define B43_BFH_PALDO 0x0200
198 #define B43_BFH_EXTLNA_5GHZ 0x1000 /* has an external LNA (5GHz mode) */
200 /* SPROM boardflags2_lo values */
201 #define B43_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
202 #define B43_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
203 #define B43_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
204 #define B43_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
205 #define B43_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
206 #define B43_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
207 #define B43_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
208 #define B43_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
209 #define B43_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
210 #define B43_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
211 #define B43_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
212 #define B43_BFL2_SINGLEANT_CCK 0x1000
213 #define B43_BFL2_2G_SPUR_WAR 0x2000
215 /* SPROM boardflags2_hi values */
216 #define B43_BFH2_GPLL_WAR2 0x0001
217 #define B43_BFH2_IPALVLSHIFT_3P3 0x0002
218 #define B43_BFH2_INTERNDET_TXIQCAL 0x0004
219 #define B43_BFH2_XTALBUFOUTEN 0x0008
221 /* GPIO register offset, in both ChipCommon and PCI core. */
222 #define B43_GPIO_CONTROL 0x6c
226 B43_SHM_UCODE, /* Microcode memory */
227 B43_SHM_SHARED, /* Shared memory */
228 B43_SHM_SCRATCH, /* Scratch memory */
229 B43_SHM_HW, /* Internal hardware register */
230 B43_SHM_RCMTA, /* Receive match transmitter address (rev >= 5 only) */
232 /* SHM Routing modifiers */
233 #define B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */
234 #define B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */
235 #define B43_SHM_AUTOINC_RW (B43_SHM_AUTOINC_R | \
238 /* Misc SHM_SHARED offsets */
239 #define B43_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */
240 #define B43_SHM_SH_PCTLWDPOS 0x0008
241 #define B43_SHM_SH_RXPADOFF 0x0034 /* RX Padding data offset (PIO only) */
242 #define B43_SHM_SH_FWCAPA 0x0042 /* Firmware capabilities (Opensource firmware only) */
243 #define B43_SHM_SH_PHYVER 0x0050 /* PHY version */
244 #define B43_SHM_SH_PHYTYPE 0x0052 /* PHY type */
245 #define B43_SHM_SH_ANTSWAP 0x005C /* Antenna swap threshold */
246 #define B43_SHM_SH_HOSTF1 0x005E /* Hostflags 1 for ucode options */
247 #define B43_SHM_SH_HOSTF2 0x0060 /* Hostflags 2 for ucode options */
248 #define B43_SHM_SH_HOSTF3 0x0062 /* Hostflags 3 for ucode options */
249 #define B43_SHM_SH_RFATT 0x0064 /* Current radio attenuation value */
250 #define B43_SHM_SH_RADAR 0x0066 /* Radar register */
251 #define B43_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */
252 #define B43_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */
253 #define B43_SHM_SH_HOSTF4 0x0078 /* Hostflags 4 for ucode options */
254 #define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */
255 #define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5 Ghz channel */
256 #define B43_SHM_SH_CHAN_40MHZ 0x0200 /* Bit set, if 40 Mhz channel width */
257 #define B43_SHM_SH_MACHW_L 0x00C0 /* Location where the ucode expects the MAC capabilities */
258 #define B43_SHM_SH_MACHW_H 0x00C2 /* Location where the ucode expects the MAC capabilities */
259 #define B43_SHM_SH_HOSTF5 0x00D4 /* Hostflags 5 for ucode options */
260 #define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */
261 /* TSSI information */
262 #define B43_SHM_SH_TSSI_CCK 0x0058 /* TSSI for last 4 CCK frames (32bit) */
263 #define B43_SHM_SH_TSSI_OFDM_A 0x0068 /* TSSI for last 4 OFDM frames (32bit) */
264 #define B43_SHM_SH_TSSI_OFDM_G 0x0070 /* TSSI for last 4 OFDM frames (32bit) */
265 #define B43_TSSI_MAX 0x7F /* Max value for one TSSI value */
266 /* SHM_SHARED TX FIFO variables */
267 #define B43_SHM_SH_SIZE01 0x0098 /* TX FIFO size for FIFO 0 (low) and 1 (high) */
268 #define B43_SHM_SH_SIZE23 0x009A /* TX FIFO size for FIFO 2 and 3 */
269 #define B43_SHM_SH_SIZE45 0x009C /* TX FIFO size for FIFO 4 and 5 */
270 #define B43_SHM_SH_SIZE67 0x009E /* TX FIFO size for FIFO 6 and 7 */
271 /* SHM_SHARED background noise */
272 #define B43_SHM_SH_JSSI0 0x0088 /* Measure JSSI 0 */
273 #define B43_SHM_SH_JSSI1 0x008A /* Measure JSSI 1 */
274 #define B43_SHM_SH_JSSIAUX 0x008C /* Measure JSSI AUX */
275 /* SHM_SHARED crypto engine */
276 #define B43_SHM_SH_DEFAULTIV 0x003C /* Default IV location */
277 #define B43_SHM_SH_NRRXTRANS 0x003E /* # of soft RX transmitter addresses (max 8) */
278 #define B43_SHM_SH_KTP 0x0056 /* Key table pointer */
279 #define B43_SHM_SH_TKIPTSCTTAK 0x0318
280 #define B43_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block (v4 firmware) */
281 #define B43_SHM_SH_PSM 0x05F4 /* PSM transmitter address match block (rev < 5) */
282 /* SHM_SHARED WME variables */
283 #define B43_SHM_SH_EDCFSTAT 0x000E /* EDCF status */
284 #define B43_SHM_SH_TXFCUR 0x0030 /* TXF current index */
285 #define B43_SHM_SH_EDCFQ 0x0240 /* EDCF Q info */
286 /* SHM_SHARED powersave mode related */
287 #define B43_SHM_SH_SLOTT 0x0010 /* Slot time */
288 #define B43_SHM_SH_DTIMPER 0x0012 /* DTIM period */
289 #define B43_SHM_SH_NOSLPZNATDTIM 0x004C /* NOSLPZNAT DTIM */
290 /* SHM_SHARED beacon/AP variables */
291 #define B43_SHM_SH_BT_BASE0 0x0068 /* Beacon template base 0 */
292 #define B43_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */
293 #define B43_SHM_SH_BT_BASE1 0x0468 /* Beacon template base 1 */
294 #define B43_SHM_SH_BTL1 0x001A /* Beacon template length 1 */
295 #define B43_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */
296 #define B43_SHM_SH_TIMBPOS 0x001E /* TIM B position in beacon */
297 #define B43_SHM_SH_DTIMP 0x0012 /* DTIP period */
298 #define B43_SHM_SH_MCASTCOOKIE 0x00A8 /* Last bcast/mcast frame ID */
299 #define B43_SHM_SH_SFFBLIM 0x0044 /* Short frame fallback retry limit */
300 #define B43_SHM_SH_LFFBLIM 0x0046 /* Long frame fallback retry limit */
301 #define B43_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word (see PHY TX control) */
302 #define B43_SHM_SH_EXTNPHYCTL 0x00B0 /* Extended bytes for beacon PHY control (N) */
303 #define B43_SHM_SH_BCN_LI 0x00B6 /* beacon listen interval */
304 /* SHM_SHARED ACK/CTS control */
305 #define B43_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word (see PHY TX control) */
306 /* SHM_SHARED probe response variables */
307 #define B43_SHM_SH_PRSSID 0x0160 /* Probe Response SSID */
308 #define B43_SHM_SH_PRSSIDLEN 0x0048 /* Probe Response SSID length */
309 #define B43_SHM_SH_PRTLEN 0x004A /* Probe Response template length */
310 #define B43_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */
311 #define B43_SHM_SH_PRPHYCTL 0x0188 /* Probe Response PHY TX control word */
312 /* SHM_SHARED rate tables */
313 #define B43_SHM_SH_OFDMDIRECT 0x01C0 /* Pointer to OFDM direct map */
314 #define B43_SHM_SH_OFDMBASIC 0x01E0 /* Pointer to OFDM basic rate map */
315 #define B43_SHM_SH_CCKDIRECT 0x0200 /* Pointer to CCK direct map */
316 #define B43_SHM_SH_CCKBASIC 0x0220 /* Pointer to CCK basic rate map */
317 /* SHM_SHARED microcode soft registers */
318 #define B43_SHM_SH_UCODEREV 0x0000 /* Microcode revision */
319 #define B43_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */
320 #define B43_SHM_SH_UCODEDATE 0x0004 /* Microcode date */
321 #define B43_SHM_SH_UCODETIME 0x0006 /* Microcode time */
322 #define B43_SHM_SH_UCODESTAT 0x0040 /* Microcode debug status code */
323 #define B43_SHM_SH_UCODESTAT_INVALID 0
324 #define B43_SHM_SH_UCODESTAT_INIT 1
325 #define B43_SHM_SH_UCODESTAT_ACTIVE 2
326 #define B43_SHM_SH_UCODESTAT_SUSP 3 /* suspended */
327 #define B43_SHM_SH_UCODESTAT_SLEEP 4 /* asleep (PS) */
328 #define B43_SHM_SH_MAXBFRAMES 0x0080 /* Maximum number of frames in a burst */
329 #define B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
330 #define B43_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */
331 /* SHM_SHARED tx iq workarounds */
332 #define B43_SHM_SH_NPHY_TXIQW0 0x0700
333 #define B43_SHM_SH_NPHY_TXIQW1 0x0702
334 #define B43_SHM_SH_NPHY_TXIQW2 0x0704
335 #define B43_SHM_SH_NPHY_TXIQW3 0x0706
336 /* SHM_SHARED tx pwr ctrl */
337 #define B43_SHM_SH_NPHY_TXPWR_INDX0 0x0708
338 #define B43_SHM_SH_NPHY_TXPWR_INDX1 0x070E
340 /* SHM_SCRATCH offsets */
341 #define B43_SHM_SC_MINCONT 0x0003 /* Minimum contention window */
342 #define B43_SHM_SC_MAXCONT 0x0004 /* Maximum contention window */
343 #define B43_SHM_SC_CURCONT 0x0005 /* Current contention window */
344 #define B43_SHM_SC_SRLIMIT 0x0006 /* Short retry count limit */
345 #define B43_SHM_SC_LRLIMIT 0x0007 /* Long retry count limit */
346 #define B43_SHM_SC_DTIMC 0x0008 /* Current DTIM count */
347 #define B43_SHM_SC_BTL0LEN 0x0015 /* Beacon 0 template length */
348 #define B43_SHM_SC_BTL1LEN 0x0016 /* Beacon 1 template length */
349 #define B43_SHM_SC_SCFB 0x0017 /* Short frame transmit count threshold for rate fallback */
350 #define B43_SHM_SC_LCFB 0x0018 /* Long frame transmit count threshold for rate fallback */
352 /* Hardware Radio Enable masks */
353 #define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
354 #define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
356 /* HostFlags. See b43_hf_read/write() */
357 #define B43_HF_ANTDIVHELP 0x000000000001ULL /* ucode antenna div helper */
358 #define B43_HF_SYMW 0x000000000002ULL /* G-PHY SYM workaround */
359 #define B43_HF_RXPULLW 0x000000000004ULL /* RX pullup workaround */
360 #define B43_HF_CCKBOOST 0x000000000008ULL /* 4dB CCK power boost (exclusive with OFDM boost) */
361 #define B43_HF_BTCOEX 0x000000000010ULL /* Bluetooth coexistance */
362 #define B43_HF_GDCW 0x000000000020ULL /* G-PHY DC canceller filter bw workaround */
363 #define B43_HF_OFDMPABOOST 0x000000000040ULL /* Enable PA gain boost for OFDM */
364 #define B43_HF_ACPR 0x000000000080ULL /* Disable for Japan, channel 14 */
365 #define B43_HF_EDCF 0x000000000100ULL /* on if WME and MAC suspended */
366 #define B43_HF_TSSIRPSMW 0x000000000200ULL /* TSSI reset PSM ucode workaround */
367 #define B43_HF_20IN40IQW 0x000000000200ULL /* 20 in 40 MHz I/Q workaround (rev >= 13 only) */
368 #define B43_HF_DSCRQ 0x000000000400ULL /* Disable slow clock request in ucode */
369 #define B43_HF_ACIW 0x000000000800ULL /* ACI workaround: shift bits by 2 on PHY CRS */
370 #define B43_HF_2060W 0x000000001000ULL /* 2060 radio workaround */
371 #define B43_HF_RADARW 0x000000002000ULL /* Radar workaround */
372 #define B43_HF_USEDEFKEYS 0x000000004000ULL /* Enable use of default keys */
373 #define B43_HF_AFTERBURNER 0x000000008000ULL /* Afterburner enabled */
374 #define B43_HF_BT4PRIOCOEX 0x000000010000ULL /* Bluetooth 4-priority coexistance */
375 #define B43_HF_FWKUP 0x000000020000ULL /* Fast wake-up ucode */
376 #define B43_HF_VCORECALC 0x000000040000ULL /* Force VCO recalculation when powering up synthpu */
377 #define B43_HF_PCISCW 0x000000080000ULL /* PCI slow clock workaround */
378 #define B43_HF_4318TSSI 0x000000200000ULL /* 4318 TSSI */
379 #define B43_HF_FBCMCFIFO 0x000000400000ULL /* Flush bcast/mcast FIFO immediately */
380 #define B43_HF_HWPCTL 0x000000800000ULL /* Enable hardwarre power control */
381 #define B43_HF_BTCOEXALT 0x000001000000ULL /* Bluetooth coexistance in alternate pins */
382 #define B43_HF_TXBTCHECK 0x000002000000ULL /* Bluetooth check during transmission */
383 #define B43_HF_SKCFPUP 0x000004000000ULL /* Skip CFP update */
384 #define B43_HF_N40W 0x000008000000ULL /* N PHY 40 MHz workaround (rev >= 13 only) */
385 #define B43_HF_ANTSEL 0x000020000000ULL /* Antenna selection (for testing antenna div.) */
386 #define B43_HF_BT3COEXT 0x000020000000ULL /* Bluetooth 3-wire coexistence (rev >= 13 only) */
387 #define B43_HF_BTCANT 0x000040000000ULL /* Bluetooth coexistence (antenna mode) (rev >= 13 only) */
388 #define B43_HF_ANTSELEN 0x000100000000ULL /* Antenna selection enabled (rev >= 13 only) */
389 #define B43_HF_ANTSELMODE 0x000200000000ULL /* Antenna selection mode (rev >= 13 only) */
390 #define B43_HF_MLADVW 0x001000000000ULL /* N PHY ML ADV workaround (rev >= 13 only) */
391 #define B43_HF_PR45960W 0x080000000000ULL /* PR 45960 workaround (rev >= 13 only) */
393 /* Firmware capabilities field in SHM (Opensource firmware only) */
394 #define B43_FWCAPA_HWCRYPTO 0x0001
395 #define B43_FWCAPA_QOS 0x0002
397 /* MacFilter offsets. */
398 #define B43_MACFILTER_SELF 0x0000
399 #define B43_MACFILTER_BSSID 0x0003
402 #define B43_PCTL_IN 0xB0
403 #define B43_PCTL_OUT 0xB4
404 #define B43_PCTL_OUTENABLE 0xB8
405 #define B43_PCTL_XTAL_POWERUP 0x40
406 #define B43_PCTL_PLL_POWERDOWN 0x80
408 /* PowerControl Clock Modes */
409 #define B43_PCTL_CLK_FAST 0x00
410 #define B43_PCTL_CLK_SLOW 0x01
411 #define B43_PCTL_CLK_DYNAMIC 0x02
413 #define B43_PCTL_FORCE_SLOW 0x0800
414 #define B43_PCTL_FORCE_PLL 0x1000
415 #define B43_PCTL_DYN_XTAL 0x2000
418 #define B43_PHYTYPE_A 0x00
419 #define B43_PHYTYPE_B 0x01
420 #define B43_PHYTYPE_G 0x02
421 #define B43_PHYTYPE_N 0x04
422 #define B43_PHYTYPE_LP 0x05
423 #define B43_PHYTYPE_SSLPN 0x06
424 #define B43_PHYTYPE_HT 0x07
425 #define B43_PHYTYPE_LCN 0x08
426 #define B43_PHYTYPE_LCNXN 0x09
427 #define B43_PHYTYPE_LCN40 0x0a
428 #define B43_PHYTYPE_AC 0x0b
431 #define B43_PHY_ILT_A_CTRL 0x0072
432 #define B43_PHY_ILT_A_DATA1 0x0073
433 #define B43_PHY_ILT_A_DATA2 0x0074
434 #define B43_PHY_G_LO_CONTROL 0x0810
435 #define B43_PHY_ILT_G_CTRL 0x0472
436 #define B43_PHY_ILT_G_DATA1 0x0473
437 #define B43_PHY_ILT_G_DATA2 0x0474
438 #define B43_PHY_A_PCTL 0x007B
439 #define B43_PHY_G_PCTL 0x0029
440 #define B43_PHY_A_CRS 0x0029
441 #define B43_PHY_RADIO_BITFIELD 0x0401
442 #define B43_PHY_G_CRS 0x0429
443 #define B43_PHY_NRSSILT_CTRL 0x0803
444 #define B43_PHY_NRSSILT_DATA 0x0804
447 #define B43_RADIOCTL_ID 0x01
449 /* MAC Control bitfield */
450 #define B43_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
451 #define B43_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */
452 #define B43_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */
453 #define B43_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */
454 #define B43_MACCTL_SHM_UPPER 0x00000200 /* SHM Upper */
455 #define B43_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */
456 #define B43_MACCTL_PSM_DBG 0x00002000 /* Microcode debugging enabled */
457 #define B43_MACCTL_GPOUTSMSK 0x0000C000 /* GPOUT Select Mask */
458 #define B43_MACCTL_BE 0x00010000 /* Big Endian mode */
459 #define B43_MACCTL_INFRA 0x00020000 /* Infrastructure mode */
460 #define B43_MACCTL_AP 0x00040000 /* AccessPoint mode */
461 #define B43_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */
462 #define B43_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */
463 #define B43_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep frames with bad PLCP */
464 #define B43_MACCTL_PHY_LOCK 0x00200000
465 #define B43_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */
466 #define B43_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */
467 #define B43_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */
468 #define B43_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */
469 #define B43_MACCTL_AWAKE 0x04000000 /* Device is awake */
470 #define B43_MACCTL_CLOSEDNET 0x08000000 /* Closed net (no SSID bcast) */
471 #define B43_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */
472 #define B43_MACCTL_DISCTXSTAT 0x20000000 /* Discard TX status */
473 #define B43_MACCTL_DISCPMQ 0x40000000 /* Discard Power Management Queue */
474 #define B43_MACCTL_GMODE 0x80000000 /* G Mode */
476 /* MAC Command bitfield */
477 #define B43_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */
478 #define B43_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */
479 #define B43_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */
480 #define B43_MACCMD_CCA 0x00000008 /* Clear channel assessment */
481 #define B43_MACCMD_BGNOISE 0x00000010 /* Background noise */
483 /* B43_MMIO_PSM_PHY_HDR bits */
484 #define B43_PSM_HDR_MAC_PHY_RESET 0x00000001
485 #define B43_PSM_HDR_MAC_PHY_CLOCK_EN 0x00000002
486 #define B43_PSM_HDR_MAC_PHY_FORCE_CLK 0x00000004
488 /* See BCMA_CLKCTLST_EXTRESREQ and BCMA_CLKCTLST_EXTRESST */
489 #define B43_BCMA_CLKCTLST_80211_PLL_REQ 0x00000100
490 #define B43_BCMA_CLKCTLST_PHY_PLL_REQ 0x00000200
491 #define B43_BCMA_CLKCTLST_80211_PLL_ST 0x01000000
492 #define B43_BCMA_CLKCTLST_PHY_PLL_ST 0x02000000
494 /* BCMA 802.11 core specific IO Control (BCMA_IOCTL) flags */
495 #define B43_BCMA_IOCTL_PHY_CLKEN 0x00000004 /* PHY Clock Enable */
496 #define B43_BCMA_IOCTL_PHY_RESET 0x00000008 /* PHY Reset */
497 #define B43_BCMA_IOCTL_MACPHYCLKEN 0x00000010 /* MAC PHY Clock Control Enable */
498 #define B43_BCMA_IOCTL_PLLREFSEL 0x00000020 /* PLL Frequency Reference Select */
499 #define B43_BCMA_IOCTL_PHY_BW 0x000000C0 /* PHY band width and clock speed mask (N-PHY+ only?) */
500 #define B43_BCMA_IOCTL_PHY_BW_10MHZ 0x00000000 /* 10 MHz bandwidth, 40 MHz PHY */
501 #define B43_BCMA_IOCTL_PHY_BW_20MHZ 0x00000040 /* 20 MHz bandwidth, 80 MHz PHY */
502 #define B43_BCMA_IOCTL_PHY_BW_40MHZ 0x00000080 /* 40 MHz bandwidth, 160 MHz PHY */
503 #define B43_BCMA_IOCTL_PHY_BW_80MHZ 0x000000C0 /* 80 MHz bandwidth */
504 #define B43_BCMA_IOCTL_DAC 0x00000300 /* Highspeed DAC mode control field */
505 #define B43_BCMA_IOCTL_GMODE 0x00002000 /* G Mode Enable */
507 /* BCMA 802.11 core specific IO status (BCMA_IOST) flags */
508 #define B43_BCMA_IOST_2G_PHY 0x00000001 /* 2.4G capable phy */
509 #define B43_BCMA_IOST_5G_PHY 0x00000002 /* 5G capable phy */
510 #define B43_BCMA_IOST_FASTCLKA 0x00000004 /* Fast Clock Available */
511 #define B43_BCMA_IOST_DUALB_PHY 0x00000008 /* Dualband phy */
513 /* 802.11 core specific TM State Low (SSB_TMSLOW) flags */
514 #define B43_TMSLOW_GMODE 0x20000000 /* G Mode Enable */
515 #define B43_TMSLOW_PHY_BANDWIDTH 0x00C00000 /* PHY band width and clock speed mask (N-PHY only) */
516 #define B43_TMSLOW_PHY_BANDWIDTH_10MHZ 0x00000000 /* 10 MHz bandwidth, 40 MHz PHY */
517 #define B43_TMSLOW_PHY_BANDWIDTH_20MHZ 0x00400000 /* 20 MHz bandwidth, 80 MHz PHY */
518 #define B43_TMSLOW_PHY_BANDWIDTH_40MHZ 0x00800000 /* 40 MHz bandwidth, 160 MHz PHY */
519 #define B43_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select (rev >= 5) */
520 #define B43_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */
521 #define B43_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */
522 #define B43_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */
524 /* 802.11 core specific TM State High (SSB_TMSHIGH) flags */
525 #define B43_TMSHIGH_DUALBAND_PHY 0x00080000 /* Dualband PHY available */
526 #define B43_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available (rev >= 5) */
527 #define B43_TMSHIGH_HAVE_5GHZ_PHY 0x00020000 /* 5 GHz PHY available (rev >= 5) */
528 #define B43_TMSHIGH_HAVE_2GHZ_PHY 0x00010000 /* 2.4 GHz PHY available (rev >= 5) */
530 /* Generic-Interrupt reasons. */
531 #define B43_IRQ_MAC_SUSPENDED 0x00000001
532 #define B43_IRQ_BEACON 0x00000002
533 #define B43_IRQ_TBTT_INDI 0x00000004
534 #define B43_IRQ_BEACON_TX_OK 0x00000008
535 #define B43_IRQ_BEACON_CANCEL 0x00000010
536 #define B43_IRQ_ATIM_END 0x00000020
537 #define B43_IRQ_PMQ 0x00000040
538 #define B43_IRQ_PIO_WORKAROUND 0x00000100
539 #define B43_IRQ_MAC_TXERR 0x00000200
540 #define B43_IRQ_PHY_TXERR 0x00000800
541 #define B43_IRQ_PMEVENT 0x00001000
542 #define B43_IRQ_TIMER0 0x00002000
543 #define B43_IRQ_TIMER1 0x00004000
544 #define B43_IRQ_DMA 0x00008000
545 #define B43_IRQ_TXFIFO_FLUSH_OK 0x00010000
546 #define B43_IRQ_CCA_MEASURE_OK 0x00020000
547 #define B43_IRQ_NOISESAMPLE_OK 0x00040000
548 #define B43_IRQ_UCODE_DEBUG 0x08000000
549 #define B43_IRQ_RFKILL 0x10000000
550 #define B43_IRQ_TX_OK 0x20000000
551 #define B43_IRQ_PHY_G_CHANGED 0x40000000
552 #define B43_IRQ_TIMEOUT 0x80000000
554 #define B43_IRQ_ALL 0xFFFFFFFF
555 #define B43_IRQ_MASKTEMPLATE (B43_IRQ_TBTT_INDI | \
558 B43_IRQ_MAC_TXERR | \
559 B43_IRQ_PHY_TXERR | \
561 B43_IRQ_TXFIFO_FLUSH_OK | \
562 B43_IRQ_NOISESAMPLE_OK | \
563 B43_IRQ_UCODE_DEBUG | \
567 /* The firmware register to fetch the debug-IRQ reason from. */
568 #define B43_DEBUGIRQ_REASON_REG 63
569 /* Debug-IRQ reasons. */
570 #define B43_DEBUGIRQ_PANIC 0 /* The firmware panic'ed */
571 #define B43_DEBUGIRQ_DUMP_SHM 1 /* Dump shared SHM */
572 #define B43_DEBUGIRQ_DUMP_REGS 2 /* Dump the microcode registers */
573 #define B43_DEBUGIRQ_MARKER 3 /* A "marker" was thrown by the firmware. */
574 #define B43_DEBUGIRQ_ACK 0xFFFF /* The host writes that to ACK the IRQ */
576 /* The firmware register that contains the "marker" line. */
577 #define B43_MARKER_ID_REG 2
578 #define B43_MARKER_LINE_REG 3
580 /* The firmware register to fetch the panic reason from. */
581 #define B43_FWPANIC_REASON_REG 3
582 /* Firmware panic reason codes */
583 #define B43_FWPANIC_DIE 0 /* Firmware died. Don't auto-restart it. */
584 #define B43_FWPANIC_RESTART 1 /* Firmware died. Schedule a controller reset. */
586 /* The firmware register that contains the watchdog counter. */
587 #define B43_WATCHDOG_REG 1
589 /* Device specific rate values.
590 * The actual values defined here are (rate_in_mbps * 2).
591 * Some code depends on this. Don't change it. */
592 #define B43_CCK_RATE_1MB 0x02
593 #define B43_CCK_RATE_2MB 0x04
594 #define B43_CCK_RATE_5MB 0x0B
595 #define B43_CCK_RATE_11MB 0x16
596 #define B43_OFDM_RATE_6MB 0x0C
597 #define B43_OFDM_RATE_9MB 0x12
598 #define B43_OFDM_RATE_12MB 0x18
599 #define B43_OFDM_RATE_18MB 0x24
600 #define B43_OFDM_RATE_24MB 0x30
601 #define B43_OFDM_RATE_36MB 0x48
602 #define B43_OFDM_RATE_48MB 0x60
603 #define B43_OFDM_RATE_54MB 0x6C
604 /* Convert a b43 rate value to a rate in 100kbps */
605 #define B43_RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2)
607 #define B43_DEFAULT_SHORT_RETRY_LIMIT 7
608 #define B43_DEFAULT_LONG_RETRY_LIMIT 4
610 #define B43_PHY_TX_BADNESS_LIMIT 1000
612 /* Max size of a security key */
613 #define B43_SEC_KEYSIZE 16
614 /* Max number of group keys */
615 #define B43_NR_GROUP_KEYS 4
616 /* Max number of pairwise keys */
617 #define B43_NR_PAIRWISE_KEYS 50
618 /* Security algorithms. */
620 B43_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
625 B43_SEC_ALGO_AES_LEGACY,
630 /* The firmware file header */
631 #define B43_FW_TYPE_UCODE 'u'
632 #define B43_FW_TYPE_PCM 'p'
633 #define B43_FW_TYPE_IV 'i'
634 struct b43_fw_header {
637 /* File format version */
640 /* Size of the data. For ucode and PCM this is in bytes.
641 * For IV this is number-of-ivs. */
645 /* Initial Value file format */
646 #define B43_IV_OFFSET_MASK 0x7FFF
647 #define B43_IV_32BIT 0x8000
657 /* Data structures for DMA transmission, per 80211 core. */
659 struct b43_dmaring *tx_ring_AC_BK; /* Background */
660 struct b43_dmaring *tx_ring_AC_BE; /* Best Effort */
661 struct b43_dmaring *tx_ring_AC_VI; /* Video */
662 struct b43_dmaring *tx_ring_AC_VO; /* Voice */
663 struct b43_dmaring *tx_ring_mcast; /* Multicast */
665 struct b43_dmaring *rx_ring;
667 u32 translation; /* Routing bits */
668 bool translation_in_low; /* Should translation bit go into low addr? */
669 bool parity; /* Check for parity */
672 struct b43_pio_txqueue;
673 struct b43_pio_rxqueue;
675 /* Data structures for PIO transmission, per 80211 core. */
677 struct b43_pio_txqueue *tx_queue_AC_BK; /* Background */
678 struct b43_pio_txqueue *tx_queue_AC_BE; /* Best Effort */
679 struct b43_pio_txqueue *tx_queue_AC_VI; /* Video */
680 struct b43_pio_txqueue *tx_queue_AC_VO; /* Voice */
681 struct b43_pio_txqueue *tx_queue_mcast; /* Multicast */
683 struct b43_pio_rxqueue *rx_queue;
686 /* Context information for a noise calculation (Link Quality). */
687 struct b43_noise_calculation {
688 bool calculation_running;
698 /* If keyconf is NULL, this key is disabled.
699 * keyconf is a cookie. Don't derefenrence it outside of the set_key
700 * path, because b43 doesn't own it. */
701 struct ieee80211_key_conf *keyconf;
705 /* SHM offsets to the QOS data structures for the 4 different queues. */
706 #define B43_QOS_QUEUE_NUM 4
707 #define B43_QOS_PARAMS(queue) (B43_SHM_SH_EDCFQ + \
708 (B43_NR_QOSPARAMS * sizeof(u16) * (queue)))
709 #define B43_QOS_BACKGROUND B43_QOS_PARAMS(0)
710 #define B43_QOS_BESTEFFORT B43_QOS_PARAMS(1)
711 #define B43_QOS_VIDEO B43_QOS_PARAMS(2)
712 #define B43_QOS_VOICE B43_QOS_PARAMS(3)
714 /* QOS parameter hardware data structure offsets. */
715 #define B43_NR_QOSPARAMS 16
717 B43_QOSPARAM_TXOP = 0,
727 /* QOS parameters for a queue. */
728 struct b43_qos_params {
729 /* The QOS parameters */
730 struct ieee80211_tx_queue_params p;
735 /* The type of the firmware file. */
736 enum b43_firmware_file_type {
737 B43_FWTYPE_PROPRIETARY,
738 B43_FWTYPE_OPENSOURCE,
742 /* Context data for fetching firmware. */
743 struct b43_request_fw_context {
744 /* The device we are requesting the fw for. */
745 struct b43_wldev *dev;
746 /* a pointer to the firmware object */
747 const struct firmware *blob;
748 /* The type of firmware to request. */
749 enum b43_firmware_file_type req_type;
750 /* Error messages for each firmware type. */
751 char errors[B43_NR_FWTYPES][128];
752 /* Temporary buffer for storing the firmware name. */
754 /* A fatal error occurred while requesting. Firmware request
755 * can not continue, as any other request will also fail. */
759 /* In-memory representation of a cached microcode file. */
760 struct b43_firmware_file {
761 const char *filename;
762 const struct firmware *data;
763 /* Type of the firmware file name. Note that this does only indicate
764 * the type by the firmware name. NOT the file contents.
765 * If you want to check for proprietary vs opensource, use (struct b43_firmware)->opensource
766 * instead! The (struct b43_firmware)->opensource flag is derived from the actual firmware
767 * binary code, not just the filename.
769 enum b43_firmware_file_type type;
772 enum b43_firmware_hdr_format {
778 /* Pointers to the firmware data and meta information about it. */
779 struct b43_firmware {
781 struct b43_firmware_file ucode;
783 struct b43_firmware_file pcm;
784 /* Initial MMIO values for the firmware */
785 struct b43_firmware_file initvals;
786 /* Initial MMIO values for the firmware, band-specific */
787 struct b43_firmware_file initvals_band;
789 /* Firmware revision */
791 /* Firmware patchlevel */
794 /* Format of header used by firmware */
795 enum b43_firmware_hdr_format hdr_format;
797 /* Set to true, if we are using an opensource firmware.
798 * Use this to check for proprietary vs opensource. */
800 /* Set to true, if the core needs a PCM firmware, but
801 * we failed to load one. This is always false for
802 * core rev > 10, as these don't need PCM firmware. */
803 bool pcm_request_failed;
813 /* Device (802.11 core) initialization status. */
815 B43_STAT_UNINIT = 0, /* Uninitialized. */
816 B43_STAT_INITIALIZED = 1, /* Initialized, but not started, yet. */
817 B43_STAT_STARTED = 2, /* Up and running. */
819 #define b43_status(wldev) atomic_read(&(wldev)->__init_status)
820 #define b43_set_status(wldev, stat) do { \
821 atomic_set(&(wldev)->__init_status, (stat)); \
825 /* Data structure for one wireless device (802.11 core) */
827 struct b43_bus_dev *dev;
829 /* a completion event structure needed if this call is asynchronous */
830 struct completion fw_load_complete;
832 /* The device initialization status.
833 * Use b43_status() to query. */
834 atomic_t __init_status;
836 bool bad_frames_preempt; /* Use "Bad Frames Preemption" (default off) */
837 bool dfq_valid; /* Directed frame queue valid (IBSS PS mode, ATIM) */
838 bool radio_hw_enable; /* saved state of radio hardware enabled state */
839 bool qos_enabled; /* TRUE, if QoS is used. */
840 bool hwcrypto_enabled; /* TRUE, if HW crypto acceleration is enabled. */
841 bool use_pio; /* TRUE if next init should use PIO */
843 /* PHY/Radio device. */
852 /* Use b43_using_pio_transfers() to check whether we are using
853 * DMA or PIO data transfers. */
854 bool __using_pio_transfers;
856 /* Various statistics about the physical device. */
857 struct b43_stats stats;
859 /* Reason code of the last interrupt. */
862 /* The currently active generic-interrupt mask. */
865 /* Link Quality calculation context. */
866 struct b43_noise_calculation noisecalc;
867 /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
871 struct delayed_work periodic_work;
872 unsigned int periodic_state;
874 struct work_struct restart_work;
876 /* encryption/decryption */
877 u16 ktp; /* Key table pointer */
878 struct b43_key key[B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS];
881 struct b43_firmware fw;
883 /* Devicelist in struct b43_wl (all 802.11 cores) */
884 struct list_head list;
886 /* Debugging stuff follows. */
887 #ifdef CONFIG_B43_DEBUG
888 struct b43_dfsentry *dfsentry;
889 unsigned int irq_count;
890 unsigned int irq_bit_count[32];
891 unsigned int tx_count;
892 unsigned int rx_count;
896 /* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */
898 /* Pointer to the active wireless device on this chip */
899 struct b43_wldev *current_dev;
900 /* Pointer to the ieee80211 hardware data structure */
901 struct ieee80211_hw *hw;
903 /* Global driver mutex. Every operation must run with this mutex locked. */
905 /* Hard-IRQ spinlock. This lock protects things used in the hard-IRQ
906 * handler, only. This basically is just the IRQ mask register. */
907 spinlock_t hardirq_lock;
909 /* Set this if we call ieee80211_register_hw() and check if we call
910 * ieee80211_unregister_hw(). */
913 /* We can only have one operating interface (802.11 core)
914 * at a time. General information about this interface follows.
917 struct ieee80211_vif *vif;
918 /* The MAC address of the operating interface. */
919 u8 mac_addr[ETH_ALEN];
922 /* Interface type. (NL80211_IFTYPE_XXX) */
924 /* Is the card operating in AP, STA or IBSS mode? */
927 unsigned int filter_flags;
928 /* Stats about the wireless interface */
929 struct ieee80211_low_level_stats ieee_stats;
931 #ifdef CONFIG_B43_HWRNG
933 bool rng_initialized;
934 char rng_name[30 + 1];
935 #endif /* CONFIG_B43_HWRNG */
937 bool radiotap_enabled;
940 /* The beacon we are currently using (AP or IBSS mode). */
941 struct sk_buff *current_beacon;
942 bool beacon0_uploaded;
943 bool beacon1_uploaded;
944 bool beacon_templates_virgin; /* Never wrote the templates? */
945 struct work_struct beacon_update_trigger;
946 spinlock_t beacon_lock;
948 /* The current QOS parameters for the 4 queues. */
949 struct b43_qos_params qos_params[B43_QOS_QUEUE_NUM];
951 /* Work for adjustment of the transmission power.
952 * This is scheduled when we determine that the actual TX output
953 * power doesn't match what we want. */
954 struct work_struct txpower_adjust_work;
956 /* Packet transmit work */
957 struct work_struct tx_work;
959 /* Queue of packets to be transmitted. */
960 struct sk_buff_head tx_queue[B43_QOS_QUEUE_NUM];
962 /* Flag that implement the queues stopping. */
963 bool tx_queue_stopped[B43_QOS_QUEUE_NUM];
965 /* firmware loading work */
966 struct work_struct firmware_load;
968 /* The device LEDs. */
969 struct b43_leds leds;
971 /* Kmalloc'ed scratch space for PIO TX/RX. Protected by wl->mutex. */
972 u8 pio_scratchspace[118] __attribute__((__aligned__(8)));
973 u8 pio_tailspace[4] __attribute__((__aligned__(8)));
976 static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw)
981 static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev)
983 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
984 return ssb_get_drvdata(ssb_dev);
987 /* Is the device operating in a specified mode (NL80211_IFTYPE_XXX). */
988 static inline int b43_is_mode(struct b43_wl *wl, int type)
990 return (wl->operating && wl->if_type == type);
994 * b43_current_band - Returns the currently used band.
995 * Returns one of NL80211_BAND_2GHZ and NL80211_BAND_5GHZ.
997 static inline enum nl80211_band b43_current_band(struct b43_wl *wl)
999 return wl->hw->conf.chandef.chan->band;
1002 static inline int b43_bus_may_powerdown(struct b43_wldev *wldev)
1004 return wldev->dev->bus_may_powerdown(wldev->dev);
1006 static inline int b43_bus_powerup(struct b43_wldev *wldev, bool dynamic_pctl)
1008 return wldev->dev->bus_powerup(wldev->dev, dynamic_pctl);
1010 static inline int b43_device_is_enabled(struct b43_wldev *wldev)
1012 return wldev->dev->device_is_enabled(wldev->dev);
1014 static inline void b43_device_enable(struct b43_wldev *wldev,
1015 u32 core_specific_flags)
1017 wldev->dev->device_enable(wldev->dev, core_specific_flags);
1019 static inline void b43_device_disable(struct b43_wldev *wldev,
1020 u32 core_specific_flags)
1022 wldev->dev->device_disable(wldev->dev, core_specific_flags);
1025 static inline u16 b43_read16(struct b43_wldev *dev, u16 offset)
1027 return dev->dev->read16(dev->dev, offset);
1030 static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value)
1032 dev->dev->write16(dev->dev, offset, value);
1035 /* To optimize this check for flush_writes on BCM47XX_BCMA only. */
1036 static inline void b43_write16f(struct b43_wldev *dev, u16 offset, u16 value)
1038 b43_write16(dev, offset, value);
1039 #if defined(CONFIG_BCM47XX_BCMA)
1040 if (dev->dev->flush_writes)
1041 b43_read16(dev, offset);
1045 static inline void b43_maskset16(struct b43_wldev *dev, u16 offset, u16 mask,
1048 b43_write16(dev, offset, (b43_read16(dev, offset) & mask) | set);
1051 static inline u32 b43_read32(struct b43_wldev *dev, u16 offset)
1053 return dev->dev->read32(dev->dev, offset);
1056 static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value)
1058 dev->dev->write32(dev->dev, offset, value);
1061 static inline void b43_maskset32(struct b43_wldev *dev, u16 offset, u32 mask,
1064 b43_write32(dev, offset, (b43_read32(dev, offset) & mask) | set);
1067 static inline void b43_block_read(struct b43_wldev *dev, void *buffer,
1068 size_t count, u16 offset, u8 reg_width)
1070 dev->dev->block_read(dev->dev, buffer, count, offset, reg_width);
1073 static inline void b43_block_write(struct b43_wldev *dev, const void *buffer,
1074 size_t count, u16 offset, u8 reg_width)
1076 dev->dev->block_write(dev->dev, buffer, count, offset, reg_width);
1079 static inline bool b43_using_pio_transfers(struct b43_wldev *dev)
1081 return dev->__using_pio_transfers;
1084 /* Message printing */
1085 __printf(2, 3) void b43info(struct b43_wl *wl, const char *fmt, ...);
1086 __printf(2, 3) void b43err(struct b43_wl *wl, const char *fmt, ...);
1087 __printf(2, 3) void b43warn(struct b43_wl *wl, const char *fmt, ...);
1088 __printf(2, 3) void b43dbg(struct b43_wl *wl, const char *fmt, ...);
1091 /* A WARN_ON variant that vanishes when b43 debugging is disabled.
1092 * This _also_ evaluates the arg with debugging disabled. */
1094 # define B43_WARN_ON(x) WARN_ON(x)
1096 static inline bool __b43_warn_on_dummy(bool x) { return x; }
1097 # define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x)))
1100 /* Convert an integer to a Q5.2 value */
1101 #define INT_TO_Q52(i) ((i) << 2)
1102 /* Convert a Q5.2 value to an integer (precision loss!) */
1103 #define Q52_TO_INT(q52) ((q52) >> 2)
1104 /* Macros for printing a value in Q5.2 format */
1105 #define Q52_FMT "%u.%u"
1106 #define Q52_ARG(q52) Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4)
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