drivers/net/wireless/intel/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  * Copyright(c) 2016 Intel Deutschland GmbH
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of version 2 of the GNU General Public License as
  14  * published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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  22  * along with this program; if not, write to the Free Software
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  27  * in the file called COPYING.
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  29  * Contact Information:
  30  *  Intel Linux Wireless <linuxwifi@intel.com>
  31  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  32  *
  33  * BSD LICENSE
  34  *
  35  * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
  36  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  37  * Copyright(c) 2016 Intel Deutschland GmbH
  38  * All rights reserved.
  39  *
  40  * Redistribution and use in source and binary forms, with or without
  41  * modification, are permitted provided that the following conditions
  42  * are met:
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  44  *  * Redistributions of source code must retain the above copyright
  45  *    notice, this list of conditions and the following disclaimer.
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  49  *    distribution.
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  51  *    contributors may be used to endorse or promote products derived
  52  *    from this software without specific prior written permission.
  53  *
  54  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  55  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  56  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  57  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  58  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  61  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  62  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  63  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  64  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  65  *
  66  *****************************************************************************/
  67 #include <linux/pci.h>
  68 #include <linux/pci-aspm.h>
  69 #include <linux/interrupt.h>
  70 #include <linux/debugfs.h>
  71 #include <linux/sched.h>
  72 #include <linux/bitops.h>
  73 #include <linux/gfp.h>
  74 #include <linux/vmalloc.h>
  75 #include <linux/pm_runtime.h>
  76
  77 #include "iwl-drv.h"
  78 #include "iwl-trans.h"
  79 #include "iwl-csr.h"
  80 #include "iwl-prph.h"
  81 #include "iwl-scd.h"
  82 #include "iwl-agn-hw.h"
  83 #include "iwl-fw-error-dump.h"
  84 #include "internal.h"
  85 #include "iwl-fh.h"
  86
  87 /* extended range in FW SRAM */
  88 #define IWL_FW_MEM_EXTENDED_START       0x40000
  89 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  90
  91 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
  92 {
  93         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  94
  95         if (!trans_pcie->fw_mon_page)
  96                 return;
  97
  98         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
  99                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
 100         __free_pages(trans_pcie->fw_mon_page,
 101                      get_order(trans_pcie->fw_mon_size));
 102         trans_pcie->fw_mon_page = NULL;
 103         trans_pcie->fw_mon_phys = 0;
 104         trans_pcie->fw_mon_size = 0;
 105 }
 106
 107 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
 108 {
 109         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 110         struct page *page = NULL;
 111         dma_addr_t phys;
 112         u32 size = 0;
 113         u8 power;
 114
 115         if (!max_power) {
 116                 /* default max_power is maximum */
 117                 max_power = 26;
 118         } else {
 119                 max_power += 11;
 120         }
 121
 122         if (WARN(max_power > 26,
 123                  "External buffer size for monitor is too big %d, check the FW TLV\n",
 124                  max_power))
 125                 return;
 126
 127         if (trans_pcie->fw_mon_page) {
 128                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 129                                            trans_pcie->fw_mon_size,
 130                                            DMA_FROM_DEVICE);
 131                 return;
 132         }
 133
 134         phys = 0;
 135         for (power = max_power; power >= 11; power--) {
 136                 int order;
 137
 138                 size = BIT(power);
 139                 order = get_order(size);
 140                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 141                                    order);
 142                 if (!page)
 143                         continue;
 144
 145                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 146                                     DMA_FROM_DEVICE);
 147                 if (dma_mapping_error(trans->dev, phys)) {
 148                         __free_pages(page, order);
 149                         page = NULL;
 150                         continue;
 151                 }
 152                 IWL_INFO(trans,
 153                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 154                          size, order);
 155                 break;
 156         }
 157
 158         if (WARN_ON_ONCE(!page))
 159                 return;
 160
 161         if (power != max_power)
 162                 IWL_ERR(trans,
 163                         "Sorry - debug buffer is only %luK while you requested %luK\n",
 164                         (unsigned long)BIT(power - 10),
 165                         (unsigned long)BIT(max_power - 10));
 166
 167         trans_pcie->fw_mon_page = page;
 168         trans_pcie->fw_mon_phys = phys;
 169         trans_pcie->fw_mon_size = size;
 170 }
 171
 172 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 173 {
 174         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 175                     ((reg & 0x0000ffff) | (2 << 28)));
 176         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 177 }
 178
 179 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 180 {
 181         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 182         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 183                     ((reg & 0x0000ffff) | (3 << 28)));
 184 }
 185
 186 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 187 {
 188         if (trans->cfg->apmg_not_supported)
 189                 return;
 190
 191         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 192                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 193                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 194                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 195         else
 196                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 197                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 198                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 199 }
 200
 201 /* PCI registers */
 202 #define PCI_CFG_RETRY_TIMEOUT   0x041
 203
 204 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 205 {
 206         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 207         u16 lctl;
 208         u16 cap;
 209
 210         /*
 211          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 212          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 213          * If so (likely), disable L0S, so device moves directly L0->L1;
 214          *    costs negligible amount of power savings.
 215          * If not (unlikely), enable L0S, so there is at least some
 216          *    power savings, even without L1.
 217          */
 218         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 219         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 220                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 221         else
 222                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 223         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 224
 225         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 226         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 227         dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
 228                  (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 229                  trans->ltr_enabled ? "En" : "Dis");
 230 }
 231
 232 /*
 233  * Start up NIC's basic functionality after it has been reset
 234  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 235  * NOTE:  This does not load uCode nor start the embedded processor
 236  */
 237 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 238 {
 239         int ret = 0;
 240         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 241
 242         /*
 243          * Use "set_bit" below rather than "write", to preserve any hardware
 244          * bits already set by default after reset.
 245          */
 246
 247         /* Disable L0S exit timer (platform NMI Work/Around) */
 248         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 249                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 250                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 251
 252         /*
 253          * Disable L0s without affecting L1;
 254          *  don't wait for ICH L0s (ICH bug W/A)
 255          */
 256         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 257                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 258
 259         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 260         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 261
 262         /*
 263          * Enable HAP INTA (interrupt from management bus) to
 264          * wake device's PCI Express link L1a -> L0s
 265          */
 266         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 267                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 268
 269         iwl_pcie_apm_config(trans);
 270
 271         /* Configure analog phase-lock-loop before activating to D0A */
 272         if (trans->cfg->base_params->pll_cfg)
 273                 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 274
 275         /*
 276          * Set "initialization complete" bit to move adapter from
 277          * D0U* --> D0A* (powered-up active) state.
 278          */
 279         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 280
 281         /*
 282          * Wait for clock stabilization; once stabilized, access to
 283          * device-internal resources is supported, e.g. iwl_write_prph()
 284          * and accesses to uCode SRAM.
 285          */
 286         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 287                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 288                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 289         if (ret < 0) {
 290                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 291                 goto out;
 292         }
 293
 294         if (trans->cfg->host_interrupt_operation_mode) {
 295                 /*
 296                  * This is a bit of an abuse - This is needed for 7260 / 3160
 297                  * only check host_interrupt_operation_mode even if this is
 298                  * not related to host_interrupt_operation_mode.
 299                  *
 300                  * Enable the oscillator to count wake up time for L1 exit. This
 301                  * consumes slightly more power (100uA) - but allows to be sure
 302                  * that we wake up from L1 on time.
 303                  *
 304                  * This looks weird: read twice the same register, discard the
 305                  * value, set a bit, and yet again, read that same register
 306                  * just to discard the value. But that's the way the hardware
 307                  * seems to like it.
 308                  */
 309                 iwl_read_prph(trans, OSC_CLK);
 310                 iwl_read_prph(trans, OSC_CLK);
 311                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 312                 iwl_read_prph(trans, OSC_CLK);
 313                 iwl_read_prph(trans, OSC_CLK);
 314         }
 315
 316         /*
 317          * Enable DMA clock and wait for it to stabilize.
 318          *
 319          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 320          * bits do not disable clocks.  This preserves any hardware
 321          * bits already set by default in "CLK_CTRL_REG" after reset.
 322          */
 323         if (!trans->cfg->apmg_not_supported) {
 324                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 325                                APMG_CLK_VAL_DMA_CLK_RQT);
 326                 udelay(20);
 327
 328                 /* Disable L1-Active */
 329                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 330                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 331
 332                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 333                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 334                                APMG_RTC_INT_STT_RFKILL);
 335         }
 336
 337         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 338
 339 out:
 340         return ret;
 341 }
 342
 343 /*
 344  * Enable LP XTAL to avoid HW bug where device may consume much power if
 345  * FW is not loaded after device reset. LP XTAL is disabled by default
 346  * after device HW reset. Do it only if XTAL is fed by internal source.
 347  * Configure device's "persistence" mode to avoid resetting XTAL again when
 348  * SHRD_HW_RST occurs in S3.
 349  */
 350 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 351 {
 352         int ret;
 353         u32 apmg_gp1_reg;
 354         u32 apmg_xtal_cfg_reg;
 355         u32 dl_cfg_reg;
 356
 357         /* Force XTAL ON */
 358         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 359                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 360
 361         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 362         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 363         usleep_range(1000, 2000);
 364
 365         /*
 366          * Set "initialization complete" bit to move adapter from
 367          * D0U* --> D0A* (powered-up active) state.
 368          */
 369         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 370
 371         /*
 372          * Wait for clock stabilization; once stabilized, access to
 373          * device-internal resources is possible.
 374          */
 375         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 376                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 377                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 378                            25000);
 379         if (WARN_ON(ret < 0)) {
 380                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 381                 /* Release XTAL ON request */
 382                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 383                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 384                 return;
 385         }
 386
 387         /*
 388          * Clear "disable persistence" to avoid LP XTAL resetting when
 389          * SHRD_HW_RST is applied in S3.
 390          */
 391         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 392                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 393
 394         /*
 395          * Force APMG XTAL to be active to prevent its disabling by HW
 396          * caused by APMG idle state.
 397          */
 398         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 399                                                     SHR_APMG_XTAL_CFG_REG);
 400         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 401                                  apmg_xtal_cfg_reg |
 402                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 403
 404         /*
 405          * Reset entire device again - do controller reset (results in
 406          * SHRD_HW_RST). Turn MAC off before proceeding.
 407          */
 408         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 409         usleep_range(1000, 2000);
 410
 411         /* Enable LP XTAL by indirect access through CSR */
 412         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 413         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 414                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 415                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 416
 417         /* Clear delay line clock power up */
 418         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 419         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 420                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 421
 422         /*
 423          * Enable persistence mode to avoid LP XTAL resetting when
 424          * SHRD_HW_RST is applied in S3.
 425          */
 426         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 427                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 428
 429         /*
 430          * Clear "initialization complete" bit to move adapter from
 431          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 432          */
 433         iwl_clear_bit(trans, CSR_GP_CNTRL,
 434                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 435
 436         /* Activates XTAL resources monitor */
 437         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 438                                  CSR_MONITOR_XTAL_RESOURCES);
 439
 440         /* Release XTAL ON request */
 441         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 442                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 443         udelay(10);
 444
 445         /* Release APMG XTAL */
 446         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 447                                  apmg_xtal_cfg_reg &
 448                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 449 }
 450
 451 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 452 {
 453         int ret = 0;
 454
 455         /* stop device's busmaster DMA activity */
 456         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 457
 458         ret = iwl_poll_bit(trans, CSR_RESET,
 459                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 460                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 461         if (ret < 0)
 462                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 463
 464         IWL_DEBUG_INFO(trans, "stop master\n");
 465
 466         return ret;
 467 }
 468
 469 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 470 {
 471         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 472
 473         if (op_mode_leave) {
 474                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 475                         iwl_pcie_apm_init(trans);
 476
 477                 /* inform ME that we are leaving */
 478                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 479                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 480                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 481                 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
 482                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 483                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 484                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 485                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 486                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 487                         mdelay(1);
 488                         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 489                                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 490                 }
 491                 mdelay(5);
 492         }
 493
 494         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 495
 496         /* Stop device's DMA activity */
 497         iwl_pcie_apm_stop_master(trans);
 498
 499         if (trans->cfg->lp_xtal_workaround) {
 500                 iwl_pcie_apm_lp_xtal_enable(trans);
 501                 return;
 502         }
 503
 504         /* Reset the entire device */
 505         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 506         usleep_range(1000, 2000);
 507
 508         /*
 509          * Clear "initialization complete" bit to move adapter from
 510          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 511          */
 512         iwl_clear_bit(trans, CSR_GP_CNTRL,
 513                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 514 }
 515
 516 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 517 {
 518         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 519
 520         /* nic_init */
 521         spin_lock(&trans_pcie->irq_lock);
 522         iwl_pcie_apm_init(trans);
 523
 524         spin_unlock(&trans_pcie->irq_lock);
 525
 526         iwl_pcie_set_pwr(trans, false);
 527
 528         iwl_op_mode_nic_config(trans->op_mode);
 529
 530         /* Allocate the RX queue, or reset if it is already allocated */
 531         iwl_pcie_rx_init(trans);
 532
 533         /* Allocate or reset and init all Tx and Command queues */
 534         if (iwl_pcie_tx_init(trans))
 535                 return -ENOMEM;
 536
 537         if (trans->cfg->base_params->shadow_reg_enable) {
 538                 /* enable shadow regs in HW */
 539                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 540                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 541         }
 542
 543         return 0;
 544 }
 545
 546 #define HW_READY_TIMEOUT (50)
 547
 548 /* Note: returns poll_bit return value, which is >= 0 if success */
 549 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 550 {
 551         int ret;
 552
 553         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 554                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 555
 556         /* See if we got it */
 557         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 558                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 559                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 560                            HW_READY_TIMEOUT);
 561
 562         if (ret >= 0)
 563                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 564
 565         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 566         return ret;
 567 }
 568
 569 /* Note: returns standard 0/-ERROR code */
 570 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 571 {
 572         int ret;
 573         int t = 0;
 574         int iter;
 575
 576         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 577
 578         ret = iwl_pcie_set_hw_ready(trans);
 579         /* If the card is ready, exit 0 */
 580         if (ret >= 0)
 581                 return 0;
 582
 583         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 584                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 585         usleep_range(1000, 2000);
 586
 587         for (iter = 0; iter < 10; iter++) {
 588                 /* If HW is not ready, prepare the conditions to check again */
 589                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 590                             CSR_HW_IF_CONFIG_REG_PREPARE);
 591
 592                 do {
 593                         ret = iwl_pcie_set_hw_ready(trans);
 594                         if (ret >= 0)
 595                                 return 0;
 596
 597                         usleep_range(200, 1000);
 598                         t += 200;
 599                 } while (t < 150000);
 600                 msleep(25);
 601         }
 602
 603         IWL_ERR(trans, "Couldn't prepare the card\n");
 604
 605         return ret;
 606 }
 607
 608 /*
 609  * ucode
 610  */
 611 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 612                                    dma_addr_t phy_addr, u32 byte_cnt)
 613 {
 614         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 615         unsigned long flags;
 616         int ret;
 617
 618         trans_pcie->ucode_write_complete = false;
 619
 620         if (!iwl_trans_grab_nic_access(trans, &flags))
 621                 return -EIO;
 622
 623         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 624                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 625
 626         iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 627                     dst_addr);
 628
 629         iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 630                     phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 631
 632         iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 633                     (iwl_get_dma_hi_addr(phy_addr)
 634                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 635
 636         iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 637                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
 638                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
 639                     FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 640
 641         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 642                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 643                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 644                     FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 645
 646         iwl_trans_release_nic_access(trans, &flags);
 647
 648         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 649                                  trans_pcie->ucode_write_complete, 5 * HZ);
 650         if (!ret) {
 651                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 652                 return -ETIMEDOUT;
 653         }
 654
 655         return 0;
 656 }
 657
 658 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 659                             const struct fw_desc *section)
 660 {
 661         u8 *v_addr;
 662         dma_addr_t p_addr;
 663         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 664         int ret = 0;
 665
 666         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 667                      section_num);
 668
 669         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 670                                     GFP_KERNEL | __GFP_NOWARN);
 671         if (!v_addr) {
 672                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 673                 chunk_sz = PAGE_SIZE;
 674                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 675                                             &p_addr, GFP_KERNEL);
 676                 if (!v_addr)
 677                         return -ENOMEM;
 678         }
 679
 680         for (offset = 0; offset < section->len; offset += chunk_sz) {
 681                 u32 copy_size, dst_addr;
 682                 bool extended_addr = false;
 683
 684                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 685                 dst_addr = section->offset + offset;
 686
 687                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 688                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 689                         extended_addr = true;
 690
 691                 if (extended_addr)
 692                         iwl_set_bits_prph(trans, LMPM_CHICK,
 693                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 694
 695                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 696                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 697                                                    copy_size);
 698
 699                 if (extended_addr)
 700                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 701                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 702
 703                 if (ret) {
 704                         IWL_ERR(trans,
 705                                 "Could not load the [%d] uCode section\n",
 706                                 section_num);
 707                         break;
 708                 }
 709         }
 710
 711         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 712         return ret;
 713 }
 714
 715 /*
 716  * Driver Takes the ownership on secure machine before FW load
 717  * and prevent race with the BT load.
 718  * W/A for ROM bug. (should be remove in the next Si step)
 719  */
 720 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
 721 {
 722         u32 val, loop = 1000;
 723
 724         /*
 725          * Check the RSA semaphore is accessible.
 726          * If the HW isn't locked and the rsa semaphore isn't accessible,
 727          * we are in trouble.
 728          */
 729         val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
 730         if (val & (BIT(1) | BIT(17))) {
 731                 IWL_DEBUG_INFO(trans,
 732                                "can't access the RSA semaphore it is write protected\n");
 733                 return 0;
 734         }
 735
 736         /* take ownership on the AUX IF */
 737         iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
 738         iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
 739
 740         do {
 741                 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
 742                 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
 743                 if (val == 0x1) {
 744                         iwl_write_prph(trans, RSA_ENABLE, 0);
 745                         return 0;
 746                 }
 747
 748                 udelay(10);
 749                 loop--;
 750         } while (loop > 0);
 751
 752         IWL_ERR(trans, "Failed to take ownership on secure machine\n");
 753         return -EIO;
 754 }
 755
 756 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 757                                            const struct fw_img *image,
 758                                            int cpu,
 759                                            int *first_ucode_section)
 760 {
 761         int shift_param;
 762         int i, ret = 0, sec_num = 0x1;
 763         u32 val, last_read_idx = 0;
 764
 765         if (cpu == 1) {
 766                 shift_param = 0;
 767                 *first_ucode_section = 0;
 768         } else {
 769                 shift_param = 16;
 770                 (*first_ucode_section)++;
 771         }
 772
 773         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 774                 last_read_idx = i;
 775
 776                 /*
 777                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 778                  * CPU1 to CPU2.
 779                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 780                  * CPU2 non paged to CPU2 paging sec.
 781                  */
 782                 if (!image->sec[i].data ||
 783                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 784                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 785                         IWL_DEBUG_FW(trans,
 786                                      "Break since Data not valid or Empty section, sec = %d\n",
 787                                      i);
 788                         break;
 789                 }
 790
 791                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 792                 if (ret)
 793                         return ret;
 794
 795                 /* Notify the ucode of the loaded section number and status */
 796                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 797                 val = val | (sec_num << shift_param);
 798                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 799                 sec_num = (sec_num << 1) | 0x1;
 800         }
 801
 802         *first_ucode_section = last_read_idx;
 803
 804         iwl_enable_interrupts(trans);
 805
 806         if (cpu == 1)
 807                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
 808         else
 809                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
 810
 811         return 0;
 812 }
 813
 814 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 815                                       const struct fw_img *image,
 816                                       int cpu,
 817                                       int *first_ucode_section)
 818 {
 819         int shift_param;
 820         int i, ret = 0;
 821         u32 last_read_idx = 0;
 822
 823         if (cpu == 1) {
 824                 shift_param = 0;
 825                 *first_ucode_section = 0;
 826         } else {
 827                 shift_param = 16;
 828                 (*first_ucode_section)++;
 829         }
 830
 831         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 832                 last_read_idx = i;
 833
 834                 /*
 835                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 836                  * CPU1 to CPU2.
 837                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 838                  * CPU2 non paged to CPU2 paging sec.
 839                  */
 840                 if (!image->sec[i].data ||
 841                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 842                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 843                         IWL_DEBUG_FW(trans,
 844                                      "Break since Data not valid or Empty section, sec = %d\n",
 845                                      i);
 846                         break;
 847                 }
 848
 849                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 850                 if (ret)
 851                         return ret;
 852         }
 853
 854         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 855                 iwl_set_bits_prph(trans,
 856                                   CSR_UCODE_LOAD_STATUS_ADDR,
 857                                   (LMPM_CPU_UCODE_LOADING_COMPLETED |
 858                                    LMPM_CPU_HDRS_LOADING_COMPLETED |
 859                                    LMPM_CPU_UCODE_LOADING_STARTED) <<
 860                                         shift_param);
 861
 862         *first_ucode_section = last_read_idx;
 863
 864         return 0;
 865 }
 866
 867 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
 868 {
 869         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 870         const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
 871         int i;
 872
 873         if (dest->version)
 874                 IWL_ERR(trans,
 875                         "DBG DEST version is %d - expect issues\n",
 876                         dest->version);
 877
 878         IWL_INFO(trans, "Applying debug destination %s\n",
 879                  get_fw_dbg_mode_string(dest->monitor_mode));
 880
 881         if (dest->monitor_mode == EXTERNAL_MODE)
 882                 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
 883         else
 884                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 885
 886         for (i = 0; i < trans->dbg_dest_reg_num; i++) {
 887                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 888                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 889
 890                 switch (dest->reg_ops[i].op) {
 891                 case CSR_ASSIGN:
 892                         iwl_write32(trans, addr, val);
 893                         break;
 894                 case CSR_SETBIT:
 895                         iwl_set_bit(trans, addr, BIT(val));
 896                         break;
 897                 case CSR_CLEARBIT:
 898                         iwl_clear_bit(trans, addr, BIT(val));
 899                         break;
 900                 case PRPH_ASSIGN:
 901                         iwl_write_prph(trans, addr, val);
 902                         break;
 903                 case PRPH_SETBIT:
 904                         iwl_set_bits_prph(trans, addr, BIT(val));
 905                         break;
 906                 case PRPH_CLEARBIT:
 907                         iwl_clear_bits_prph(trans, addr, BIT(val));
 908                         break;
 909                 case PRPH_BLOCKBIT:
 910                         if (iwl_read_prph(trans, addr) & BIT(val)) {
 911                                 IWL_ERR(trans,
 912                                         "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
 913                                         val, addr);
 914                                 goto monitor;
 915                         }
 916                         break;
 917                 default:
 918                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 919                                 dest->reg_ops[i].op);
 920                         break;
 921                 }
 922         }
 923
 924 monitor:
 925         if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
 926                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 927                                trans_pcie->fw_mon_phys >> dest->base_shift);
 928                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 929                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 930                                        (trans_pcie->fw_mon_phys +
 931                                         trans_pcie->fw_mon_size - 256) >>
 932                                                 dest->end_shift);
 933                 else
 934                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 935                                        (trans_pcie->fw_mon_phys +
 936                                         trans_pcie->fw_mon_size) >>
 937                                                 dest->end_shift);
 938         }
 939 }
 940
 941 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 942                                 const struct fw_img *image)
 943 {
 944         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 945         int ret = 0;
 946         int first_ucode_section;
 947
 948         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 949                      image->is_dual_cpus ? "Dual" : "Single");
 950
 951         /* load to FW the binary non secured sections of CPU1 */
 952         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
 953         if (ret)
 954                 return ret;
 955
 956         if (image->is_dual_cpus) {
 957                 /* set CPU2 header address */
 958                 iwl_write_prph(trans,
 959                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
 960                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
 961
 962                 /* load to FW the binary sections of CPU2 */
 963                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
 964                                                  &first_ucode_section);
 965                 if (ret)
 966                         return ret;
 967         }
 968
 969         /* supported for 7000 only for the moment */
 970         if (iwlwifi_mod_params.fw_monitor &&
 971             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
 972                 iwl_pcie_alloc_fw_monitor(trans, 0);
 973
 974                 if (trans_pcie->fw_mon_size) {
 975                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
 976                                        trans_pcie->fw_mon_phys >> 4);
 977                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
 978                                        (trans_pcie->fw_mon_phys +
 979                                         trans_pcie->fw_mon_size) >> 4);
 980                 }
 981         } else if (trans->dbg_dest_tlv) {
 982                 iwl_pcie_apply_destination(trans);
 983         }
 984
 985         iwl_enable_interrupts(trans);
 986
 987         /* release CPU reset */
 988         iwl_write32(trans, CSR_RESET, 0);
 989
 990         return 0;
 991 }
 992
 993 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
 994                                           const struct fw_img *image)
 995 {
 996         int ret = 0;
 997         int first_ucode_section;
 998
 999         IWL_DEBUG_FW(trans, "working with %s CPU\n",
1000                      image->is_dual_cpus ? "Dual" : "Single");
1001
1002         if (trans->dbg_dest_tlv)
1003                 iwl_pcie_apply_destination(trans);
1004
1005         /* TODO: remove in the next Si step */
1006         ret = iwl_pcie_rsa_race_bug_wa(trans);
1007         if (ret)
1008                 return ret;
1009
1010         /* configure the ucode to be ready to get the secured image */
1011         /* release CPU reset */
1012         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1013
1014         /* load to FW the binary Secured sections of CPU1 */
1015         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1016                                               &first_ucode_section);
1017         if (ret)
1018                 return ret;
1019
1020         /* load to FW the binary sections of CPU2 */
1021         return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1022                                                &first_ucode_section);
1023 }
1024
1025 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1026 {
1027         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1028         bool hw_rfkill, was_hw_rfkill;
1029
1030         lockdep_assert_held(&trans_pcie->mutex);
1031
1032         if (trans_pcie->is_down)
1033                 return;
1034
1035         trans_pcie->is_down = true;
1036
1037         was_hw_rfkill = iwl_is_rfkill_set(trans);
1038
1039         /* tell the device to stop sending interrupts */
1040         spin_lock(&trans_pcie->irq_lock);
1041         iwl_disable_interrupts(trans);
1042         spin_unlock(&trans_pcie->irq_lock);
1043
1044         /* device going down, Stop using ICT table */
1045         iwl_pcie_disable_ict(trans);
1046
1047         /*
1048          * If a HW restart happens during firmware loading,
1049          * then the firmware loading might call this function
1050          * and later it might be called again due to the
1051          * restart. So don't process again if the device is
1052          * already dead.
1053          */
1054         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1055                 IWL_DEBUG_INFO(trans,
1056                                "DEVICE_ENABLED bit was set and is now cleared\n");
1057                 iwl_pcie_tx_stop(trans);
1058                 iwl_pcie_rx_stop(trans);
1059
1060                 /* Power-down device's busmaster DMA clocks */
1061                 if (!trans->cfg->apmg_not_supported) {
1062                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1063                                        APMG_CLK_VAL_DMA_CLK_RQT);
1064                         udelay(5);
1065                 }
1066         }
1067
1068         /* Make sure (redundant) we've released our request to stay awake */
1069         iwl_clear_bit(trans, CSR_GP_CNTRL,
1070                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1071
1072         /* Stop the device, and put it in low power state */
1073         iwl_pcie_apm_stop(trans, false);
1074
1075         /* stop and reset the on-board processor */
1076         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1077         usleep_range(1000, 2000);
1078
1079         /*
1080          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1081          * This is a bug in certain verions of the hardware.
1082          * Certain devices also keep sending HW RF kill interrupt all
1083          * the time, unless the interrupt is ACKed even if the interrupt
1084          * should be masked. Re-ACK all the interrupts here.
1085          */
1086         spin_lock(&trans_pcie->irq_lock);
1087         iwl_disable_interrupts(trans);
1088         spin_unlock(&trans_pcie->irq_lock);
1089
1090         /* clear all status bits */
1091         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1092         clear_bit(STATUS_INT_ENABLED, &trans->status);
1093         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1094         clear_bit(STATUS_RFKILL, &trans->status);
1095
1096         /*
1097          * Even if we stop the HW, we still want the RF kill
1098          * interrupt
1099          */
1100         iwl_enable_rfkill_int(trans);
1101
1102         /*
1103          * Check again since the RF kill state may have changed while
1104          * all the interrupts were disabled, in this case we couldn't
1105          * receive the RF kill interrupt and update the state in the
1106          * op_mode.
1107          * Don't call the op_mode if the rkfill state hasn't changed.
1108          * This allows the op_mode to call stop_device from the rfkill
1109          * notification without endless recursion. Under very rare
1110          * circumstances, we might have a small recursion if the rfkill
1111          * state changed exactly now while we were called from stop_device.
1112          * This is very unlikely but can happen and is supported.
1113          */
1114         hw_rfkill = iwl_is_rfkill_set(trans);
1115         if (hw_rfkill)
1116                 set_bit(STATUS_RFKILL, &trans->status);
1117         else
1118                 clear_bit(STATUS_RFKILL, &trans->status);
1119         if (hw_rfkill != was_hw_rfkill)
1120                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1121
1122         /* re-take ownership to prevent other users from stealing the device */
1123         iwl_pcie_prepare_card_hw(trans);
1124 }
1125
1126 static void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1127 {
1128         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1129
1130         if (trans_pcie->msix_enabled) {
1131                 int i;
1132
1133                 for (i = 0; i < trans_pcie->allocated_vector; i++)
1134                         synchronize_irq(trans_pcie->msix_entries[i].vector);
1135         } else {
1136                 synchronize_irq(trans_pcie->pci_dev->irq);
1137         }
1138 }
1139
1140 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1141                                    const struct fw_img *fw, bool run_in_rfkill)
1142 {
1143         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1144         bool hw_rfkill;
1145         int ret;
1146
1147         /* This may fail if AMT took ownership of the device */
1148         if (iwl_pcie_prepare_card_hw(trans)) {
1149                 IWL_WARN(trans, "Exit HW not ready\n");
1150                 ret = -EIO;
1151                 goto out;
1152         }
1153
1154         iwl_enable_rfkill_int(trans);
1155
1156         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1157
1158         /*
1159          * We enabled the RF-Kill interrupt and the handler may very
1160          * well be running. Disable the interrupts to make sure no other
1161          * interrupt can be fired.
1162          */
1163         iwl_disable_interrupts(trans);
1164
1165         /* Make sure it finished running */
1166         iwl_pcie_synchronize_irqs(trans);
1167
1168         mutex_lock(&trans_pcie->mutex);
1169
1170         /* If platform's RF_KILL switch is NOT set to KILL */
1171         hw_rfkill = iwl_is_rfkill_set(trans);
1172         if (hw_rfkill)
1173                 set_bit(STATUS_RFKILL, &trans->status);
1174         else
1175                 clear_bit(STATUS_RFKILL, &trans->status);
1176         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1177         if (hw_rfkill && !run_in_rfkill) {
1178                 ret = -ERFKILL;
1179                 goto out;
1180         }
1181
1182         /* Someone called stop_device, don't try to start_fw */
1183         if (trans_pcie->is_down) {
1184                 IWL_WARN(trans,
1185                          "Can't start_fw since the HW hasn't been started\n");
1186                 ret = -EIO;
1187                 goto out;
1188         }
1189
1190         /* make sure rfkill handshake bits are cleared */
1191         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1192         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1193                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1194
1195         /* clear (again), then enable host interrupts */
1196         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1197
1198         ret = iwl_pcie_nic_init(trans);
1199         if (ret) {
1200                 IWL_ERR(trans, "Unable to init nic\n");
1201                 goto out;
1202         }
1203
1204         /*
1205          * Now, we load the firmware and don't want to be interrupted, even
1206          * by the RF-Kill interrupt (hence mask all the interrupt besides the
1207          * FH_TX interrupt which is needed to load the firmware). If the
1208          * RF-Kill switch is toggled, we will find out after having loaded
1209          * the firmware and return the proper value to the caller.
1210          */
1211         iwl_enable_fw_load_int(trans);
1212
1213         /* really make sure rfkill handshake bits are cleared */
1214         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1215         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1216
1217         /* Load the given image to the HW */
1218         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1219                 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1220         else
1221                 ret = iwl_pcie_load_given_ucode(trans, fw);
1222
1223         /* re-check RF-Kill state since we may have missed the interrupt */
1224         hw_rfkill = iwl_is_rfkill_set(trans);
1225         if (hw_rfkill)
1226                 set_bit(STATUS_RFKILL, &trans->status);
1227         else
1228                 clear_bit(STATUS_RFKILL, &trans->status);
1229
1230         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1231         if (hw_rfkill && !run_in_rfkill)
1232                 ret = -ERFKILL;
1233
1234 out:
1235         mutex_unlock(&trans_pcie->mutex);
1236         return ret;
1237 }
1238
1239 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1240 {
1241         iwl_pcie_reset_ict(trans);
1242         iwl_pcie_tx_start(trans, scd_addr);
1243 }
1244
1245 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1246 {
1247         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1248
1249         mutex_lock(&trans_pcie->mutex);
1250         _iwl_trans_pcie_stop_device(trans, low_power);
1251         mutex_unlock(&trans_pcie->mutex);
1252 }
1253
1254 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1255 {
1256         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1257                 IWL_TRANS_GET_PCIE_TRANS(trans);
1258
1259         lockdep_assert_held(&trans_pcie->mutex);
1260
1261         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1262                 _iwl_trans_pcie_stop_device(trans, true);
1263 }
1264
1265 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1266                                       bool reset)
1267 {
1268         if (!reset) {
1269                 /* Enable persistence mode to avoid reset */
1270                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1271                             CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1272         }
1273
1274         iwl_disable_interrupts(trans);
1275
1276         /*
1277          * in testing mode, the host stays awake and the
1278          * hardware won't be reset (not even partially)
1279          */
1280         if (test)
1281                 return;
1282
1283         iwl_pcie_disable_ict(trans);
1284
1285         iwl_pcie_synchronize_irqs(trans);
1286
1287         iwl_clear_bit(trans, CSR_GP_CNTRL,
1288                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1289         iwl_clear_bit(trans, CSR_GP_CNTRL,
1290                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1291
1292         iwl_pcie_enable_rx_wake(trans, false);
1293
1294         if (reset) {
1295                 /*
1296                  * reset TX queues -- some of their registers reset during S3
1297                  * so if we don't reset everything here the D3 image would try
1298                  * to execute some invalid memory upon resume
1299                  */
1300                 iwl_trans_pcie_tx_reset(trans);
1301         }
1302
1303         iwl_pcie_set_pwr(trans, true);
1304 }
1305
1306 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1307                                     enum iwl_d3_status *status,
1308                                     bool test,  bool reset)
1309 {
1310         u32 val;
1311         int ret;
1312
1313         if (test) {
1314                 iwl_enable_interrupts(trans);
1315                 *status = IWL_D3_STATUS_ALIVE;
1316                 return 0;
1317         }
1318
1319         iwl_pcie_enable_rx_wake(trans, true);
1320
1321         /*
1322          * Also enables interrupts - none will happen as the device doesn't
1323          * know we're waking it up, only when the opmode actually tells it
1324          * after this call.
1325          */
1326         iwl_pcie_reset_ict(trans);
1327         iwl_enable_interrupts(trans);
1328
1329         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1330         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1331
1332         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1333                 udelay(2);
1334
1335         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1336                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1337                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1338                            25000);
1339         if (ret < 0) {
1340                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1341                 return ret;
1342         }
1343
1344         iwl_pcie_set_pwr(trans, false);
1345
1346         if (!reset) {
1347                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1348                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1349         } else {
1350                 iwl_trans_pcie_tx_reset(trans);
1351
1352                 ret = iwl_pcie_rx_init(trans);
1353                 if (ret) {
1354                         IWL_ERR(trans,
1355                                 "Failed to resume the device (RX reset)\n");
1356                         return ret;
1357                 }
1358         }
1359
1360         val = iwl_read32(trans, CSR_RESET);
1361         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1362                 *status = IWL_D3_STATUS_RESET;
1363         else
1364                 *status = IWL_D3_STATUS_ALIVE;
1365
1366         return 0;
1367 }
1368
1369 struct iwl_causes_list {
1370         u32 cause_num;
1371         u32 mask_reg;
1372         u8 addr;
1373 };
1374
1375 static struct iwl_causes_list causes_list[] = {
1376         {MSIX_FH_INT_CAUSES_D2S_CH0_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0},
1377         {MSIX_FH_INT_CAUSES_D2S_CH1_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0x1},
1378         {MSIX_FH_INT_CAUSES_S2D,                CSR_MSIX_FH_INT_MASK_AD, 0x3},
1379         {MSIX_FH_INT_CAUSES_FH_ERR,             CSR_MSIX_FH_INT_MASK_AD, 0x5},
1380         {MSIX_HW_INT_CAUSES_REG_ALIVE,          CSR_MSIX_HW_INT_MASK_AD, 0x10},
1381         {MSIX_HW_INT_CAUSES_REG_WAKEUP,         CSR_MSIX_HW_INT_MASK_AD, 0x11},
1382         {MSIX_HW_INT_CAUSES_REG_CT_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x16},
1383         {MSIX_HW_INT_CAUSES_REG_RF_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x17},
1384         {MSIX_HW_INT_CAUSES_REG_PERIODIC,       CSR_MSIX_HW_INT_MASK_AD, 0x18},
1385         {MSIX_HW_INT_CAUSES_REG_SW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x29},
1386         {MSIX_HW_INT_CAUSES_REG_SCD,            CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1387         {MSIX_HW_INT_CAUSES_REG_FH_TX,          CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1388         {MSIX_HW_INT_CAUSES_REG_HW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1389         {MSIX_HW_INT_CAUSES_REG_HAP,            CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1390 };
1391
1392 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1393 {
1394         u32 val, max_rx_vector, i;
1395         struct iwl_trans *trans = trans_pcie->trans;
1396
1397         max_rx_vector = trans_pcie->allocated_vector - 1;
1398
1399         if (!trans_pcie->msix_enabled) {
1400                 if (trans->cfg->mq_rx_supported)
1401                         iwl_write_prph(trans, UREG_CHICK,
1402                                        UREG_CHICK_MSI_ENABLE);
1403                 return;
1404         }
1405
1406         iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1407
1408         /*
1409          * Each cause from the list above and the RX causes is represented as
1410          * a byte in the IVAR table. We access the first (N - 1) bytes and map
1411          * them to the (N - 1) vectors so these vectors will be used as rx
1412          * vectors. Then access all non rx causes and map them to the
1413          * default queue (N'th queue).
1414          */
1415         for (i = 0; i < max_rx_vector; i++) {
1416                 iwl_write8(trans, CSR_MSIX_RX_IVAR(i), MSIX_FH_INT_CAUSES_Q(i));
1417                 iwl_clear_bit(trans, CSR_MSIX_FH_INT_MASK_AD,
1418                               BIT(MSIX_FH_INT_CAUSES_Q(i)));
1419         }
1420
1421         for (i = 0; i < ARRAY_SIZE(causes_list); i++) {
1422                 val = trans_pcie->default_irq_num |
1423                         MSIX_NON_AUTO_CLEAR_CAUSE;
1424                 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val);
1425                 iwl_clear_bit(trans, causes_list[i].mask_reg,
1426                               causes_list[i].cause_num);
1427         }
1428         trans_pcie->fh_init_mask =
1429                 ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1430         trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1431         trans_pcie->hw_init_mask =
1432                 ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1433         trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1434 }
1435
1436 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1437                                         struct iwl_trans *trans)
1438 {
1439         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1440         u16 pci_cmd;
1441         int max_vector;
1442         int ret, i;
1443
1444         if (trans->cfg->mq_rx_supported) {
1445                 max_vector = min_t(u32, (num_possible_cpus() + 2),
1446                                    IWL_MAX_RX_HW_QUEUES);
1447                 for (i = 0; i < max_vector; i++)
1448                         trans_pcie->msix_entries[i].entry = i;
1449
1450                 ret = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1451                                             MSIX_MIN_INTERRUPT_VECTORS,
1452                                             max_vector);
1453                 if (ret > 1) {
1454                         IWL_DEBUG_INFO(trans,
1455                                        "Enable MSI-X allocate %d interrupt vector\n",
1456                                        ret);
1457                         trans_pcie->allocated_vector = ret;
1458                         trans_pcie->default_irq_num =
1459                                 trans_pcie->allocated_vector - 1;
1460                         trans_pcie->trans->num_rx_queues =
1461                                 trans_pcie->allocated_vector - 1;
1462                         trans_pcie->msix_enabled = true;
1463
1464                         return;
1465                 }
1466                 IWL_DEBUG_INFO(trans,
1467                                "ret = %d %s move to msi mode\n", ret,
1468                                (ret == 1) ?
1469                                "can't allocate more than 1 interrupt vector" :
1470                                "failed to enable msi-x mode");
1471                 pci_disable_msix(pdev);
1472         }
1473
1474         ret = pci_enable_msi(pdev);
1475         if (ret) {
1476                 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1477                 /* enable rfkill interrupt: hw bug w/a */
1478                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1479                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1480                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1481                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1482                 }
1483         }
1484 }
1485
1486 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1487                                       struct iwl_trans_pcie *trans_pcie)
1488 {
1489         int i, last_vector;
1490
1491         last_vector = trans_pcie->trans->num_rx_queues;
1492
1493         for (i = 0; i < trans_pcie->allocated_vector; i++) {
1494                 int ret;
1495
1496                 ret = request_threaded_irq(trans_pcie->msix_entries[i].vector,
1497                                            iwl_pcie_msix_isr,
1498                                            (i == last_vector) ?
1499                                            iwl_pcie_irq_msix_handler :
1500                                            iwl_pcie_irq_rx_msix_handler,
1501                                            IRQF_SHARED,
1502                                            DRV_NAME,
1503                                            &trans_pcie->msix_entries[i]);
1504                 if (ret) {
1505                         int j;
1506
1507                         IWL_ERR(trans_pcie->trans,
1508                                 "Error allocating IRQ %d\n", i);
1509                         for (j = 0; j < i; j++)
1510                                 free_irq(trans_pcie->msix_entries[j].vector,
1511                                          &trans_pcie->msix_entries[j]);
1512                         pci_disable_msix(pdev);
1513                         return ret;
1514                 }
1515         }
1516
1517         return 0;
1518 }
1519
1520 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1521 {
1522         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1523         bool hw_rfkill;
1524         int err;
1525
1526         lockdep_assert_held(&trans_pcie->mutex);
1527
1528         err = iwl_pcie_prepare_card_hw(trans);
1529         if (err) {
1530                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1531                 return err;
1532         }
1533
1534         /* Reset the entire device */
1535         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1536         usleep_range(1000, 2000);
1537
1538         iwl_pcie_apm_init(trans);
1539
1540         iwl_pcie_init_msix(trans_pcie);
1541         /* From now on, the op_mode will be kept updated about RF kill state */
1542         iwl_enable_rfkill_int(trans);
1543
1544         /* Set is_down to false here so that...*/
1545         trans_pcie->is_down = false;
1546
1547         hw_rfkill = iwl_is_rfkill_set(trans);
1548         if (hw_rfkill)
1549                 set_bit(STATUS_RFKILL, &trans->status);
1550         else
1551                 clear_bit(STATUS_RFKILL, &trans->status);
1552         /* ... rfkill can call stop_device and set it false if needed */
1553         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1554
1555         /* Make sure we sync here, because we'll need full access later */
1556         if (low_power)
1557                 pm_runtime_resume(trans->dev);
1558
1559         return 0;
1560 }
1561
1562 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1563 {
1564         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1565         int ret;
1566
1567         mutex_lock(&trans_pcie->mutex);
1568         ret = _iwl_trans_pcie_start_hw(trans, low_power);
1569         mutex_unlock(&trans_pcie->mutex);
1570
1571         return ret;
1572 }
1573
1574 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1575 {
1576         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1577
1578         mutex_lock(&trans_pcie->mutex);
1579
1580         /* disable interrupts - don't enable HW RF kill interrupt */
1581         spin_lock(&trans_pcie->irq_lock);
1582         iwl_disable_interrupts(trans);
1583         spin_unlock(&trans_pcie->irq_lock);
1584
1585         iwl_pcie_apm_stop(trans, true);
1586
1587         spin_lock(&trans_pcie->irq_lock);
1588         iwl_disable_interrupts(trans);
1589         spin_unlock(&trans_pcie->irq_lock);
1590
1591         iwl_pcie_disable_ict(trans);
1592
1593         mutex_unlock(&trans_pcie->mutex);
1594
1595         iwl_pcie_synchronize_irqs(trans);
1596 }
1597
1598 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1599 {
1600         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1601 }
1602
1603 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1604 {
1605         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1606 }
1607
1608 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1609 {
1610         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1611 }
1612
1613 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1614 {
1615         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1616                                ((reg & 0x000FFFFF) | (3 << 24)));
1617         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1618 }
1619
1620 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1621                                       u32 val)
1622 {
1623         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1624                                ((addr & 0x000FFFFF) | (3 << 24)));
1625         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1626 }
1627
1628 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1629                                      const struct iwl_trans_config *trans_cfg)
1630 {
1631         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1632
1633         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1634         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1635         trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1636         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1637                 trans_pcie->n_no_reclaim_cmds = 0;
1638         else
1639                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1640         if (trans_pcie->n_no_reclaim_cmds)
1641                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1642                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1643
1644         trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1645         trans_pcie->rx_page_order =
1646                 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1647
1648         trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header;
1649         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1650         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1651         trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1652
1653         trans_pcie->page_offs = trans_cfg->cb_data_offs;
1654         trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1655
1656         trans->command_groups = trans_cfg->command_groups;
1657         trans->command_groups_size = trans_cfg->command_groups_size;
1658
1659         /* Initialize NAPI here - it should be before registering to mac80211
1660          * in the opmode but after the HW struct is allocated.
1661          * As this function may be called again in some corner cases don't
1662          * do anything if NAPI was already initialized.
1663          */
1664         if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1665                 init_dummy_netdev(&trans_pcie->napi_dev);
1666 }
1667
1668 void iwl_trans_pcie_free(struct iwl_trans *trans)
1669 {
1670         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1671         int i;
1672
1673         iwl_pcie_synchronize_irqs(trans);
1674
1675         iwl_pcie_tx_free(trans);
1676         iwl_pcie_rx_free(trans);
1677
1678         if (trans_pcie->msix_enabled) {
1679                 for (i = 0; i < trans_pcie->allocated_vector; i++)
1680                         free_irq(trans_pcie->msix_entries[i].vector,
1681                                  &trans_pcie->msix_entries[i]);
1682
1683                 pci_disable_msix(trans_pcie->pci_dev);
1684                 trans_pcie->msix_enabled = false;
1685         } else {
1686                 free_irq(trans_pcie->pci_dev->irq, trans);
1687
1688                 iwl_pcie_free_ict(trans);
1689
1690                 pci_disable_msi(trans_pcie->pci_dev);
1691         }
1692         iounmap(trans_pcie->hw_base);
1693         pci_release_regions(trans_pcie->pci_dev);
1694         pci_disable_device(trans_pcie->pci_dev);
1695
1696         iwl_pcie_free_fw_monitor(trans);
1697
1698         for_each_possible_cpu(i) {
1699                 struct iwl_tso_hdr_page *p =
1700                         per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1701
1702                 if (p->page)
1703                         __free_page(p->page);
1704         }
1705
1706         free_percpu(trans_pcie->tso_hdr_page);
1707         mutex_destroy(&trans_pcie->mutex);
1708         iwl_trans_free(trans);
1709 }
1710
1711 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1712 {
1713         if (state)
1714                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1715         else
1716                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1717 }
1718
1719 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1720                                            unsigned long *flags)
1721 {
1722         int ret;
1723         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1724
1725         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1726
1727         if (trans_pcie->cmd_hold_nic_awake)
1728                 goto out;
1729
1730         /* this bit wakes up the NIC */
1731         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1732                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1733         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1734                 udelay(2);
1735
1736         /*
1737          * These bits say the device is running, and should keep running for
1738          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1739          * but they do not indicate that embedded SRAM is restored yet;
1740          * 3945 and 4965 have volatile SRAM, and must save/restore contents
1741          * to/from host DRAM when sleeping/waking for power-saving.
1742          * Each direction takes approximately 1/4 millisecond; with this
1743          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1744          * series of register accesses are expected (e.g. reading Event Log),
1745          * to keep device from sleeping.
1746          *
1747          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1748          * SRAM is okay/restored.  We don't check that here because this call
1749          * is just for hardware register access; but GP1 MAC_SLEEP check is a
1750          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1751          *
1752          * 5000 series and later (including 1000 series) have non-volatile SRAM,
1753          * and do not save/restore SRAM when power cycling.
1754          */
1755         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1756                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1757                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1758                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1759         if (unlikely(ret < 0)) {
1760                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1761                 WARN_ONCE(1,
1762                           "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1763                           iwl_read32(trans, CSR_GP_CNTRL));
1764                 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1765                 return false;
1766         }
1767
1768 out:
1769         /*
1770          * Fool sparse by faking we release the lock - sparse will
1771          * track nic_access anyway.
1772          */
1773         __release(&trans_pcie->reg_lock);
1774         return true;
1775 }
1776
1777 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1778                                               unsigned long *flags)
1779 {
1780         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1781
1782         lockdep_assert_held(&trans_pcie->reg_lock);
1783
1784         /*
1785          * Fool sparse by faking we acquiring the lock - sparse will
1786          * track nic_access anyway.
1787          */
1788         __acquire(&trans_pcie->reg_lock);
1789
1790         if (trans_pcie->cmd_hold_nic_awake)
1791                 goto out;
1792
1793         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1794                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1795         /*
1796          * Above we read the CSR_GP_CNTRL register, which will flush
1797          * any previous writes, but we need the write that clears the
1798          * MAC_ACCESS_REQ bit to be performed before any other writes
1799          * scheduled on different CPUs (after we drop reg_lock).
1800          */
1801         mmiowb();
1802 out:
1803         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1804 }
1805
1806 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1807                                    void *buf, int dwords)
1808 {
1809         unsigned long flags;
1810         int offs, ret = 0;
1811         u32 *vals = buf;
1812
1813         if (iwl_trans_grab_nic_access(trans, &flags)) {
1814                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1815                 for (offs = 0; offs < dwords; offs++)
1816                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1817                 iwl_trans_release_nic_access(trans, &flags);
1818         } else {
1819                 ret = -EBUSY;
1820         }
1821         return ret;
1822 }
1823
1824 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1825                                     const void *buf, int dwords)
1826 {
1827         unsigned long flags;
1828         int offs, ret = 0;
1829         const u32 *vals = buf;
1830
1831         if (iwl_trans_grab_nic_access(trans, &flags)) {
1832                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1833                 for (offs = 0; offs < dwords; offs++)
1834                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1835                                     vals ? vals[offs] : 0);
1836                 iwl_trans_release_nic_access(trans, &flags);
1837         } else {
1838                 ret = -EBUSY;
1839         }
1840         return ret;
1841 }
1842
1843 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1844                                             unsigned long txqs,
1845                                             bool freeze)
1846 {
1847         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1848         int queue;
1849
1850         for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1851                 struct iwl_txq *txq = &trans_pcie->txq[queue];
1852                 unsigned long now;
1853
1854                 spin_lock_bh(&txq->lock);
1855
1856                 now = jiffies;
1857
1858                 if (txq->frozen == freeze)
1859                         goto next_queue;
1860
1861                 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1862                                     freeze ? "Freezing" : "Waking", queue);
1863
1864                 txq->frozen = freeze;
1865
1866                 if (txq->q.read_ptr == txq->q.write_ptr)
1867                         goto next_queue;
1868
1869                 if (freeze) {
1870                         if (unlikely(time_after(now,
1871                                                 txq->stuck_timer.expires))) {
1872                                 /*
1873                                  * The timer should have fired, maybe it is
1874                                  * spinning right now on the lock.
1875                                  */
1876                                 goto next_queue;
1877                         }
1878                         /* remember how long until the timer fires */
1879                         txq->frozen_expiry_remainder =
1880                                 txq->stuck_timer.expires - now;
1881                         del_timer(&txq->stuck_timer);
1882                         goto next_queue;
1883                 }
1884
1885                 /*
1886                  * Wake a non-empty queue -> arm timer with the
1887                  * remainder before it froze
1888                  */
1889                 mod_timer(&txq->stuck_timer,
1890                           now + txq->frozen_expiry_remainder);
1891
1892 next_queue:
1893                 spin_unlock_bh(&txq->lock);
1894         }
1895 }
1896
1897 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
1898 {
1899         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1900         int i;
1901
1902         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
1903                 struct iwl_txq *txq = &trans_pcie->txq[i];
1904
1905                 if (i == trans_pcie->cmd_queue)
1906                         continue;
1907
1908                 spin_lock_bh(&txq->lock);
1909
1910                 if (!block && !(WARN_ON_ONCE(!txq->block))) {
1911                         txq->block--;
1912                         if (!txq->block) {
1913                                 iwl_write32(trans, HBUS_TARG_WRPTR,
1914                                             txq->q.write_ptr | (i << 8));
1915                         }
1916                 } else if (block) {
1917                         txq->block++;
1918                 }
1919
1920                 spin_unlock_bh(&txq->lock);
1921         }
1922 }
1923
1924 #define IWL_FLUSH_WAIT_MS       2000
1925
1926 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1927 {
1928         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1929         struct iwl_txq *txq;
1930         struct iwl_queue *q;
1931         int cnt;
1932         unsigned long now = jiffies;
1933         u32 scd_sram_addr;
1934         u8 buf[16];
1935         int ret = 0;
1936
1937         /* waiting for all the tx frames complete might take a while */
1938         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1939                 u8 wr_ptr;
1940
1941                 if (cnt == trans_pcie->cmd_queue)
1942                         continue;
1943                 if (!test_bit(cnt, trans_pcie->queue_used))
1944                         continue;
1945                 if (!(BIT(cnt) & txq_bm))
1946                         continue;
1947
1948                 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1949                 txq = &trans_pcie->txq[cnt];
1950                 q = &txq->q;
1951                 wr_ptr = ACCESS_ONCE(q->write_ptr);
1952
1953                 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1954                        !time_after(jiffies,
1955                                    now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1956                         u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1957
1958                         if (WARN_ONCE(wr_ptr != write_ptr,
1959                                       "WR pointer moved while flushing %d -> %d\n",
1960                                       wr_ptr, write_ptr))
1961                                 return -ETIMEDOUT;
1962                         usleep_range(1000, 2000);
1963                 }
1964
1965                 if (q->read_ptr != q->write_ptr) {
1966                         IWL_ERR(trans,
1967                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1968                         ret = -ETIMEDOUT;
1969                         break;
1970                 }
1971                 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1972         }
1973
1974         if (!ret)
1975                 return 0;
1976
1977         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1978                 txq->q.read_ptr, txq->q.write_ptr);
1979
1980         scd_sram_addr = trans_pcie->scd_base_addr +
1981                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1982         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1983
1984         iwl_print_hex_error(trans, buf, sizeof(buf));
1985
1986         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1987                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1988                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1989
1990         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1991                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1992                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1993                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1994                 u32 tbl_dw =
1995                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1996                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1997
1998                 if (cnt & 0x1)
1999                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
2000                 else
2001                         tbl_dw = tbl_dw & 0x0000FFFF;
2002
2003                 IWL_ERR(trans,
2004                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
2005                         cnt, active ? "" : "in", fifo, tbl_dw,
2006                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
2007                                 (TFD_QUEUE_SIZE_MAX - 1),
2008                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
2009         }
2010
2011         return ret;
2012 }
2013
2014 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2015                                          u32 mask, u32 value)
2016 {
2017         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2018         unsigned long flags;
2019
2020         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
2021         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2022         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
2023 }
2024
2025 static void iwl_trans_pcie_ref(struct iwl_trans *trans)
2026 {
2027         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2028
2029         if (iwlwifi_mod_params.d0i3_disable)
2030                 return;
2031
2032         pm_runtime_get(&trans_pcie->pci_dev->dev);
2033
2034 #ifdef CONFIG_PM
2035         IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2036                       atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2037 #endif /* CONFIG_PM */
2038 }
2039
2040 static void iwl_trans_pcie_unref(struct iwl_trans *trans)
2041 {
2042         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2043
2044         if (iwlwifi_mod_params.d0i3_disable)
2045                 return;
2046
2047         pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2048         pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
2049
2050 #ifdef CONFIG_PM
2051         IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2052                       atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2053 #endif /* CONFIG_PM */
2054 }
2055
2056 static const char *get_csr_string(int cmd)
2057 {
2058 #define IWL_CMD(x) case x: return #x
2059         switch (cmd) {
2060         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2061         IWL_CMD(CSR_INT_COALESCING);
2062         IWL_CMD(CSR_INT);
2063         IWL_CMD(CSR_INT_MASK);
2064         IWL_CMD(CSR_FH_INT_STATUS);
2065         IWL_CMD(CSR_GPIO_IN);
2066         IWL_CMD(CSR_RESET);
2067         IWL_CMD(CSR_GP_CNTRL);
2068         IWL_CMD(CSR_HW_REV);
2069         IWL_CMD(CSR_EEPROM_REG);
2070         IWL_CMD(CSR_EEPROM_GP);
2071         IWL_CMD(CSR_OTP_GP_REG);
2072         IWL_CMD(CSR_GIO_REG);
2073         IWL_CMD(CSR_GP_UCODE_REG);
2074         IWL_CMD(CSR_GP_DRIVER_REG);
2075         IWL_CMD(CSR_UCODE_DRV_GP1);
2076         IWL_CMD(CSR_UCODE_DRV_GP2);
2077         IWL_CMD(CSR_LED_REG);
2078         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2079         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2080         IWL_CMD(CSR_ANA_PLL_CFG);
2081         IWL_CMD(CSR_HW_REV_WA_REG);
2082         IWL_CMD(CSR_MONITOR_STATUS_REG);
2083         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2084         default:
2085                 return "UNKNOWN";
2086         }
2087 #undef IWL_CMD
2088 }
2089
2090 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2091 {
2092         int i;
2093         static const u32 csr_tbl[] = {
2094                 CSR_HW_IF_CONFIG_REG,
2095                 CSR_INT_COALESCING,
2096                 CSR_INT,
2097                 CSR_INT_MASK,
2098                 CSR_FH_INT_STATUS,
2099                 CSR_GPIO_IN,
2100                 CSR_RESET,
2101                 CSR_GP_CNTRL,
2102                 CSR_HW_REV,
2103                 CSR_EEPROM_REG,
2104                 CSR_EEPROM_GP,
2105                 CSR_OTP_GP_REG,
2106                 CSR_GIO_REG,
2107                 CSR_GP_UCODE_REG,
2108                 CSR_GP_DRIVER_REG,
2109                 CSR_UCODE_DRV_GP1,
2110                 CSR_UCODE_DRV_GP2,
2111                 CSR_LED_REG,
2112                 CSR_DRAM_INT_TBL_REG,
2113                 CSR_GIO_CHICKEN_BITS,
2114                 CSR_ANA_PLL_CFG,
2115                 CSR_MONITOR_STATUS_REG,
2116                 CSR_HW_REV_WA_REG,
2117                 CSR_DBG_HPET_MEM_REG
2118         };
2119         IWL_ERR(trans, "CSR values:\n");
2120         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2121                 "CSR_INT_PERIODIC_REG)\n");
2122         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2123                 IWL_ERR(trans, "  %25s: 0X%08x\n",
2124                         get_csr_string(csr_tbl[i]),
2125                         iwl_read32(trans, csr_tbl[i]));
2126         }
2127 }
2128
2129 #ifdef CONFIG_IWLWIFI_DEBUGFS
2130 /* create and remove of files */
2131 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
2132         if (!debugfs_create_file(#name, mode, parent, trans,            \
2133                                  &iwl_dbgfs_##name##_ops))              \
2134                 goto err;                                               \
2135 } while (0)
2136
2137 /* file operation */
2138 #define DEBUGFS_READ_FILE_OPS(name)                                     \
2139 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2140         .read = iwl_dbgfs_##name##_read,                                \
2141         .open = simple_open,                                            \
2142         .llseek = generic_file_llseek,                                  \
2143 };
2144
2145 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
2146 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2147         .write = iwl_dbgfs_##name##_write,                              \
2148         .open = simple_open,                                            \
2149         .llseek = generic_file_llseek,                                  \
2150 };
2151
2152 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
2153 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2154         .write = iwl_dbgfs_##name##_write,                              \
2155         .read = iwl_dbgfs_##name##_read,                                \
2156         .open = simple_open,                                            \
2157         .llseek = generic_file_llseek,                                  \
2158 };
2159
2160 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
2161                                        char __user *user_buf,
2162                                        size_t count, loff_t *ppos)
2163 {
2164         struct iwl_trans *trans = file->private_data;
2165         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2166         struct iwl_txq *txq;
2167         struct iwl_queue *q;
2168         char *buf;
2169         int pos = 0;
2170         int cnt;
2171         int ret;
2172         size_t bufsz;
2173
2174         bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
2175
2176         if (!trans_pcie->txq)
2177                 return -EAGAIN;
2178
2179         buf = kzalloc(bufsz, GFP_KERNEL);
2180         if (!buf)
2181                 return -ENOMEM;
2182
2183         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2184                 txq = &trans_pcie->txq[cnt];
2185                 q = &txq->q;
2186                 pos += scnprintf(buf + pos, bufsz - pos,
2187                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2188                                 cnt, q->read_ptr, q->write_ptr,
2189                                 !!test_bit(cnt, trans_pcie->queue_used),
2190                                  !!test_bit(cnt, trans_pcie->queue_stopped),
2191                                  txq->need_update, txq->frozen,
2192                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
2193         }
2194         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2195         kfree(buf);
2196         return ret;
2197 }
2198
2199 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2200                                        char __user *user_buf,
2201                                        size_t count, loff_t *ppos)
2202 {
2203         struct iwl_trans *trans = file->private_data;
2204         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2205         char *buf;
2206         int pos = 0, i, ret;
2207         size_t bufsz = sizeof(buf);
2208
2209         bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2210
2211         if (!trans_pcie->rxq)
2212                 return -EAGAIN;
2213
2214         buf = kzalloc(bufsz, GFP_KERNEL);
2215         if (!buf)
2216                 return -ENOMEM;
2217
2218         for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2219                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2220
2221                 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2222                                  i);
2223                 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2224                                  rxq->read);
2225                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2226                                  rxq->write);
2227                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2228                                  rxq->write_actual);
2229                 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2230                                  rxq->need_update);
2231                 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2232                                  rxq->free_count);
2233                 if (rxq->rb_stts) {
2234                         pos += scnprintf(buf + pos, bufsz - pos,
2235                                          "\tclosed_rb_num: %u\n",
2236                                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2237                                          0x0FFF);
2238                 } else {
2239                         pos += scnprintf(buf + pos, bufsz - pos,
2240                                          "\tclosed_rb_num: Not Allocated\n");
2241                 }
2242         }
2243         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2244         kfree(buf);
2245
2246         return ret;
2247 }
2248
2249 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2250                                         char __user *user_buf,
2251                                         size_t count, loff_t *ppos)
2252 {
2253         struct iwl_trans *trans = file->private_data;
2254         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2255         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2256
2257         int pos = 0;
2258         char *buf;
2259         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2260         ssize_t ret;
2261
2262         buf = kzalloc(bufsz, GFP_KERNEL);
2263         if (!buf)
2264                 return -ENOMEM;
2265
2266         pos += scnprintf(buf + pos, bufsz - pos,
2267                         "Interrupt Statistics Report:\n");
2268
2269         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2270                 isr_stats->hw);
2271         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2272                 isr_stats->sw);
2273         if (isr_stats->sw || isr_stats->hw) {
2274                 pos += scnprintf(buf + pos, bufsz - pos,
2275                         "\tLast Restarting Code:  0x%X\n",
2276                         isr_stats->err_code);
2277         }
2278 #ifdef CONFIG_IWLWIFI_DEBUG
2279         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2280                 isr_stats->sch);
2281         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2282                 isr_stats->alive);
2283 #endif
2284         pos += scnprintf(buf + pos, bufsz - pos,
2285                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2286
2287         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2288                 isr_stats->ctkill);
2289
2290         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2291                 isr_stats->wakeup);
2292
2293         pos += scnprintf(buf + pos, bufsz - pos,
2294                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2295
2296         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2297                 isr_stats->tx);
2298
2299         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2300                 isr_stats->unhandled);
2301
2302         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2303         kfree(buf);
2304         return ret;
2305 }
2306
2307 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2308                                          const char __user *user_buf,
2309                                          size_t count, loff_t *ppos)
2310 {
2311         struct iwl_trans *trans = file->private_data;
2312         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2313         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2314
2315         char buf[8];
2316         int buf_size;
2317         u32 reset_flag;
2318
2319         memset(buf, 0, sizeof(buf));
2320         buf_size = min(count, sizeof(buf) -  1);
2321         if (copy_from_user(buf, user_buf, buf_size))
2322                 return -EFAULT;
2323         if (sscanf(buf, "%x", &reset_flag) != 1)
2324                 return -EFAULT;
2325         if (reset_flag == 0)
2326                 memset(isr_stats, 0, sizeof(*isr_stats));
2327
2328         return count;
2329 }
2330
2331 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2332                                    const char __user *user_buf,
2333                                    size_t count, loff_t *ppos)
2334 {
2335         struct iwl_trans *trans = file->private_data;
2336         char buf[8];
2337         int buf_size;
2338         int csr;
2339
2340         memset(buf, 0, sizeof(buf));
2341         buf_size = min(count, sizeof(buf) -  1);
2342         if (copy_from_user(buf, user_buf, buf_size))
2343                 return -EFAULT;
2344         if (sscanf(buf, "%d", &csr) != 1)
2345                 return -EFAULT;
2346
2347         iwl_pcie_dump_csr(trans);
2348
2349         return count;
2350 }
2351
2352 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2353                                      char __user *user_buf,
2354                                      size_t count, loff_t *ppos)
2355 {
2356         struct iwl_trans *trans = file->private_data;
2357         char *buf = NULL;
2358         ssize_t ret;
2359
2360         ret = iwl_dump_fh(trans, &buf);
2361         if (ret < 0)
2362                 return ret;
2363         if (!buf)
2364                 return -EINVAL;
2365         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2366         kfree(buf);
2367         return ret;
2368 }
2369
2370 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2371 DEBUGFS_READ_FILE_OPS(fh_reg);
2372 DEBUGFS_READ_FILE_OPS(rx_queue);
2373 DEBUGFS_READ_FILE_OPS(tx_queue);
2374 DEBUGFS_WRITE_FILE_OPS(csr);
2375
2376 /* Create the debugfs files and directories */
2377 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2378 {
2379         struct dentry *dir = trans->dbgfs_dir;
2380
2381         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2382         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2383         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2384         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2385         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2386         return 0;
2387
2388 err:
2389         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2390         return -ENOMEM;
2391 }
2392 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2393
2394 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2395 {
2396         u32 cmdlen = 0;
2397         int i;
2398
2399         for (i = 0; i < IWL_NUM_OF_TBS; i++)
2400                 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2401
2402         return cmdlen;
2403 }
2404
2405 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2406                                    struct iwl_fw_error_dump_data **data,
2407                                    int allocated_rb_nums)
2408 {
2409         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2410         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2411         /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2412         struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2413         u32 i, r, j, rb_len = 0;
2414
2415         spin_lock(&rxq->lock);
2416
2417         r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2418
2419         for (i = rxq->read, j = 0;
2420              i != r && j < allocated_rb_nums;
2421              i = (i + 1) & RX_QUEUE_MASK, j++) {
2422                 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2423                 struct iwl_fw_error_dump_rb *rb;
2424
2425                 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2426                                DMA_FROM_DEVICE);
2427
2428                 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2429
2430                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2431                 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2432                 rb = (void *)(*data)->data;
2433                 rb->index = cpu_to_le32(i);
2434                 memcpy(rb->data, page_address(rxb->page), max_len);
2435                 /* remap the page for the free benefit */
2436                 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2437                                                      max_len,
2438                                                      DMA_FROM_DEVICE);
2439
2440                 *data = iwl_fw_error_next_data(*data);
2441         }
2442
2443         spin_unlock(&rxq->lock);
2444
2445         return rb_len;
2446 }
2447 #define IWL_CSR_TO_DUMP (0x250)
2448
2449 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2450                                    struct iwl_fw_error_dump_data **data)
2451 {
2452         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2453         __le32 *val;
2454         int i;
2455
2456         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2457         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2458         val = (void *)(*data)->data;
2459
2460         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2461                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2462
2463         *data = iwl_fw_error_next_data(*data);
2464
2465         return csr_len;
2466 }
2467
2468 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2469                                        struct iwl_fw_error_dump_data **data)
2470 {
2471         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2472         unsigned long flags;
2473         __le32 *val;
2474         int i;
2475
2476         if (!iwl_trans_grab_nic_access(trans, &flags))
2477                 return 0;
2478
2479         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2480         (*data)->len = cpu_to_le32(fh_regs_len);
2481         val = (void *)(*data)->data;
2482
2483         for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2484                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2485
2486         iwl_trans_release_nic_access(trans, &flags);
2487
2488         *data = iwl_fw_error_next_data(*data);
2489
2490         return sizeof(**data) + fh_regs_len;
2491 }
2492
2493 static u32
2494 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2495                                  struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2496                                  u32 monitor_len)
2497 {
2498         u32 buf_size_in_dwords = (monitor_len >> 2);
2499         u32 *buffer = (u32 *)fw_mon_data->data;
2500         unsigned long flags;
2501         u32 i;
2502
2503         if (!iwl_trans_grab_nic_access(trans, &flags))
2504                 return 0;
2505
2506         iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2507         for (i = 0; i < buf_size_in_dwords; i++)
2508                 buffer[i] = iwl_read_prph_no_grab(trans,
2509                                 MON_DMARB_RD_DATA_ADDR);
2510         iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2511
2512         iwl_trans_release_nic_access(trans, &flags);
2513
2514         return monitor_len;
2515 }
2516
2517 static u32
2518 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2519                             struct iwl_fw_error_dump_data **data,
2520                             u32 monitor_len)
2521 {
2522         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2523         u32 len = 0;
2524
2525         if ((trans_pcie->fw_mon_page &&
2526              trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2527             trans->dbg_dest_tlv) {
2528                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2529                 u32 base, write_ptr, wrap_cnt;
2530
2531                 /* If there was a dest TLV - use the values from there */
2532                 if (trans->dbg_dest_tlv) {
2533                         write_ptr =
2534                                 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2535                         wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2536                         base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2537                 } else {
2538                         base = MON_BUFF_BASE_ADDR;
2539                         write_ptr = MON_BUFF_WRPTR;
2540                         wrap_cnt = MON_BUFF_CYCLE_CNT;
2541                 }
2542
2543                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2544                 fw_mon_data = (void *)(*data)->data;
2545                 fw_mon_data->fw_mon_wr_ptr =
2546                         cpu_to_le32(iwl_read_prph(trans, write_ptr));
2547                 fw_mon_data->fw_mon_cycle_cnt =
2548                         cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2549                 fw_mon_data->fw_mon_base_ptr =
2550                         cpu_to_le32(iwl_read_prph(trans, base));
2551
2552                 len += sizeof(**data) + sizeof(*fw_mon_data);
2553                 if (trans_pcie->fw_mon_page) {
2554                         /*
2555                          * The firmware is now asserted, it won't write anything
2556                          * to the buffer. CPU can take ownership to fetch the
2557                          * data. The buffer will be handed back to the device
2558                          * before the firmware will be restarted.
2559                          */
2560                         dma_sync_single_for_cpu(trans->dev,
2561                                                 trans_pcie->fw_mon_phys,
2562                                                 trans_pcie->fw_mon_size,
2563                                                 DMA_FROM_DEVICE);
2564                         memcpy(fw_mon_data->data,
2565                                page_address(trans_pcie->fw_mon_page),
2566                                trans_pcie->fw_mon_size);
2567
2568                         monitor_len = trans_pcie->fw_mon_size;
2569                 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2570                         /*
2571                          * Update pointers to reflect actual values after
2572                          * shifting
2573                          */
2574                         base = iwl_read_prph(trans, base) <<
2575                                trans->dbg_dest_tlv->base_shift;
2576                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
2577                                            monitor_len / sizeof(u32));
2578                 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2579                         monitor_len =
2580                                 iwl_trans_pci_dump_marbh_monitor(trans,
2581                                                                  fw_mon_data,
2582                                                                  monitor_len);
2583                 } else {
2584                         /* Didn't match anything - output no monitor data */
2585                         monitor_len = 0;
2586                 }
2587
2588                 len += monitor_len;
2589                 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2590         }
2591
2592         return len;
2593 }
2594
2595 static struct iwl_trans_dump_data
2596 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
2597                           const struct iwl_fw_dbg_trigger_tlv *trigger)
2598 {
2599         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2600         struct iwl_fw_error_dump_data *data;
2601         struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2602         struct iwl_fw_error_dump_txcmd *txcmd;
2603         struct iwl_trans_dump_data *dump_data;
2604         u32 len, num_rbs;
2605         u32 monitor_len;
2606         int i, ptr;
2607         bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2608                         !trans->cfg->mq_rx_supported;
2609
2610         /* transport dump header */
2611         len = sizeof(*dump_data);
2612
2613         /* host commands */
2614         len += sizeof(*data) +
2615                 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2616
2617         /* FW monitor */
2618         if (trans_pcie->fw_mon_page) {
2619                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2620                        trans_pcie->fw_mon_size;
2621                 monitor_len = trans_pcie->fw_mon_size;
2622         } else if (trans->dbg_dest_tlv) {
2623                 u32 base, end;
2624
2625                 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2626                 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2627
2628                 base = iwl_read_prph(trans, base) <<
2629                        trans->dbg_dest_tlv->base_shift;
2630                 end = iwl_read_prph(trans, end) <<
2631                       trans->dbg_dest_tlv->end_shift;
2632
2633                 /* Make "end" point to the actual end */
2634                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2635                     trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2636                         end += (1 << trans->dbg_dest_tlv->end_shift);
2637                 monitor_len = end - base;
2638                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2639                        monitor_len;
2640         } else {
2641                 monitor_len = 0;
2642         }
2643
2644         if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2645                 dump_data = vzalloc(len);
2646                 if (!dump_data)
2647                         return NULL;
2648
2649                 data = (void *)dump_data->data;
2650                 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2651                 dump_data->len = len;
2652
2653                 return dump_data;
2654         }
2655
2656         /* CSR registers */
2657         len += sizeof(*data) + IWL_CSR_TO_DUMP;
2658
2659         /* FH registers */
2660         len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2661
2662         if (dump_rbs) {
2663                 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2664                 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2665                 /* RBs */
2666                 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num))
2667                                       & 0x0FFF;
2668                 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
2669                 len += num_rbs * (sizeof(*data) +
2670                                   sizeof(struct iwl_fw_error_dump_rb) +
2671                                   (PAGE_SIZE << trans_pcie->rx_page_order));
2672         }
2673
2674         dump_data = vzalloc(len);
2675         if (!dump_data)
2676                 return NULL;
2677
2678         len = 0;
2679         data = (void *)dump_data->data;
2680         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2681         txcmd = (void *)data->data;
2682         spin_lock_bh(&cmdq->lock);
2683         ptr = cmdq->q.write_ptr;
2684         for (i = 0; i < cmdq->q.n_window; i++) {
2685                 u8 idx = get_cmd_index(&cmdq->q, ptr);
2686                 u32 caplen, cmdlen;
2687
2688                 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2689                 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2690
2691                 if (cmdlen) {
2692                         len += sizeof(*txcmd) + caplen;
2693                         txcmd->cmdlen = cpu_to_le32(cmdlen);
2694                         txcmd->caplen = cpu_to_le32(caplen);
2695                         memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2696                         txcmd = (void *)((u8 *)txcmd->data + caplen);
2697                 }
2698
2699                 ptr = iwl_queue_dec_wrap(ptr);
2700         }
2701         spin_unlock_bh(&cmdq->lock);
2702
2703         data->len = cpu_to_le32(len);
2704         len += sizeof(*data);
2705         data = iwl_fw_error_next_data(data);
2706
2707         len += iwl_trans_pcie_dump_csr(trans, &data);
2708         len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2709         if (dump_rbs)
2710                 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
2711
2712         len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2713
2714         dump_data->len = len;
2715
2716         return dump_data;
2717 }
2718
2719 #ifdef CONFIG_PM_SLEEP
2720 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
2721 {
2722         if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2723                 return iwl_pci_fw_enter_d0i3(trans);
2724
2725         return 0;
2726 }
2727
2728 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
2729 {
2730         if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2731                 iwl_pci_fw_exit_d0i3(trans);
2732 }
2733 #endif /* CONFIG_PM_SLEEP */
2734
2735 static const struct iwl_trans_ops trans_ops_pcie = {
2736         .start_hw = iwl_trans_pcie_start_hw,
2737         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2738         .fw_alive = iwl_trans_pcie_fw_alive,
2739         .start_fw = iwl_trans_pcie_start_fw,
2740         .stop_device = iwl_trans_pcie_stop_device,
2741
2742         .d3_suspend = iwl_trans_pcie_d3_suspend,
2743         .d3_resume = iwl_trans_pcie_d3_resume,
2744
2745 #ifdef CONFIG_PM_SLEEP
2746         .suspend = iwl_trans_pcie_suspend,
2747         .resume = iwl_trans_pcie_resume,
2748 #endif /* CONFIG_PM_SLEEP */
2749
2750         .send_cmd = iwl_trans_pcie_send_hcmd,
2751
2752         .tx = iwl_trans_pcie_tx,
2753         .reclaim = iwl_trans_pcie_reclaim,
2754
2755         .txq_disable = iwl_trans_pcie_txq_disable,
2756         .txq_enable = iwl_trans_pcie_txq_enable,
2757
2758         .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
2759
2760         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2761         .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2762         .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
2763
2764         .write8 = iwl_trans_pcie_write8,
2765         .write32 = iwl_trans_pcie_write32,
2766         .read32 = iwl_trans_pcie_read32,
2767         .read_prph = iwl_trans_pcie_read_prph,
2768         .write_prph = iwl_trans_pcie_write_prph,
2769         .read_mem = iwl_trans_pcie_read_mem,
2770         .write_mem = iwl_trans_pcie_write_mem,
2771         .configure = iwl_trans_pcie_configure,
2772         .set_pmi = iwl_trans_pcie_set_pmi,
2773         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2774         .release_nic_access = iwl_trans_pcie_release_nic_access,
2775         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2776
2777         .ref = iwl_trans_pcie_ref,
2778         .unref = iwl_trans_pcie_unref,
2779
2780         .dump_data = iwl_trans_pcie_dump_data,
2781 };
2782
2783 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2784                                        const struct pci_device_id *ent,
2785                                        const struct iwl_cfg *cfg)
2786 {
2787         struct iwl_trans_pcie *trans_pcie;
2788         struct iwl_trans *trans;
2789         int ret, addr_size;
2790
2791         trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2792                                 &pdev->dev, cfg, &trans_ops_pcie, 0);
2793         if (!trans)
2794                 return ERR_PTR(-ENOMEM);
2795
2796         trans->max_skb_frags = IWL_PCIE_MAX_FRAGS;
2797
2798         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2799
2800         trans_pcie->trans = trans;
2801         spin_lock_init(&trans_pcie->irq_lock);
2802         spin_lock_init(&trans_pcie->reg_lock);
2803         mutex_init(&trans_pcie->mutex);
2804         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2805         trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
2806         if (!trans_pcie->tso_hdr_page) {
2807                 ret = -ENOMEM;
2808                 goto out_no_pci;
2809         }
2810
2811         ret = pci_enable_device(pdev);
2812         if (ret)
2813                 goto out_no_pci;
2814
2815         if (!cfg->base_params->pcie_l1_allowed) {
2816                 /*
2817                  * W/A - seems to solve weird behavior. We need to remove this
2818                  * if we don't want to stay in L1 all the time. This wastes a
2819                  * lot of power.
2820                  */
2821                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2822                                        PCIE_LINK_STATE_L1 |
2823                                        PCIE_LINK_STATE_CLKPM);
2824         }
2825
2826         if (cfg->mq_rx_supported)
2827                 addr_size = 64;
2828         else
2829                 addr_size = 36;
2830
2831         pci_set_master(pdev);
2832
2833         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
2834         if (!ret)
2835                 ret = pci_set_consistent_dma_mask(pdev,
2836                                                   DMA_BIT_MASK(addr_size));
2837         if (ret) {
2838                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2839                 if (!ret)
2840                         ret = pci_set_consistent_dma_mask(pdev,
2841                                                           DMA_BIT_MASK(32));
2842                 /* both attempts failed: */
2843                 if (ret) {
2844                         dev_err(&pdev->dev, "No suitable DMA available\n");
2845                         goto out_pci_disable_device;
2846                 }
2847         }
2848
2849         ret = pci_request_regions(pdev, DRV_NAME);
2850         if (ret) {
2851                 dev_err(&pdev->dev, "pci_request_regions failed\n");
2852                 goto out_pci_disable_device;
2853         }
2854
2855         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2856         if (!trans_pcie->hw_base) {
2857                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2858                 ret = -ENODEV;
2859                 goto out_pci_release_regions;
2860         }
2861
2862         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2863          * PCI Tx retries from interfering with C3 CPU state */
2864         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2865
2866         trans->dev = &pdev->dev;
2867         trans_pcie->pci_dev = pdev;
2868         iwl_disable_interrupts(trans);
2869
2870         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2871         /*
2872          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2873          * changed, and now the revision step also includes bit 0-1 (no more
2874          * "dash" value). To keep hw_rev backwards compatible - we'll store it
2875          * in the old format.
2876          */
2877         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2878                 unsigned long flags;
2879
2880                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2881                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2882
2883                 ret = iwl_pcie_prepare_card_hw(trans);
2884                 if (ret) {
2885                         IWL_WARN(trans, "Exit HW not ready\n");
2886                         goto out_pci_disable_msi;
2887                 }
2888
2889                 /*
2890                  * in-order to recognize C step driver should read chip version
2891                  * id located at the AUX bus MISC address space.
2892                  */
2893                 iwl_set_bit(trans, CSR_GP_CNTRL,
2894                             CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2895                 udelay(2);
2896
2897                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2898                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2899                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2900                                    25000);
2901                 if (ret < 0) {
2902                         IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2903                         goto out_pci_disable_msi;
2904                 }
2905
2906                 if (iwl_trans_grab_nic_access(trans, &flags)) {
2907                         u32 hw_step;
2908
2909                         hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
2910                         hw_step |= ENABLE_WFPM;
2911                         iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
2912                         hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
2913                         hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2914                         if (hw_step == 0x3)
2915                                 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2916                                                 (SILICON_C_STEP << 2);
2917                         iwl_trans_release_nic_access(trans, &flags);
2918                 }
2919         }
2920
2921         trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
2922
2923         iwl_pcie_set_interrupt_capa(pdev, trans);
2924         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2925         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2926                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2927
2928         /* Initialize the wait queue for commands */
2929         init_waitqueue_head(&trans_pcie->wait_command_queue);
2930
2931         init_waitqueue_head(&trans_pcie->d0i3_waitq);
2932
2933         if (trans_pcie->msix_enabled) {
2934                 if (iwl_pcie_init_msix_handler(pdev, trans_pcie))
2935                         goto out_pci_release_regions;
2936          } else {
2937                 ret = iwl_pcie_alloc_ict(trans);
2938                 if (ret)
2939                         goto out_pci_disable_msi;
2940
2941                 ret = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2942                                            iwl_pcie_irq_handler,
2943                                            IRQF_SHARED, DRV_NAME, trans);
2944                 if (ret) {
2945                         IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2946                         goto out_free_ict;
2947                 }
2948                 trans_pcie->inta_mask = CSR_INI_SET_MASK;
2949          }
2950
2951 #ifdef CONFIG_IWLWIFI_PCIE_RTPM
2952         trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
2953 #else
2954         trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
2955 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */
2956
2957         return trans;
2958
2959 out_free_ict:
2960         iwl_pcie_free_ict(trans);
2961 out_pci_disable_msi:
2962         pci_disable_msi(pdev);
2963 out_pci_release_regions:
2964         pci_release_regions(pdev);
2965 out_pci_disable_device:
2966         pci_disable_device(pdev);
2967 out_no_pci:
2968         free_percpu(trans_pcie->tso_hdr_page);
2969         iwl_trans_free(trans);
2970         return ERR_PTR(ret);
2971 }