drivers/net/wireless/intel/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  * Copyright(c) 2016 Intel Deutschland GmbH
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of version 2 of the GNU General Public License as
  14  * published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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  22  * along with this program; if not, write to the Free Software
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  27  * in the file called COPYING.
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  29  * Contact Information:
  30  *  Intel Linux Wireless <linuxwifi@intel.com>
  31  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  32  *
  33  * BSD LICENSE
  34  *
  35  * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
  36  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  37  * Copyright(c) 2016 Intel Deutschland GmbH
  38  * All rights reserved.
  39  *
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  41  * modification, are permitted provided that the following conditions
  42  * are met:
  43  *
  44  *  * Redistributions of source code must retain the above copyright
  45  *    notice, this list of conditions and the following disclaimer.
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  49  *    distribution.
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  51  *    contributors may be used to endorse or promote products derived
  52  *    from this software without specific prior written permission.
  53  *
  54  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  55  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  56  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  57  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  58  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  61  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  62  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  63  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  64  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  65  *
  66  *****************************************************************************/
  67 #include <linux/pci.h>
  68 #include <linux/pci-aspm.h>
  69 #include <linux/interrupt.h>
  70 #include <linux/debugfs.h>
  71 #include <linux/sched.h>
  72 #include <linux/bitops.h>
  73 #include <linux/gfp.h>
  74 #include <linux/vmalloc.h>
  75 #include <linux/pm_runtime.h>
  76
  77 #include "iwl-drv.h"
  78 #include "iwl-trans.h"
  79 #include "iwl-csr.h"
  80 #include "iwl-prph.h"
  81 #include "iwl-scd.h"
  82 #include "iwl-agn-hw.h"
  83 #include "iwl-fw-error-dump.h"
  84 #include "internal.h"
  85 #include "iwl-fh.h"
  86
  87 /* extended range in FW SRAM */
  88 #define IWL_FW_MEM_EXTENDED_START       0x40000
  89 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  90
  91 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
  92 {
  93         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  94
  95         if (!trans_pcie->fw_mon_page)
  96                 return;
  97
  98         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
  99                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
 100         __free_pages(trans_pcie->fw_mon_page,
 101                      get_order(trans_pcie->fw_mon_size));
 102         trans_pcie->fw_mon_page = NULL;
 103         trans_pcie->fw_mon_phys = 0;
 104         trans_pcie->fw_mon_size = 0;
 105 }
 106
 107 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
 108 {
 109         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 110         struct page *page = NULL;
 111         dma_addr_t phys;
 112         u32 size = 0;
 113         u8 power;
 114
 115         if (!max_power) {
 116                 /* default max_power is maximum */
 117                 max_power = 26;
 118         } else {
 119                 max_power += 11;
 120         }
 121
 122         if (WARN(max_power > 26,
 123                  "External buffer size for monitor is too big %d, check the FW TLV\n",
 124                  max_power))
 125                 return;
 126
 127         if (trans_pcie->fw_mon_page) {
 128                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 129                                            trans_pcie->fw_mon_size,
 130                                            DMA_FROM_DEVICE);
 131                 return;
 132         }
 133
 134         phys = 0;
 135         for (power = max_power; power >= 11; power--) {
 136                 int order;
 137
 138                 size = BIT(power);
 139                 order = get_order(size);
 140                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 141                                    order);
 142                 if (!page)
 143                         continue;
 144
 145                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 146                                     DMA_FROM_DEVICE);
 147                 if (dma_mapping_error(trans->dev, phys)) {
 148                         __free_pages(page, order);
 149                         page = NULL;
 150                         continue;
 151                 }
 152                 IWL_INFO(trans,
 153                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 154                          size, order);
 155                 break;
 156         }
 157
 158         if (WARN_ON_ONCE(!page))
 159                 return;
 160
 161         if (power != max_power)
 162                 IWL_ERR(trans,
 163                         "Sorry - debug buffer is only %luK while you requested %luK\n",
 164                         (unsigned long)BIT(power - 10),
 165                         (unsigned long)BIT(max_power - 10));
 166
 167         trans_pcie->fw_mon_page = page;
 168         trans_pcie->fw_mon_phys = phys;
 169         trans_pcie->fw_mon_size = size;
 170 }
 171
 172 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 173 {
 174         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 175                     ((reg & 0x0000ffff) | (2 << 28)));
 176         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 177 }
 178
 179 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 180 {
 181         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 182         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 183                     ((reg & 0x0000ffff) | (3 << 28)));
 184 }
 185
 186 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 187 {
 188         if (trans->cfg->apmg_not_supported)
 189                 return;
 190
 191         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 192                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 193                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 194                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 195         else
 196                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 197                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 198                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 199 }
 200
 201 /* PCI registers */
 202 #define PCI_CFG_RETRY_TIMEOUT   0x041
 203
 204 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 205 {
 206         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 207         u16 lctl;
 208         u16 cap;
 209
 210         /*
 211          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 212          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 213          * If so (likely), disable L0S, so device moves directly L0->L1;
 214          *    costs negligible amount of power savings.
 215          * If not (unlikely), enable L0S, so there is at least some
 216          *    power savings, even without L1.
 217          */
 218         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 219         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 220                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 221         else
 222                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 223         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 224
 225         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 226         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 227         dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
 228                  (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 229                  trans->ltr_enabled ? "En" : "Dis");
 230 }
 231
 232 /*
 233  * Start up NIC's basic functionality after it has been reset
 234  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 235  * NOTE:  This does not load uCode nor start the embedded processor
 236  */
 237 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 238 {
 239         int ret = 0;
 240         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 241
 242         /*
 243          * Use "set_bit" below rather than "write", to preserve any hardware
 244          * bits already set by default after reset.
 245          */
 246
 247         /* Disable L0S exit timer (platform NMI Work/Around) */
 248         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 249                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 250                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 251
 252         /*
 253          * Disable L0s without affecting L1;
 254          *  don't wait for ICH L0s (ICH bug W/A)
 255          */
 256         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 257                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 258
 259         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 260         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 261
 262         /*
 263          * Enable HAP INTA (interrupt from management bus) to
 264          * wake device's PCI Express link L1a -> L0s
 265          */
 266         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 267                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 268
 269         iwl_pcie_apm_config(trans);
 270
 271         /* Configure analog phase-lock-loop before activating to D0A */
 272         if (trans->cfg->base_params->pll_cfg)
 273                 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 274
 275         /*
 276          * Set "initialization complete" bit to move adapter from
 277          * D0U* --> D0A* (powered-up active) state.
 278          */
 279         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 280
 281         /*
 282          * Wait for clock stabilization; once stabilized, access to
 283          * device-internal resources is supported, e.g. iwl_write_prph()
 284          * and accesses to uCode SRAM.
 285          */
 286         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 287                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 288                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 289         if (ret < 0) {
 290                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 291                 goto out;
 292         }
 293
 294         if (trans->cfg->host_interrupt_operation_mode) {
 295                 /*
 296                  * This is a bit of an abuse - This is needed for 7260 / 3160
 297                  * only check host_interrupt_operation_mode even if this is
 298                  * not related to host_interrupt_operation_mode.
 299                  *
 300                  * Enable the oscillator to count wake up time for L1 exit. This
 301                  * consumes slightly more power (100uA) - but allows to be sure
 302                  * that we wake up from L1 on time.
 303                  *
 304                  * This looks weird: read twice the same register, discard the
 305                  * value, set a bit, and yet again, read that same register
 306                  * just to discard the value. But that's the way the hardware
 307                  * seems to like it.
 308                  */
 309                 iwl_read_prph(trans, OSC_CLK);
 310                 iwl_read_prph(trans, OSC_CLK);
 311                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 312                 iwl_read_prph(trans, OSC_CLK);
 313                 iwl_read_prph(trans, OSC_CLK);
 314         }
 315
 316         /*
 317          * Enable DMA clock and wait for it to stabilize.
 318          *
 319          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 320          * bits do not disable clocks.  This preserves any hardware
 321          * bits already set by default in "CLK_CTRL_REG" after reset.
 322          */
 323         if (!trans->cfg->apmg_not_supported) {
 324                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 325                                APMG_CLK_VAL_DMA_CLK_RQT);
 326                 udelay(20);
 327
 328                 /* Disable L1-Active */
 329                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 330                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 331
 332                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 333                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 334                                APMG_RTC_INT_STT_RFKILL);
 335         }
 336
 337         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 338
 339 out:
 340         return ret;
 341 }
 342
 343 /*
 344  * Enable LP XTAL to avoid HW bug where device may consume much power if
 345  * FW is not loaded after device reset. LP XTAL is disabled by default
 346  * after device HW reset. Do it only if XTAL is fed by internal source.
 347  * Configure device's "persistence" mode to avoid resetting XTAL again when
 348  * SHRD_HW_RST occurs in S3.
 349  */
 350 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 351 {
 352         int ret;
 353         u32 apmg_gp1_reg;
 354         u32 apmg_xtal_cfg_reg;
 355         u32 dl_cfg_reg;
 356
 357         /* Force XTAL ON */
 358         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 359                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 360
 361         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 362         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 363
 364         udelay(10);
 365
 366         /*
 367          * Set "initialization complete" bit to move adapter from
 368          * D0U* --> D0A* (powered-up active) state.
 369          */
 370         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 371
 372         /*
 373          * Wait for clock stabilization; once stabilized, access to
 374          * device-internal resources is possible.
 375          */
 376         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 377                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 378                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 379                            25000);
 380         if (WARN_ON(ret < 0)) {
 381                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 382                 /* Release XTAL ON request */
 383                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 384                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 385                 return;
 386         }
 387
 388         /*
 389          * Clear "disable persistence" to avoid LP XTAL resetting when
 390          * SHRD_HW_RST is applied in S3.
 391          */
 392         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 393                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 394
 395         /*
 396          * Force APMG XTAL to be active to prevent its disabling by HW
 397          * caused by APMG idle state.
 398          */
 399         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 400                                                     SHR_APMG_XTAL_CFG_REG);
 401         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 402                                  apmg_xtal_cfg_reg |
 403                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 404
 405         /*
 406          * Reset entire device again - do controller reset (results in
 407          * SHRD_HW_RST). Turn MAC off before proceeding.
 408          */
 409         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 410
 411         udelay(10);
 412
 413         /* Enable LP XTAL by indirect access through CSR */
 414         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 415         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 416                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 417                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 418
 419         /* Clear delay line clock power up */
 420         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 421         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 422                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 423
 424         /*
 425          * Enable persistence mode to avoid LP XTAL resetting when
 426          * SHRD_HW_RST is applied in S3.
 427          */
 428         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 429                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 430
 431         /*
 432          * Clear "initialization complete" bit to move adapter from
 433          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 434          */
 435         iwl_clear_bit(trans, CSR_GP_CNTRL,
 436                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 437
 438         /* Activates XTAL resources monitor */
 439         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 440                                  CSR_MONITOR_XTAL_RESOURCES);
 441
 442         /* Release XTAL ON request */
 443         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 444                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 445         udelay(10);
 446
 447         /* Release APMG XTAL */
 448         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 449                                  apmg_xtal_cfg_reg &
 450                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 451 }
 452
 453 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 454 {
 455         int ret = 0;
 456
 457         /* stop device's busmaster DMA activity */
 458         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 459
 460         ret = iwl_poll_bit(trans, CSR_RESET,
 461                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 462                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 463         if (ret < 0)
 464                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 465
 466         IWL_DEBUG_INFO(trans, "stop master\n");
 467
 468         return ret;
 469 }
 470
 471 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 472 {
 473         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 474
 475         if (op_mode_leave) {
 476                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 477                         iwl_pcie_apm_init(trans);
 478
 479                 /* inform ME that we are leaving */
 480                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 481                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 482                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 483                 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
 484                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 485                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 486                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 487                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 488                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 489                         mdelay(1);
 490                         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 491                                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 492                 }
 493                 mdelay(5);
 494         }
 495
 496         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 497
 498         /* Stop device's DMA activity */
 499         iwl_pcie_apm_stop_master(trans);
 500
 501         if (trans->cfg->lp_xtal_workaround) {
 502                 iwl_pcie_apm_lp_xtal_enable(trans);
 503                 return;
 504         }
 505
 506         /* Reset the entire device */
 507         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 508
 509         udelay(10);
 510
 511         /*
 512          * Clear "initialization complete" bit to move adapter from
 513          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 514          */
 515         iwl_clear_bit(trans, CSR_GP_CNTRL,
 516                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 517 }
 518
 519 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 520 {
 521         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 522
 523         /* nic_init */
 524         spin_lock(&trans_pcie->irq_lock);
 525         iwl_pcie_apm_init(trans);
 526
 527         spin_unlock(&trans_pcie->irq_lock);
 528
 529         iwl_pcie_set_pwr(trans, false);
 530
 531         iwl_op_mode_nic_config(trans->op_mode);
 532
 533         /* Allocate the RX queue, or reset if it is already allocated */
 534         iwl_pcie_rx_init(trans);
 535
 536         /* Allocate or reset and init all Tx and Command queues */
 537         if (iwl_pcie_tx_init(trans))
 538                 return -ENOMEM;
 539
 540         if (trans->cfg->base_params->shadow_reg_enable) {
 541                 /* enable shadow regs in HW */
 542                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 543                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 544         }
 545
 546         return 0;
 547 }
 548
 549 #define HW_READY_TIMEOUT (50)
 550
 551 /* Note: returns poll_bit return value, which is >= 0 if success */
 552 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 553 {
 554         int ret;
 555
 556         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 557                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 558
 559         /* See if we got it */
 560         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 561                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 562                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 563                            HW_READY_TIMEOUT);
 564
 565         if (ret >= 0)
 566                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 567
 568         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 569         return ret;
 570 }
 571
 572 /* Note: returns standard 0/-ERROR code */
 573 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 574 {
 575         int ret;
 576         int t = 0;
 577         int iter;
 578
 579         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 580
 581         ret = iwl_pcie_set_hw_ready(trans);
 582         /* If the card is ready, exit 0 */
 583         if (ret >= 0)
 584                 return 0;
 585
 586         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 587                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 588         msleep(1);
 589
 590         for (iter = 0; iter < 10; iter++) {
 591                 /* If HW is not ready, prepare the conditions to check again */
 592                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 593                             CSR_HW_IF_CONFIG_REG_PREPARE);
 594
 595                 do {
 596                         ret = iwl_pcie_set_hw_ready(trans);
 597                         if (ret >= 0)
 598                                 return 0;
 599
 600                         usleep_range(200, 1000);
 601                         t += 200;
 602                 } while (t < 150000);
 603                 msleep(25);
 604         }
 605
 606         IWL_ERR(trans, "Couldn't prepare the card\n");
 607
 608         return ret;
 609 }
 610
 611 /*
 612  * ucode
 613  */
 614 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 615                                    dma_addr_t phy_addr, u32 byte_cnt)
 616 {
 617         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 618         unsigned long flags;
 619         int ret;
 620
 621         trans_pcie->ucode_write_complete = false;
 622
 623         if (!iwl_trans_grab_nic_access(trans, &flags))
 624                 return -EIO;
 625
 626         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 627                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 628
 629         iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 630                     dst_addr);
 631
 632         iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 633                     phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 634
 635         iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 636                     (iwl_get_dma_hi_addr(phy_addr)
 637                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 638
 639         iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 640                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
 641                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
 642                     FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 643
 644         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 645                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 646                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 647                     FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 648
 649         iwl_trans_release_nic_access(trans, &flags);
 650
 651         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 652                                  trans_pcie->ucode_write_complete, 5 * HZ);
 653         if (!ret) {
 654                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 655                 return -ETIMEDOUT;
 656         }
 657
 658         return 0;
 659 }
 660
 661 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 662                             const struct fw_desc *section)
 663 {
 664         u8 *v_addr;
 665         dma_addr_t p_addr;
 666         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 667         int ret = 0;
 668
 669         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 670                      section_num);
 671
 672         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 673                                     GFP_KERNEL | __GFP_NOWARN);
 674         if (!v_addr) {
 675                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 676                 chunk_sz = PAGE_SIZE;
 677                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 678                                             &p_addr, GFP_KERNEL);
 679                 if (!v_addr)
 680                         return -ENOMEM;
 681         }
 682
 683         for (offset = 0; offset < section->len; offset += chunk_sz) {
 684                 u32 copy_size, dst_addr;
 685                 bool extended_addr = false;
 686
 687                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 688                 dst_addr = section->offset + offset;
 689
 690                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 691                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 692                         extended_addr = true;
 693
 694                 if (extended_addr)
 695                         iwl_set_bits_prph(trans, LMPM_CHICK,
 696                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 697
 698                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 699                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 700                                                    copy_size);
 701
 702                 if (extended_addr)
 703                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 704                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 705
 706                 if (ret) {
 707                         IWL_ERR(trans,
 708                                 "Could not load the [%d] uCode section\n",
 709                                 section_num);
 710                         break;
 711                 }
 712         }
 713
 714         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 715         return ret;
 716 }
 717
 718 /*
 719  * Driver Takes the ownership on secure machine before FW load
 720  * and prevent race with the BT load.
 721  * W/A for ROM bug. (should be remove in the next Si step)
 722  */
 723 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
 724 {
 725         u32 val, loop = 1000;
 726
 727         /*
 728          * Check the RSA semaphore is accessible.
 729          * If the HW isn't locked and the rsa semaphore isn't accessible,
 730          * we are in trouble.
 731          */
 732         val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
 733         if (val & (BIT(1) | BIT(17))) {
 734                 IWL_DEBUG_INFO(trans,
 735                                "can't access the RSA semaphore it is write protected\n");
 736                 return 0;
 737         }
 738
 739         /* take ownership on the AUX IF */
 740         iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
 741         iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
 742
 743         do {
 744                 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
 745                 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
 746                 if (val == 0x1) {
 747                         iwl_write_prph(trans, RSA_ENABLE, 0);
 748                         return 0;
 749                 }
 750
 751                 udelay(10);
 752                 loop--;
 753         } while (loop > 0);
 754
 755         IWL_ERR(trans, "Failed to take ownership on secure machine\n");
 756         return -EIO;
 757 }
 758
 759 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 760                                            const struct fw_img *image,
 761                                            int cpu,
 762                                            int *first_ucode_section)
 763 {
 764         int shift_param;
 765         int i, ret = 0, sec_num = 0x1;
 766         u32 val, last_read_idx = 0;
 767
 768         if (cpu == 1) {
 769                 shift_param = 0;
 770                 *first_ucode_section = 0;
 771         } else {
 772                 shift_param = 16;
 773                 (*first_ucode_section)++;
 774         }
 775
 776         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 777                 last_read_idx = i;
 778
 779                 /*
 780                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 781                  * CPU1 to CPU2.
 782                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 783                  * CPU2 non paged to CPU2 paging sec.
 784                  */
 785                 if (!image->sec[i].data ||
 786                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 787                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 788                         IWL_DEBUG_FW(trans,
 789                                      "Break since Data not valid or Empty section, sec = %d\n",
 790                                      i);
 791                         break;
 792                 }
 793
 794                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 795                 if (ret)
 796                         return ret;
 797
 798                 /* Notify the ucode of the loaded section number and status */
 799                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 800                 val = val | (sec_num << shift_param);
 801                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 802                 sec_num = (sec_num << 1) | 0x1;
 803         }
 804
 805         *first_ucode_section = last_read_idx;
 806
 807         if (cpu == 1)
 808                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
 809         else
 810                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
 811
 812         return 0;
 813 }
 814
 815 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 816                                       const struct fw_img *image,
 817                                       int cpu,
 818                                       int *first_ucode_section)
 819 {
 820         int shift_param;
 821         int i, ret = 0;
 822         u32 last_read_idx = 0;
 823
 824         if (cpu == 1) {
 825                 shift_param = 0;
 826                 *first_ucode_section = 0;
 827         } else {
 828                 shift_param = 16;
 829                 (*first_ucode_section)++;
 830         }
 831
 832         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 833                 last_read_idx = i;
 834
 835                 /*
 836                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 837                  * CPU1 to CPU2.
 838                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 839                  * CPU2 non paged to CPU2 paging sec.
 840                  */
 841                 if (!image->sec[i].data ||
 842                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 843                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 844                         IWL_DEBUG_FW(trans,
 845                                      "Break since Data not valid or Empty section, sec = %d\n",
 846                                      i);
 847                         break;
 848                 }
 849
 850                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 851                 if (ret)
 852                         return ret;
 853         }
 854
 855         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 856                 iwl_set_bits_prph(trans,
 857                                   CSR_UCODE_LOAD_STATUS_ADDR,
 858                                   (LMPM_CPU_UCODE_LOADING_COMPLETED |
 859                                    LMPM_CPU_HDRS_LOADING_COMPLETED |
 860                                    LMPM_CPU_UCODE_LOADING_STARTED) <<
 861                                         shift_param);
 862
 863         *first_ucode_section = last_read_idx;
 864
 865         return 0;
 866 }
 867
 868 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
 869 {
 870         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 871         const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
 872         int i;
 873
 874         if (dest->version)
 875                 IWL_ERR(trans,
 876                         "DBG DEST version is %d - expect issues\n",
 877                         dest->version);
 878
 879         IWL_INFO(trans, "Applying debug destination %s\n",
 880                  get_fw_dbg_mode_string(dest->monitor_mode));
 881
 882         if (dest->monitor_mode == EXTERNAL_MODE)
 883                 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
 884         else
 885                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 886
 887         for (i = 0; i < trans->dbg_dest_reg_num; i++) {
 888                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 889                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 890
 891                 switch (dest->reg_ops[i].op) {
 892                 case CSR_ASSIGN:
 893                         iwl_write32(trans, addr, val);
 894                         break;
 895                 case CSR_SETBIT:
 896                         iwl_set_bit(trans, addr, BIT(val));
 897                         break;
 898                 case CSR_CLEARBIT:
 899                         iwl_clear_bit(trans, addr, BIT(val));
 900                         break;
 901                 case PRPH_ASSIGN:
 902                         iwl_write_prph(trans, addr, val);
 903                         break;
 904                 case PRPH_SETBIT:
 905                         iwl_set_bits_prph(trans, addr, BIT(val));
 906                         break;
 907                 case PRPH_CLEARBIT:
 908                         iwl_clear_bits_prph(trans, addr, BIT(val));
 909                         break;
 910                 case PRPH_BLOCKBIT:
 911                         if (iwl_read_prph(trans, addr) & BIT(val)) {
 912                                 IWL_ERR(trans,
 913                                         "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
 914                                         val, addr);
 915                                 goto monitor;
 916                         }
 917                         break;
 918                 default:
 919                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 920                                 dest->reg_ops[i].op);
 921                         break;
 922                 }
 923         }
 924
 925 monitor:
 926         if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
 927                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 928                                trans_pcie->fw_mon_phys >> dest->base_shift);
 929                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 930                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 931                                        (trans_pcie->fw_mon_phys +
 932                                         trans_pcie->fw_mon_size - 256) >>
 933                                                 dest->end_shift);
 934                 else
 935                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 936                                        (trans_pcie->fw_mon_phys +
 937                                         trans_pcie->fw_mon_size) >>
 938                                                 dest->end_shift);
 939         }
 940 }
 941
 942 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 943                                 const struct fw_img *image)
 944 {
 945         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 946         int ret = 0;
 947         int first_ucode_section;
 948
 949         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 950                      image->is_dual_cpus ? "Dual" : "Single");
 951
 952         /* load to FW the binary non secured sections of CPU1 */
 953         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
 954         if (ret)
 955                 return ret;
 956
 957         if (image->is_dual_cpus) {
 958                 /* set CPU2 header address */
 959                 iwl_write_prph(trans,
 960                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
 961                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
 962
 963                 /* load to FW the binary sections of CPU2 */
 964                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
 965                                                  &first_ucode_section);
 966                 if (ret)
 967                         return ret;
 968         }
 969
 970         /* supported for 7000 only for the moment */
 971         if (iwlwifi_mod_params.fw_monitor &&
 972             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
 973                 iwl_pcie_alloc_fw_monitor(trans, 0);
 974
 975                 if (trans_pcie->fw_mon_size) {
 976                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
 977                                        trans_pcie->fw_mon_phys >> 4);
 978                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
 979                                        (trans_pcie->fw_mon_phys +
 980                                         trans_pcie->fw_mon_size) >> 4);
 981                 }
 982         } else if (trans->dbg_dest_tlv) {
 983                 iwl_pcie_apply_destination(trans);
 984         }
 985
 986         /* release CPU reset */
 987         iwl_write32(trans, CSR_RESET, 0);
 988
 989         return 0;
 990 }
 991
 992 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
 993                                           const struct fw_img *image)
 994 {
 995         int ret = 0;
 996         int first_ucode_section;
 997
 998         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 999                      image->is_dual_cpus ? "Dual" : "Single");
1000
1001         if (trans->dbg_dest_tlv)
1002                 iwl_pcie_apply_destination(trans);
1003
1004         /* TODO: remove in the next Si step */
1005         ret = iwl_pcie_rsa_race_bug_wa(trans);
1006         if (ret)
1007                 return ret;
1008
1009         /* configure the ucode to be ready to get the secured image */
1010         /* release CPU reset */
1011         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1012
1013         /* load to FW the binary Secured sections of CPU1 */
1014         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1015                                               &first_ucode_section);
1016         if (ret)
1017                 return ret;
1018
1019         /* load to FW the binary sections of CPU2 */
1020         return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1021                                                &first_ucode_section);
1022 }
1023
1024 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1025 {
1026         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1027         bool hw_rfkill, was_hw_rfkill;
1028
1029         lockdep_assert_held(&trans_pcie->mutex);
1030
1031         if (trans_pcie->is_down)
1032                 return;
1033
1034         trans_pcie->is_down = true;
1035
1036         was_hw_rfkill = iwl_is_rfkill_set(trans);
1037
1038         /* tell the device to stop sending interrupts */
1039         spin_lock(&trans_pcie->irq_lock);
1040         iwl_disable_interrupts(trans);
1041         spin_unlock(&trans_pcie->irq_lock);
1042
1043         /* device going down, Stop using ICT table */
1044         iwl_pcie_disable_ict(trans);
1045
1046         /*
1047          * If a HW restart happens during firmware loading,
1048          * then the firmware loading might call this function
1049          * and later it might be called again due to the
1050          * restart. So don't process again if the device is
1051          * already dead.
1052          */
1053         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1054                 IWL_DEBUG_INFO(trans,
1055                                "DEVICE_ENABLED bit was set and is now cleared\n");
1056                 iwl_pcie_tx_stop(trans);
1057                 iwl_pcie_rx_stop(trans);
1058
1059                 /* Power-down device's busmaster DMA clocks */
1060                 if (!trans->cfg->apmg_not_supported) {
1061                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1062                                        APMG_CLK_VAL_DMA_CLK_RQT);
1063                         udelay(5);
1064                 }
1065         }
1066
1067         /* Make sure (redundant) we've released our request to stay awake */
1068         iwl_clear_bit(trans, CSR_GP_CNTRL,
1069                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1070
1071         /* Stop the device, and put it in low power state */
1072         iwl_pcie_apm_stop(trans, false);
1073
1074         /* stop and reset the on-board processor */
1075         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1076         udelay(20);
1077
1078         /*
1079          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1080          * This is a bug in certain verions of the hardware.
1081          * Certain devices also keep sending HW RF kill interrupt all
1082          * the time, unless the interrupt is ACKed even if the interrupt
1083          * should be masked. Re-ACK all the interrupts here.
1084          */
1085         spin_lock(&trans_pcie->irq_lock);
1086         iwl_disable_interrupts(trans);
1087         spin_unlock(&trans_pcie->irq_lock);
1088
1089         /* clear all status bits */
1090         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1091         clear_bit(STATUS_INT_ENABLED, &trans->status);
1092         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1093         clear_bit(STATUS_RFKILL, &trans->status);
1094
1095         /*
1096          * Even if we stop the HW, we still want the RF kill
1097          * interrupt
1098          */
1099         iwl_enable_rfkill_int(trans);
1100
1101         /*
1102          * Check again since the RF kill state may have changed while
1103          * all the interrupts were disabled, in this case we couldn't
1104          * receive the RF kill interrupt and update the state in the
1105          * op_mode.
1106          * Don't call the op_mode if the rkfill state hasn't changed.
1107          * This allows the op_mode to call stop_device from the rfkill
1108          * notification without endless recursion. Under very rare
1109          * circumstances, we might have a small recursion if the rfkill
1110          * state changed exactly now while we were called from stop_device.
1111          * This is very unlikely but can happen and is supported.
1112          */
1113         hw_rfkill = iwl_is_rfkill_set(trans);
1114         if (hw_rfkill)
1115                 set_bit(STATUS_RFKILL, &trans->status);
1116         else
1117                 clear_bit(STATUS_RFKILL, &trans->status);
1118         if (hw_rfkill != was_hw_rfkill)
1119                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1120
1121         /* re-take ownership to prevent other users from stealing the device */
1122         iwl_pcie_prepare_card_hw(trans);
1123 }
1124
1125 static void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1126 {
1127         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1128
1129         if (trans_pcie->msix_enabled) {
1130                 int i;
1131
1132                 for (i = 0; i < trans_pcie->allocated_vector; i++)
1133                         synchronize_irq(trans_pcie->msix_entries[i].vector);
1134         } else {
1135                 synchronize_irq(trans_pcie->pci_dev->irq);
1136         }
1137 }
1138
1139 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1140                                    const struct fw_img *fw, bool run_in_rfkill)
1141 {
1142         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1143         bool hw_rfkill;
1144         int ret;
1145
1146         /* This may fail if AMT took ownership of the device */
1147         if (iwl_pcie_prepare_card_hw(trans)) {
1148                 IWL_WARN(trans, "Exit HW not ready\n");
1149                 ret = -EIO;
1150                 goto out;
1151         }
1152
1153         iwl_enable_rfkill_int(trans);
1154
1155         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1156
1157         /*
1158          * We enabled the RF-Kill interrupt and the handler may very
1159          * well be running. Disable the interrupts to make sure no other
1160          * interrupt can be fired.
1161          */
1162         iwl_disable_interrupts(trans);
1163
1164         /* Make sure it finished running */
1165         iwl_pcie_synchronize_irqs(trans);
1166
1167         mutex_lock(&trans_pcie->mutex);
1168
1169         /* If platform's RF_KILL switch is NOT set to KILL */
1170         hw_rfkill = iwl_is_rfkill_set(trans);
1171         if (hw_rfkill)
1172                 set_bit(STATUS_RFKILL, &trans->status);
1173         else
1174                 clear_bit(STATUS_RFKILL, &trans->status);
1175         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1176         if (hw_rfkill && !run_in_rfkill) {
1177                 ret = -ERFKILL;
1178                 goto out;
1179         }
1180
1181         /* Someone called stop_device, don't try to start_fw */
1182         if (trans_pcie->is_down) {
1183                 IWL_WARN(trans,
1184                          "Can't start_fw since the HW hasn't been started\n");
1185                 ret = -EIO;
1186                 goto out;
1187         }
1188
1189         /* make sure rfkill handshake bits are cleared */
1190         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1191         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1192                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1193
1194         /* clear (again), then enable host interrupts */
1195         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1196
1197         ret = iwl_pcie_nic_init(trans);
1198         if (ret) {
1199                 IWL_ERR(trans, "Unable to init nic\n");
1200                 goto out;
1201         }
1202
1203         /*
1204          * Now, we load the firmware and don't want to be interrupted, even
1205          * by the RF-Kill interrupt (hence mask all the interrupt besides the
1206          * FH_TX interrupt which is needed to load the firmware). If the
1207          * RF-Kill switch is toggled, we will find out after having loaded
1208          * the firmware and return the proper value to the caller.
1209          */
1210         iwl_enable_fw_load_int(trans);
1211
1212         /* really make sure rfkill handshake bits are cleared */
1213         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1214         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1215
1216         /* Load the given image to the HW */
1217         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1218                 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1219         else
1220                 ret = iwl_pcie_load_given_ucode(trans, fw);
1221         iwl_enable_interrupts(trans);
1222
1223         /* re-check RF-Kill state since we may have missed the interrupt */
1224         hw_rfkill = iwl_is_rfkill_set(trans);
1225         if (hw_rfkill)
1226                 set_bit(STATUS_RFKILL, &trans->status);
1227         else
1228                 clear_bit(STATUS_RFKILL, &trans->status);
1229
1230         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1231         if (hw_rfkill && !run_in_rfkill)
1232                 ret = -ERFKILL;
1233
1234 out:
1235         mutex_unlock(&trans_pcie->mutex);
1236         return ret;
1237 }
1238
1239 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1240 {
1241         iwl_pcie_reset_ict(trans);
1242         iwl_pcie_tx_start(trans, scd_addr);
1243 }
1244
1245 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1246 {
1247         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1248
1249         mutex_lock(&trans_pcie->mutex);
1250         _iwl_trans_pcie_stop_device(trans, low_power);
1251         mutex_unlock(&trans_pcie->mutex);
1252 }
1253
1254 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1255 {
1256         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1257                 IWL_TRANS_GET_PCIE_TRANS(trans);
1258
1259         lockdep_assert_held(&trans_pcie->mutex);
1260
1261         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1262                 _iwl_trans_pcie_stop_device(trans, true);
1263 }
1264
1265 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1266                                       bool reset)
1267 {
1268         if (!reset) {
1269                 /* Enable persistence mode to avoid reset */
1270                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1271                             CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1272         }
1273
1274         iwl_disable_interrupts(trans);
1275
1276         /*
1277          * in testing mode, the host stays awake and the
1278          * hardware won't be reset (not even partially)
1279          */
1280         if (test)
1281                 return;
1282
1283         iwl_pcie_disable_ict(trans);
1284
1285         iwl_pcie_synchronize_irqs(trans);
1286
1287         iwl_clear_bit(trans, CSR_GP_CNTRL,
1288                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1289         iwl_clear_bit(trans, CSR_GP_CNTRL,
1290                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1291
1292         if (reset) {
1293                 /*
1294                  * reset TX queues -- some of their registers reset during S3
1295                  * so if we don't reset everything here the D3 image would try
1296                  * to execute some invalid memory upon resume
1297                  */
1298                 iwl_trans_pcie_tx_reset(trans);
1299         }
1300
1301         iwl_pcie_set_pwr(trans, true);
1302 }
1303
1304 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1305                                     enum iwl_d3_status *status,
1306                                     bool test,  bool reset)
1307 {
1308         u32 val;
1309         int ret;
1310
1311         if (test) {
1312                 iwl_enable_interrupts(trans);
1313                 *status = IWL_D3_STATUS_ALIVE;
1314                 return 0;
1315         }
1316
1317         /*
1318          * Also enables interrupts - none will happen as the device doesn't
1319          * know we're waking it up, only when the opmode actually tells it
1320          * after this call.
1321          */
1322         iwl_pcie_reset_ict(trans);
1323         iwl_enable_interrupts(trans);
1324
1325         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1326         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1327
1328         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1329                 udelay(2);
1330
1331         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1332                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1333                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1334                            25000);
1335         if (ret < 0) {
1336                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1337                 return ret;
1338         }
1339
1340         iwl_pcie_set_pwr(trans, false);
1341
1342         if (!reset) {
1343                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1344                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1345         } else {
1346                 iwl_trans_pcie_tx_reset(trans);
1347
1348                 ret = iwl_pcie_rx_init(trans);
1349                 if (ret) {
1350                         IWL_ERR(trans,
1351                                 "Failed to resume the device (RX reset)\n");
1352                         return ret;
1353                 }
1354         }
1355
1356         val = iwl_read32(trans, CSR_RESET);
1357         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1358                 *status = IWL_D3_STATUS_RESET;
1359         else
1360                 *status = IWL_D3_STATUS_ALIVE;
1361
1362         return 0;
1363 }
1364
1365 struct iwl_causes_list {
1366         u32 cause_num;
1367         u32 mask_reg;
1368         u8 addr;
1369 };
1370
1371 static struct iwl_causes_list causes_list[] = {
1372         {MSIX_FH_INT_CAUSES_D2S_CH0_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0},
1373         {MSIX_FH_INT_CAUSES_D2S_CH1_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0x1},
1374         {MSIX_FH_INT_CAUSES_S2D,                CSR_MSIX_FH_INT_MASK_AD, 0x3},
1375         {MSIX_FH_INT_CAUSES_FH_ERR,             CSR_MSIX_FH_INT_MASK_AD, 0x5},
1376         {MSIX_HW_INT_CAUSES_REG_ALIVE,          CSR_MSIX_HW_INT_MASK_AD, 0x10},
1377         {MSIX_HW_INT_CAUSES_REG_WAKEUP,         CSR_MSIX_HW_INT_MASK_AD, 0x11},
1378         {MSIX_HW_INT_CAUSES_REG_CT_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x16},
1379         {MSIX_HW_INT_CAUSES_REG_RF_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x17},
1380         {MSIX_HW_INT_CAUSES_REG_PERIODIC,       CSR_MSIX_HW_INT_MASK_AD, 0x18},
1381         {MSIX_HW_INT_CAUSES_REG_SW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x29},
1382         {MSIX_HW_INT_CAUSES_REG_SCD,            CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1383         {MSIX_HW_INT_CAUSES_REG_FH_TX,          CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1384         {MSIX_HW_INT_CAUSES_REG_HW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1385         {MSIX_HW_INT_CAUSES_REG_HAP,            CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1386 };
1387
1388 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1389 {
1390         u32 val, max_rx_vector, i;
1391         struct iwl_trans *trans = trans_pcie->trans;
1392
1393         max_rx_vector = trans_pcie->allocated_vector - 1;
1394
1395         if (!trans_pcie->msix_enabled)
1396                 return;
1397
1398         iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1399
1400         /*
1401          * Each cause from the list above and the RX causes is represented as
1402          * a byte in the IVAR table. We access the first (N - 1) bytes and map
1403          * them to the (N - 1) vectors so these vectors will be used as rx
1404          * vectors. Then access all non rx causes and map them to the
1405          * default queue (N'th queue).
1406          */
1407         for (i = 0; i < max_rx_vector; i++) {
1408                 iwl_write8(trans, CSR_MSIX_RX_IVAR(i), MSIX_FH_INT_CAUSES_Q(i));
1409                 iwl_clear_bit(trans, CSR_MSIX_FH_INT_MASK_AD,
1410                               BIT(MSIX_FH_INT_CAUSES_Q(i)));
1411         }
1412
1413         for (i = 0; i < ARRAY_SIZE(causes_list); i++) {
1414                 val = trans_pcie->default_irq_num |
1415                         MSIX_NON_AUTO_CLEAR_CAUSE;
1416                 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val);
1417                 iwl_clear_bit(trans, causes_list[i].mask_reg,
1418                               causes_list[i].cause_num);
1419         }
1420         trans_pcie->fh_init_mask =
1421                 ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1422         trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1423         trans_pcie->hw_init_mask =
1424                 ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1425         trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1426 }
1427
1428 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1429                                         struct iwl_trans *trans)
1430 {
1431         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1432         u16 pci_cmd;
1433         int max_vector;
1434         int ret, i;
1435
1436         if (trans->cfg->mq_rx_supported) {
1437                 max_vector = min_t(u32, (num_possible_cpus() + 2),
1438                                    IWL_MAX_RX_HW_QUEUES);
1439                 for (i = 0; i < max_vector; i++)
1440                         trans_pcie->msix_entries[i].entry = i;
1441
1442                 ret = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1443                                             MSIX_MIN_INTERRUPT_VECTORS,
1444                                             max_vector);
1445                 if (ret > 1) {
1446                         IWL_DEBUG_INFO(trans,
1447                                        "Enable MSI-X allocate %d interrupt vector\n",
1448                                        ret);
1449                         trans_pcie->allocated_vector = ret;
1450                         trans_pcie->default_irq_num =
1451                                 trans_pcie->allocated_vector - 1;
1452                         trans_pcie->trans->num_rx_queues =
1453                                 trans_pcie->allocated_vector - 1;
1454                         trans_pcie->msix_enabled = true;
1455
1456                         return;
1457                 }
1458                 IWL_DEBUG_INFO(trans,
1459                                "ret = %d %s move to msi mode\n", ret,
1460                                (ret == 1) ?
1461                                "can't allocate more than 1 interrupt vector" :
1462                                "failed to enable msi-x mode");
1463                 pci_disable_msix(pdev);
1464         }
1465
1466         ret = pci_enable_msi(pdev);
1467         if (ret) {
1468                 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1469                 /* enable rfkill interrupt: hw bug w/a */
1470                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1471                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1472                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1473                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1474                 }
1475         }
1476 }
1477
1478 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1479                                       struct iwl_trans_pcie *trans_pcie)
1480 {
1481         int i, last_vector;
1482
1483         last_vector = trans_pcie->trans->num_rx_queues;
1484
1485         for (i = 0; i < trans_pcie->allocated_vector; i++) {
1486                 int ret;
1487
1488                 ret = request_threaded_irq(trans_pcie->msix_entries[i].vector,
1489                                            iwl_pcie_msix_isr,
1490                                            (i == last_vector) ?
1491                                            iwl_pcie_irq_msix_handler :
1492                                            iwl_pcie_irq_rx_msix_handler,
1493                                            IRQF_SHARED,
1494                                            DRV_NAME,
1495                                            &trans_pcie->msix_entries[i]);
1496                 if (ret) {
1497                         int j;
1498
1499                         IWL_ERR(trans_pcie->trans,
1500                                 "Error allocating IRQ %d\n", i);
1501                         for (j = 0; j < i; j++)
1502                                 free_irq(trans_pcie->msix_entries[j].vector,
1503                                          &trans_pcie->msix_entries[j]);
1504                         pci_disable_msix(pdev);
1505                         return ret;
1506                 }
1507         }
1508
1509         return 0;
1510 }
1511
1512 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1513 {
1514         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1515         bool hw_rfkill;
1516         int err;
1517
1518         lockdep_assert_held(&trans_pcie->mutex);
1519
1520         err = iwl_pcie_prepare_card_hw(trans);
1521         if (err) {
1522                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1523                 return err;
1524         }
1525
1526         /* Reset the entire device */
1527         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1528
1529         usleep_range(10, 15);
1530
1531         iwl_pcie_apm_init(trans);
1532
1533         iwl_pcie_init_msix(trans_pcie);
1534         /* From now on, the op_mode will be kept updated about RF kill state */
1535         iwl_enable_rfkill_int(trans);
1536
1537         /* Set is_down to false here so that...*/
1538         trans_pcie->is_down = false;
1539
1540         hw_rfkill = iwl_is_rfkill_set(trans);
1541         if (hw_rfkill)
1542                 set_bit(STATUS_RFKILL, &trans->status);
1543         else
1544                 clear_bit(STATUS_RFKILL, &trans->status);
1545         /* ... rfkill can call stop_device and set it false if needed */
1546         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1547
1548         /* Make sure we sync here, because we'll need full access later */
1549         if (low_power)
1550                 pm_runtime_resume(trans->dev);
1551
1552         return 0;
1553 }
1554
1555 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1556 {
1557         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1558         int ret;
1559
1560         mutex_lock(&trans_pcie->mutex);
1561         ret = _iwl_trans_pcie_start_hw(trans, low_power);
1562         mutex_unlock(&trans_pcie->mutex);
1563
1564         return ret;
1565 }
1566
1567 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1568 {
1569         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1570
1571         mutex_lock(&trans_pcie->mutex);
1572
1573         /* disable interrupts - don't enable HW RF kill interrupt */
1574         spin_lock(&trans_pcie->irq_lock);
1575         iwl_disable_interrupts(trans);
1576         spin_unlock(&trans_pcie->irq_lock);
1577
1578         iwl_pcie_apm_stop(trans, true);
1579
1580         spin_lock(&trans_pcie->irq_lock);
1581         iwl_disable_interrupts(trans);
1582         spin_unlock(&trans_pcie->irq_lock);
1583
1584         iwl_pcie_disable_ict(trans);
1585
1586         mutex_unlock(&trans_pcie->mutex);
1587
1588         iwl_pcie_synchronize_irqs(trans);
1589 }
1590
1591 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1592 {
1593         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1594 }
1595
1596 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1597 {
1598         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1599 }
1600
1601 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1602 {
1603         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1604 }
1605
1606 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1607 {
1608         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1609                                ((reg & 0x000FFFFF) | (3 << 24)));
1610         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1611 }
1612
1613 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1614                                       u32 val)
1615 {
1616         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1617                                ((addr & 0x000FFFFF) | (3 << 24)));
1618         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1619 }
1620
1621 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1622                                      const struct iwl_trans_config *trans_cfg)
1623 {
1624         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1625
1626         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1627         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1628         trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1629         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1630                 trans_pcie->n_no_reclaim_cmds = 0;
1631         else
1632                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1633         if (trans_pcie->n_no_reclaim_cmds)
1634                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1635                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1636
1637         trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1638         trans_pcie->rx_page_order =
1639                 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1640
1641         trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header;
1642         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1643         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1644         trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1645
1646         trans->command_groups = trans_cfg->command_groups;
1647         trans->command_groups_size = trans_cfg->command_groups_size;
1648
1649         /* Initialize NAPI here - it should be before registering to mac80211
1650          * in the opmode but after the HW struct is allocated.
1651          * As this function may be called again in some corner cases don't
1652          * do anything if NAPI was already initialized.
1653          */
1654         if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1655                 init_dummy_netdev(&trans_pcie->napi_dev);
1656 }
1657
1658 void iwl_trans_pcie_free(struct iwl_trans *trans)
1659 {
1660         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1661         int i;
1662
1663         iwl_pcie_synchronize_irqs(trans);
1664
1665         iwl_pcie_tx_free(trans);
1666         iwl_pcie_rx_free(trans);
1667
1668         if (trans_pcie->msix_enabled) {
1669                 for (i = 0; i < trans_pcie->allocated_vector; i++)
1670                         free_irq(trans_pcie->msix_entries[i].vector,
1671                                  &trans_pcie->msix_entries[i]);
1672
1673                 pci_disable_msix(trans_pcie->pci_dev);
1674                 trans_pcie->msix_enabled = false;
1675         } else {
1676                 free_irq(trans_pcie->pci_dev->irq, trans);
1677
1678                 iwl_pcie_free_ict(trans);
1679
1680                 pci_disable_msi(trans_pcie->pci_dev);
1681         }
1682         iounmap(trans_pcie->hw_base);
1683         pci_release_regions(trans_pcie->pci_dev);
1684         pci_disable_device(trans_pcie->pci_dev);
1685
1686         iwl_pcie_free_fw_monitor(trans);
1687
1688         for_each_possible_cpu(i) {
1689                 struct iwl_tso_hdr_page *p =
1690                         per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1691
1692                 if (p->page)
1693                         __free_page(p->page);
1694         }
1695
1696         free_percpu(trans_pcie->tso_hdr_page);
1697         mutex_destroy(&trans_pcie->mutex);
1698         iwl_trans_free(trans);
1699 }
1700
1701 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1702 {
1703         if (state)
1704                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1705         else
1706                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1707 }
1708
1709 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1710                                            unsigned long *flags)
1711 {
1712         int ret;
1713         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1714
1715         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1716
1717         if (trans_pcie->cmd_hold_nic_awake)
1718                 goto out;
1719
1720         /* this bit wakes up the NIC */
1721         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1722                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1723         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1724                 udelay(2);
1725
1726         /*
1727          * These bits say the device is running, and should keep running for
1728          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1729          * but they do not indicate that embedded SRAM is restored yet;
1730          * 3945 and 4965 have volatile SRAM, and must save/restore contents
1731          * to/from host DRAM when sleeping/waking for power-saving.
1732          * Each direction takes approximately 1/4 millisecond; with this
1733          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1734          * series of register accesses are expected (e.g. reading Event Log),
1735          * to keep device from sleeping.
1736          *
1737          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1738          * SRAM is okay/restored.  We don't check that here because this call
1739          * is just for hardware register access; but GP1 MAC_SLEEP check is a
1740          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1741          *
1742          * 5000 series and later (including 1000 series) have non-volatile SRAM,
1743          * and do not save/restore SRAM when power cycling.
1744          */
1745         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1746                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1747                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1748                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1749         if (unlikely(ret < 0)) {
1750                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1751                 WARN_ONCE(1,
1752                           "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1753                           iwl_read32(trans, CSR_GP_CNTRL));
1754                 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1755                 return false;
1756         }
1757
1758 out:
1759         /*
1760          * Fool sparse by faking we release the lock - sparse will
1761          * track nic_access anyway.
1762          */
1763         __release(&trans_pcie->reg_lock);
1764         return true;
1765 }
1766
1767 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1768                                               unsigned long *flags)
1769 {
1770         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1771
1772         lockdep_assert_held(&trans_pcie->reg_lock);
1773
1774         /*
1775          * Fool sparse by faking we acquiring the lock - sparse will
1776          * track nic_access anyway.
1777          */
1778         __acquire(&trans_pcie->reg_lock);
1779
1780         if (trans_pcie->cmd_hold_nic_awake)
1781                 goto out;
1782
1783         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1784                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1785         /*
1786          * Above we read the CSR_GP_CNTRL register, which will flush
1787          * any previous writes, but we need the write that clears the
1788          * MAC_ACCESS_REQ bit to be performed before any other writes
1789          * scheduled on different CPUs (after we drop reg_lock).
1790          */
1791         mmiowb();
1792 out:
1793         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1794 }
1795
1796 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1797                                    void *buf, int dwords)
1798 {
1799         unsigned long flags;
1800         int offs, ret = 0;
1801         u32 *vals = buf;
1802
1803         if (iwl_trans_grab_nic_access(trans, &flags)) {
1804                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1805                 for (offs = 0; offs < dwords; offs++)
1806                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1807                 iwl_trans_release_nic_access(trans, &flags);
1808         } else {
1809                 ret = -EBUSY;
1810         }
1811         return ret;
1812 }
1813
1814 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1815                                     const void *buf, int dwords)
1816 {
1817         unsigned long flags;
1818         int offs, ret = 0;
1819         const u32 *vals = buf;
1820
1821         if (iwl_trans_grab_nic_access(trans, &flags)) {
1822                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1823                 for (offs = 0; offs < dwords; offs++)
1824                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1825                                     vals ? vals[offs] : 0);
1826                 iwl_trans_release_nic_access(trans, &flags);
1827         } else {
1828                 ret = -EBUSY;
1829         }
1830         return ret;
1831 }
1832
1833 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1834                                             unsigned long txqs,
1835                                             bool freeze)
1836 {
1837         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1838         int queue;
1839
1840         for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1841                 struct iwl_txq *txq = &trans_pcie->txq[queue];
1842                 unsigned long now;
1843
1844                 spin_lock_bh(&txq->lock);
1845
1846                 now = jiffies;
1847
1848                 if (txq->frozen == freeze)
1849                         goto next_queue;
1850
1851                 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1852                                     freeze ? "Freezing" : "Waking", queue);
1853
1854                 txq->frozen = freeze;
1855
1856                 if (txq->q.read_ptr == txq->q.write_ptr)
1857                         goto next_queue;
1858
1859                 if (freeze) {
1860                         if (unlikely(time_after(now,
1861                                                 txq->stuck_timer.expires))) {
1862                                 /*
1863                                  * The timer should have fired, maybe it is
1864                                  * spinning right now on the lock.
1865                                  */
1866                                 goto next_queue;
1867                         }
1868                         /* remember how long until the timer fires */
1869                         txq->frozen_expiry_remainder =
1870                                 txq->stuck_timer.expires - now;
1871                         del_timer(&txq->stuck_timer);
1872                         goto next_queue;
1873                 }
1874
1875                 /*
1876                  * Wake a non-empty queue -> arm timer with the
1877                  * remainder before it froze
1878                  */
1879                 mod_timer(&txq->stuck_timer,
1880                           now + txq->frozen_expiry_remainder);
1881
1882 next_queue:
1883                 spin_unlock_bh(&txq->lock);
1884         }
1885 }
1886
1887 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
1888 {
1889         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1890         int i;
1891
1892         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
1893                 struct iwl_txq *txq = &trans_pcie->txq[i];
1894
1895                 if (i == trans_pcie->cmd_queue)
1896                         continue;
1897
1898                 spin_lock_bh(&txq->lock);
1899
1900                 if (!block && !(WARN_ON_ONCE(!txq->block))) {
1901                         txq->block--;
1902                         if (!txq->block) {
1903                                 iwl_write32(trans, HBUS_TARG_WRPTR,
1904                                             txq->q.write_ptr | (i << 8));
1905                         }
1906                 } else if (block) {
1907                         txq->block++;
1908                 }
1909
1910                 spin_unlock_bh(&txq->lock);
1911         }
1912 }
1913
1914 #define IWL_FLUSH_WAIT_MS       2000
1915
1916 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1917 {
1918         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1919         struct iwl_txq *txq;
1920         struct iwl_queue *q;
1921         int cnt;
1922         unsigned long now = jiffies;
1923         u32 scd_sram_addr;
1924         u8 buf[16];
1925         int ret = 0;
1926
1927         /* waiting for all the tx frames complete might take a while */
1928         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1929                 u8 wr_ptr;
1930
1931                 if (cnt == trans_pcie->cmd_queue)
1932                         continue;
1933                 if (!test_bit(cnt, trans_pcie->queue_used))
1934                         continue;
1935                 if (!(BIT(cnt) & txq_bm))
1936                         continue;
1937
1938                 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1939                 txq = &trans_pcie->txq[cnt];
1940                 q = &txq->q;
1941                 wr_ptr = ACCESS_ONCE(q->write_ptr);
1942
1943                 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1944                        !time_after(jiffies,
1945                                    now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1946                         u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1947
1948                         if (WARN_ONCE(wr_ptr != write_ptr,
1949                                       "WR pointer moved while flushing %d -> %d\n",
1950                                       wr_ptr, write_ptr))
1951                                 return -ETIMEDOUT;
1952                         msleep(1);
1953                 }
1954
1955                 if (q->read_ptr != q->write_ptr) {
1956                         IWL_ERR(trans,
1957                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1958                         ret = -ETIMEDOUT;
1959                         break;
1960                 }
1961                 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1962         }
1963
1964         if (!ret)
1965                 return 0;
1966
1967         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1968                 txq->q.read_ptr, txq->q.write_ptr);
1969
1970         scd_sram_addr = trans_pcie->scd_base_addr +
1971                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1972         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1973
1974         iwl_print_hex_error(trans, buf, sizeof(buf));
1975
1976         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1977                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1978                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1979
1980         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1981                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1982                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1983                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1984                 u32 tbl_dw =
1985                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1986                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1987
1988                 if (cnt & 0x1)
1989                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1990                 else
1991                         tbl_dw = tbl_dw & 0x0000FFFF;
1992
1993                 IWL_ERR(trans,
1994                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1995                         cnt, active ? "" : "in", fifo, tbl_dw,
1996                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1997                                 (TFD_QUEUE_SIZE_MAX - 1),
1998                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1999         }
2000
2001         return ret;
2002 }
2003
2004 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2005                                          u32 mask, u32 value)
2006 {
2007         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2008         unsigned long flags;
2009
2010         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
2011         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2012         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
2013 }
2014
2015 static void iwl_trans_pcie_ref(struct iwl_trans *trans)
2016 {
2017         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2018
2019         if (iwlwifi_mod_params.d0i3_disable)
2020                 return;
2021
2022         pm_runtime_get(&trans_pcie->pci_dev->dev);
2023
2024 #ifdef CONFIG_PM
2025         IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2026                       atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2027 #endif /* CONFIG_PM */
2028 }
2029
2030 static void iwl_trans_pcie_unref(struct iwl_trans *trans)
2031 {
2032         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2033
2034         if (iwlwifi_mod_params.d0i3_disable)
2035                 return;
2036
2037         pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2038         pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
2039
2040 #ifdef CONFIG_PM
2041         IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2042                       atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2043 #endif /* CONFIG_PM */
2044 }
2045
2046 static const char *get_csr_string(int cmd)
2047 {
2048 #define IWL_CMD(x) case x: return #x
2049         switch (cmd) {
2050         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2051         IWL_CMD(CSR_INT_COALESCING);
2052         IWL_CMD(CSR_INT);
2053         IWL_CMD(CSR_INT_MASK);
2054         IWL_CMD(CSR_FH_INT_STATUS);
2055         IWL_CMD(CSR_GPIO_IN);
2056         IWL_CMD(CSR_RESET);
2057         IWL_CMD(CSR_GP_CNTRL);
2058         IWL_CMD(CSR_HW_REV);
2059         IWL_CMD(CSR_EEPROM_REG);
2060         IWL_CMD(CSR_EEPROM_GP);
2061         IWL_CMD(CSR_OTP_GP_REG);
2062         IWL_CMD(CSR_GIO_REG);
2063         IWL_CMD(CSR_GP_UCODE_REG);
2064         IWL_CMD(CSR_GP_DRIVER_REG);
2065         IWL_CMD(CSR_UCODE_DRV_GP1);
2066         IWL_CMD(CSR_UCODE_DRV_GP2);
2067         IWL_CMD(CSR_LED_REG);
2068         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2069         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2070         IWL_CMD(CSR_ANA_PLL_CFG);
2071         IWL_CMD(CSR_HW_REV_WA_REG);
2072         IWL_CMD(CSR_MONITOR_STATUS_REG);
2073         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2074         default:
2075                 return "UNKNOWN";
2076         }
2077 #undef IWL_CMD
2078 }
2079
2080 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2081 {
2082         int i;
2083         static const u32 csr_tbl[] = {
2084                 CSR_HW_IF_CONFIG_REG,
2085                 CSR_INT_COALESCING,
2086                 CSR_INT,
2087                 CSR_INT_MASK,
2088                 CSR_FH_INT_STATUS,
2089                 CSR_GPIO_IN,
2090                 CSR_RESET,
2091                 CSR_GP_CNTRL,
2092                 CSR_HW_REV,
2093                 CSR_EEPROM_REG,
2094                 CSR_EEPROM_GP,
2095                 CSR_OTP_GP_REG,
2096                 CSR_GIO_REG,
2097                 CSR_GP_UCODE_REG,
2098                 CSR_GP_DRIVER_REG,
2099                 CSR_UCODE_DRV_GP1,
2100                 CSR_UCODE_DRV_GP2,
2101                 CSR_LED_REG,
2102                 CSR_DRAM_INT_TBL_REG,
2103                 CSR_GIO_CHICKEN_BITS,
2104                 CSR_ANA_PLL_CFG,
2105                 CSR_MONITOR_STATUS_REG,
2106                 CSR_HW_REV_WA_REG,
2107                 CSR_DBG_HPET_MEM_REG
2108         };
2109         IWL_ERR(trans, "CSR values:\n");
2110         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2111                 "CSR_INT_PERIODIC_REG)\n");
2112         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2113                 IWL_ERR(trans, "  %25s: 0X%08x\n",
2114                         get_csr_string(csr_tbl[i]),
2115                         iwl_read32(trans, csr_tbl[i]));
2116         }
2117 }
2118
2119 #ifdef CONFIG_IWLWIFI_DEBUGFS
2120 /* create and remove of files */
2121 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
2122         if (!debugfs_create_file(#name, mode, parent, trans,            \
2123                                  &iwl_dbgfs_##name##_ops))              \
2124                 goto err;                                               \
2125 } while (0)
2126
2127 /* file operation */
2128 #define DEBUGFS_READ_FILE_OPS(name)                                     \
2129 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2130         .read = iwl_dbgfs_##name##_read,                                \
2131         .open = simple_open,                                            \
2132         .llseek = generic_file_llseek,                                  \
2133 };
2134
2135 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
2136 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2137         .write = iwl_dbgfs_##name##_write,                              \
2138         .open = simple_open,                                            \
2139         .llseek = generic_file_llseek,                                  \
2140 };
2141
2142 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
2143 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2144         .write = iwl_dbgfs_##name##_write,                              \
2145         .read = iwl_dbgfs_##name##_read,                                \
2146         .open = simple_open,                                            \
2147         .llseek = generic_file_llseek,                                  \
2148 };
2149
2150 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
2151                                        char __user *user_buf,
2152                                        size_t count, loff_t *ppos)
2153 {
2154         struct iwl_trans *trans = file->private_data;
2155         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2156         struct iwl_txq *txq;
2157         struct iwl_queue *q;
2158         char *buf;
2159         int pos = 0;
2160         int cnt;
2161         int ret;
2162         size_t bufsz;
2163
2164         bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
2165
2166         if (!trans_pcie->txq)
2167                 return -EAGAIN;
2168
2169         buf = kzalloc(bufsz, GFP_KERNEL);
2170         if (!buf)
2171                 return -ENOMEM;
2172
2173         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2174                 txq = &trans_pcie->txq[cnt];
2175                 q = &txq->q;
2176                 pos += scnprintf(buf + pos, bufsz - pos,
2177                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2178                                 cnt, q->read_ptr, q->write_ptr,
2179                                 !!test_bit(cnt, trans_pcie->queue_used),
2180                                  !!test_bit(cnt, trans_pcie->queue_stopped),
2181                                  txq->need_update, txq->frozen,
2182                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
2183         }
2184         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2185         kfree(buf);
2186         return ret;
2187 }
2188
2189 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2190                                        char __user *user_buf,
2191                                        size_t count, loff_t *ppos)
2192 {
2193         struct iwl_trans *trans = file->private_data;
2194         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2195         char *buf;
2196         int pos = 0, i, ret;
2197         size_t bufsz = sizeof(buf);
2198
2199         bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2200
2201         if (!trans_pcie->rxq)
2202                 return -EAGAIN;
2203
2204         buf = kzalloc(bufsz, GFP_KERNEL);
2205         if (!buf)
2206                 return -ENOMEM;
2207
2208         for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2209                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2210
2211                 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2212                                  i);
2213                 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2214                                  rxq->read);
2215                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2216                                  rxq->write);
2217                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2218                                  rxq->write_actual);
2219                 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2220                                  rxq->need_update);
2221                 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2222                                  rxq->free_count);
2223                 if (rxq->rb_stts) {
2224                         pos += scnprintf(buf + pos, bufsz - pos,
2225                                          "\tclosed_rb_num: %u\n",
2226                                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2227                                          0x0FFF);
2228                 } else {
2229                         pos += scnprintf(buf + pos, bufsz - pos,
2230                                          "\tclosed_rb_num: Not Allocated\n");
2231                 }
2232         }
2233         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2234         kfree(buf);
2235
2236         return ret;
2237 }
2238
2239 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2240                                         char __user *user_buf,
2241                                         size_t count, loff_t *ppos)
2242 {
2243         struct iwl_trans *trans = file->private_data;
2244         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2245         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2246
2247         int pos = 0;
2248         char *buf;
2249         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2250         ssize_t ret;
2251
2252         buf = kzalloc(bufsz, GFP_KERNEL);
2253         if (!buf)
2254                 return -ENOMEM;
2255
2256         pos += scnprintf(buf + pos, bufsz - pos,
2257                         "Interrupt Statistics Report:\n");
2258
2259         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2260                 isr_stats->hw);
2261         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2262                 isr_stats->sw);
2263         if (isr_stats->sw || isr_stats->hw) {
2264                 pos += scnprintf(buf + pos, bufsz - pos,
2265                         "\tLast Restarting Code:  0x%X\n",
2266                         isr_stats->err_code);
2267         }
2268 #ifdef CONFIG_IWLWIFI_DEBUG
2269         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2270                 isr_stats->sch);
2271         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2272                 isr_stats->alive);
2273 #endif
2274         pos += scnprintf(buf + pos, bufsz - pos,
2275                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2276
2277         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2278                 isr_stats->ctkill);
2279
2280         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2281                 isr_stats->wakeup);
2282
2283         pos += scnprintf(buf + pos, bufsz - pos,
2284                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2285
2286         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2287                 isr_stats->tx);
2288
2289         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2290                 isr_stats->unhandled);
2291
2292         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2293         kfree(buf);
2294         return ret;
2295 }
2296
2297 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2298                                          const char __user *user_buf,
2299                                          size_t count, loff_t *ppos)
2300 {
2301         struct iwl_trans *trans = file->private_data;
2302         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2303         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2304
2305         char buf[8];
2306         int buf_size;
2307         u32 reset_flag;
2308
2309         memset(buf, 0, sizeof(buf));
2310         buf_size = min(count, sizeof(buf) -  1);
2311         if (copy_from_user(buf, user_buf, buf_size))
2312                 return -EFAULT;
2313         if (sscanf(buf, "%x", &reset_flag) != 1)
2314                 return -EFAULT;
2315         if (reset_flag == 0)
2316                 memset(isr_stats, 0, sizeof(*isr_stats));
2317
2318         return count;
2319 }
2320
2321 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2322                                    const char __user *user_buf,
2323                                    size_t count, loff_t *ppos)
2324 {
2325         struct iwl_trans *trans = file->private_data;
2326         char buf[8];
2327         int buf_size;
2328         int csr;
2329
2330         memset(buf, 0, sizeof(buf));
2331         buf_size = min(count, sizeof(buf) -  1);
2332         if (copy_from_user(buf, user_buf, buf_size))
2333                 return -EFAULT;
2334         if (sscanf(buf, "%d", &csr) != 1)
2335                 return -EFAULT;
2336
2337         iwl_pcie_dump_csr(trans);
2338
2339         return count;
2340 }
2341
2342 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2343                                      char __user *user_buf,
2344                                      size_t count, loff_t *ppos)
2345 {
2346         struct iwl_trans *trans = file->private_data;
2347         char *buf = NULL;
2348         ssize_t ret;
2349
2350         ret = iwl_dump_fh(trans, &buf);
2351         if (ret < 0)
2352                 return ret;
2353         if (!buf)
2354                 return -EINVAL;
2355         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2356         kfree(buf);
2357         return ret;
2358 }
2359
2360 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2361 DEBUGFS_READ_FILE_OPS(fh_reg);
2362 DEBUGFS_READ_FILE_OPS(rx_queue);
2363 DEBUGFS_READ_FILE_OPS(tx_queue);
2364 DEBUGFS_WRITE_FILE_OPS(csr);
2365
2366 /* Create the debugfs files and directories */
2367 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2368 {
2369         struct dentry *dir = trans->dbgfs_dir;
2370
2371         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2372         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2373         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2374         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2375         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2376         return 0;
2377
2378 err:
2379         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2380         return -ENOMEM;
2381 }
2382 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2383
2384 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2385 {
2386         u32 cmdlen = 0;
2387         int i;
2388
2389         for (i = 0; i < IWL_NUM_OF_TBS; i++)
2390                 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2391
2392         return cmdlen;
2393 }
2394
2395 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2396                                    struct iwl_fw_error_dump_data **data,
2397                                    int allocated_rb_nums)
2398 {
2399         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2400         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2401         /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2402         struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2403         u32 i, r, j, rb_len = 0;
2404
2405         spin_lock(&rxq->lock);
2406
2407         r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2408
2409         for (i = rxq->read, j = 0;
2410              i != r && j < allocated_rb_nums;
2411              i = (i + 1) & RX_QUEUE_MASK, j++) {
2412                 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2413                 struct iwl_fw_error_dump_rb *rb;
2414
2415                 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2416                                DMA_FROM_DEVICE);
2417
2418                 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2419
2420                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2421                 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2422                 rb = (void *)(*data)->data;
2423                 rb->index = cpu_to_le32(i);
2424                 memcpy(rb->data, page_address(rxb->page), max_len);
2425                 /* remap the page for the free benefit */
2426                 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2427                                                      max_len,
2428                                                      DMA_FROM_DEVICE);
2429
2430                 *data = iwl_fw_error_next_data(*data);
2431         }
2432
2433         spin_unlock(&rxq->lock);
2434
2435         return rb_len;
2436 }
2437 #define IWL_CSR_TO_DUMP (0x250)
2438
2439 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2440                                    struct iwl_fw_error_dump_data **data)
2441 {
2442         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2443         __le32 *val;
2444         int i;
2445
2446         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2447         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2448         val = (void *)(*data)->data;
2449
2450         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2451                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2452
2453         *data = iwl_fw_error_next_data(*data);
2454
2455         return csr_len;
2456 }
2457
2458 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2459                                        struct iwl_fw_error_dump_data **data)
2460 {
2461         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2462         unsigned long flags;
2463         __le32 *val;
2464         int i;
2465
2466         if (!iwl_trans_grab_nic_access(trans, &flags))
2467                 return 0;
2468
2469         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2470         (*data)->len = cpu_to_le32(fh_regs_len);
2471         val = (void *)(*data)->data;
2472
2473         for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2474                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2475
2476         iwl_trans_release_nic_access(trans, &flags);
2477
2478         *data = iwl_fw_error_next_data(*data);
2479
2480         return sizeof(**data) + fh_regs_len;
2481 }
2482
2483 static u32
2484 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2485                                  struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2486                                  u32 monitor_len)
2487 {
2488         u32 buf_size_in_dwords = (monitor_len >> 2);
2489         u32 *buffer = (u32 *)fw_mon_data->data;
2490         unsigned long flags;
2491         u32 i;
2492
2493         if (!iwl_trans_grab_nic_access(trans, &flags))
2494                 return 0;
2495
2496         iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2497         for (i = 0; i < buf_size_in_dwords; i++)
2498                 buffer[i] = iwl_read_prph_no_grab(trans,
2499                                 MON_DMARB_RD_DATA_ADDR);
2500         iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2501
2502         iwl_trans_release_nic_access(trans, &flags);
2503
2504         return monitor_len;
2505 }
2506
2507 static u32
2508 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2509                             struct iwl_fw_error_dump_data **data,
2510                             u32 monitor_len)
2511 {
2512         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2513         u32 len = 0;
2514
2515         if ((trans_pcie->fw_mon_page &&
2516              trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2517             trans->dbg_dest_tlv) {
2518                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2519                 u32 base, write_ptr, wrap_cnt;
2520
2521                 /* If there was a dest TLV - use the values from there */
2522                 if (trans->dbg_dest_tlv) {
2523                         write_ptr =
2524                                 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2525                         wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2526                         base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2527                 } else {
2528                         base = MON_BUFF_BASE_ADDR;
2529                         write_ptr = MON_BUFF_WRPTR;
2530                         wrap_cnt = MON_BUFF_CYCLE_CNT;
2531                 }
2532
2533                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2534                 fw_mon_data = (void *)(*data)->data;
2535                 fw_mon_data->fw_mon_wr_ptr =
2536                         cpu_to_le32(iwl_read_prph(trans, write_ptr));
2537                 fw_mon_data->fw_mon_cycle_cnt =
2538                         cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2539                 fw_mon_data->fw_mon_base_ptr =
2540                         cpu_to_le32(iwl_read_prph(trans, base));
2541
2542                 len += sizeof(**data) + sizeof(*fw_mon_data);
2543                 if (trans_pcie->fw_mon_page) {
2544                         /*
2545                          * The firmware is now asserted, it won't write anything
2546                          * to the buffer. CPU can take ownership to fetch the
2547                          * data. The buffer will be handed back to the device
2548                          * before the firmware will be restarted.
2549                          */
2550                         dma_sync_single_for_cpu(trans->dev,
2551                                                 trans_pcie->fw_mon_phys,
2552                                                 trans_pcie->fw_mon_size,
2553                                                 DMA_FROM_DEVICE);
2554                         memcpy(fw_mon_data->data,
2555                                page_address(trans_pcie->fw_mon_page),
2556                                trans_pcie->fw_mon_size);
2557
2558                         monitor_len = trans_pcie->fw_mon_size;
2559                 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2560                         /*
2561                          * Update pointers to reflect actual values after
2562                          * shifting
2563                          */
2564                         base = iwl_read_prph(trans, base) <<
2565                                trans->dbg_dest_tlv->base_shift;
2566                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
2567                                            monitor_len / sizeof(u32));
2568                 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2569                         monitor_len =
2570                                 iwl_trans_pci_dump_marbh_monitor(trans,
2571                                                                  fw_mon_data,
2572                                                                  monitor_len);
2573                 } else {
2574                         /* Didn't match anything - output no monitor data */
2575                         monitor_len = 0;
2576                 }
2577
2578                 len += monitor_len;
2579                 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2580         }
2581
2582         return len;
2583 }
2584
2585 static struct iwl_trans_dump_data
2586 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
2587                           const struct iwl_fw_dbg_trigger_tlv *trigger)
2588 {
2589         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2590         struct iwl_fw_error_dump_data *data;
2591         struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2592         struct iwl_fw_error_dump_txcmd *txcmd;
2593         struct iwl_trans_dump_data *dump_data;
2594         u32 len, num_rbs;
2595         u32 monitor_len;
2596         int i, ptr;
2597         bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2598                         !trans->cfg->mq_rx_supported;
2599
2600         /* transport dump header */
2601         len = sizeof(*dump_data);
2602
2603         /* host commands */
2604         len += sizeof(*data) +
2605                 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2606
2607         /* FW monitor */
2608         if (trans_pcie->fw_mon_page) {
2609                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2610                        trans_pcie->fw_mon_size;
2611                 monitor_len = trans_pcie->fw_mon_size;
2612         } else if (trans->dbg_dest_tlv) {
2613                 u32 base, end;
2614
2615                 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2616                 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2617
2618                 base = iwl_read_prph(trans, base) <<
2619                        trans->dbg_dest_tlv->base_shift;
2620                 end = iwl_read_prph(trans, end) <<
2621                       trans->dbg_dest_tlv->end_shift;
2622
2623                 /* Make "end" point to the actual end */
2624                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2625                     trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2626                         end += (1 << trans->dbg_dest_tlv->end_shift);
2627                 monitor_len = end - base;
2628                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2629                        monitor_len;
2630         } else {
2631                 monitor_len = 0;
2632         }
2633
2634         if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2635                 dump_data = vzalloc(len);
2636                 if (!dump_data)
2637                         return NULL;
2638
2639                 data = (void *)dump_data->data;
2640                 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2641                 dump_data->len = len;
2642
2643                 return dump_data;
2644         }
2645
2646         /* CSR registers */
2647         len += sizeof(*data) + IWL_CSR_TO_DUMP;
2648
2649         /* FH registers */
2650         len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2651
2652         if (dump_rbs) {
2653                 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2654                 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2655                 /* RBs */
2656                 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num))
2657                                       & 0x0FFF;
2658                 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
2659                 len += num_rbs * (sizeof(*data) +
2660                                   sizeof(struct iwl_fw_error_dump_rb) +
2661                                   (PAGE_SIZE << trans_pcie->rx_page_order));
2662         }
2663
2664         dump_data = vzalloc(len);
2665         if (!dump_data)
2666                 return NULL;
2667
2668         len = 0;
2669         data = (void *)dump_data->data;
2670         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2671         txcmd = (void *)data->data;
2672         spin_lock_bh(&cmdq->lock);
2673         ptr = cmdq->q.write_ptr;
2674         for (i = 0; i < cmdq->q.n_window; i++) {
2675                 u8 idx = get_cmd_index(&cmdq->q, ptr);
2676                 u32 caplen, cmdlen;
2677
2678                 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2679                 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2680
2681                 if (cmdlen) {
2682                         len += sizeof(*txcmd) + caplen;
2683                         txcmd->cmdlen = cpu_to_le32(cmdlen);
2684                         txcmd->caplen = cpu_to_le32(caplen);
2685                         memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2686                         txcmd = (void *)((u8 *)txcmd->data + caplen);
2687                 }
2688
2689                 ptr = iwl_queue_dec_wrap(ptr);
2690         }
2691         spin_unlock_bh(&cmdq->lock);
2692
2693         data->len = cpu_to_le32(len);
2694         len += sizeof(*data);
2695         data = iwl_fw_error_next_data(data);
2696
2697         len += iwl_trans_pcie_dump_csr(trans, &data);
2698         len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2699         if (dump_rbs)
2700                 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
2701
2702         len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2703
2704         dump_data->len = len;
2705
2706         return dump_data;
2707 }
2708
2709 #ifdef CONFIG_PM_SLEEP
2710 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
2711 {
2712         if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2713                 return iwl_pci_fw_enter_d0i3(trans);
2714
2715         return 0;
2716 }
2717
2718 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
2719 {
2720         if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2721                 iwl_pci_fw_exit_d0i3(trans);
2722 }
2723 #endif /* CONFIG_PM_SLEEP */
2724
2725 static const struct iwl_trans_ops trans_ops_pcie = {
2726         .start_hw = iwl_trans_pcie_start_hw,
2727         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2728         .fw_alive = iwl_trans_pcie_fw_alive,
2729         .start_fw = iwl_trans_pcie_start_fw,
2730         .stop_device = iwl_trans_pcie_stop_device,
2731
2732         .d3_suspend = iwl_trans_pcie_d3_suspend,
2733         .d3_resume = iwl_trans_pcie_d3_resume,
2734
2735 #ifdef CONFIG_PM_SLEEP
2736         .suspend = iwl_trans_pcie_suspend,
2737         .resume = iwl_trans_pcie_resume,
2738 #endif /* CONFIG_PM_SLEEP */
2739
2740         .send_cmd = iwl_trans_pcie_send_hcmd,
2741
2742         .tx = iwl_trans_pcie_tx,
2743         .reclaim = iwl_trans_pcie_reclaim,
2744
2745         .txq_disable = iwl_trans_pcie_txq_disable,
2746         .txq_enable = iwl_trans_pcie_txq_enable,
2747
2748         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2749         .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2750         .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
2751
2752         .write8 = iwl_trans_pcie_write8,
2753         .write32 = iwl_trans_pcie_write32,
2754         .read32 = iwl_trans_pcie_read32,
2755         .read_prph = iwl_trans_pcie_read_prph,
2756         .write_prph = iwl_trans_pcie_write_prph,
2757         .read_mem = iwl_trans_pcie_read_mem,
2758         .write_mem = iwl_trans_pcie_write_mem,
2759         .configure = iwl_trans_pcie_configure,
2760         .set_pmi = iwl_trans_pcie_set_pmi,
2761         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2762         .release_nic_access = iwl_trans_pcie_release_nic_access,
2763         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2764
2765         .ref = iwl_trans_pcie_ref,
2766         .unref = iwl_trans_pcie_unref,
2767
2768         .dump_data = iwl_trans_pcie_dump_data,
2769 };
2770
2771 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2772                                        const struct pci_device_id *ent,
2773                                        const struct iwl_cfg *cfg)
2774 {
2775         struct iwl_trans_pcie *trans_pcie;
2776         struct iwl_trans *trans;
2777         int ret, addr_size;
2778
2779         trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2780                                 &pdev->dev, cfg, &trans_ops_pcie, 0);
2781         if (!trans)
2782                 return ERR_PTR(-ENOMEM);
2783
2784         trans->max_skb_frags = IWL_PCIE_MAX_FRAGS;
2785
2786         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2787
2788         trans_pcie->trans = trans;
2789         spin_lock_init(&trans_pcie->irq_lock);
2790         spin_lock_init(&trans_pcie->reg_lock);
2791         mutex_init(&trans_pcie->mutex);
2792         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2793         trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
2794         if (!trans_pcie->tso_hdr_page) {
2795                 ret = -ENOMEM;
2796                 goto out_no_pci;
2797         }
2798
2799         ret = pci_enable_device(pdev);
2800         if (ret)
2801                 goto out_no_pci;
2802
2803         if (!cfg->base_params->pcie_l1_allowed) {
2804                 /*
2805                  * W/A - seems to solve weird behavior. We need to remove this
2806                  * if we don't want to stay in L1 all the time. This wastes a
2807                  * lot of power.
2808                  */
2809                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2810                                        PCIE_LINK_STATE_L1 |
2811                                        PCIE_LINK_STATE_CLKPM);
2812         }
2813
2814         if (cfg->mq_rx_supported)
2815                 addr_size = 64;
2816         else
2817                 addr_size = 36;
2818
2819         pci_set_master(pdev);
2820
2821         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
2822         if (!ret)
2823                 ret = pci_set_consistent_dma_mask(pdev,
2824                                                   DMA_BIT_MASK(addr_size));
2825         if (ret) {
2826                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2827                 if (!ret)
2828                         ret = pci_set_consistent_dma_mask(pdev,
2829                                                           DMA_BIT_MASK(32));
2830                 /* both attempts failed: */
2831                 if (ret) {
2832                         dev_err(&pdev->dev, "No suitable DMA available\n");
2833                         goto out_pci_disable_device;
2834                 }
2835         }
2836
2837         ret = pci_request_regions(pdev, DRV_NAME);
2838         if (ret) {
2839                 dev_err(&pdev->dev, "pci_request_regions failed\n");
2840                 goto out_pci_disable_device;
2841         }
2842
2843         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2844         if (!trans_pcie->hw_base) {
2845                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2846                 ret = -ENODEV;
2847                 goto out_pci_release_regions;
2848         }
2849
2850         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2851          * PCI Tx retries from interfering with C3 CPU state */
2852         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2853
2854         trans->dev = &pdev->dev;
2855         trans_pcie->pci_dev = pdev;
2856         iwl_disable_interrupts(trans);
2857
2858         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2859         /*
2860          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2861          * changed, and now the revision step also includes bit 0-1 (no more
2862          * "dash" value). To keep hw_rev backwards compatible - we'll store it
2863          * in the old format.
2864          */
2865         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2866                 unsigned long flags;
2867
2868                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2869                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2870
2871                 ret = iwl_pcie_prepare_card_hw(trans);
2872                 if (ret) {
2873                         IWL_WARN(trans, "Exit HW not ready\n");
2874                         goto out_pci_disable_msi;
2875                 }
2876
2877                 /*
2878                  * in-order to recognize C step driver should read chip version
2879                  * id located at the AUX bus MISC address space.
2880                  */
2881                 iwl_set_bit(trans, CSR_GP_CNTRL,
2882                             CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2883                 udelay(2);
2884
2885                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2886                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2887                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2888                                    25000);
2889                 if (ret < 0) {
2890                         IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2891                         goto out_pci_disable_msi;
2892                 }
2893
2894                 if (iwl_trans_grab_nic_access(trans, &flags)) {
2895                         u32 hw_step;
2896
2897                         hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
2898                         hw_step |= ENABLE_WFPM;
2899                         iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
2900                         hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
2901                         hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2902                         if (hw_step == 0x3)
2903                                 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2904                                                 (SILICON_C_STEP << 2);
2905                         iwl_trans_release_nic_access(trans, &flags);
2906                 }
2907         }
2908
2909         trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
2910
2911         iwl_pcie_set_interrupt_capa(pdev, trans);
2912         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2913         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2914                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2915
2916         /* Initialize the wait queue for commands */
2917         init_waitqueue_head(&trans_pcie->wait_command_queue);
2918
2919         init_waitqueue_head(&trans_pcie->d0i3_waitq);
2920
2921         if (trans_pcie->msix_enabled) {
2922                 if (iwl_pcie_init_msix_handler(pdev, trans_pcie))
2923                         goto out_pci_release_regions;
2924          } else {
2925                 ret = iwl_pcie_alloc_ict(trans);
2926                 if (ret)
2927                         goto out_pci_disable_msi;
2928
2929                 ret = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2930                                            iwl_pcie_irq_handler,
2931                                            IRQF_SHARED, DRV_NAME, trans);
2932                 if (ret) {
2933                         IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2934                         goto out_free_ict;
2935                 }
2936                 trans_pcie->inta_mask = CSR_INI_SET_MASK;
2937          }
2938
2939 #ifdef CONFIG_IWLWIFI_PCIE_RTPM
2940         trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
2941 #else
2942         trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
2943 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */
2944
2945         return trans;
2946
2947 out_free_ict:
2948         iwl_pcie_free_ict(trans);
2949 out_pci_disable_msi:
2950         pci_disable_msi(pdev);
2951 out_pci_release_regions:
2952         pci_release_regions(pdev);
2953 out_pci_disable_device:
2954         pci_disable_device(pdev);
2955 out_no_pci:
2956         free_percpu(trans_pcie->tso_hdr_page);
2957         iwl_trans_free(trans);
2958         return ERR_PTR(ret);
2959 }