drivers/net/wireless/intel/iwlwifi/pcie/tx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
   4  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
   5  * Copyright(c) 2016 Intel Deutschland GmbH
   6  *
   7  * Portions of this file are derived from the ipw3945 project, as well
   8  * as portions of the ieee80211 subsystem header files.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program; if not, write to the Free Software Foundation, Inc.,
  21  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  22  *
  23  * The full GNU General Public License is included in this distribution in the
  24  * file called LICENSE.
  25  *
  26  * Contact Information:
  27  *  Intel Linux Wireless <linuxwifi@intel.com>
  28  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  29  *
  30  *****************************************************************************/
  31 #include <linux/etherdevice.h>
  32 #include <linux/ieee80211.h>
  33 #include <linux/slab.h>
  34 #include <linux/sched.h>
  35 #include <net/ip6_checksum.h>
  36 #include <net/tso.h>
  37 #include <net/ip6_checksum.h>
  38
  39 #include "iwl-debug.h"
  40 #include "iwl-csr.h"
  41 #include "iwl-prph.h"
  42 #include "iwl-io.h"
  43 #include "iwl-scd.h"
  44 #include "iwl-op-mode.h"
  45 #include "internal.h"
  46 /* FIXME: need to abstract out TX command (once we know what it looks like) */
  47 #include "dvm/commands.h"
  48
  49 #define IWL_TX_CRC_SIZE 4
  50 #define IWL_TX_DELIMITER_SIZE 4
  51
  52 /*************** DMA-QUEUE-GENERAL-FUNCTIONS  *****
  53  * DMA services
  54  *
  55  * Theory of operation
  56  *
  57  * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  58  * of buffer descriptors, each of which points to one or more data buffers for
  59  * the device to read from or fill.  Driver and device exchange status of each
  60  * queue via "read" and "write" pointers.  Driver keeps minimum of 2 empty
  61  * entries in each circular buffer, to protect against confusing empty and full
  62  * queue states.
  63  *
  64  * The device reads or writes the data in the queues via the device's several
  65  * DMA/FIFO channels.  Each queue is mapped to a single DMA channel.
  66  *
  67  * For Tx queue, there are low mark and high mark limits. If, after queuing
  68  * the packet for Tx, free space become < low mark, Tx queue stopped. When
  69  * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  70  * Tx queue resumed.
  71  *
  72  ***************************************************/
  73 static int iwl_queue_space(const struct iwl_queue *q)
  74 {
  75         unsigned int max;
  76         unsigned int used;
  77
  78         /*
  79          * To avoid ambiguity between empty and completely full queues, there
  80          * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.
  81          * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need
  82          * to reserve any queue entries for this purpose.
  83          */
  84         if (q->n_window < TFD_QUEUE_SIZE_MAX)
  85                 max = q->n_window;
  86         else
  87                 max = TFD_QUEUE_SIZE_MAX - 1;
  88
  89         /*
  90          * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to
  91          * modulo by TFD_QUEUE_SIZE_MAX and is well defined.
  92          */
  93         used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1);
  94
  95         if (WARN_ON(used > max))
  96                 return 0;
  97
  98         return max - used;
  99 }
 100
 101 /*
 102  * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
 103  */
 104 static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id)
 105 {
 106         q->n_window = slots_num;
 107         q->id = id;
 108
 109         /* slots_num must be power-of-two size, otherwise
 110          * get_cmd_index is broken. */
 111         if (WARN_ON(!is_power_of_2(slots_num)))
 112                 return -EINVAL;
 113
 114         q->low_mark = q->n_window / 4;
 115         if (q->low_mark < 4)
 116                 q->low_mark = 4;
 117
 118         q->high_mark = q->n_window / 8;
 119         if (q->high_mark < 2)
 120                 q->high_mark = 2;
 121
 122         q->write_ptr = 0;
 123         q->read_ptr = 0;
 124
 125         return 0;
 126 }
 127
 128 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
 129                                   struct iwl_dma_ptr *ptr, size_t size)
 130 {
 131         if (WARN_ON(ptr->addr))
 132                 return -EINVAL;
 133
 134         ptr->addr = dma_alloc_coherent(trans->dev, size,
 135                                        &ptr->dma, GFP_KERNEL);
 136         if (!ptr->addr)
 137                 return -ENOMEM;
 138         ptr->size = size;
 139         return 0;
 140 }
 141
 142 static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans,
 143                                   struct iwl_dma_ptr *ptr)
 144 {
 145         if (unlikely(!ptr->addr))
 146                 return;
 147
 148         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 149         memset(ptr, 0, sizeof(*ptr));
 150 }
 151
 152 static void iwl_pcie_txq_stuck_timer(unsigned long data)
 153 {
 154         struct iwl_txq *txq = (void *)data;
 155         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
 156         struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
 157         u32 scd_sram_addr = trans_pcie->scd_base_addr +
 158                                 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
 159         u8 buf[16];
 160         int i;
 161
 162         spin_lock(&txq->lock);
 163         /* check if triggered erroneously */
 164         if (txq->q.read_ptr == txq->q.write_ptr) {
 165                 spin_unlock(&txq->lock);
 166                 return;
 167         }
 168         spin_unlock(&txq->lock);
 169
 170         IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
 171                 jiffies_to_msecs(txq->wd_timeout));
 172         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
 173                 txq->q.read_ptr, txq->q.write_ptr);
 174
 175         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
 176
 177         iwl_print_hex_error(trans, buf, sizeof(buf));
 178
 179         for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
 180                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
 181                         iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
 182
 183         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
 184                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
 185                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
 186                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
 187                 u32 tbl_dw =
 188                         iwl_trans_read_mem32(trans,
 189                                              trans_pcie->scd_base_addr +
 190                                              SCD_TRANS_TBL_OFFSET_QUEUE(i));
 191
 192                 if (i & 0x1)
 193                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
 194                 else
 195                         tbl_dw = tbl_dw & 0x0000FFFF;
 196
 197                 IWL_ERR(trans,
 198                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
 199                         i, active ? "" : "in", fifo, tbl_dw,
 200                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(i)) &
 201                                 (TFD_QUEUE_SIZE_MAX - 1),
 202                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
 203         }
 204
 205         iwl_force_nmi(trans);
 206 }
 207
 208 /*
 209  * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 210  */
 211 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
 212                                              struct iwl_txq *txq, u16 byte_cnt)
 213 {
 214         struct iwlagn_scd_bc_tbl *scd_bc_tbl;
 215         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 216         int write_ptr = txq->q.write_ptr;
 217         int txq_id = txq->q.id;
 218         u8 sec_ctl = 0;
 219         u8 sta_id = 0;
 220         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 221         __le16 bc_ent;
 222         struct iwl_tx_cmd *tx_cmd =
 223                 (void *) txq->entries[txq->q.write_ptr].cmd->payload;
 224
 225         scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 226
 227         sta_id = tx_cmd->sta_id;
 228         sec_ctl = tx_cmd->sec_ctl;
 229
 230         switch (sec_ctl & TX_CMD_SEC_MSK) {
 231         case TX_CMD_SEC_CCM:
 232                 len += IEEE80211_CCMP_MIC_LEN;
 233                 break;
 234         case TX_CMD_SEC_TKIP:
 235                 len += IEEE80211_TKIP_ICV_LEN;
 236                 break;
 237         case TX_CMD_SEC_WEP:
 238                 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
 239                 break;
 240         }
 241
 242         if (trans_pcie->bc_table_dword)
 243                 len = DIV_ROUND_UP(len, 4);
 244
 245         if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
 246                 return;
 247
 248         bc_ent = cpu_to_le16(len | (sta_id << 12));
 249
 250         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
 251
 252         if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 253                 scd_bc_tbl[txq_id].
 254                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
 255 }
 256
 257 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
 258                                             struct iwl_txq *txq)
 259 {
 260         struct iwl_trans_pcie *trans_pcie =
 261                 IWL_TRANS_GET_PCIE_TRANS(trans);
 262         struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 263         int txq_id = txq->q.id;
 264         int read_ptr = txq->q.read_ptr;
 265         u8 sta_id = 0;
 266         __le16 bc_ent;
 267         struct iwl_tx_cmd *tx_cmd =
 268                 (void *)txq->entries[txq->q.read_ptr].cmd->payload;
 269
 270         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 271
 272         if (txq_id != trans_pcie->cmd_queue)
 273                 sta_id = tx_cmd->sta_id;
 274
 275         bc_ent = cpu_to_le16(1 | (sta_id << 12));
 276         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 277
 278         if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
 279                 scd_bc_tbl[txq_id].
 280                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
 281 }
 282
 283 /*
 284  * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
 285  */
 286 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
 287                                     struct iwl_txq *txq)
 288 {
 289         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 290         u32 reg = 0;
 291         int txq_id = txq->q.id;
 292
 293         lockdep_assert_held(&txq->lock);
 294
 295         /*
 296          * explicitly wake up the NIC if:
 297          * 1. shadow registers aren't enabled
 298          * 2. NIC is woken up for CMD regardless of shadow outside this function
 299          * 3. there is a chance that the NIC is asleep
 300          */
 301         if (!trans->cfg->base_params->shadow_reg_enable &&
 302             txq_id != trans_pcie->cmd_queue &&
 303             test_bit(STATUS_TPOWER_PMI, &trans->status)) {
 304                 /*
 305                  * wake up nic if it's powered down ...
 306                  * uCode will wake up, and interrupt us again, so next
 307                  * time we'll skip this part.
 308                  */
 309                 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 310
 311                 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 312                         IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
 313                                        txq_id, reg);
 314                         iwl_set_bit(trans, CSR_GP_CNTRL,
 315                                     CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 316                         txq->need_update = true;
 317                         return;
 318                 }
 319         }
 320
 321         /*
 322          * if not in power-save mode, uCode will never sleep when we're
 323          * trying to tx (during RFKILL, we're not trying to tx).
 324          */
 325         IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr);
 326         if (!txq->block)
 327                 iwl_write32(trans, HBUS_TARG_WRPTR,
 328                             txq->q.write_ptr | (txq_id << 8));
 329 }
 330
 331 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
 332 {
 333         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 334         int i;
 335
 336         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
 337                 struct iwl_txq *txq = &trans_pcie->txq[i];
 338
 339                 spin_lock_bh(&txq->lock);
 340                 if (trans_pcie->txq[i].need_update) {
 341                         iwl_pcie_txq_inc_wr_ptr(trans, txq);
 342                         trans_pcie->txq[i].need_update = false;
 343                 }
 344                 spin_unlock_bh(&txq->lock);
 345         }
 346 }
 347
 348 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 349 {
 350         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 351
 352         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 353         if (sizeof(dma_addr_t) > sizeof(u32))
 354                 addr |=
 355                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 356
 357         return addr;
 358 }
 359
 360 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 361                                        dma_addr_t addr, u16 len)
 362 {
 363         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 364         u16 hi_n_len = len << 4;
 365
 366         put_unaligned_le32(addr, &tb->lo);
 367         if (sizeof(dma_addr_t) > sizeof(u32))
 368                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 369
 370         tb->hi_n_len = cpu_to_le16(hi_n_len);
 371
 372         tfd->num_tbs = idx + 1;
 373 }
 374
 375 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd)
 376 {
 377         return tfd->num_tbs & 0x1f;
 378 }
 379
 380 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
 381                                struct iwl_cmd_meta *meta,
 382                                struct iwl_tfd *tfd)
 383 {
 384         int i;
 385         int num_tbs;
 386
 387         /* Sanity check on number of chunks */
 388         num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
 389
 390         if (num_tbs >= IWL_NUM_OF_TBS) {
 391                 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
 392                 /* @todo issue fatal error, it is quite serious situation */
 393                 return;
 394         }
 395
 396         /* first TB is never freed - it's the scratchbuf data */
 397
 398         for (i = 1; i < num_tbs; i++) {
 399                 if (meta->flags & BIT(i + CMD_TB_BITMAP_POS))
 400                         dma_unmap_page(trans->dev,
 401                                        iwl_pcie_tfd_tb_get_addr(tfd, i),
 402                                        iwl_pcie_tfd_tb_get_len(tfd, i),
 403                                        DMA_TO_DEVICE);
 404                 else
 405                         dma_unmap_single(trans->dev,
 406                                          iwl_pcie_tfd_tb_get_addr(tfd, i),
 407                                          iwl_pcie_tfd_tb_get_len(tfd, i),
 408                                          DMA_TO_DEVICE);
 409         }
 410         tfd->num_tbs = 0;
 411 }
 412
 413 /*
 414  * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 415  * @trans - transport private data
 416  * @txq - tx queue
 417  * @dma_dir - the direction of the DMA mapping
 418  *
 419  * Does NOT advance any TFD circular buffer read/write indexes
 420  * Does NOT free the TFD itself (which is within circular buffer)
 421  */
 422 static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
 423 {
 424         struct iwl_tfd *tfd_tmp = txq->tfds;
 425
 426         /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
 427          * idx is bounded by n_window
 428          */
 429         int rd_ptr = txq->q.read_ptr;
 430         int idx = get_cmd_index(&txq->q, rd_ptr);
 431
 432         lockdep_assert_held(&txq->lock);
 433
 434         /* We have only q->n_window txq->entries, but we use
 435          * TFD_QUEUE_SIZE_MAX tfds
 436          */
 437         iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);
 438
 439         /* free SKB */
 440         if (txq->entries) {
 441                 struct sk_buff *skb;
 442
 443                 skb = txq->entries[idx].skb;
 444
 445                 /* Can be called from irqs-disabled context
 446                  * If skb is not NULL, it means that the whole queue is being
 447                  * freed and that the queue is not empty - free the skb
 448                  */
 449                 if (skb) {
 450                         iwl_op_mode_free_skb(trans->op_mode, skb);
 451                         txq->entries[idx].skb = NULL;
 452                 }
 453         }
 454 }
 455
 456 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
 457                                   dma_addr_t addr, u16 len, bool reset)
 458 {
 459         struct iwl_queue *q;
 460         struct iwl_tfd *tfd, *tfd_tmp;
 461         u32 num_tbs;
 462
 463         q = &txq->q;
 464         tfd_tmp = txq->tfds;
 465         tfd = &tfd_tmp[q->write_ptr];
 466
 467         if (reset)
 468                 memset(tfd, 0, sizeof(*tfd));
 469
 470         num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
 471
 472         /* Each TFD can point to a maximum 20 Tx buffers */
 473         if (num_tbs >= IWL_NUM_OF_TBS) {
 474                 IWL_ERR(trans, "Error can not send more than %d chunks\n",
 475                         IWL_NUM_OF_TBS);
 476                 return -EINVAL;
 477         }
 478
 479         if (WARN(addr & ~IWL_TX_DMA_MASK,
 480                  "Unaligned address = %llx\n", (unsigned long long)addr))
 481                 return -EINVAL;
 482
 483         iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len);
 484
 485         return num_tbs;
 486 }
 487
 488 static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
 489                                struct iwl_txq *txq, int slots_num,
 490                                u32 txq_id)
 491 {
 492         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 493         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 494         size_t scratchbuf_sz;
 495         int i;
 496
 497         if (WARN_ON(txq->entries || txq->tfds))
 498                 return -EINVAL;
 499
 500         setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
 501                     (unsigned long)txq);
 502         txq->trans_pcie = trans_pcie;
 503
 504         txq->q.n_window = slots_num;
 505
 506         txq->entries = kcalloc(slots_num,
 507                                sizeof(struct iwl_pcie_txq_entry),
 508                                GFP_KERNEL);
 509
 510         if (!txq->entries)
 511                 goto error;
 512
 513         if (txq_id == trans_pcie->cmd_queue)
 514                 for (i = 0; i < slots_num; i++) {
 515                         txq->entries[i].cmd =
 516                                 kmalloc(sizeof(struct iwl_device_cmd),
 517                                         GFP_KERNEL);
 518                         if (!txq->entries[i].cmd)
 519                                 goto error;
 520                 }
 521
 522         /* Circular buffer of transmit frame descriptors (TFDs),
 523          * shared with device */
 524         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 525                                        &txq->q.dma_addr, GFP_KERNEL);
 526         if (!txq->tfds)
 527                 goto error;
 528
 529         BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs));
 530         BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) !=
 531                         sizeof(struct iwl_cmd_header) +
 532                         offsetof(struct iwl_tx_cmd, scratch));
 533
 534         scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num;
 535
 536         txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz,
 537                                               &txq->scratchbufs_dma,
 538                                               GFP_KERNEL);
 539         if (!txq->scratchbufs)
 540                 goto err_free_tfds;
 541
 542         txq->q.id = txq_id;
 543
 544         return 0;
 545 err_free_tfds:
 546         dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr);
 547 error:
 548         if (txq->entries && txq_id == trans_pcie->cmd_queue)
 549                 for (i = 0; i < slots_num; i++)
 550                         kfree(txq->entries[i].cmd);
 551         kfree(txq->entries);
 552         txq->entries = NULL;
 553
 554         return -ENOMEM;
 555
 556 }
 557
 558 static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
 559                               int slots_num, u32 txq_id)
 560 {
 561         int ret;
 562
 563         txq->need_update = false;
 564
 565         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 566          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 567         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 568
 569         /* Initialize queue's high/low-water marks, and head/tail indexes */
 570         ret = iwl_queue_init(&txq->q, slots_num, txq_id);
 571         if (ret)
 572                 return ret;
 573
 574         spin_lock_init(&txq->lock);
 575         __skb_queue_head_init(&txq->overflow_q);
 576
 577         /*
 578          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 579          * given Tx queue, and enable the DMA channel used for that queue.
 580          * Circular buffer (TFD queue in DRAM) physical base address */
 581         iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 582                            txq->q.dma_addr >> 8);
 583
 584         return 0;
 585 }
 586
 587 static void iwl_pcie_free_tso_page(struct sk_buff *skb)
 588 {
 589         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
 590
 591         if (info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA]) {
 592                 struct page *page =
 593                         info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA];
 594
 595                 __free_page(page);
 596                 info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA] = NULL;
 597         }
 598 }
 599
 600 /*
 601  * iwl_pcie_txq_unmap -  Unmap any remaining DMA mappings and free skb's
 602  */
 603 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
 604 {
 605         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 606         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
 607         struct iwl_queue *q = &txq->q;
 608
 609         spin_lock_bh(&txq->lock);
 610         while (q->write_ptr != q->read_ptr) {
 611                 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
 612                                    txq_id, q->read_ptr);
 613
 614                 if (txq_id != trans_pcie->cmd_queue) {
 615                         struct sk_buff *skb = txq->entries[q->read_ptr].skb;
 616
 617                         if (WARN_ON_ONCE(!skb))
 618                                 continue;
 619
 620                         iwl_pcie_free_tso_page(skb);
 621                 }
 622                 iwl_pcie_txq_free_tfd(trans, txq);
 623                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr);
 624         }
 625         txq->active = false;
 626
 627         while (!skb_queue_empty(&txq->overflow_q)) {
 628                 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q);
 629
 630                 iwl_op_mode_free_skb(trans->op_mode, skb);
 631         }
 632
 633         spin_unlock_bh(&txq->lock);
 634
 635         /* just in case - this queue may have been stopped */
 636         iwl_wake_queue(trans, txq);
 637 }
 638
 639 /*
 640  * iwl_pcie_txq_free - Deallocate DMA queue.
 641  * @txq: Transmit queue to deallocate.
 642  *
 643  * Empty queue by removing and destroying all BD's.
 644  * Free all buffers.
 645  * 0-fill, but do not free "txq" descriptor structure.
 646  */
 647 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
 648 {
 649         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 650         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
 651         struct device *dev = trans->dev;
 652         int i;
 653
 654         if (WARN_ON(!txq))
 655                 return;
 656
 657         iwl_pcie_txq_unmap(trans, txq_id);
 658
 659         /* De-alloc array of command/tx buffers */
 660         if (txq_id == trans_pcie->cmd_queue)
 661                 for (i = 0; i < txq->q.n_window; i++) {
 662                         kzfree(txq->entries[i].cmd);
 663                         kzfree(txq->entries[i].free_buf);
 664                 }
 665
 666         /* De-alloc circular buffer of TFDs */
 667         if (txq->tfds) {
 668                 dma_free_coherent(dev,
 669                                   sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX,
 670                                   txq->tfds, txq->q.dma_addr);
 671                 txq->q.dma_addr = 0;
 672                 txq->tfds = NULL;
 673
 674                 dma_free_coherent(dev,
 675                                   sizeof(*txq->scratchbufs) * txq->q.n_window,
 676                                   txq->scratchbufs, txq->scratchbufs_dma);
 677         }
 678
 679         kfree(txq->entries);
 680         txq->entries = NULL;
 681
 682         del_timer_sync(&txq->stuck_timer);
 683
 684         /* 0-fill queue descriptor structure */
 685         memset(txq, 0, sizeof(*txq));
 686 }
 687
 688 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
 689 {
 690         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 691         int nq = trans->cfg->base_params->num_of_queues;
 692         int chan;
 693         u32 reg_val;
 694         int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
 695                                 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
 696
 697         /* make sure all queue are not stopped/used */
 698         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
 699         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 700
 701         trans_pcie->scd_base_addr =
 702                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
 703
 704         WARN_ON(scd_base_addr != 0 &&
 705                 scd_base_addr != trans_pcie->scd_base_addr);
 706
 707         /* reset context data, TX status and translation data */
 708         iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
 709                                    SCD_CONTEXT_MEM_LOWER_BOUND,
 710                             NULL, clear_dwords);
 711
 712         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
 713                        trans_pcie->scd_bc_tbls.dma >> 10);
 714
 715         /* The chain extension of the SCD doesn't work well. This feature is
 716          * enabled by default by the HW, so we need to disable it manually.
 717          */
 718         if (trans->cfg->base_params->scd_chain_ext_wa)
 719                 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
 720
 721         iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
 722                                 trans_pcie->cmd_fifo,
 723                                 trans_pcie->cmd_q_wdg_timeout);
 724
 725         /* Activate all Tx DMA/FIFO channels */
 726         iwl_scd_activate_fifos(trans);
 727
 728         /* Enable DMA channel */
 729         for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
 730                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 731                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 732                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 733
 734         /* Update FH chicken bits */
 735         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
 736         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
 737                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 738
 739         /* Enable L1-Active */
 740         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 741                 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 742                                     APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 743 }
 744
 745 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
 746 {
 747         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 748         int txq_id;
 749
 750         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 751              txq_id++) {
 752                 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
 753
 754                 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 755                                    txq->q.dma_addr >> 8);
 756                 iwl_pcie_txq_unmap(trans, txq_id);
 757                 txq->q.read_ptr = 0;
 758                 txq->q.write_ptr = 0;
 759         }
 760
 761         /* Tell NIC where to find the "keep warm" buffer */
 762         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 763                            trans_pcie->kw.dma >> 4);
 764
 765         /*
 766          * Send 0 as the scd_base_addr since the device may have be reset
 767          * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
 768          * contain garbage.
 769          */
 770         iwl_pcie_tx_start(trans, 0);
 771 }
 772
 773 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
 774 {
 775         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 776         unsigned long flags;
 777         int ch, ret;
 778         u32 mask = 0;
 779
 780         spin_lock(&trans_pcie->irq_lock);
 781
 782         if (!iwl_trans_grab_nic_access(trans, &flags))
 783                 goto out;
 784
 785         /* Stop each Tx DMA channel */
 786         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
 787                 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
 788                 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
 789         }
 790
 791         /* Wait for DMA channels to be idle */
 792         ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
 793         if (ret < 0)
 794                 IWL_ERR(trans,
 795                         "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
 796                         ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
 797
 798         iwl_trans_release_nic_access(trans, &flags);
 799
 800 out:
 801         spin_unlock(&trans_pcie->irq_lock);
 802 }
 803
 804 /*
 805  * iwl_pcie_tx_stop - Stop all Tx DMA channels
 806  */
 807 int iwl_pcie_tx_stop(struct iwl_trans *trans)
 808 {
 809         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 810         int txq_id;
 811
 812         /* Turn off all Tx DMA fifos */
 813         iwl_scd_deactivate_fifos(trans);
 814
 815         /* Turn off all Tx DMA channels */
 816         iwl_pcie_tx_stop_fh(trans);
 817
 818         /*
 819          * This function can be called before the op_mode disabled the
 820          * queues. This happens when we have an rfkill interrupt.
 821          * Since we stop Tx altogether - mark the queues as stopped.
 822          */
 823         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
 824         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 825
 826         /* This can happen: start_hw, stop_device */
 827         if (!trans_pcie->txq)
 828                 return 0;
 829
 830         /* Unmap DMA from host system and free skb's */
 831         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 832              txq_id++)
 833                 iwl_pcie_txq_unmap(trans, txq_id);
 834
 835         return 0;
 836 }
 837
 838 /*
 839  * iwl_trans_tx_free - Free TXQ Context
 840  *
 841  * Destroy all TX DMA queues and structures
 842  */
 843 void iwl_pcie_tx_free(struct iwl_trans *trans)
 844 {
 845         int txq_id;
 846         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 847
 848         /* Tx queues */
 849         if (trans_pcie->txq) {
 850                 for (txq_id = 0;
 851                      txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
 852                         iwl_pcie_txq_free(trans, txq_id);
 853         }
 854
 855         kfree(trans_pcie->txq);
 856         trans_pcie->txq = NULL;
 857
 858         iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
 859
 860         iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 861 }
 862
 863 /*
 864  * iwl_pcie_tx_alloc - allocate TX context
 865  * Allocate all Tx DMA structures and initialize them
 866  */
 867 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
 868 {
 869         int ret;
 870         int txq_id, slots_num;
 871         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 872
 873         u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
 874                         sizeof(struct iwlagn_scd_bc_tbl);
 875
 876         /*It is not allowed to alloc twice, so warn when this happens.
 877          * We cannot rely on the previous allocation, so free and fail */
 878         if (WARN_ON(trans_pcie->txq)) {
 879                 ret = -EINVAL;
 880                 goto error;
 881         }
 882
 883         ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 884                                    scd_bc_tbls_size);
 885         if (ret) {
 886                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 887                 goto error;
 888         }
 889
 890         /* Alloc keep-warm buffer */
 891         ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 892         if (ret) {
 893                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 894                 goto error;
 895         }
 896
 897         trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
 898                                   sizeof(struct iwl_txq), GFP_KERNEL);
 899         if (!trans_pcie->txq) {
 900                 IWL_ERR(trans, "Not enough memory for txq\n");
 901                 ret = -ENOMEM;
 902                 goto error;
 903         }
 904
 905         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 906         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 907              txq_id++) {
 908                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
 909                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 910                 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id],
 911                                           slots_num, txq_id);
 912                 if (ret) {
 913                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 914                         goto error;
 915                 }
 916         }
 917
 918         return 0;
 919
 920 error:
 921         iwl_pcie_tx_free(trans);
 922
 923         return ret;
 924 }
 925 int iwl_pcie_tx_init(struct iwl_trans *trans)
 926 {
 927         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 928         int ret;
 929         int txq_id, slots_num;
 930         bool alloc = false;
 931
 932         if (!trans_pcie->txq) {
 933                 ret = iwl_pcie_tx_alloc(trans);
 934                 if (ret)
 935                         goto error;
 936                 alloc = true;
 937         }
 938
 939         spin_lock(&trans_pcie->irq_lock);
 940
 941         /* Turn off all Tx DMA fifos */
 942         iwl_scd_deactivate_fifos(trans);
 943
 944         /* Tell NIC where to find the "keep warm" buffer */
 945         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 946                            trans_pcie->kw.dma >> 4);
 947
 948         spin_unlock(&trans_pcie->irq_lock);
 949
 950         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 951         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 952              txq_id++) {
 953                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
 954                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 955                 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id],
 956                                          slots_num, txq_id);
 957                 if (ret) {
 958                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 959                         goto error;
 960                 }
 961         }
 962
 963         iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
 964         if (trans->cfg->base_params->num_of_queues > 20)
 965                 iwl_set_bits_prph(trans, SCD_GP_CTRL,
 966                                   SCD_GP_CTRL_ENABLE_31_QUEUES);
 967
 968         return 0;
 969 error:
 970         /*Upon error, free only if we allocated something */
 971         if (alloc)
 972                 iwl_pcie_tx_free(trans);
 973         return ret;
 974 }
 975
 976 static inline void iwl_pcie_txq_progress(struct iwl_txq *txq)
 977 {
 978         lockdep_assert_held(&txq->lock);
 979
 980         if (!txq->wd_timeout)
 981                 return;
 982
 983         /*
 984          * station is asleep and we send data - that must
 985          * be uAPSD or PS-Poll. Don't rearm the timer.
 986          */
 987         if (txq->frozen)
 988                 return;
 989
 990         /*
 991          * if empty delete timer, otherwise move timer forward
 992          * since we're making progress on this queue
 993          */
 994         if (txq->q.read_ptr == txq->q.write_ptr)
 995                 del_timer(&txq->stuck_timer);
 996         else
 997                 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
 998 }
 999
1000 /* Frees buffers until index _not_ inclusive */
1001 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1002                             struct sk_buff_head *skbs)
1003 {
1004         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1005         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1006         int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1);
1007         struct iwl_queue *q = &txq->q;
1008         int last_to_free;
1009
1010         /* This function is not meant to release cmd queue*/
1011         if (WARN_ON(txq_id == trans_pcie->cmd_queue))
1012                 return;
1013
1014         spin_lock_bh(&txq->lock);
1015
1016         if (!txq->active) {
1017                 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
1018                                     txq_id, ssn);
1019                 goto out;
1020         }
1021
1022         if (txq->q.read_ptr == tfd_num)
1023                 goto out;
1024
1025         IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1026                            txq_id, txq->q.read_ptr, tfd_num, ssn);
1027
1028         /*Since we free until index _not_ inclusive, the one before index is
1029          * the last we will free. This one must be used */
1030         last_to_free = iwl_queue_dec_wrap(tfd_num);
1031
1032         if (!iwl_queue_used(q, last_to_free)) {
1033                 IWL_ERR(trans,
1034                         "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
1035                         __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX,
1036                         q->write_ptr, q->read_ptr);
1037                 goto out;
1038         }
1039
1040         if (WARN_ON(!skb_queue_empty(skbs)))
1041                 goto out;
1042
1043         for (;
1044              q->read_ptr != tfd_num;
1045              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
1046                 struct sk_buff *skb = txq->entries[txq->q.read_ptr].skb;
1047
1048                 if (WARN_ON_ONCE(!skb))
1049                         continue;
1050
1051                 iwl_pcie_free_tso_page(skb);
1052
1053                 __skb_queue_tail(skbs, skb);
1054
1055                 txq->entries[txq->q.read_ptr].skb = NULL;
1056
1057                 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
1058
1059                 iwl_pcie_txq_free_tfd(trans, txq);
1060         }
1061
1062         iwl_pcie_txq_progress(txq);
1063
1064         if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1065             test_bit(txq_id, trans_pcie->queue_stopped)) {
1066                 struct sk_buff_head skbs;
1067
1068                 __skb_queue_head_init(&skbs);
1069                 skb_queue_splice_init(&txq->overflow_q, &skbs);
1070
1071                 /*
1072                  * This is tricky: we are in reclaim path which is non
1073                  * re-entrant, so noone will try to take the access the
1074                  * txq data from that path. We stopped tx, so we can't
1075                  * have tx as well. Bottom line, we can unlock and re-lock
1076                  * later.
1077                  */
1078                 spin_unlock_bh(&txq->lock);
1079
1080                 while (!skb_queue_empty(&skbs)) {
1081                         struct sk_buff *skb = __skb_dequeue(&skbs);
1082                         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1083                         u8 dev_cmd_idx = IWL_TRANS_FIRST_DRIVER_DATA + 1;
1084                         struct iwl_device_cmd *dev_cmd =
1085                                 info->driver_data[dev_cmd_idx];
1086
1087                         /*
1088                          * Note that we can very well be overflowing again.
1089                          * In that case, iwl_queue_space will be small again
1090                          * and we won't wake mac80211's queue.
1091                          */
1092                         iwl_trans_pcie_tx(trans, skb, dev_cmd, txq_id);
1093                 }
1094                 spin_lock_bh(&txq->lock);
1095
1096                 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1097                         iwl_wake_queue(trans, txq);
1098         }
1099
1100         if (q->read_ptr == q->write_ptr) {
1101                 IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", q->id);
1102                 iwl_trans_pcie_unref(trans);
1103         }
1104
1105 out:
1106         spin_unlock_bh(&txq->lock);
1107 }
1108
1109 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1110                                       const struct iwl_host_cmd *cmd)
1111 {
1112         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1113         int ret;
1114
1115         lockdep_assert_held(&trans_pcie->reg_lock);
1116
1117         if (!(cmd->flags & CMD_SEND_IN_IDLE) &&
1118             !trans_pcie->ref_cmd_in_flight) {
1119                 trans_pcie->ref_cmd_in_flight = true;
1120                 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n");
1121                 iwl_trans_pcie_ref(trans);
1122         }
1123
1124         /*
1125          * wake up the NIC to make sure that the firmware will see the host
1126          * command - we will let the NIC sleep once all the host commands
1127          * returned. This needs to be done only on NICs that have
1128          * apmg_wake_up_wa set.
1129          */
1130         if (trans->cfg->base_params->apmg_wake_up_wa &&
1131             !trans_pcie->cmd_hold_nic_awake) {
1132                 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1133                                          CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1134
1135                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1136                                    CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1137                                    (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1138                                     CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1139                                    15000);
1140                 if (ret < 0) {
1141                         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1142                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1143                         IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1144                         return -EIO;
1145                 }
1146                 trans_pcie->cmd_hold_nic_awake = true;
1147         }
1148
1149         return 0;
1150 }
1151
1152 static int iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
1153 {
1154         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1155
1156         lockdep_assert_held(&trans_pcie->reg_lock);
1157
1158         if (trans_pcie->ref_cmd_in_flight) {
1159                 trans_pcie->ref_cmd_in_flight = false;
1160                 IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n");
1161                 iwl_trans_pcie_unref(trans);
1162         }
1163
1164         if (trans->cfg->base_params->apmg_wake_up_wa) {
1165                 if (WARN_ON(!trans_pcie->cmd_hold_nic_awake))
1166                         return 0;
1167
1168                 trans_pcie->cmd_hold_nic_awake = false;
1169                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1170                                            CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1171         }
1172         return 0;
1173 }
1174
1175 /*
1176  * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1177  *
1178  * When FW advances 'R' index, all entries between old and new 'R' index
1179  * need to be reclaimed. As result, some free space forms.  If there is
1180  * enough free space (> low mark), wake the stack that feeds us.
1181  */
1182 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1183 {
1184         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1185         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1186         struct iwl_queue *q = &txq->q;
1187         unsigned long flags;
1188         int nfreed = 0;
1189
1190         lockdep_assert_held(&txq->lock);
1191
1192         if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) {
1193                 IWL_ERR(trans,
1194                         "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1195                         __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX,
1196                         q->write_ptr, q->read_ptr);
1197                 return;
1198         }
1199
1200         for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx;
1201              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
1202
1203                 if (nfreed++ > 0) {
1204                         IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1205                                 idx, q->write_ptr, q->read_ptr);
1206                         iwl_force_nmi(trans);
1207                 }
1208         }
1209
1210         if (q->read_ptr == q->write_ptr) {
1211                 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1212                 iwl_pcie_clear_cmd_in_flight(trans);
1213                 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1214         }
1215
1216         iwl_pcie_txq_progress(txq);
1217 }
1218
1219 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1220                                  u16 txq_id)
1221 {
1222         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1223         u32 tbl_dw_addr;
1224         u32 tbl_dw;
1225         u16 scd_q2ratid;
1226
1227         scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1228
1229         tbl_dw_addr = trans_pcie->scd_base_addr +
1230                         SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1231
1232         tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1233
1234         if (txq_id & 0x1)
1235                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1236         else
1237                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1238
1239         iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1240
1241         return 0;
1242 }
1243
1244 /* Receiver address (actually, Rx station's index into station table),
1245  * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1246 #define BUILD_RAxTID(sta_id, tid)       (((sta_id) << 4) + (tid))
1247
1248 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1249                                const struct iwl_trans_txq_scd_cfg *cfg,
1250                                unsigned int wdg_timeout)
1251 {
1252         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1253         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1254         int fifo = -1;
1255
1256         if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1257                 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1258
1259         txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1260
1261         if (cfg) {
1262                 fifo = cfg->fifo;
1263
1264                 /* Disable the scheduler prior configuring the cmd queue */
1265                 if (txq_id == trans_pcie->cmd_queue &&
1266                     trans_pcie->scd_set_active)
1267                         iwl_scd_enable_set_active(trans, 0);
1268
1269                 /* Stop this Tx queue before configuring it */
1270                 iwl_scd_txq_set_inactive(trans, txq_id);
1271
1272                 /* Set this queue as a chain-building queue unless it is CMD */
1273                 if (txq_id != trans_pcie->cmd_queue)
1274                         iwl_scd_txq_set_chain(trans, txq_id);
1275
1276                 if (cfg->aggregate) {
1277                         u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1278
1279                         /* Map receiver-address / traffic-ID to this queue */
1280                         iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1281
1282                         /* enable aggregations for the queue */
1283                         iwl_scd_txq_enable_agg(trans, txq_id);
1284                         txq->ampdu = true;
1285                 } else {
1286                         /*
1287                          * disable aggregations for the queue, this will also
1288                          * make the ra_tid mapping configuration irrelevant
1289                          * since it is now a non-AGG queue.
1290                          */
1291                         iwl_scd_txq_disable_agg(trans, txq_id);
1292
1293                         ssn = txq->q.read_ptr;
1294                 }
1295         }
1296
1297         /* Place first TFD at index corresponding to start sequence number.
1298          * Assumes that ssn_idx is valid (!= 0xFFF) */
1299         txq->q.read_ptr = (ssn & 0xff);
1300         txq->q.write_ptr = (ssn & 0xff);
1301         iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1302                            (ssn & 0xff) | (txq_id << 8));
1303
1304         if (cfg) {
1305                 u8 frame_limit = cfg->frame_limit;
1306
1307                 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1308
1309                 /* Set up Tx window size and frame limit for this queue */
1310                 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1311                                 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1312                 iwl_trans_write_mem32(trans,
1313                         trans_pcie->scd_base_addr +
1314                         SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1315                         ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1316                                         SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1317                         ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1318                                         SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1319
1320                 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1321                 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1322                                (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1323                                (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1324                                (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1325                                SCD_QUEUE_STTS_REG_MSK);
1326
1327                 /* enable the scheduler for this queue (only) */
1328                 if (txq_id == trans_pcie->cmd_queue &&
1329                     trans_pcie->scd_set_active)
1330                         iwl_scd_enable_set_active(trans, BIT(txq_id));
1331
1332                 IWL_DEBUG_TX_QUEUES(trans,
1333                                     "Activate queue %d on FIFO %d WrPtr: %d\n",
1334                                     txq_id, fifo, ssn & 0xff);
1335         } else {
1336                 IWL_DEBUG_TX_QUEUES(trans,
1337                                     "Activate queue %d WrPtr: %d\n",
1338                                     txq_id, ssn & 0xff);
1339         }
1340
1341         txq->active = true;
1342 }
1343
1344 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1345                                 bool configure_scd)
1346 {
1347         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1348         u32 stts_addr = trans_pcie->scd_base_addr +
1349                         SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1350         static const u32 zero_val[4] = {};
1351
1352         trans_pcie->txq[txq_id].frozen_expiry_remainder = 0;
1353         trans_pcie->txq[txq_id].frozen = false;
1354
1355         /*
1356          * Upon HW Rfkill - we stop the device, and then stop the queues
1357          * in the op_mode. Just for the sake of the simplicity of the op_mode,
1358          * allow the op_mode to call txq_disable after it already called
1359          * stop_device.
1360          */
1361         if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1362                 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1363                           "queue %d not used", txq_id);
1364                 return;
1365         }
1366
1367         if (configure_scd) {
1368                 iwl_scd_txq_set_inactive(trans, txq_id);
1369
1370                 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1371                                     ARRAY_SIZE(zero_val));
1372         }
1373
1374         iwl_pcie_txq_unmap(trans, txq_id);
1375         trans_pcie->txq[txq_id].ampdu = false;
1376
1377         IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1378 }
1379
1380 /*************** HOST COMMAND QUEUE FUNCTIONS   *****/
1381
1382 /*
1383  * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1384  * @priv: device private data point
1385  * @cmd: a pointer to the ucode command structure
1386  *
1387  * The function returns < 0 values to indicate the operation
1388  * failed. On success, it returns the index (>= 0) of command in the
1389  * command queue.
1390  */
1391 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1392                                  struct iwl_host_cmd *cmd)
1393 {
1394         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1395         struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1396         struct iwl_queue *q = &txq->q;
1397         struct iwl_device_cmd *out_cmd;
1398         struct iwl_cmd_meta *out_meta;
1399         unsigned long flags;
1400         void *dup_buf = NULL;
1401         dma_addr_t phys_addr;
1402         int idx;
1403         u16 copy_size, cmd_size, scratch_size;
1404         bool had_nocopy = false;
1405         u8 group_id = iwl_cmd_groupid(cmd->id);
1406         int i, ret;
1407         u32 cmd_pos;
1408         const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1409         u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1410
1411         if (WARN(!trans_pcie->wide_cmd_header &&
1412                  group_id > IWL_ALWAYS_LONG_GROUP,
1413                  "unsupported wide command %#x\n", cmd->id))
1414                 return -EINVAL;
1415
1416         if (group_id != 0) {
1417                 copy_size = sizeof(struct iwl_cmd_header_wide);
1418                 cmd_size = sizeof(struct iwl_cmd_header_wide);
1419         } else {
1420                 copy_size = sizeof(struct iwl_cmd_header);
1421                 cmd_size = sizeof(struct iwl_cmd_header);
1422         }
1423
1424         /* need one for the header if the first is NOCOPY */
1425         BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1426
1427         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1428                 cmddata[i] = cmd->data[i];
1429                 cmdlen[i] = cmd->len[i];
1430
1431                 if (!cmd->len[i])
1432                         continue;
1433
1434                 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1435                 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1436                         int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1437
1438                         if (copy > cmdlen[i])
1439                                 copy = cmdlen[i];
1440                         cmdlen[i] -= copy;
1441                         cmddata[i] += copy;
1442                         copy_size += copy;
1443                 }
1444
1445                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1446                         had_nocopy = true;
1447                         if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1448                                 idx = -EINVAL;
1449                                 goto free_dup_buf;
1450                         }
1451                 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1452                         /*
1453                          * This is also a chunk that isn't copied
1454                          * to the static buffer so set had_nocopy.
1455                          */
1456                         had_nocopy = true;
1457
1458                         /* only allowed once */
1459                         if (WARN_ON(dup_buf)) {
1460                                 idx = -EINVAL;
1461                                 goto free_dup_buf;
1462                         }
1463
1464                         dup_buf = kmemdup(cmddata[i], cmdlen[i],
1465                                           GFP_ATOMIC);
1466                         if (!dup_buf)
1467                                 return -ENOMEM;
1468                 } else {
1469                         /* NOCOPY must not be followed by normal! */
1470                         if (WARN_ON(had_nocopy)) {
1471                                 idx = -EINVAL;
1472                                 goto free_dup_buf;
1473                         }
1474                         copy_size += cmdlen[i];
1475                 }
1476                 cmd_size += cmd->len[i];
1477         }
1478
1479         /*
1480          * If any of the command structures end up being larger than
1481          * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1482          * allocated into separate TFDs, then we will need to
1483          * increase the size of the buffers.
1484          */
1485         if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1486                  "Command %s (%#x) is too large (%d bytes)\n",
1487                  iwl_get_cmd_string(trans, cmd->id),
1488                  cmd->id, copy_size)) {
1489                 idx = -EINVAL;
1490                 goto free_dup_buf;
1491         }
1492
1493         spin_lock_bh(&txq->lock);
1494
1495         if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1496                 spin_unlock_bh(&txq->lock);
1497
1498                 IWL_ERR(trans, "No space in command queue\n");
1499                 iwl_op_mode_cmd_queue_full(trans->op_mode);
1500                 idx = -ENOSPC;
1501                 goto free_dup_buf;
1502         }
1503
1504         idx = get_cmd_index(q, q->write_ptr);
1505         out_cmd = txq->entries[idx].cmd;
1506         out_meta = &txq->entries[idx].meta;
1507
1508         memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1509         if (cmd->flags & CMD_WANT_SKB)
1510                 out_meta->source = cmd;
1511
1512         /* set up the header */
1513         if (group_id != 0) {
1514                 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
1515                 out_cmd->hdr_wide.group_id = group_id;
1516                 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
1517                 out_cmd->hdr_wide.length =
1518                         cpu_to_le16(cmd_size -
1519                                     sizeof(struct iwl_cmd_header_wide));
1520                 out_cmd->hdr_wide.reserved = 0;
1521                 out_cmd->hdr_wide.sequence =
1522                         cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1523                                                  INDEX_TO_SEQ(q->write_ptr));
1524
1525                 cmd_pos = sizeof(struct iwl_cmd_header_wide);
1526                 copy_size = sizeof(struct iwl_cmd_header_wide);
1527         } else {
1528                 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id);
1529                 out_cmd->hdr.sequence =
1530                         cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1531                                                  INDEX_TO_SEQ(q->write_ptr));
1532                 out_cmd->hdr.group_id = 0;
1533
1534                 cmd_pos = sizeof(struct iwl_cmd_header);
1535                 copy_size = sizeof(struct iwl_cmd_header);
1536         }
1537
1538         /* and copy the data that needs to be copied */
1539         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1540                 int copy;
1541
1542                 if (!cmd->len[i])
1543                         continue;
1544
1545                 /* copy everything if not nocopy/dup */
1546                 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1547                                            IWL_HCMD_DFL_DUP))) {
1548                         copy = cmd->len[i];
1549
1550                         memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1551                         cmd_pos += copy;
1552                         copy_size += copy;
1553                         continue;
1554                 }
1555
1556                 /*
1557                  * Otherwise we need at least IWL_HCMD_SCRATCHBUF_SIZE copied
1558                  * in total (for the scratchbuf handling), but copy up to what
1559                  * we can fit into the payload for debug dump purposes.
1560                  */
1561                 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1562
1563                 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1564                 cmd_pos += copy;
1565
1566                 /* However, treat copy_size the proper way, we need it below */
1567                 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1568                         copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1569
1570                         if (copy > cmd->len[i])
1571                                 copy = cmd->len[i];
1572                         copy_size += copy;
1573                 }
1574         }
1575
1576         IWL_DEBUG_HC(trans,
1577                      "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1578                      iwl_get_cmd_string(trans, cmd->id),
1579                      group_id, out_cmd->hdr.cmd,
1580                      le16_to_cpu(out_cmd->hdr.sequence),
1581                      cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
1582
1583         /* start the TFD with the scratchbuf */
1584         scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE);
1585         memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size);
1586         iwl_pcie_txq_build_tfd(trans, txq,
1587                                iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr),
1588                                scratch_size, true);
1589
1590         /* map first command fragment, if any remains */
1591         if (copy_size > scratch_size) {
1592                 phys_addr = dma_map_single(trans->dev,
1593                                            ((u8 *)&out_cmd->hdr) + scratch_size,
1594                                            copy_size - scratch_size,
1595                                            DMA_TO_DEVICE);
1596                 if (dma_mapping_error(trans->dev, phys_addr)) {
1597                         iwl_pcie_tfd_unmap(trans, out_meta,
1598                                            &txq->tfds[q->write_ptr]);
1599                         idx = -ENOMEM;
1600                         goto out;
1601                 }
1602
1603                 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1604                                        copy_size - scratch_size, false);
1605         }
1606
1607         /* map the remaining (adjusted) nocopy/dup fragments */
1608         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1609                 const void *data = cmddata[i];
1610
1611                 if (!cmdlen[i])
1612                         continue;
1613                 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1614                                            IWL_HCMD_DFL_DUP)))
1615                         continue;
1616                 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1617                         data = dup_buf;
1618                 phys_addr = dma_map_single(trans->dev, (void *)data,
1619                                            cmdlen[i], DMA_TO_DEVICE);
1620                 if (dma_mapping_error(trans->dev, phys_addr)) {
1621                         iwl_pcie_tfd_unmap(trans, out_meta,
1622                                            &txq->tfds[q->write_ptr]);
1623                         idx = -ENOMEM;
1624                         goto out;
1625                 }
1626
1627                 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1628         }
1629
1630         BUILD_BUG_ON(IWL_NUM_OF_TBS + CMD_TB_BITMAP_POS >
1631                      sizeof(out_meta->flags) * BITS_PER_BYTE);
1632         out_meta->flags = cmd->flags;
1633         if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1634                 kzfree(txq->entries[idx].free_buf);
1635         txq->entries[idx].free_buf = dup_buf;
1636
1637         trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
1638
1639         /* start timer if queue currently empty */
1640         if (q->read_ptr == q->write_ptr && txq->wd_timeout)
1641                 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1642
1643         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1644         ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
1645         if (ret < 0) {
1646                 idx = ret;
1647                 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1648                 goto out;
1649         }
1650
1651         /* Increment and update queue's write index */
1652         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
1653         iwl_pcie_txq_inc_wr_ptr(trans, txq);
1654
1655         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1656
1657  out:
1658         spin_unlock_bh(&txq->lock);
1659  free_dup_buf:
1660         if (idx < 0)
1661                 kfree(dup_buf);
1662         return idx;
1663 }
1664
1665 /*
1666  * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1667  * @rxb: Rx buffer to reclaim
1668  */
1669 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1670                             struct iwl_rx_cmd_buffer *rxb)
1671 {
1672         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1673         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1674         u8 group_id = iwl_cmd_groupid(pkt->hdr.group_id);
1675         u32 cmd_id;
1676         int txq_id = SEQ_TO_QUEUE(sequence);
1677         int index = SEQ_TO_INDEX(sequence);
1678         int cmd_index;
1679         struct iwl_device_cmd *cmd;
1680         struct iwl_cmd_meta *meta;
1681         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1682         struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1683
1684         /* If a Tx command is being handled and it isn't in the actual
1685          * command queue then there a command routing bug has been introduced
1686          * in the queue management code. */
1687         if (WARN(txq_id != trans_pcie->cmd_queue,
1688                  "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1689                  txq_id, trans_pcie->cmd_queue, sequence,
1690                  trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
1691                  trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
1692                 iwl_print_hex_error(trans, pkt, 32);
1693                 return;
1694         }
1695
1696         spin_lock_bh(&txq->lock);
1697
1698         cmd_index = get_cmd_index(&txq->q, index);
1699         cmd = txq->entries[cmd_index].cmd;
1700         meta = &txq->entries[cmd_index].meta;
1701         cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0);
1702
1703         iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]);
1704
1705         /* Input error checking is done when commands are added to queue. */
1706         if (meta->flags & CMD_WANT_SKB) {
1707                 struct page *p = rxb_steal_page(rxb);
1708
1709                 meta->source->resp_pkt = pkt;
1710                 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1711                 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1712         }
1713
1714         if (meta->flags & CMD_WANT_ASYNC_CALLBACK)
1715                 iwl_op_mode_async_cb(trans->op_mode, cmd);
1716
1717         iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1718
1719         if (!(meta->flags & CMD_ASYNC)) {
1720                 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1721                         IWL_WARN(trans,
1722                                  "HCMD_ACTIVE already clear for command %s\n",
1723                                  iwl_get_cmd_string(trans, cmd_id));
1724                 }
1725                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1726                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1727                                iwl_get_cmd_string(trans, cmd_id));
1728                 wake_up(&trans_pcie->wait_command_queue);
1729         }
1730
1731         if (meta->flags & CMD_MAKE_TRANS_IDLE) {
1732                 IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n",
1733                                iwl_get_cmd_string(trans, cmd->hdr.cmd));
1734                 set_bit(STATUS_TRANS_IDLE, &trans->status);
1735                 wake_up(&trans_pcie->d0i3_waitq);
1736         }
1737
1738         if (meta->flags & CMD_WAKE_UP_TRANS) {
1739                 IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n",
1740                                iwl_get_cmd_string(trans, cmd->hdr.cmd));
1741                 clear_bit(STATUS_TRANS_IDLE, &trans->status);
1742                 wake_up(&trans_pcie->d0i3_waitq);
1743         }
1744
1745         meta->flags = 0;
1746
1747         spin_unlock_bh(&txq->lock);
1748 }
1749
1750 #define HOST_COMPLETE_TIMEOUT   (2 * HZ)
1751
1752 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1753                                     struct iwl_host_cmd *cmd)
1754 {
1755         int ret;
1756
1757         /* An asynchronous command can not expect an SKB to be set. */
1758         if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1759                 return -EINVAL;
1760
1761         ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1762         if (ret < 0) {
1763                 IWL_ERR(trans,
1764                         "Error sending %s: enqueue_hcmd failed: %d\n",
1765                         iwl_get_cmd_string(trans, cmd->id), ret);
1766                 return ret;
1767         }
1768         return 0;
1769 }
1770
1771 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1772                                    struct iwl_host_cmd *cmd)
1773 {
1774         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1775         int cmd_idx;
1776         int ret;
1777
1778         IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1779                        iwl_get_cmd_string(trans, cmd->id));
1780
1781         if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1782                                   &trans->status),
1783                  "Command %s: a command is already active!\n",
1784                  iwl_get_cmd_string(trans, cmd->id)))
1785                 return -EIO;
1786
1787         IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1788                        iwl_get_cmd_string(trans, cmd->id));
1789
1790         cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1791         if (cmd_idx < 0) {
1792                 ret = cmd_idx;
1793                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1794                 IWL_ERR(trans,
1795                         "Error sending %s: enqueue_hcmd failed: %d\n",
1796                         iwl_get_cmd_string(trans, cmd->id), ret);
1797                 return ret;
1798         }
1799
1800         ret = wait_event_timeout(trans_pcie->wait_command_queue,
1801                                  !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1802                                            &trans->status),
1803                                  HOST_COMPLETE_TIMEOUT);
1804         if (!ret) {
1805                 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1806                 struct iwl_queue *q = &txq->q;
1807
1808                 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1809                         iwl_get_cmd_string(trans, cmd->id),
1810                         jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1811
1812                 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1813                         q->read_ptr, q->write_ptr);
1814
1815                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1816                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1817                                iwl_get_cmd_string(trans, cmd->id));
1818                 ret = -ETIMEDOUT;
1819
1820                 iwl_force_nmi(trans);
1821                 iwl_trans_fw_error(trans);
1822
1823                 goto cancel;
1824         }
1825
1826         if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1827                 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1828                         iwl_get_cmd_string(trans, cmd->id));
1829                 dump_stack();
1830                 ret = -EIO;
1831                 goto cancel;
1832         }
1833
1834         if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1835             test_bit(STATUS_RFKILL, &trans->status)) {
1836                 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1837                 ret = -ERFKILL;
1838                 goto cancel;
1839         }
1840
1841         if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1842                 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1843                         iwl_get_cmd_string(trans, cmd->id));
1844                 ret = -EIO;
1845                 goto cancel;
1846         }
1847
1848         return 0;
1849
1850 cancel:
1851         if (cmd->flags & CMD_WANT_SKB) {
1852                 /*
1853                  * Cancel the CMD_WANT_SKB flag for the cmd in the
1854                  * TX cmd queue. Otherwise in case the cmd comes
1855                  * in later, it will possibly set an invalid
1856                  * address (cmd->meta.source).
1857                  */
1858                 trans_pcie->txq[trans_pcie->cmd_queue].
1859                         entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1860         }
1861
1862         if (cmd->resp_pkt) {
1863                 iwl_free_resp(cmd);
1864                 cmd->resp_pkt = NULL;
1865         }
1866
1867         return ret;
1868 }
1869
1870 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1871 {
1872         if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1873             test_bit(STATUS_RFKILL, &trans->status)) {
1874                 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1875                                   cmd->id);
1876                 return -ERFKILL;
1877         }
1878
1879         if (cmd->flags & CMD_ASYNC)
1880                 return iwl_pcie_send_hcmd_async(trans, cmd);
1881
1882         /* We still can fail on RFKILL that can be asserted while we wait */
1883         return iwl_pcie_send_hcmd_sync(trans, cmd);
1884 }
1885
1886 static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb,
1887                              struct iwl_txq *txq, u8 hdr_len,
1888                              struct iwl_cmd_meta *out_meta,
1889                              struct iwl_device_cmd *dev_cmd, u16 tb1_len)
1890 {
1891         struct iwl_queue *q = &txq->q;
1892         u16 tb2_len;
1893         int i;
1894
1895         /*
1896          * Set up TFD's third entry to point directly to remainder
1897          * of skb's head, if any
1898          */
1899         tb2_len = skb_headlen(skb) - hdr_len;
1900
1901         if (tb2_len > 0) {
1902                 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1903                                                      skb->data + hdr_len,
1904                                                      tb2_len, DMA_TO_DEVICE);
1905                 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
1906                         iwl_pcie_tfd_unmap(trans, out_meta,
1907                                            &txq->tfds[q->write_ptr]);
1908                         return -EINVAL;
1909                 }
1910                 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false);
1911         }
1912
1913         /* set up the remaining entries to point to the data */
1914         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1915                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1916                 dma_addr_t tb_phys;
1917                 int tb_idx;
1918
1919                 if (!skb_frag_size(frag))
1920                         continue;
1921
1922                 tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
1923                                            skb_frag_size(frag), DMA_TO_DEVICE);
1924
1925                 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
1926                         iwl_pcie_tfd_unmap(trans, out_meta,
1927                                            &txq->tfds[q->write_ptr]);
1928                         return -EINVAL;
1929                 }
1930                 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
1931                                                 skb_frag_size(frag), false);
1932
1933                 out_meta->flags |= BIT(tb_idx + CMD_TB_BITMAP_POS);
1934         }
1935
1936         trace_iwlwifi_dev_tx(trans->dev, skb,
1937                              &txq->tfds[txq->q.write_ptr],
1938                              sizeof(struct iwl_tfd),
1939                              &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
1940                              skb->data + hdr_len, tb2_len);
1941         trace_iwlwifi_dev_tx_data(trans->dev, skb,
1942                                   hdr_len, skb->len - hdr_len);
1943         return 0;
1944 }
1945
1946 #ifdef CONFIG_INET
1947 static struct iwl_tso_hdr_page *
1948 get_page_hdr(struct iwl_trans *trans, size_t len)
1949 {
1950         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1951         struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page);
1952
1953         if (!p->page)
1954                 goto alloc;
1955
1956         /* enough room on this page */
1957         if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE)
1958                 return p;
1959
1960         /* We don't have enough room on this page, get a new one. */
1961         __free_page(p->page);
1962
1963 alloc:
1964         p->page = alloc_page(GFP_ATOMIC);
1965         if (!p->page)
1966                 return NULL;
1967         p->pos = page_address(p->page);
1968         return p;
1969 }
1970
1971 static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph,
1972                                         bool ipv6, unsigned int len)
1973 {
1974         if (ipv6) {
1975                 struct ipv6hdr *iphv6 = iph;
1976
1977                 tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr,
1978                                                len + tcph->doff * 4,
1979                                                IPPROTO_TCP, 0);
1980         } else {
1981                 struct iphdr *iphv4 = iph;
1982
1983                 ip_send_check(iphv4);
1984                 tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr,
1985                                                  len + tcph->doff * 4,
1986                                                  IPPROTO_TCP, 0);
1987         }
1988 }
1989
1990 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
1991                                    struct iwl_txq *txq, u8 hdr_len,
1992                                    struct iwl_cmd_meta *out_meta,
1993                                    struct iwl_device_cmd *dev_cmd, u16 tb1_len)
1994 {
1995         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1996         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
1997         struct ieee80211_hdr *hdr = (void *)skb->data;
1998         unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room;
1999         unsigned int mss = skb_shinfo(skb)->gso_size;
2000         struct iwl_queue *q = &txq->q;
2001         u16 length, iv_len, amsdu_pad;
2002         u8 *start_hdr;
2003         struct iwl_tso_hdr_page *hdr_page;
2004         int ret;
2005         struct tso_t tso;
2006
2007         /* if the packet is protected, then it must be CCMP or GCMP */
2008         BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN);
2009         iv_len = ieee80211_has_protected(hdr->frame_control) ?
2010                 IEEE80211_CCMP_HDR_LEN : 0;
2011
2012         trace_iwlwifi_dev_tx(trans->dev, skb,
2013                              &txq->tfds[txq->q.write_ptr],
2014                              sizeof(struct iwl_tfd),
2015                              &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
2016                              NULL, 0);
2017
2018         ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb);
2019         snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb);
2020         total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len;
2021         amsdu_pad = 0;
2022
2023         /* total amount of header we may need for this A-MSDU */
2024         hdr_room = DIV_ROUND_UP(total_len, mss) *
2025                 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len;
2026
2027         /* Our device supports 9 segments at most, it will fit in 1 page */
2028         hdr_page = get_page_hdr(trans, hdr_room);
2029         if (!hdr_page)
2030                 return -ENOMEM;
2031
2032         get_page(hdr_page->page);
2033         start_hdr = hdr_page->pos;
2034         info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA] = hdr_page->page;
2035         memcpy(hdr_page->pos, skb->data + hdr_len, iv_len);
2036         hdr_page->pos += iv_len;
2037
2038         /*
2039          * Pull the ieee80211 header + IV to be able to use TSO core,
2040          * we will restore it for the tx_status flow.
2041          */
2042         skb_pull(skb, hdr_len + iv_len);
2043
2044         tso_start(skb, &tso);
2045
2046         while (total_len) {
2047                 /* this is the data left for this subframe */
2048                 unsigned int data_left =
2049                         min_t(unsigned int, mss, total_len);
2050                 struct sk_buff *csum_skb = NULL;
2051                 unsigned int hdr_tb_len;
2052                 dma_addr_t hdr_tb_phys;
2053                 struct tcphdr *tcph;
2054                 u8 *iph;
2055
2056                 total_len -= data_left;
2057
2058                 memset(hdr_page->pos, 0, amsdu_pad);
2059                 hdr_page->pos += amsdu_pad;
2060                 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen +
2061                                   data_left)) & 0x3;
2062                 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr));
2063                 hdr_page->pos += ETH_ALEN;
2064                 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr));
2065                 hdr_page->pos += ETH_ALEN;
2066
2067                 length = snap_ip_tcp_hdrlen + data_left;
2068                 *((__be16 *)hdr_page->pos) = cpu_to_be16(length);
2069                 hdr_page->pos += sizeof(length);
2070
2071                 /*
2072                  * This will copy the SNAP as well which will be considered
2073                  * as MAC header.
2074                  */
2075                 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len);
2076                 iph = hdr_page->pos + 8;
2077                 tcph = (void *)(iph + ip_hdrlen);
2078
2079                 /* For testing on current hardware only */
2080                 if (trans_pcie->sw_csum_tx) {
2081                         csum_skb = alloc_skb(data_left + tcp_hdrlen(skb),
2082                                              GFP_ATOMIC);
2083                         if (!csum_skb) {
2084                                 ret = -ENOMEM;
2085                                 goto out_unmap;
2086                         }
2087
2088                         iwl_compute_pseudo_hdr_csum(iph, tcph,
2089                                                     skb->protocol ==
2090                                                         htons(ETH_P_IPV6),
2091                                                     data_left);
2092
2093                         memcpy(skb_put(csum_skb, tcp_hdrlen(skb)),
2094                                tcph, tcp_hdrlen(skb));
2095                         skb_set_transport_header(csum_skb, 0);
2096                         csum_skb->csum_start =
2097                                 (unsigned char *)tcp_hdr(csum_skb) -
2098                                                  csum_skb->head;
2099                 }
2100
2101                 hdr_page->pos += snap_ip_tcp_hdrlen;
2102
2103                 hdr_tb_len = hdr_page->pos - start_hdr;
2104                 hdr_tb_phys = dma_map_single(trans->dev, start_hdr,
2105                                              hdr_tb_len, DMA_TO_DEVICE);
2106                 if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) {
2107                         dev_kfree_skb(csum_skb);
2108                         ret = -EINVAL;
2109                         goto out_unmap;
2110                 }
2111                 iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys,
2112                                        hdr_tb_len, false);
2113                 trace_iwlwifi_dev_tx_tso_chunk(trans->dev, start_hdr,
2114                                                hdr_tb_len);
2115
2116                 /* prepare the start_hdr for the next subframe */
2117                 start_hdr = hdr_page->pos;
2118
2119                 /* put the payload */
2120                 while (data_left) {
2121                         unsigned int size = min_t(unsigned int, tso.size,
2122                                                   data_left);
2123                         dma_addr_t tb_phys;
2124
2125                         if (trans_pcie->sw_csum_tx)
2126                                 memcpy(skb_put(csum_skb, size), tso.data, size);
2127
2128                         tb_phys = dma_map_single(trans->dev, tso.data,
2129                                                  size, DMA_TO_DEVICE);
2130                         if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
2131                                 dev_kfree_skb(csum_skb);
2132                                 ret = -EINVAL;
2133                                 goto out_unmap;
2134                         }
2135
2136                         iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2137                                                size, false);
2138                         trace_iwlwifi_dev_tx_tso_chunk(trans->dev, tso.data,
2139                                                        size);
2140
2141                         data_left -= size;
2142                         tso_build_data(skb, &tso, size);
2143                 }
2144
2145                 /* For testing on early hardware only */
2146                 if (trans_pcie->sw_csum_tx) {
2147                         __wsum csum;
2148
2149                         csum = skb_checksum(csum_skb,
2150                                             skb_checksum_start_offset(csum_skb),
2151                                             csum_skb->len -
2152                                             skb_checksum_start_offset(csum_skb),
2153                                             0);
2154                         dev_kfree_skb(csum_skb);
2155                         dma_sync_single_for_cpu(trans->dev, hdr_tb_phys,
2156                                                 hdr_tb_len, DMA_TO_DEVICE);
2157                         tcph->check = csum_fold(csum);
2158                         dma_sync_single_for_device(trans->dev, hdr_tb_phys,
2159                                                    hdr_tb_len, DMA_TO_DEVICE);
2160                 }
2161         }
2162
2163         /* re -add the WiFi header and IV */
2164         skb_push(skb, hdr_len + iv_len);
2165
2166         return 0;
2167
2168 out_unmap:
2169         iwl_pcie_tfd_unmap(trans, out_meta, &txq->tfds[q->write_ptr]);
2170         return ret;
2171 }
2172 #else /* CONFIG_INET */
2173 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2174                                    struct iwl_txq *txq, u8 hdr_len,
2175                                    struct iwl_cmd_meta *out_meta,
2176                                    struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2177 {
2178         /* No A-MSDU without CONFIG_INET */
2179         WARN_ON(1);
2180
2181         return -1;
2182 }
2183 #endif /* CONFIG_INET */
2184
2185 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
2186                       struct iwl_device_cmd *dev_cmd, int txq_id)
2187 {
2188         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2189         struct ieee80211_hdr *hdr;
2190         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
2191         struct iwl_cmd_meta *out_meta;
2192         struct iwl_txq *txq;
2193         struct iwl_queue *q;
2194         dma_addr_t tb0_phys, tb1_phys, scratch_phys;
2195         void *tb1_addr;
2196         u16 len, tb1_len;
2197         bool wait_write_ptr;
2198         __le16 fc;
2199         u8 hdr_len;
2200         u16 wifi_seq;
2201
2202         txq = &trans_pcie->txq[txq_id];
2203         q = &txq->q;
2204
2205         if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
2206                       "TX on unused queue %d\n", txq_id))
2207                 return -EINVAL;
2208
2209         if (unlikely(trans_pcie->sw_csum_tx &&
2210                      skb->ip_summed == CHECKSUM_PARTIAL)) {
2211                 int offs = skb_checksum_start_offset(skb);
2212                 int csum_offs = offs + skb->csum_offset;
2213                 __wsum csum;
2214
2215                 if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16)))
2216                         return -1;
2217
2218                 csum = skb_checksum(skb, offs, skb->len - offs, 0);
2219                 *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum);
2220
2221                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2222         }
2223
2224         if (skb_is_nonlinear(skb) &&
2225             skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS &&
2226             __skb_linearize(skb))
2227                 return -ENOMEM;
2228
2229         /* mac80211 always puts the full header into the SKB's head,
2230          * so there's no need to check if it's readable there
2231          */
2232         hdr = (struct ieee80211_hdr *)skb->data;
2233         fc = hdr->frame_control;
2234         hdr_len = ieee80211_hdrlen(fc);
2235
2236         spin_lock(&txq->lock);
2237
2238         if (iwl_queue_space(q) < q->high_mark) {
2239                 iwl_stop_queue(trans, txq);
2240
2241                 /* don't put the packet on the ring, if there is no room */
2242                 if (unlikely(iwl_queue_space(q) < 3)) {
2243                         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2244
2245                         info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA + 1] =
2246                                 dev_cmd;
2247                         __skb_queue_tail(&txq->overflow_q, skb);
2248
2249                         spin_unlock(&txq->lock);
2250                         return 0;
2251                 }
2252         }
2253
2254         /* In AGG mode, the index in the ring must correspond to the WiFi
2255          * sequence number. This is a HW requirements to help the SCD to parse
2256          * the BA.
2257          * Check here that the packets are in the right place on the ring.
2258          */
2259         wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
2260         WARN_ONCE(txq->ampdu &&
2261                   (wifi_seq & 0xff) != q->write_ptr,
2262                   "Q: %d WiFi Seq %d tfdNum %d",
2263                   txq_id, wifi_seq, q->write_ptr);
2264
2265         /* Set up driver data for this TFD */
2266         txq->entries[q->write_ptr].skb = skb;
2267         txq->entries[q->write_ptr].cmd = dev_cmd;
2268
2269         dev_cmd->hdr.sequence =
2270                 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
2271                             INDEX_TO_SEQ(q->write_ptr)));
2272
2273         tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr);
2274         scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
2275                        offsetof(struct iwl_tx_cmd, scratch);
2276
2277         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
2278         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
2279
2280         /* Set up first empty entry in queue's array of Tx/cmd buffers */
2281         out_meta = &txq->entries[q->write_ptr].meta;
2282         out_meta->flags = 0;
2283
2284         /*
2285          * The second TB (tb1) points to the remainder of the TX command
2286          * and the 802.11 header - dword aligned size
2287          * (This calculation modifies the TX command, so do it before the
2288          * setup of the first TB)
2289          */
2290         len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
2291               hdr_len - IWL_HCMD_SCRATCHBUF_SIZE;
2292         tb1_len = ALIGN(len, 4);
2293
2294         /* Tell NIC about any 2-byte padding after MAC header */
2295         if (tb1_len != len)
2296                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
2297
2298         /* The first TB points to the scratchbuf data - min_copy bytes */
2299         memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr,
2300                IWL_HCMD_SCRATCHBUF_SIZE);
2301         iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
2302                                IWL_HCMD_SCRATCHBUF_SIZE, true);
2303
2304         /* there must be data left over for TB1 or this code must be changed */
2305         BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE);
2306
2307         /* map the data for TB1 */
2308         tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE;
2309         tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
2310         if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
2311                 goto out_err;
2312         iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
2313
2314         if (ieee80211_is_data_qos(fc) &&
2315             (*ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_A_MSDU_PRESENT)) {
2316                 if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len,
2317                                                      out_meta, dev_cmd,
2318                                                      tb1_len)))
2319                         goto out_err;
2320         } else if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len,
2321                                        out_meta, dev_cmd, tb1_len))) {
2322                 goto out_err;
2323         }
2324
2325         /* Set up entry for this TFD in Tx byte-count array */
2326         iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
2327
2328         wait_write_ptr = ieee80211_has_morefrags(fc);
2329
2330         /* start timer if queue currently empty */
2331         if (q->read_ptr == q->write_ptr) {
2332                 if (txq->wd_timeout) {
2333                         /*
2334                          * If the TXQ is active, then set the timer, if not,
2335                          * set the timer in remainder so that the timer will
2336                          * be armed with the right value when the station will
2337                          * wake up.
2338                          */
2339                         if (!txq->frozen)
2340                                 mod_timer(&txq->stuck_timer,
2341                                           jiffies + txq->wd_timeout);
2342                         else
2343                                 txq->frozen_expiry_remainder = txq->wd_timeout;
2344                 }
2345                 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", q->id);
2346                 iwl_trans_pcie_ref(trans);
2347         }
2348
2349         /* Tell device the write index *just past* this latest filled TFD */
2350         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
2351         if (!wait_write_ptr)
2352                 iwl_pcie_txq_inc_wr_ptr(trans, txq);
2353
2354         /*
2355          * At this point the frame is "transmitted" successfully
2356          * and we will get a TX status notification eventually.
2357          */
2358         spin_unlock(&txq->lock);
2359         return 0;
2360 out_err:
2361         spin_unlock(&txq->lock);
2362         return -1;
2363 }