drivers/net/wireless/iwlwifi/iwl-eeprom.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  22  * USA
  23  *
  24  * The full GNU General Public License is included in this distribution
  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30  *
  31  * BSD LICENSE
  32  *
  33  * Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
  34  * All rights reserved.
  35  *
  36  * Redistribution and use in source and binary forms, with or without
  37  * modification, are permitted provided that the following conditions
  38  * are met:
  39  *
  40  *  * Redistributions of source code must retain the above copyright
  41  *    notice, this list of conditions and the following disclaimer.
  42  *  * Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
  46  *  * Neither the name Intel Corporation nor the names of its
  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *****************************************************************************/
  62
  63
  64 #include <linux/kernel.h>
  65 #include <linux/module.h>
  66 #include <linux/slab.h>
  67 #include <linux/init.h>
  68
  69 #include <net/mac80211.h>
  70
  71 #include "iwl-commands.h"
  72 #include "iwl-dev.h"
  73 #include "iwl-core.h"
  74 #include "iwl-debug.h"
  75 #include "iwl-eeprom.h"
  76 #include "iwl-io.h"
  77
  78 /************************** EEPROM BANDS ****************************
  79  *
  80  * The iwl_eeprom_band definitions below provide the mapping from the
  81  * EEPROM contents to the specific channel number supported for each
  82  * band.
  83  *
  84  * For example, iwl_priv->eeprom.band_3_channels[4] from the band_3
  85  * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  86  * The specific geography and calibration information for that channel
  87  * is contained in the eeprom map itself.
  88  *
  89  * During init, we copy the eeprom information and channel map
  90  * information into priv->channel_info_24/52 and priv->channel_map_24/52
  91  *
  92  * channel_map_24/52 provides the index in the channel_info array for a
  93  * given channel.  We have to have two separate maps as there is channel
  94  * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  95  * band_2
  96  *
  97  * A value of 0xff stored in the channel_map indicates that the channel
  98  * is not supported by the hardware at all.
  99  *
 100  * A value of 0xfe in the channel_map indicates that the channel is not
 101  * valid for Tx with the current hardware.  This means that
 102  * while the system can tune and receive on a given channel, it may not
 103  * be able to associate or transmit any frames on that
 104  * channel.  There is no corresponding channel information for that
 105  * entry.
 106  *
 107  *********************************************************************/
 108
 109 /* 2.4 GHz */
 110 const u8 iwl_eeprom_band_1[14] = {
 111         1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
 112 };
 113
 114 /* 5.2 GHz bands */
 115 static const u8 iwl_eeprom_band_2[] = { /* 4915-5080MHz */
 116         183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
 117 };
 118
 119 static const u8 iwl_eeprom_band_3[] = { /* 5170-5320MHz */
 120         34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
 121 };
 122
 123 static const u8 iwl_eeprom_band_4[] = { /* 5500-5700MHz */
 124         100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
 125 };
 126
 127 static const u8 iwl_eeprom_band_5[] = { /* 5725-5825MHz */
 128         145, 149, 153, 157, 161, 165
 129 };
 130
 131 static const u8 iwl_eeprom_band_6[] = {       /* 2.4 ht40 channel */
 132         1, 2, 3, 4, 5, 6, 7
 133 };
 134
 135 static const u8 iwl_eeprom_band_7[] = {       /* 5.2 ht40 channel */
 136         36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
 137 };
 138
 139 /******************************************************************************
 140  *
 141  * EEPROM related functions
 142  *
 143 ******************************************************************************/
 144
 145 static int iwl_eeprom_verify_signature(struct iwl_priv *priv)
 146 {
 147         u32 gp = iwl_read32(priv, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
 148         int ret = 0;
 149
 150         IWL_DEBUG_INFO(priv, "EEPROM signature=0x%08x\n", gp);
 151         switch (gp) {
 152         case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP:
 153                 if (priv->nvm_device_type != NVM_DEVICE_TYPE_OTP) {
 154                         IWL_ERR(priv, "EEPROM with bad signature: 0x%08x\n",
 155                                 gp);
 156                         ret = -ENOENT;
 157                 }
 158                 break;
 159         case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
 160         case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
 161                 if (priv->nvm_device_type != NVM_DEVICE_TYPE_EEPROM) {
 162                         IWL_ERR(priv, "OTP with bad signature: 0x%08x\n", gp);
 163                         ret = -ENOENT;
 164                 }
 165                 break;
 166         case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP:
 167         default:
 168                 IWL_ERR(priv, "bad EEPROM/OTP signature, type=%s, "
 169                         "EEPROM_GP=0x%08x\n",
 170                         (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
 171                         ? "OTP" : "EEPROM", gp);
 172                 ret = -ENOENT;
 173                 break;
 174         }
 175         return ret;
 176 }
 177
 178 static void iwl_set_otp_access(struct iwl_priv *priv, enum iwl_access_mode mode)
 179 {
 180         u32 otpgp;
 181
 182         otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
 183         if (mode == IWL_OTP_ACCESS_ABSOLUTE)
 184                 iwl_clear_bit(priv, CSR_OTP_GP_REG,
 185                                 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
 186         else
 187                 iwl_set_bit(priv, CSR_OTP_GP_REG,
 188                                 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
 189 }
 190
 191 static int iwlcore_get_nvm_type(struct iwl_priv *priv)
 192 {
 193         u32 otpgp;
 194         int nvm_type;
 195
 196         /* OTP only valid for CP/PP and after */
 197         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 198         case CSR_HW_REV_TYPE_NONE:
 199                 IWL_ERR(priv, "Unknown hardware type\n");
 200                 return -ENOENT;
 201         case CSR_HW_REV_TYPE_3945:
 202         case CSR_HW_REV_TYPE_4965:
 203         case CSR_HW_REV_TYPE_5300:
 204         case CSR_HW_REV_TYPE_5350:
 205         case CSR_HW_REV_TYPE_5100:
 206         case CSR_HW_REV_TYPE_5150:
 207                 nvm_type = NVM_DEVICE_TYPE_EEPROM;
 208                 break;
 209         default:
 210                 otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
 211                 if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
 212                         nvm_type = NVM_DEVICE_TYPE_OTP;
 213                 else
 214                         nvm_type = NVM_DEVICE_TYPE_EEPROM;
 215                 break;
 216         }
 217         return  nvm_type;
 218 }
 219
 220 const u8 *iwlcore_eeprom_query_addr(const struct iwl_priv *priv, size_t offset)
 221 {
 222         BUG_ON(offset >= priv->cfg->base_params->eeprom_size);
 223         return &priv->eeprom[offset];
 224 }
 225 EXPORT_SYMBOL(iwlcore_eeprom_query_addr);
 226
 227 static int iwl_init_otp_access(struct iwl_priv *priv)
 228 {
 229         int ret;
 230
 231         /* Enable 40MHz radio clock */
 232         _iwl_write32(priv, CSR_GP_CNTRL,
 233                      _iwl_read32(priv, CSR_GP_CNTRL) |
 234                      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 235
 236         /* wait for clock to be ready */
 237         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
 238                                   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 239                                   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 240                                   25000);
 241         if (ret < 0)
 242                 IWL_ERR(priv, "Time out access OTP\n");
 243         else {
 244                 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
 245                                   APMG_PS_CTRL_VAL_RESET_REQ);
 246                 udelay(5);
 247                 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
 248                                     APMG_PS_CTRL_VAL_RESET_REQ);
 249
 250                 /*
 251                  * CSR auto clock gate disable bit -
 252                  * this is only applicable for HW with OTP shadow RAM
 253                  */
 254                 if (priv->cfg->base_params->shadow_ram_support)
 255                         iwl_set_bit(priv, CSR_DBG_LINK_PWR_MGMT_REG,
 256                                 CSR_RESET_LINK_PWR_MGMT_DISABLED);
 257         }
 258         return ret;
 259 }
 260
 261 static int iwl_read_otp_word(struct iwl_priv *priv, u16 addr, __le16 *eeprom_data)
 262 {
 263         int ret = 0;
 264         u32 r;
 265         u32 otpgp;
 266
 267         _iwl_write32(priv, CSR_EEPROM_REG,
 268                      CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
 269         ret = iwl_poll_bit(priv, CSR_EEPROM_REG,
 270                                   CSR_EEPROM_REG_READ_VALID_MSK,
 271                                   CSR_EEPROM_REG_READ_VALID_MSK,
 272                                   IWL_EEPROM_ACCESS_TIMEOUT);
 273         if (ret < 0) {
 274                 IWL_ERR(priv, "Time out reading OTP[%d]\n", addr);
 275                 return ret;
 276         }
 277         r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
 278         /* check for ECC errors: */
 279         otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
 280         if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
 281                 /* stop in this case */
 282                 /* set the uncorrectable OTP ECC bit for acknowledgement */
 283                 iwl_set_bit(priv, CSR_OTP_GP_REG,
 284                         CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
 285                 IWL_ERR(priv, "Uncorrectable OTP ECC error, abort OTP read\n");
 286                 return -EINVAL;
 287         }
 288         if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
 289                 /* continue in this case */
 290                 /* set the correctable OTP ECC bit for acknowledgement */
 291                 iwl_set_bit(priv, CSR_OTP_GP_REG,
 292                                 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
 293                 IWL_ERR(priv, "Correctable OTP ECC error, continue read\n");
 294         }
 295         *eeprom_data = cpu_to_le16(r >> 16);
 296         return 0;
 297 }
 298
 299 /*
 300  * iwl_is_otp_empty: check for empty OTP
 301  */
 302 static bool iwl_is_otp_empty(struct iwl_priv *priv)
 303 {
 304         u16 next_link_addr = 0;
 305         __le16 link_value;
 306         bool is_empty = false;
 307
 308         /* locate the beginning of OTP link list */
 309         if (!iwl_read_otp_word(priv, next_link_addr, &link_value)) {
 310                 if (!link_value) {
 311                         IWL_ERR(priv, "OTP is empty\n");
 312                         is_empty = true;
 313                 }
 314         } else {
 315                 IWL_ERR(priv, "Unable to read first block of OTP list.\n");
 316                 is_empty = true;
 317         }
 318
 319         return is_empty;
 320 }
 321
 322
 323 /*
 324  * iwl_find_otp_image: find EEPROM image in OTP
 325  *   finding the OTP block that contains the EEPROM image.
 326  *   the last valid block on the link list (the block _before_ the last block)
 327  *   is the block we should read and used to configure the device.
 328  *   If all the available OTP blocks are full, the last block will be the block
 329  *   we should read and used to configure the device.
 330  *   only perform this operation if shadow RAM is disabled
 331  */
 332 static int iwl_find_otp_image(struct iwl_priv *priv,
 333                                         u16 *validblockaddr)
 334 {
 335         u16 next_link_addr = 0, valid_addr;
 336         __le16 link_value = 0;
 337         int usedblocks = 0;
 338
 339         /* set addressing mode to absolute to traverse the link list */
 340         iwl_set_otp_access(priv, IWL_OTP_ACCESS_ABSOLUTE);
 341
 342         /* checking for empty OTP or error */
 343         if (iwl_is_otp_empty(priv))
 344                 return -EINVAL;
 345
 346         /*
 347          * start traverse link list
 348          * until reach the max number of OTP blocks
 349          * different devices have different number of OTP blocks
 350          */
 351         do {
 352                 /* save current valid block address
 353                  * check for more block on the link list
 354                  */
 355                 valid_addr = next_link_addr;
 356                 next_link_addr = le16_to_cpu(link_value) * sizeof(u16);
 357                 IWL_DEBUG_INFO(priv, "OTP blocks %d addr 0x%x\n",
 358                                usedblocks, next_link_addr);
 359                 if (iwl_read_otp_word(priv, next_link_addr, &link_value))
 360                         return -EINVAL;
 361                 if (!link_value) {
 362                         /*
 363                          * reach the end of link list, return success and
 364                          * set address point to the starting address
 365                          * of the image
 366                          */
 367                         *validblockaddr = valid_addr;
 368                         /* skip first 2 bytes (link list pointer) */
 369                         *validblockaddr += 2;
 370                         return 0;
 371                 }
 372                 /* more in the link list, continue */
 373                 usedblocks++;
 374         } while (usedblocks <= priv->cfg->base_params->max_ll_items);
 375
 376         /* OTP has no valid blocks */
 377         IWL_DEBUG_INFO(priv, "OTP has no valid blocks\n");
 378         return -EINVAL;
 379 }
 380
 381 const u8 *iwl_eeprom_query_addr(const struct iwl_priv *priv, size_t offset)
 382 {
 383         return priv->cfg->ops->lib->eeprom_ops.query_addr(priv, offset);
 384 }
 385 EXPORT_SYMBOL(iwl_eeprom_query_addr);
 386
 387 u16 iwl_eeprom_query16(const struct iwl_priv *priv, size_t offset)
 388 {
 389         if (!priv->eeprom)
 390                 return 0;
 391         return (u16)priv->eeprom[offset] | ((u16)priv->eeprom[offset + 1] << 8);
 392 }
 393 EXPORT_SYMBOL(iwl_eeprom_query16);
 394
 395 /**
 396  * iwl_eeprom_init - read EEPROM contents
 397  *
 398  * Load the EEPROM contents from adapter into priv->eeprom
 399  *
 400  * NOTE:  This routine uses the non-debug IO access functions.
 401  */
 402 int iwl_eeprom_init(struct iwl_priv *priv)
 403 {
 404         __le16 *e;
 405         u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
 406         int sz;
 407         int ret;
 408         u16 addr;
 409         u16 validblockaddr = 0;
 410         u16 cache_addr = 0;
 411
 412         priv->nvm_device_type = iwlcore_get_nvm_type(priv);
 413         if (priv->nvm_device_type == -ENOENT)
 414                 return -ENOENT;
 415         /* allocate eeprom */
 416         sz = priv->cfg->base_params->eeprom_size;
 417         IWL_DEBUG_INFO(priv, "NVM size = %d\n", sz);
 418         priv->eeprom = kzalloc(sz, GFP_KERNEL);
 419         if (!priv->eeprom) {
 420                 ret = -ENOMEM;
 421                 goto alloc_err;
 422         }
 423         e = (__le16 *)priv->eeprom;
 424
 425         priv->cfg->ops->lib->apm_ops.init(priv);
 426
 427         ret = iwl_eeprom_verify_signature(priv);
 428         if (ret < 0) {
 429                 IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
 430                 ret = -ENOENT;
 431                 goto err;
 432         }
 433
 434         /* Make sure driver (instead of uCode) is allowed to read EEPROM */
 435         ret = priv->cfg->ops->lib->eeprom_ops.acquire_semaphore(priv);
 436         if (ret < 0) {
 437                 IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n");
 438                 ret = -ENOENT;
 439                 goto err;
 440         }
 441
 442         if (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP) {
 443
 444                 ret = iwl_init_otp_access(priv);
 445                 if (ret) {
 446                         IWL_ERR(priv, "Failed to initialize OTP access.\n");
 447                         ret = -ENOENT;
 448                         goto done;
 449                 }
 450                 _iwl_write32(priv, CSR_EEPROM_GP,
 451                              iwl_read32(priv, CSR_EEPROM_GP) &
 452                              ~CSR_EEPROM_GP_IF_OWNER_MSK);
 453
 454                 iwl_set_bit(priv, CSR_OTP_GP_REG,
 455                              CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
 456                              CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
 457                 /* traversing the linked list if no shadow ram supported */
 458                 if (!priv->cfg->base_params->shadow_ram_support) {
 459                         if (iwl_find_otp_image(priv, &validblockaddr)) {
 460                                 ret = -ENOENT;
 461                                 goto done;
 462                         }
 463                 }
 464                 for (addr = validblockaddr; addr < validblockaddr + sz;
 465                      addr += sizeof(u16)) {
 466                         __le16 eeprom_data;
 467
 468                         ret = iwl_read_otp_word(priv, addr, &eeprom_data);
 469                         if (ret)
 470                                 goto done;
 471                         e[cache_addr / 2] = eeprom_data;
 472                         cache_addr += sizeof(u16);
 473                 }
 474         } else {
 475                 /* eeprom is an array of 16bit values */
 476                 for (addr = 0; addr < sz; addr += sizeof(u16)) {
 477                         u32 r;
 478
 479                         _iwl_write32(priv, CSR_EEPROM_REG,
 480                                      CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
 481
 482                         ret = iwl_poll_bit(priv, CSR_EEPROM_REG,
 483                                                   CSR_EEPROM_REG_READ_VALID_MSK,
 484                                                   CSR_EEPROM_REG_READ_VALID_MSK,
 485                                                   IWL_EEPROM_ACCESS_TIMEOUT);
 486                         if (ret < 0) {
 487                                 IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
 488                                 goto done;
 489                         }
 490                         r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
 491                         e[addr / 2] = cpu_to_le16(r >> 16);
 492                 }
 493         }
 494
 495         IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
 496                        (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
 497                        ? "OTP" : "EEPROM",
 498                        iwl_eeprom_query16(priv, EEPROM_VERSION));
 499
 500         ret = 0;
 501 done:
 502         priv->cfg->ops->lib->eeprom_ops.release_semaphore(priv);
 503
 504 err:
 505         if (ret)
 506                 iwl_eeprom_free(priv);
 507         /* Reset chip to save power until we load uCode during "up". */
 508         iwl_apm_stop(priv);
 509 alloc_err:
 510         return ret;
 511 }
 512 EXPORT_SYMBOL(iwl_eeprom_init);
 513
 514 void iwl_eeprom_free(struct iwl_priv *priv)
 515 {
 516         kfree(priv->eeprom);
 517         priv->eeprom = NULL;
 518 }
 519 EXPORT_SYMBOL(iwl_eeprom_free);
 520
 521 static void iwl_init_band_reference(const struct iwl_priv *priv,
 522                         int eep_band, int *eeprom_ch_count,
 523                         const struct iwl_eeprom_channel **eeprom_ch_info,
 524                         const u8 **eeprom_ch_index)
 525 {
 526         u32 offset = priv->cfg->ops->lib->
 527                         eeprom_ops.regulatory_bands[eep_band - 1];
 528         switch (eep_band) {
 529         case 1:         /* 2.4GHz band */
 530                 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_1);
 531                 *eeprom_ch_info = (struct iwl_eeprom_channel *)
 532                                 iwl_eeprom_query_addr(priv, offset);
 533                 *eeprom_ch_index = iwl_eeprom_band_1;
 534                 break;
 535         case 2:         /* 4.9GHz band */
 536                 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_2);
 537                 *eeprom_ch_info = (struct iwl_eeprom_channel *)
 538                                 iwl_eeprom_query_addr(priv, offset);
 539                 *eeprom_ch_index = iwl_eeprom_band_2;
 540                 break;
 541         case 3:         /* 5.2GHz band */
 542                 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_3);
 543                 *eeprom_ch_info = (struct iwl_eeprom_channel *)
 544                                 iwl_eeprom_query_addr(priv, offset);
 545                 *eeprom_ch_index = iwl_eeprom_band_3;
 546                 break;
 547         case 4:         /* 5.5GHz band */
 548                 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_4);
 549                 *eeprom_ch_info = (struct iwl_eeprom_channel *)
 550                                 iwl_eeprom_query_addr(priv, offset);
 551                 *eeprom_ch_index = iwl_eeprom_band_4;
 552                 break;
 553         case 5:         /* 5.7GHz band */
 554                 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_5);
 555                 *eeprom_ch_info = (struct iwl_eeprom_channel *)
 556                                 iwl_eeprom_query_addr(priv, offset);
 557                 *eeprom_ch_index = iwl_eeprom_band_5;
 558                 break;
 559         case 6:         /* 2.4GHz ht40 channels */
 560                 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_6);
 561                 *eeprom_ch_info = (struct iwl_eeprom_channel *)
 562                                 iwl_eeprom_query_addr(priv, offset);
 563                 *eeprom_ch_index = iwl_eeprom_band_6;
 564                 break;
 565         case 7:         /* 5 GHz ht40 channels */
 566                 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_7);
 567                 *eeprom_ch_info = (struct iwl_eeprom_channel *)
 568                                 iwl_eeprom_query_addr(priv, offset);
 569                 *eeprom_ch_index = iwl_eeprom_band_7;
 570                 break;
 571         default:
 572                 BUG();
 573                 return;
 574         }
 575 }
 576
 577 #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
 578                             ? # x " " : "")
 579 /**
 580  * iwl_mod_ht40_chan_info - Copy ht40 channel info into driver's priv.
 581  *
 582  * Does not set up a command, or touch hardware.
 583  */
 584 static int iwl_mod_ht40_chan_info(struct iwl_priv *priv,
 585                               enum ieee80211_band band, u16 channel,
 586                               const struct iwl_eeprom_channel *eeprom_ch,
 587                               u8 clear_ht40_extension_channel)
 588 {
 589         struct iwl_channel_info *ch_info;
 590
 591         ch_info = (struct iwl_channel_info *)
 592                         iwl_get_channel_info(priv, band, channel);
 593
 594         if (!is_channel_valid(ch_info))
 595                 return -1;
 596
 597         IWL_DEBUG_INFO(priv, "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
 598                         " Ad-Hoc %ssupported\n",
 599                         ch_info->channel,
 600                         is_channel_a_band(ch_info) ?
 601                         "5.2" : "2.4",
 602                         CHECK_AND_PRINT(IBSS),
 603                         CHECK_AND_PRINT(ACTIVE),
 604                         CHECK_AND_PRINT(RADAR),
 605                         CHECK_AND_PRINT(WIDE),
 606                         CHECK_AND_PRINT(DFS),
 607                         eeprom_ch->flags,
 608                         eeprom_ch->max_power_avg,
 609                         ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS)
 610                          && !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ?
 611                         "" : "not ");
 612
 613         ch_info->ht40_eeprom = *eeprom_ch;
 614         ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
 615         ch_info->ht40_flags = eeprom_ch->flags;
 616         if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
 617                 ch_info->ht40_extension_channel &= ~clear_ht40_extension_channel;
 618
 619         return 0;
 620 }
 621
 622 #define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
 623                             ? # x " " : "")
 624
 625 /**
 626  * iwl_init_channel_map - Set up driver's info for all possible channels
 627  */
 628 int iwl_init_channel_map(struct iwl_priv *priv)
 629 {
 630         int eeprom_ch_count = 0;
 631         const u8 *eeprom_ch_index = NULL;
 632         const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
 633         int band, ch;
 634         struct iwl_channel_info *ch_info;
 635
 636         if (priv->channel_count) {
 637                 IWL_DEBUG_INFO(priv, "Channel map already initialized.\n");
 638                 return 0;
 639         }
 640
 641         IWL_DEBUG_INFO(priv, "Initializing regulatory info from EEPROM\n");
 642
 643         priv->channel_count =
 644             ARRAY_SIZE(iwl_eeprom_band_1) +
 645             ARRAY_SIZE(iwl_eeprom_band_2) +
 646             ARRAY_SIZE(iwl_eeprom_band_3) +
 647             ARRAY_SIZE(iwl_eeprom_band_4) +
 648             ARRAY_SIZE(iwl_eeprom_band_5);
 649
 650         IWL_DEBUG_INFO(priv, "Parsing data for %d channels.\n", priv->channel_count);
 651
 652         priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) *
 653                                      priv->channel_count, GFP_KERNEL);
 654         if (!priv->channel_info) {
 655                 IWL_ERR(priv, "Could not allocate channel_info\n");
 656                 priv->channel_count = 0;
 657                 return -ENOMEM;
 658         }
 659
 660         ch_info = priv->channel_info;
 661
 662         /* Loop through the 5 EEPROM bands adding them in order to the
 663          * channel map we maintain (that contains additional information than
 664          * what just in the EEPROM) */
 665         for (band = 1; band <= 5; band++) {
 666
 667                 iwl_init_band_reference(priv, band, &eeprom_ch_count,
 668                                         &eeprom_ch_info, &eeprom_ch_index);
 669
 670                 /* Loop through each band adding each of the channels */
 671                 for (ch = 0; ch < eeprom_ch_count; ch++) {
 672                         ch_info->channel = eeprom_ch_index[ch];
 673                         ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
 674                             IEEE80211_BAND_5GHZ;
 675
 676                         /* permanently store EEPROM's channel regulatory flags
 677                          *   and max power in channel info database. */
 678                         ch_info->eeprom = eeprom_ch_info[ch];
 679
 680                         /* Copy the run-time flags so they are there even on
 681                          * invalid channels */
 682                         ch_info->flags = eeprom_ch_info[ch].flags;
 683                         /* First write that ht40 is not enabled, and then enable
 684                          * one by one */
 685                         ch_info->ht40_extension_channel =
 686                                         IEEE80211_CHAN_NO_HT40;
 687
 688                         if (!(is_channel_valid(ch_info))) {
 689                                 IWL_DEBUG_INFO(priv, "Ch. %d Flags %x [%sGHz] - "
 690                                                "No traffic\n",
 691                                                ch_info->channel,
 692                                                ch_info->flags,
 693                                                is_channel_a_band(ch_info) ?
 694                                                "5.2" : "2.4");
 695                                 ch_info++;
 696                                 continue;
 697                         }
 698
 699                         /* Initialize regulatory-based run-time data */
 700                         ch_info->max_power_avg = ch_info->curr_txpow =
 701                             eeprom_ch_info[ch].max_power_avg;
 702                         ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
 703                         ch_info->min_power = 0;
 704
 705                         IWL_DEBUG_INFO(priv, "Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x %ddBm):"
 706                                        " Ad-Hoc %ssupported\n",
 707                                        ch_info->channel,
 708                                        is_channel_a_band(ch_info) ?
 709                                        "5.2" : "2.4",
 710                                        CHECK_AND_PRINT_I(VALID),
 711                                        CHECK_AND_PRINT_I(IBSS),
 712                                        CHECK_AND_PRINT_I(ACTIVE),
 713                                        CHECK_AND_PRINT_I(RADAR),
 714                                        CHECK_AND_PRINT_I(WIDE),
 715                                        CHECK_AND_PRINT_I(DFS),
 716                                        eeprom_ch_info[ch].flags,
 717                                        eeprom_ch_info[ch].max_power_avg,
 718                                        ((eeprom_ch_info[ch].
 719                                          flags & EEPROM_CHANNEL_IBSS)
 720                                         && !(eeprom_ch_info[ch].
 721                                              flags & EEPROM_CHANNEL_RADAR))
 722                                        ? "" : "not ");
 723
 724                         /* Set the tx_power_user_lmt to the highest power
 725                          * supported by any channel */
 726                         if (eeprom_ch_info[ch].max_power_avg >
 727                                                 priv->tx_power_user_lmt)
 728                                 priv->tx_power_user_lmt =
 729                                     eeprom_ch_info[ch].max_power_avg;
 730
 731                         ch_info++;
 732                 }
 733         }
 734
 735         /* Check if we do have HT40 channels */
 736         if (priv->cfg->ops->lib->eeprom_ops.regulatory_bands[5] ==
 737             EEPROM_REGULATORY_BAND_NO_HT40 &&
 738             priv->cfg->ops->lib->eeprom_ops.regulatory_bands[6] ==
 739             EEPROM_REGULATORY_BAND_NO_HT40)
 740                 return 0;
 741
 742         /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
 743         for (band = 6; band <= 7; band++) {
 744                 enum ieee80211_band ieeeband;
 745
 746                 iwl_init_band_reference(priv, band, &eeprom_ch_count,
 747                                         &eeprom_ch_info, &eeprom_ch_index);
 748
 749                 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
 750                 ieeeband =
 751                         (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 752
 753                 /* Loop through each band adding each of the channels */
 754                 for (ch = 0; ch < eeprom_ch_count; ch++) {
 755                         /* Set up driver's info for lower half */
 756                         iwl_mod_ht40_chan_info(priv, ieeeband,
 757                                                 eeprom_ch_index[ch],
 758                                                 &eeprom_ch_info[ch],
 759                                                 IEEE80211_CHAN_NO_HT40PLUS);
 760
 761                         /* Set up driver's info for upper half */
 762                         iwl_mod_ht40_chan_info(priv, ieeeband,
 763                                                 eeprom_ch_index[ch] + 4,
 764                                                 &eeprom_ch_info[ch],
 765                                                 IEEE80211_CHAN_NO_HT40MINUS);
 766                 }
 767         }
 768
 769         /* for newer device (6000 series and up)
 770          * EEPROM contain enhanced tx power information
 771          * driver need to process addition information
 772          * to determine the max channel tx power limits
 773          */
 774         if (priv->cfg->ops->lib->eeprom_ops.update_enhanced_txpower)
 775                 priv->cfg->ops->lib->eeprom_ops.update_enhanced_txpower(priv);
 776
 777         return 0;
 778 }
 779 EXPORT_SYMBOL(iwl_init_channel_map);
 780
 781 /*
 782  * iwl_free_channel_map - undo allocations in iwl_init_channel_map
 783  */
 784 void iwl_free_channel_map(struct iwl_priv *priv)
 785 {
 786         kfree(priv->channel_info);
 787         priv->channel_count = 0;
 788 }
 789 EXPORT_SYMBOL(iwl_free_channel_map);
 790
 791 /**
 792  * iwl_get_channel_info - Find driver's private channel info
 793  *
 794  * Based on band and channel number.
 795  */
 796 const struct iwl_channel_info *iwl_get_channel_info(const struct iwl_priv *priv,
 797                                         enum ieee80211_band band, u16 channel)
 798 {
 799         int i;
 800
 801         switch (band) {
 802         case IEEE80211_BAND_5GHZ:
 803                 for (i = 14; i < priv->channel_count; i++) {
 804                         if (priv->channel_info[i].channel == channel)
 805                                 return &priv->channel_info[i];
 806                 }
 807                 break;
 808         case IEEE80211_BAND_2GHZ:
 809                 if (channel >= 1 && channel <= 14)
 810                         return &priv->channel_info[channel - 1];
 811                 break;
 812         default:
 813                 BUG();
 814         }
 815
 816         return NULL;
 817 }
 818 EXPORT_SYMBOL(iwl_get_channel_info);