drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
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   4  * redistributing this file, you may do so under either license.
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   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of version 2 of the GNU General Public License as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
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  49  *    contributors may be used to endorse or promote products derived
  50  *    from this software without specific prior written permission.
  51  *
  52  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  53  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  54  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  55  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  56  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  62  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  63  *
  64  *****************************************************************************/
  65 #include <linux/pci.h>
  66 #include <linux/pci-aspm.h>
  67 #include <linux/interrupt.h>
  68 #include <linux/debugfs.h>
  69 #include <linux/sched.h>
  70 #include <linux/bitops.h>
  71 #include <linux/gfp.h>
  72 #include <linux/vmalloc.h>
  73
  74 #include "iwl-drv.h"
  75 #include "iwl-trans.h"
  76 #include "iwl-csr.h"
  77 #include "iwl-prph.h"
  78 #include "iwl-scd.h"
  79 #include "iwl-agn-hw.h"
  80 #include "iwl-fw-error-dump.h"
  81 #include "internal.h"
  82 #include "iwl-fh.h"
  83
  84 /* extended range in FW SRAM */
  85 #define IWL_FW_MEM_EXTENDED_START       0x40000
  86 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  87
  88 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
  89 {
  90         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  91
  92         if (!trans_pcie->fw_mon_page)
  93                 return;
  94
  95         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
  96                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
  97         __free_pages(trans_pcie->fw_mon_page,
  98                      get_order(trans_pcie->fw_mon_size));
  99         trans_pcie->fw_mon_page = NULL;
 100         trans_pcie->fw_mon_phys = 0;
 101         trans_pcie->fw_mon_size = 0;
 102 }
 103
 104 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
 105 {
 106         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 107         struct page *page = NULL;
 108         dma_addr_t phys;
 109         u32 size = 0;
 110         u8 power;
 111
 112         if (!max_power) {
 113                 /* default max_power is maximum */
 114                 max_power = 26;
 115         } else {
 116                 max_power += 11;
 117         }
 118
 119         if (WARN(max_power > 26,
 120                  "External buffer size for monitor is too big %d, check the FW TLV\n",
 121                  max_power))
 122                 return;
 123
 124         if (trans_pcie->fw_mon_page) {
 125                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 126                                            trans_pcie->fw_mon_size,
 127                                            DMA_FROM_DEVICE);
 128                 return;
 129         }
 130
 131         phys = 0;
 132         for (power = max_power; power >= 11; power--) {
 133                 int order;
 134
 135                 size = BIT(power);
 136                 order = get_order(size);
 137                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 138                                    order);
 139                 if (!page)
 140                         continue;
 141
 142                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 143                                     DMA_FROM_DEVICE);
 144                 if (dma_mapping_error(trans->dev, phys)) {
 145                         __free_pages(page, order);
 146                         page = NULL;
 147                         continue;
 148                 }
 149                 IWL_INFO(trans,
 150                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 151                          size, order);
 152                 break;
 153         }
 154
 155         if (WARN_ON_ONCE(!page))
 156                 return;
 157
 158         if (power != max_power)
 159                 IWL_ERR(trans,
 160                         "Sorry - debug buffer is only %luK while you requested %luK\n",
 161                         (unsigned long)BIT(power - 10),
 162                         (unsigned long)BIT(max_power - 10));
 163
 164         trans_pcie->fw_mon_page = page;
 165         trans_pcie->fw_mon_phys = phys;
 166         trans_pcie->fw_mon_size = size;
 167 }
 168
 169 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 170 {
 171         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 172                     ((reg & 0x0000ffff) | (2 << 28)));
 173         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 174 }
 175
 176 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 177 {
 178         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 179         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 180                     ((reg & 0x0000ffff) | (3 << 28)));
 181 }
 182
 183 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 184 {
 185         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 186                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 187                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 188                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 189         else
 190                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 191                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 192                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 193 }
 194
 195 /* PCI registers */
 196 #define PCI_CFG_RETRY_TIMEOUT   0x041
 197
 198 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 199 {
 200         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 201         u16 lctl;
 202         u16 cap;
 203
 204         /*
 205          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 206          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 207          * If so (likely), disable L0S, so device moves directly L0->L1;
 208          *    costs negligible amount of power savings.
 209          * If not (unlikely), enable L0S, so there is at least some
 210          *    power savings, even without L1.
 211          */
 212         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 213         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 214                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 215         else
 216                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 217         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 218
 219         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 220         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 221         dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
 222                  (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 223                  trans->ltr_enabled ? "En" : "Dis");
 224 }
 225
 226 /*
 227  * Start up NIC's basic functionality after it has been reset
 228  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 229  * NOTE:  This does not load uCode nor start the embedded processor
 230  */
 231 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 232 {
 233         int ret = 0;
 234         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 235
 236         /*
 237          * Use "set_bit" below rather than "write", to preserve any hardware
 238          * bits already set by default after reset.
 239          */
 240
 241         /* Disable L0S exit timer (platform NMI Work/Around) */
 242         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 243                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 244                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 245
 246         /*
 247          * Disable L0s without affecting L1;
 248          *  don't wait for ICH L0s (ICH bug W/A)
 249          */
 250         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 251                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 252
 253         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 254         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 255
 256         /*
 257          * Enable HAP INTA (interrupt from management bus) to
 258          * wake device's PCI Express link L1a -> L0s
 259          */
 260         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 261                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 262
 263         iwl_pcie_apm_config(trans);
 264
 265         /* Configure analog phase-lock-loop before activating to D0A */
 266         if (trans->cfg->base_params->pll_cfg_val)
 267                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 268                             trans->cfg->base_params->pll_cfg_val);
 269
 270         /*
 271          * Set "initialization complete" bit to move adapter from
 272          * D0U* --> D0A* (powered-up active) state.
 273          */
 274         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 275
 276         /*
 277          * Wait for clock stabilization; once stabilized, access to
 278          * device-internal resources is supported, e.g. iwl_write_prph()
 279          * and accesses to uCode SRAM.
 280          */
 281         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 282                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 283                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 284         if (ret < 0) {
 285                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 286                 goto out;
 287         }
 288
 289         if (trans->cfg->host_interrupt_operation_mode) {
 290                 /*
 291                  * This is a bit of an abuse - This is needed for 7260 / 3160
 292                  * only check host_interrupt_operation_mode even if this is
 293                  * not related to host_interrupt_operation_mode.
 294                  *
 295                  * Enable the oscillator to count wake up time for L1 exit. This
 296                  * consumes slightly more power (100uA) - but allows to be sure
 297                  * that we wake up from L1 on time.
 298                  *
 299                  * This looks weird: read twice the same register, discard the
 300                  * value, set a bit, and yet again, read that same register
 301                  * just to discard the value. But that's the way the hardware
 302                  * seems to like it.
 303                  */
 304                 iwl_read_prph(trans, OSC_CLK);
 305                 iwl_read_prph(trans, OSC_CLK);
 306                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 307                 iwl_read_prph(trans, OSC_CLK);
 308                 iwl_read_prph(trans, OSC_CLK);
 309         }
 310
 311         /*
 312          * Enable DMA clock and wait for it to stabilize.
 313          *
 314          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 315          * bits do not disable clocks.  This preserves any hardware
 316          * bits already set by default in "CLK_CTRL_REG" after reset.
 317          */
 318         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
 319                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 320                                APMG_CLK_VAL_DMA_CLK_RQT);
 321                 udelay(20);
 322
 323                 /* Disable L1-Active */
 324                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 325                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 326
 327                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 328                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 329                                APMG_RTC_INT_STT_RFKILL);
 330         }
 331
 332         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 333
 334 out:
 335         return ret;
 336 }
 337
 338 /*
 339  * Enable LP XTAL to avoid HW bug where device may consume much power if
 340  * FW is not loaded after device reset. LP XTAL is disabled by default
 341  * after device HW reset. Do it only if XTAL is fed by internal source.
 342  * Configure device's "persistence" mode to avoid resetting XTAL again when
 343  * SHRD_HW_RST occurs in S3.
 344  */
 345 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 346 {
 347         int ret;
 348         u32 apmg_gp1_reg;
 349         u32 apmg_xtal_cfg_reg;
 350         u32 dl_cfg_reg;
 351
 352         /* Force XTAL ON */
 353         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 354                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 355
 356         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 357         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 358
 359         udelay(10);
 360
 361         /*
 362          * Set "initialization complete" bit to move adapter from
 363          * D0U* --> D0A* (powered-up active) state.
 364          */
 365         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 366
 367         /*
 368          * Wait for clock stabilization; once stabilized, access to
 369          * device-internal resources is possible.
 370          */
 371         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 372                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 373                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 374                            25000);
 375         if (WARN_ON(ret < 0)) {
 376                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 377                 /* Release XTAL ON request */
 378                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 379                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 380                 return;
 381         }
 382
 383         /*
 384          * Clear "disable persistence" to avoid LP XTAL resetting when
 385          * SHRD_HW_RST is applied in S3.
 386          */
 387         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 388                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 389
 390         /*
 391          * Force APMG XTAL to be active to prevent its disabling by HW
 392          * caused by APMG idle state.
 393          */
 394         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 395                                                     SHR_APMG_XTAL_CFG_REG);
 396         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 397                                  apmg_xtal_cfg_reg |
 398                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 399
 400         /*
 401          * Reset entire device again - do controller reset (results in
 402          * SHRD_HW_RST). Turn MAC off before proceeding.
 403          */
 404         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 405
 406         udelay(10);
 407
 408         /* Enable LP XTAL by indirect access through CSR */
 409         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 410         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 411                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 412                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 413
 414         /* Clear delay line clock power up */
 415         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 416         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 417                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 418
 419         /*
 420          * Enable persistence mode to avoid LP XTAL resetting when
 421          * SHRD_HW_RST is applied in S3.
 422          */
 423         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 424                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 425
 426         /*
 427          * Clear "initialization complete" bit to move adapter from
 428          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 429          */
 430         iwl_clear_bit(trans, CSR_GP_CNTRL,
 431                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 432
 433         /* Activates XTAL resources monitor */
 434         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 435                                  CSR_MONITOR_XTAL_RESOURCES);
 436
 437         /* Release XTAL ON request */
 438         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 439                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 440         udelay(10);
 441
 442         /* Release APMG XTAL */
 443         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 444                                  apmg_xtal_cfg_reg &
 445                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 446 }
 447
 448 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 449 {
 450         int ret = 0;
 451
 452         /* stop device's busmaster DMA activity */
 453         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 454
 455         ret = iwl_poll_bit(trans, CSR_RESET,
 456                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 457                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 458         if (ret < 0)
 459                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 460
 461         IWL_DEBUG_INFO(trans, "stop master\n");
 462
 463         return ret;
 464 }
 465
 466 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 467 {
 468         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 469
 470         if (op_mode_leave) {
 471                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 472                         iwl_pcie_apm_init(trans);
 473
 474                 /* inform ME that we are leaving */
 475                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 476                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 477                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 478                 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 479                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 480                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 481                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 482                 mdelay(5);
 483         }
 484
 485         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 486
 487         /* Stop device's DMA activity */
 488         iwl_pcie_apm_stop_master(trans);
 489
 490         if (trans->cfg->lp_xtal_workaround) {
 491                 iwl_pcie_apm_lp_xtal_enable(trans);
 492                 return;
 493         }
 494
 495         /* Reset the entire device */
 496         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 497
 498         udelay(10);
 499
 500         /*
 501          * Clear "initialization complete" bit to move adapter from
 502          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 503          */
 504         iwl_clear_bit(trans, CSR_GP_CNTRL,
 505                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 506 }
 507
 508 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 509 {
 510         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 511
 512         /* nic_init */
 513         spin_lock(&trans_pcie->irq_lock);
 514         iwl_pcie_apm_init(trans);
 515
 516         spin_unlock(&trans_pcie->irq_lock);
 517
 518         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 519                 iwl_pcie_set_pwr(trans, false);
 520
 521         iwl_op_mode_nic_config(trans->op_mode);
 522
 523         /* Allocate the RX queue, or reset if it is already allocated */
 524         iwl_pcie_rx_init(trans);
 525
 526         /* Allocate or reset and init all Tx and Command queues */
 527         if (iwl_pcie_tx_init(trans))
 528                 return -ENOMEM;
 529
 530         if (trans->cfg->base_params->shadow_reg_enable) {
 531                 /* enable shadow regs in HW */
 532                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 533                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 534         }
 535
 536         return 0;
 537 }
 538
 539 #define HW_READY_TIMEOUT (50)
 540
 541 /* Note: returns poll_bit return value, which is >= 0 if success */
 542 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 543 {
 544         int ret;
 545
 546         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 547                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 548
 549         /* See if we got it */
 550         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 551                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 552                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 553                            HW_READY_TIMEOUT);
 554
 555         if (ret >= 0)
 556                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 557
 558         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 559         return ret;
 560 }
 561
 562 /* Note: returns standard 0/-ERROR code */
 563 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 564 {
 565         int ret;
 566         int t = 0;
 567         int iter;
 568
 569         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 570
 571         ret = iwl_pcie_set_hw_ready(trans);
 572         /* If the card is ready, exit 0 */
 573         if (ret >= 0)
 574                 return 0;
 575
 576         for (iter = 0; iter < 10; iter++) {
 577                 /* If HW is not ready, prepare the conditions to check again */
 578                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 579                             CSR_HW_IF_CONFIG_REG_PREPARE);
 580
 581                 do {
 582                         ret = iwl_pcie_set_hw_ready(trans);
 583                         if (ret >= 0)
 584                                 return 0;
 585
 586                         usleep_range(200, 1000);
 587                         t += 200;
 588                 } while (t < 150000);
 589                 msleep(25);
 590         }
 591
 592         IWL_ERR(trans, "Couldn't prepare the card\n");
 593
 594         return ret;
 595 }
 596
 597 /*
 598  * ucode
 599  */
 600 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 601                                    dma_addr_t phy_addr, u32 byte_cnt)
 602 {
 603         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 604         int ret;
 605
 606         trans_pcie->ucode_write_complete = false;
 607
 608         iwl_write_direct32(trans,
 609                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 610                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 611
 612         iwl_write_direct32(trans,
 613                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 614                            dst_addr);
 615
 616         iwl_write_direct32(trans,
 617                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 618                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 619
 620         iwl_write_direct32(trans,
 621                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 622                            (iwl_get_dma_hi_addr(phy_addr)
 623                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 624
 625         iwl_write_direct32(trans,
 626                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 627                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 628                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 629                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 630
 631         iwl_write_direct32(trans,
 632                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 633                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 634                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 635                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 636
 637         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 638                                  trans_pcie->ucode_write_complete, 5 * HZ);
 639         if (!ret) {
 640                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 641                 return -ETIMEDOUT;
 642         }
 643
 644         return 0;
 645 }
 646
 647 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 648                             const struct fw_desc *section)
 649 {
 650         u8 *v_addr;
 651         dma_addr_t p_addr;
 652         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 653         int ret = 0;
 654
 655         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 656                      section_num);
 657
 658         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 659                                     GFP_KERNEL | __GFP_NOWARN);
 660         if (!v_addr) {
 661                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 662                 chunk_sz = PAGE_SIZE;
 663                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 664                                             &p_addr, GFP_KERNEL);
 665                 if (!v_addr)
 666                         return -ENOMEM;
 667         }
 668
 669         for (offset = 0; offset < section->len; offset += chunk_sz) {
 670                 u32 copy_size, dst_addr;
 671                 bool extended_addr = false;
 672
 673                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 674                 dst_addr = section->offset + offset;
 675
 676                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 677                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 678                         extended_addr = true;
 679
 680                 if (extended_addr)
 681                         iwl_set_bits_prph(trans, LMPM_CHICK,
 682                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 683
 684                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 685                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 686                                                    copy_size);
 687
 688                 if (extended_addr)
 689                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 690                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 691
 692                 if (ret) {
 693                         IWL_ERR(trans,
 694                                 "Could not load the [%d] uCode section\n",
 695                                 section_num);
 696                         break;
 697                 }
 698         }
 699
 700         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 701         return ret;
 702 }
 703
 704 /*
 705  * Driver Takes the ownership on secure machine before FW load
 706  * and prevent race with the BT load.
 707  * W/A for ROM bug. (should be remove in the next Si step)
 708  */
 709 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
 710 {
 711         u32 val, loop = 1000;
 712
 713         /*
 714          * Check the RSA semaphore is accessible.
 715          * If the HW isn't locked and the rsa semaphore isn't accessible,
 716          * we are in trouble.
 717          */
 718         val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
 719         if (val & (BIT(1) | BIT(17))) {
 720                 IWL_INFO(trans,
 721                          "can't access the RSA semaphore it is write protected\n");
 722                 return 0;
 723         }
 724
 725         /* take ownership on the AUX IF */
 726         iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
 727         iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
 728
 729         do {
 730                 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
 731                 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
 732                 if (val == 0x1) {
 733                         iwl_write_prph(trans, RSA_ENABLE, 0);
 734                         return 0;
 735                 }
 736
 737                 udelay(10);
 738                 loop--;
 739         } while (loop > 0);
 740
 741         IWL_ERR(trans, "Failed to take ownership on secure machine\n");
 742         return -EIO;
 743 }
 744
 745 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 746                                            const struct fw_img *image,
 747                                            int cpu,
 748                                            int *first_ucode_section)
 749 {
 750         int shift_param;
 751         int i, ret = 0, sec_num = 0x1;
 752         u32 val, last_read_idx = 0;
 753
 754         if (cpu == 1) {
 755                 shift_param = 0;
 756                 *first_ucode_section = 0;
 757         } else {
 758                 shift_param = 16;
 759                 (*first_ucode_section)++;
 760         }
 761
 762         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 763                 last_read_idx = i;
 764
 765                 if (!image->sec[i].data ||
 766                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 767                         IWL_DEBUG_FW(trans,
 768                                      "Break since Data not valid or Empty section, sec = %d\n",
 769                                      i);
 770                         break;
 771                 }
 772
 773                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 774                 if (ret)
 775                         return ret;
 776
 777                 /* Notify the ucode of the loaded section number and status */
 778                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 779                 val = val | (sec_num << shift_param);
 780                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 781                 sec_num = (sec_num << 1) | 0x1;
 782         }
 783
 784         *first_ucode_section = last_read_idx;
 785
 786         if (cpu == 1)
 787                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
 788         else
 789                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
 790
 791         return 0;
 792 }
 793
 794 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 795                                       const struct fw_img *image,
 796                                       int cpu,
 797                                       int *first_ucode_section)
 798 {
 799         int shift_param;
 800         int i, ret = 0;
 801         u32 last_read_idx = 0;
 802
 803         if (cpu == 1) {
 804                 shift_param = 0;
 805                 *first_ucode_section = 0;
 806         } else {
 807                 shift_param = 16;
 808                 (*first_ucode_section)++;
 809         }
 810
 811         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 812                 last_read_idx = i;
 813
 814                 if (!image->sec[i].data ||
 815                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 816                         IWL_DEBUG_FW(trans,
 817                                      "Break since Data not valid or Empty section, sec = %d\n",
 818                                      i);
 819                         break;
 820                 }
 821
 822                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 823                 if (ret)
 824                         return ret;
 825         }
 826
 827         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 828                 iwl_set_bits_prph(trans,
 829                                   CSR_UCODE_LOAD_STATUS_ADDR,
 830                                   (LMPM_CPU_UCODE_LOADING_COMPLETED |
 831                                    LMPM_CPU_HDRS_LOADING_COMPLETED |
 832                                    LMPM_CPU_UCODE_LOADING_STARTED) <<
 833                                         shift_param);
 834
 835         *first_ucode_section = last_read_idx;
 836
 837         return 0;
 838 }
 839
 840 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
 841 {
 842         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 843         const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
 844         int i;
 845
 846         if (dest->version)
 847                 IWL_ERR(trans,
 848                         "DBG DEST version is %d - expect issues\n",
 849                         dest->version);
 850
 851         IWL_INFO(trans, "Applying debug destination %s\n",
 852                  get_fw_dbg_mode_string(dest->monitor_mode));
 853
 854         if (dest->monitor_mode == EXTERNAL_MODE)
 855                 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
 856         else
 857                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 858
 859         for (i = 0; i < trans->dbg_dest_reg_num; i++) {
 860                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 861                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 862
 863                 switch (dest->reg_ops[i].op) {
 864                 case CSR_ASSIGN:
 865                         iwl_write32(trans, addr, val);
 866                         break;
 867                 case CSR_SETBIT:
 868                         iwl_set_bit(trans, addr, BIT(val));
 869                         break;
 870                 case CSR_CLEARBIT:
 871                         iwl_clear_bit(trans, addr, BIT(val));
 872                         break;
 873                 case PRPH_ASSIGN:
 874                         iwl_write_prph(trans, addr, val);
 875                         break;
 876                 case PRPH_SETBIT:
 877                         iwl_set_bits_prph(trans, addr, BIT(val));
 878                         break;
 879                 case PRPH_CLEARBIT:
 880                         iwl_clear_bits_prph(trans, addr, BIT(val));
 881                         break;
 882                 default:
 883                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 884                                 dest->reg_ops[i].op);
 885                         break;
 886                 }
 887         }
 888
 889         if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
 890                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 891                                trans_pcie->fw_mon_phys >> dest->base_shift);
 892                 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 893                                (trans_pcie->fw_mon_phys +
 894                                 trans_pcie->fw_mon_size) >> dest->end_shift);
 895         }
 896 }
 897
 898 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 899                                 const struct fw_img *image)
 900 {
 901         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 902         int ret = 0;
 903         int first_ucode_section;
 904
 905         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 906                      image->is_dual_cpus ? "Dual" : "Single");
 907
 908         /* load to FW the binary non secured sections of CPU1 */
 909         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
 910         if (ret)
 911                 return ret;
 912
 913         if (image->is_dual_cpus) {
 914                 /* set CPU2 header address */
 915                 iwl_write_prph(trans,
 916                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
 917                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
 918
 919                 /* load to FW the binary sections of CPU2 */
 920                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
 921                                                  &first_ucode_section);
 922                 if (ret)
 923                         return ret;
 924         }
 925
 926         /* supported for 7000 only for the moment */
 927         if (iwlwifi_mod_params.fw_monitor &&
 928             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
 929                 iwl_pcie_alloc_fw_monitor(trans, 0);
 930
 931                 if (trans_pcie->fw_mon_size) {
 932                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
 933                                        trans_pcie->fw_mon_phys >> 4);
 934                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
 935                                        (trans_pcie->fw_mon_phys +
 936                                         trans_pcie->fw_mon_size) >> 4);
 937                 }
 938         } else if (trans->dbg_dest_tlv) {
 939                 iwl_pcie_apply_destination(trans);
 940         }
 941
 942         /* release CPU reset */
 943         iwl_write32(trans, CSR_RESET, 0);
 944
 945         return 0;
 946 }
 947
 948 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
 949                                           const struct fw_img *image)
 950 {
 951         int ret = 0;
 952         int first_ucode_section;
 953
 954         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 955                      image->is_dual_cpus ? "Dual" : "Single");
 956
 957         if (trans->dbg_dest_tlv)
 958                 iwl_pcie_apply_destination(trans);
 959
 960         /* TODO: remove in the next Si step */
 961         ret = iwl_pcie_rsa_race_bug_wa(trans);
 962         if (ret)
 963                 return ret;
 964
 965         /* configure the ucode to be ready to get the secured image */
 966         /* release CPU reset */
 967         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
 968
 969         /* load to FW the binary Secured sections of CPU1 */
 970         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
 971                                               &first_ucode_section);
 972         if (ret)
 973                 return ret;
 974
 975         /* load to FW the binary sections of CPU2 */
 976         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 2,
 977                                               &first_ucode_section);
 978         if (ret)
 979                 return ret;
 980
 981         return 0;
 982 }
 983
 984 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 985                                    const struct fw_img *fw, bool run_in_rfkill)
 986 {
 987         int ret;
 988         bool hw_rfkill;
 989
 990         /* This may fail if AMT took ownership of the device */
 991         if (iwl_pcie_prepare_card_hw(trans)) {
 992                 IWL_WARN(trans, "Exit HW not ready\n");
 993                 return -EIO;
 994         }
 995
 996         iwl_enable_rfkill_int(trans);
 997
 998         /* If platform's RF_KILL switch is NOT set to KILL */
 999         hw_rfkill = iwl_is_rfkill_set(trans);
1000         if (hw_rfkill)
1001                 set_bit(STATUS_RFKILL, &trans->status);
1002         else
1003                 clear_bit(STATUS_RFKILL, &trans->status);
1004         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1005         if (hw_rfkill && !run_in_rfkill)
1006                 return -ERFKILL;
1007
1008         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1009
1010         ret = iwl_pcie_nic_init(trans);
1011         if (ret) {
1012                 IWL_ERR(trans, "Unable to init nic\n");
1013                 return ret;
1014         }
1015
1016         /* make sure rfkill handshake bits are cleared */
1017         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1018         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1019                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1020
1021         /* clear (again), then enable host interrupts */
1022         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1023         iwl_enable_interrupts(trans);
1024
1025         /* really make sure rfkill handshake bits are cleared */
1026         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1027         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1028
1029         /* Load the given image to the HW */
1030         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1031                 return iwl_pcie_load_given_ucode_8000(trans, fw);
1032         else
1033                 return iwl_pcie_load_given_ucode(trans, fw);
1034 }
1035
1036 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1037 {
1038         iwl_pcie_reset_ict(trans);
1039         iwl_pcie_tx_start(trans, scd_addr);
1040 }
1041
1042 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1043 {
1044         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1045         bool hw_rfkill, was_hw_rfkill;
1046
1047         was_hw_rfkill = iwl_is_rfkill_set(trans);
1048
1049         /* tell the device to stop sending interrupts */
1050         spin_lock(&trans_pcie->irq_lock);
1051         iwl_disable_interrupts(trans);
1052         spin_unlock(&trans_pcie->irq_lock);
1053
1054         /* device going down, Stop using ICT table */
1055         iwl_pcie_disable_ict(trans);
1056
1057         /*
1058          * If a HW restart happens during firmware loading,
1059          * then the firmware loading might call this function
1060          * and later it might be called again due to the
1061          * restart. So don't process again if the device is
1062          * already dead.
1063          */
1064         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1065                 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
1066                 iwl_pcie_tx_stop(trans);
1067                 iwl_pcie_rx_stop(trans);
1068
1069                 /* Power-down device's busmaster DMA clocks */
1070                 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
1071                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1072                                        APMG_CLK_VAL_DMA_CLK_RQT);
1073                         udelay(5);
1074                 }
1075         }
1076
1077         /* Make sure (redundant) we've released our request to stay awake */
1078         iwl_clear_bit(trans, CSR_GP_CNTRL,
1079                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1080
1081         /* Stop the device, and put it in low power state */
1082         iwl_pcie_apm_stop(trans, false);
1083
1084         /* stop and reset the on-board processor */
1085         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1086         udelay(20);
1087
1088         /*
1089          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1090          * This is a bug in certain verions of the hardware.
1091          * Certain devices also keep sending HW RF kill interrupt all
1092          * the time, unless the interrupt is ACKed even if the interrupt
1093          * should be masked. Re-ACK all the interrupts here.
1094          */
1095         spin_lock(&trans_pcie->irq_lock);
1096         iwl_disable_interrupts(trans);
1097         spin_unlock(&trans_pcie->irq_lock);
1098
1099
1100         /* clear all status bits */
1101         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1102         clear_bit(STATUS_INT_ENABLED, &trans->status);
1103         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1104         clear_bit(STATUS_RFKILL, &trans->status);
1105
1106         /*
1107          * Even if we stop the HW, we still want the RF kill
1108          * interrupt
1109          */
1110         iwl_enable_rfkill_int(trans);
1111
1112         /*
1113          * Check again since the RF kill state may have changed while
1114          * all the interrupts were disabled, in this case we couldn't
1115          * receive the RF kill interrupt and update the state in the
1116          * op_mode.
1117          * Don't call the op_mode if the rkfill state hasn't changed.
1118          * This allows the op_mode to call stop_device from the rfkill
1119          * notification without endless recursion. Under very rare
1120          * circumstances, we might have a small recursion if the rfkill
1121          * state changed exactly now while we were called from stop_device.
1122          * This is very unlikely but can happen and is supported.
1123          */
1124         hw_rfkill = iwl_is_rfkill_set(trans);
1125         if (hw_rfkill)
1126                 set_bit(STATUS_RFKILL, &trans->status);
1127         else
1128                 clear_bit(STATUS_RFKILL, &trans->status);
1129         if (hw_rfkill != was_hw_rfkill)
1130                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1131
1132         /* re-take ownership to prevent other users from stealing the deivce */
1133         iwl_pcie_prepare_card_hw(trans);
1134 }
1135
1136 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1137 {
1138         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1139                 iwl_trans_pcie_stop_device(trans, true);
1140 }
1141
1142 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
1143 {
1144         iwl_disable_interrupts(trans);
1145
1146         /*
1147          * in testing mode, the host stays awake and the
1148          * hardware won't be reset (not even partially)
1149          */
1150         if (test)
1151                 return;
1152
1153         iwl_pcie_disable_ict(trans);
1154
1155         iwl_clear_bit(trans, CSR_GP_CNTRL,
1156                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1157         iwl_clear_bit(trans, CSR_GP_CNTRL,
1158                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1159
1160         /*
1161          * reset TX queues -- some of their registers reset during S3
1162          * so if we don't reset everything here the D3 image would try
1163          * to execute some invalid memory upon resume
1164          */
1165         iwl_trans_pcie_tx_reset(trans);
1166
1167         iwl_pcie_set_pwr(trans, true);
1168 }
1169
1170 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1171                                     enum iwl_d3_status *status,
1172                                     bool test)
1173 {
1174         u32 val;
1175         int ret;
1176
1177         if (test) {
1178                 iwl_enable_interrupts(trans);
1179                 *status = IWL_D3_STATUS_ALIVE;
1180                 return 0;
1181         }
1182
1183         /*
1184          * Also enables interrupts - none will happen as the device doesn't
1185          * know we're waking it up, only when the opmode actually tells it
1186          * after this call.
1187          */
1188         iwl_pcie_reset_ict(trans);
1189
1190         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1191         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1192
1193         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1194                 udelay(2);
1195
1196         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1197                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1198                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1199                            25000);
1200         if (ret < 0) {
1201                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1202                 return ret;
1203         }
1204
1205         iwl_pcie_set_pwr(trans, false);
1206
1207         iwl_trans_pcie_tx_reset(trans);
1208
1209         ret = iwl_pcie_rx_init(trans);
1210         if (ret) {
1211                 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1212                 return ret;
1213         }
1214
1215         val = iwl_read32(trans, CSR_RESET);
1216         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1217                 *status = IWL_D3_STATUS_RESET;
1218         else
1219                 *status = IWL_D3_STATUS_ALIVE;
1220
1221         return 0;
1222 }
1223
1224 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1225 {
1226         bool hw_rfkill;
1227         int err;
1228
1229         err = iwl_pcie_prepare_card_hw(trans);
1230         if (err) {
1231                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1232                 return err;
1233         }
1234
1235         /* Reset the entire device */
1236         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1237
1238         usleep_range(10, 15);
1239
1240         iwl_pcie_apm_init(trans);
1241
1242         /* From now on, the op_mode will be kept updated about RF kill state */
1243         iwl_enable_rfkill_int(trans);
1244
1245         hw_rfkill = iwl_is_rfkill_set(trans);
1246         if (hw_rfkill)
1247                 set_bit(STATUS_RFKILL, &trans->status);
1248         else
1249                 clear_bit(STATUS_RFKILL, &trans->status);
1250         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1251
1252         return 0;
1253 }
1254
1255 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1256 {
1257         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1258
1259         /* disable interrupts - don't enable HW RF kill interrupt */
1260         spin_lock(&trans_pcie->irq_lock);
1261         iwl_disable_interrupts(trans);
1262         spin_unlock(&trans_pcie->irq_lock);
1263
1264         iwl_pcie_apm_stop(trans, true);
1265
1266         spin_lock(&trans_pcie->irq_lock);
1267         iwl_disable_interrupts(trans);
1268         spin_unlock(&trans_pcie->irq_lock);
1269
1270         iwl_pcie_disable_ict(trans);
1271 }
1272
1273 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1274 {
1275         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1276 }
1277
1278 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1279 {
1280         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1281 }
1282
1283 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1284 {
1285         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1286 }
1287
1288 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1289 {
1290         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1291                                ((reg & 0x000FFFFF) | (3 << 24)));
1292         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1293 }
1294
1295 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1296                                       u32 val)
1297 {
1298         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1299                                ((addr & 0x000FFFFF) | (3 << 24)));
1300         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1301 }
1302
1303 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1304 {
1305         WARN_ON(1);
1306         return 0;
1307 }
1308
1309 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1310                                      const struct iwl_trans_config *trans_cfg)
1311 {
1312         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1313
1314         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1315         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1316         trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1317         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1318                 trans_pcie->n_no_reclaim_cmds = 0;
1319         else
1320                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1321         if (trans_pcie->n_no_reclaim_cmds)
1322                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1323                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1324
1325         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1326         if (trans_pcie->rx_buf_size_8k)
1327                 trans_pcie->rx_page_order = get_order(8 * 1024);
1328         else
1329                 trans_pcie->rx_page_order = get_order(4 * 1024);
1330
1331         trans_pcie->command_names = trans_cfg->command_names;
1332         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1333         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1334
1335         /* init ref_count to 1 (should be cleared when ucode is loaded) */
1336         trans_pcie->ref_count = 1;
1337
1338         /* Initialize NAPI here - it should be before registering to mac80211
1339          * in the opmode but after the HW struct is allocated.
1340          * As this function may be called again in some corner cases don't
1341          * do anything if NAPI was already initialized.
1342          */
1343         if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1344                 init_dummy_netdev(&trans_pcie->napi_dev);
1345                 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1346                                      &trans_pcie->napi_dev,
1347                                      iwl_pcie_dummy_napi_poll, 64);
1348         }
1349 }
1350
1351 void iwl_trans_pcie_free(struct iwl_trans *trans)
1352 {
1353         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1354
1355         synchronize_irq(trans_pcie->pci_dev->irq);
1356
1357         iwl_pcie_tx_free(trans);
1358         iwl_pcie_rx_free(trans);
1359
1360         free_irq(trans_pcie->pci_dev->irq, trans);
1361         iwl_pcie_free_ict(trans);
1362
1363         pci_disable_msi(trans_pcie->pci_dev);
1364         iounmap(trans_pcie->hw_base);
1365         pci_release_regions(trans_pcie->pci_dev);
1366         pci_disable_device(trans_pcie->pci_dev);
1367         kmem_cache_destroy(trans->dev_cmd_pool);
1368
1369         if (trans_pcie->napi.poll)
1370                 netif_napi_del(&trans_pcie->napi);
1371
1372         iwl_pcie_free_fw_monitor(trans);
1373
1374         kfree(trans);
1375 }
1376
1377 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1378 {
1379         if (state)
1380                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1381         else
1382                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1383 }
1384
1385 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1386                                                 unsigned long *flags)
1387 {
1388         int ret;
1389         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1390
1391         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1392
1393         if (trans_pcie->cmd_hold_nic_awake)
1394                 goto out;
1395
1396         /* this bit wakes up the NIC */
1397         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1398                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1399         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1400                 udelay(2);
1401
1402         /*
1403          * These bits say the device is running, and should keep running for
1404          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1405          * but they do not indicate that embedded SRAM is restored yet;
1406          * 3945 and 4965 have volatile SRAM, and must save/restore contents
1407          * to/from host DRAM when sleeping/waking for power-saving.
1408          * Each direction takes approximately 1/4 millisecond; with this
1409          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1410          * series of register accesses are expected (e.g. reading Event Log),
1411          * to keep device from sleeping.
1412          *
1413          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1414          * SRAM is okay/restored.  We don't check that here because this call
1415          * is just for hardware register access; but GP1 MAC_SLEEP check is a
1416          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1417          *
1418          * 5000 series and later (including 1000 series) have non-volatile SRAM,
1419          * and do not save/restore SRAM when power cycling.
1420          */
1421         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1422                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1423                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1424                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1425         if (unlikely(ret < 0)) {
1426                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1427                 if (!silent) {
1428                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1429                         WARN_ONCE(1,
1430                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1431                                   val);
1432                         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1433                         return false;
1434                 }
1435         }
1436
1437 out:
1438         /*
1439          * Fool sparse by faking we release the lock - sparse will
1440          * track nic_access anyway.
1441          */
1442         __release(&trans_pcie->reg_lock);
1443         return true;
1444 }
1445
1446 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1447                                               unsigned long *flags)
1448 {
1449         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1450
1451         lockdep_assert_held(&trans_pcie->reg_lock);
1452
1453         /*
1454          * Fool sparse by faking we acquiring the lock - sparse will
1455          * track nic_access anyway.
1456          */
1457         __acquire(&trans_pcie->reg_lock);
1458
1459         if (trans_pcie->cmd_hold_nic_awake)
1460                 goto out;
1461
1462         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1463                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1464         /*
1465          * Above we read the CSR_GP_CNTRL register, which will flush
1466          * any previous writes, but we need the write that clears the
1467          * MAC_ACCESS_REQ bit to be performed before any other writes
1468          * scheduled on different CPUs (after we drop reg_lock).
1469          */
1470         mmiowb();
1471 out:
1472         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1473 }
1474
1475 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1476                                    void *buf, int dwords)
1477 {
1478         unsigned long flags;
1479         int offs, ret = 0;
1480         u32 *vals = buf;
1481
1482         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1483                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1484                 for (offs = 0; offs < dwords; offs++)
1485                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1486                 iwl_trans_release_nic_access(trans, &flags);
1487         } else {
1488                 ret = -EBUSY;
1489         }
1490         return ret;
1491 }
1492
1493 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1494                                     const void *buf, int dwords)
1495 {
1496         unsigned long flags;
1497         int offs, ret = 0;
1498         const u32 *vals = buf;
1499
1500         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1501                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1502                 for (offs = 0; offs < dwords; offs++)
1503                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1504                                     vals ? vals[offs] : 0);
1505                 iwl_trans_release_nic_access(trans, &flags);
1506         } else {
1507                 ret = -EBUSY;
1508         }
1509         return ret;
1510 }
1511
1512 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1513                                             unsigned long txqs,
1514                                             bool freeze)
1515 {
1516         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1517         int queue;
1518
1519         for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1520                 struct iwl_txq *txq = &trans_pcie->txq[queue];
1521                 unsigned long now;
1522
1523                 spin_lock_bh(&txq->lock);
1524
1525                 now = jiffies;
1526
1527                 if (txq->frozen == freeze)
1528                         goto next_queue;
1529
1530                 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1531                                     freeze ? "Freezing" : "Waking", queue);
1532
1533                 txq->frozen = freeze;
1534
1535                 if (txq->q.read_ptr == txq->q.write_ptr)
1536                         goto next_queue;
1537
1538                 if (freeze) {
1539                         if (unlikely(time_after(now,
1540                                                 txq->stuck_timer.expires))) {
1541                                 /*
1542                                  * The timer should have fired, maybe it is
1543                                  * spinning right now on the lock.
1544                                  */
1545                                 goto next_queue;
1546                         }
1547                         /* remember how long until the timer fires */
1548                         txq->frozen_expiry_remainder =
1549                                 txq->stuck_timer.expires - now;
1550                         del_timer(&txq->stuck_timer);
1551                         goto next_queue;
1552                 }
1553
1554                 /*
1555                  * Wake a non-empty queue -> arm timer with the
1556                  * remainder before it froze
1557                  */
1558                 mod_timer(&txq->stuck_timer,
1559                           now + txq->frozen_expiry_remainder);
1560
1561 next_queue:
1562                 spin_unlock_bh(&txq->lock);
1563         }
1564 }
1565
1566 #define IWL_FLUSH_WAIT_MS       2000
1567
1568 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1569 {
1570         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1571         struct iwl_txq *txq;
1572         struct iwl_queue *q;
1573         int cnt;
1574         unsigned long now = jiffies;
1575         u32 scd_sram_addr;
1576         u8 buf[16];
1577         int ret = 0;
1578
1579         /* waiting for all the tx frames complete might take a while */
1580         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1581                 u8 wr_ptr;
1582
1583                 if (cnt == trans_pcie->cmd_queue)
1584                         continue;
1585                 if (!test_bit(cnt, trans_pcie->queue_used))
1586                         continue;
1587                 if (!(BIT(cnt) & txq_bm))
1588                         continue;
1589
1590                 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1591                 txq = &trans_pcie->txq[cnt];
1592                 q = &txq->q;
1593                 wr_ptr = ACCESS_ONCE(q->write_ptr);
1594
1595                 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1596                        !time_after(jiffies,
1597                                    now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1598                         u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1599
1600                         if (WARN_ONCE(wr_ptr != write_ptr,
1601                                       "WR pointer moved while flushing %d -> %d\n",
1602                                       wr_ptr, write_ptr))
1603                                 return -ETIMEDOUT;
1604                         msleep(1);
1605                 }
1606
1607                 if (q->read_ptr != q->write_ptr) {
1608                         IWL_ERR(trans,
1609                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1610                         ret = -ETIMEDOUT;
1611                         break;
1612                 }
1613                 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1614         }
1615
1616         if (!ret)
1617                 return 0;
1618
1619         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1620                 txq->q.read_ptr, txq->q.write_ptr);
1621
1622         scd_sram_addr = trans_pcie->scd_base_addr +
1623                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1624         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1625
1626         iwl_print_hex_error(trans, buf, sizeof(buf));
1627
1628         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1629                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1630                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1631
1632         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1633                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1634                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1635                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1636                 u32 tbl_dw =
1637                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1638                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1639
1640                 if (cnt & 0x1)
1641                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1642                 else
1643                         tbl_dw = tbl_dw & 0x0000FFFF;
1644
1645                 IWL_ERR(trans,
1646                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1647                         cnt, active ? "" : "in", fifo, tbl_dw,
1648                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1649                                 (TFD_QUEUE_SIZE_MAX - 1),
1650                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1651         }
1652
1653         return ret;
1654 }
1655
1656 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1657                                          u32 mask, u32 value)
1658 {
1659         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1660         unsigned long flags;
1661
1662         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1663         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1664         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1665 }
1666
1667 void iwl_trans_pcie_ref(struct iwl_trans *trans)
1668 {
1669         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1670         unsigned long flags;
1671
1672         if (iwlwifi_mod_params.d0i3_disable)
1673                 return;
1674
1675         spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1676         IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1677         trans_pcie->ref_count++;
1678         spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1679 }
1680
1681 void iwl_trans_pcie_unref(struct iwl_trans *trans)
1682 {
1683         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1684         unsigned long flags;
1685
1686         if (iwlwifi_mod_params.d0i3_disable)
1687                 return;
1688
1689         spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1690         IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1691         if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1692                 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1693                 return;
1694         }
1695         trans_pcie->ref_count--;
1696         spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1697 }
1698
1699 static const char *get_csr_string(int cmd)
1700 {
1701 #define IWL_CMD(x) case x: return #x
1702         switch (cmd) {
1703         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1704         IWL_CMD(CSR_INT_COALESCING);
1705         IWL_CMD(CSR_INT);
1706         IWL_CMD(CSR_INT_MASK);
1707         IWL_CMD(CSR_FH_INT_STATUS);
1708         IWL_CMD(CSR_GPIO_IN);
1709         IWL_CMD(CSR_RESET);
1710         IWL_CMD(CSR_GP_CNTRL);
1711         IWL_CMD(CSR_HW_REV);
1712         IWL_CMD(CSR_EEPROM_REG);
1713         IWL_CMD(CSR_EEPROM_GP);
1714         IWL_CMD(CSR_OTP_GP_REG);
1715         IWL_CMD(CSR_GIO_REG);
1716         IWL_CMD(CSR_GP_UCODE_REG);
1717         IWL_CMD(CSR_GP_DRIVER_REG);
1718         IWL_CMD(CSR_UCODE_DRV_GP1);
1719         IWL_CMD(CSR_UCODE_DRV_GP2);
1720         IWL_CMD(CSR_LED_REG);
1721         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1722         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1723         IWL_CMD(CSR_ANA_PLL_CFG);
1724         IWL_CMD(CSR_HW_REV_WA_REG);
1725         IWL_CMD(CSR_MONITOR_STATUS_REG);
1726         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1727         default:
1728                 return "UNKNOWN";
1729         }
1730 #undef IWL_CMD
1731 }
1732
1733 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1734 {
1735         int i;
1736         static const u32 csr_tbl[] = {
1737                 CSR_HW_IF_CONFIG_REG,
1738                 CSR_INT_COALESCING,
1739                 CSR_INT,
1740                 CSR_INT_MASK,
1741                 CSR_FH_INT_STATUS,
1742                 CSR_GPIO_IN,
1743                 CSR_RESET,
1744                 CSR_GP_CNTRL,
1745                 CSR_HW_REV,
1746                 CSR_EEPROM_REG,
1747                 CSR_EEPROM_GP,
1748                 CSR_OTP_GP_REG,
1749                 CSR_GIO_REG,
1750                 CSR_GP_UCODE_REG,
1751                 CSR_GP_DRIVER_REG,
1752                 CSR_UCODE_DRV_GP1,
1753                 CSR_UCODE_DRV_GP2,
1754                 CSR_LED_REG,
1755                 CSR_DRAM_INT_TBL_REG,
1756                 CSR_GIO_CHICKEN_BITS,
1757                 CSR_ANA_PLL_CFG,
1758                 CSR_MONITOR_STATUS_REG,
1759                 CSR_HW_REV_WA_REG,
1760                 CSR_DBG_HPET_MEM_REG
1761         };
1762         IWL_ERR(trans, "CSR values:\n");
1763         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1764                 "CSR_INT_PERIODIC_REG)\n");
1765         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1766                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1767                         get_csr_string(csr_tbl[i]),
1768                         iwl_read32(trans, csr_tbl[i]));
1769         }
1770 }
1771
1772 #ifdef CONFIG_IWLWIFI_DEBUGFS
1773 /* create and remove of files */
1774 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1775         if (!debugfs_create_file(#name, mode, parent, trans,            \
1776                                  &iwl_dbgfs_##name##_ops))              \
1777                 goto err;                                               \
1778 } while (0)
1779
1780 /* file operation */
1781 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1782 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1783         .read = iwl_dbgfs_##name##_read,                                \
1784         .open = simple_open,                                            \
1785         .llseek = generic_file_llseek,                                  \
1786 };
1787
1788 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1789 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1790         .write = iwl_dbgfs_##name##_write,                              \
1791         .open = simple_open,                                            \
1792         .llseek = generic_file_llseek,                                  \
1793 };
1794
1795 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1796 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1797         .write = iwl_dbgfs_##name##_write,                              \
1798         .read = iwl_dbgfs_##name##_read,                                \
1799         .open = simple_open,                                            \
1800         .llseek = generic_file_llseek,                                  \
1801 };
1802
1803 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1804                                        char __user *user_buf,
1805                                        size_t count, loff_t *ppos)
1806 {
1807         struct iwl_trans *trans = file->private_data;
1808         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1809         struct iwl_txq *txq;
1810         struct iwl_queue *q;
1811         char *buf;
1812         int pos = 0;
1813         int cnt;
1814         int ret;
1815         size_t bufsz;
1816
1817         bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
1818
1819         if (!trans_pcie->txq)
1820                 return -EAGAIN;
1821
1822         buf = kzalloc(bufsz, GFP_KERNEL);
1823         if (!buf)
1824                 return -ENOMEM;
1825
1826         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1827                 txq = &trans_pcie->txq[cnt];
1828                 q = &txq->q;
1829                 pos += scnprintf(buf + pos, bufsz - pos,
1830                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
1831                                 cnt, q->read_ptr, q->write_ptr,
1832                                 !!test_bit(cnt, trans_pcie->queue_used),
1833                                  !!test_bit(cnt, trans_pcie->queue_stopped),
1834                                  txq->need_update, txq->frozen,
1835                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
1836         }
1837         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1838         kfree(buf);
1839         return ret;
1840 }
1841
1842 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1843                                        char __user *user_buf,
1844                                        size_t count, loff_t *ppos)
1845 {
1846         struct iwl_trans *trans = file->private_data;
1847         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1848         struct iwl_rxq *rxq = &trans_pcie->rxq;
1849         char buf[256];
1850         int pos = 0;
1851         const size_t bufsz = sizeof(buf);
1852
1853         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1854                                                 rxq->read);
1855         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1856                                                 rxq->write);
1857         pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1858                                                 rxq->write_actual);
1859         pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1860                                                 rxq->need_update);
1861         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1862                                                 rxq->free_count);
1863         if (rxq->rb_stts) {
1864                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1865                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1866         } else {
1867                 pos += scnprintf(buf + pos, bufsz - pos,
1868                                         "closed_rb_num: Not Allocated\n");
1869         }
1870         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1871 }
1872
1873 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1874                                         char __user *user_buf,
1875                                         size_t count, loff_t *ppos)
1876 {
1877         struct iwl_trans *trans = file->private_data;
1878         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1879         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1880
1881         int pos = 0;
1882         char *buf;
1883         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1884         ssize_t ret;
1885
1886         buf = kzalloc(bufsz, GFP_KERNEL);
1887         if (!buf)
1888                 return -ENOMEM;
1889
1890         pos += scnprintf(buf + pos, bufsz - pos,
1891                         "Interrupt Statistics Report:\n");
1892
1893         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1894                 isr_stats->hw);
1895         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1896                 isr_stats->sw);
1897         if (isr_stats->sw || isr_stats->hw) {
1898                 pos += scnprintf(buf + pos, bufsz - pos,
1899                         "\tLast Restarting Code:  0x%X\n",
1900                         isr_stats->err_code);
1901         }
1902 #ifdef CONFIG_IWLWIFI_DEBUG
1903         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1904                 isr_stats->sch);
1905         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1906                 isr_stats->alive);
1907 #endif
1908         pos += scnprintf(buf + pos, bufsz - pos,
1909                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1910
1911         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1912                 isr_stats->ctkill);
1913
1914         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1915                 isr_stats->wakeup);
1916
1917         pos += scnprintf(buf + pos, bufsz - pos,
1918                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1919
1920         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1921                 isr_stats->tx);
1922
1923         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1924                 isr_stats->unhandled);
1925
1926         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1927         kfree(buf);
1928         return ret;
1929 }
1930
1931 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1932                                          const char __user *user_buf,
1933                                          size_t count, loff_t *ppos)
1934 {
1935         struct iwl_trans *trans = file->private_data;
1936         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1937         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1938
1939         char buf[8];
1940         int buf_size;
1941         u32 reset_flag;
1942
1943         memset(buf, 0, sizeof(buf));
1944         buf_size = min(count, sizeof(buf) -  1);
1945         if (copy_from_user(buf, user_buf, buf_size))
1946                 return -EFAULT;
1947         if (sscanf(buf, "%x", &reset_flag) != 1)
1948                 return -EFAULT;
1949         if (reset_flag == 0)
1950                 memset(isr_stats, 0, sizeof(*isr_stats));
1951
1952         return count;
1953 }
1954
1955 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1956                                    const char __user *user_buf,
1957                                    size_t count, loff_t *ppos)
1958 {
1959         struct iwl_trans *trans = file->private_data;
1960         char buf[8];
1961         int buf_size;
1962         int csr;
1963
1964         memset(buf, 0, sizeof(buf));
1965         buf_size = min(count, sizeof(buf) -  1);
1966         if (copy_from_user(buf, user_buf, buf_size))
1967                 return -EFAULT;
1968         if (sscanf(buf, "%d", &csr) != 1)
1969                 return -EFAULT;
1970
1971         iwl_pcie_dump_csr(trans);
1972
1973         return count;
1974 }
1975
1976 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1977                                      char __user *user_buf,
1978                                      size_t count, loff_t *ppos)
1979 {
1980         struct iwl_trans *trans = file->private_data;
1981         char *buf = NULL;
1982         ssize_t ret;
1983
1984         ret = iwl_dump_fh(trans, &buf);
1985         if (ret < 0)
1986                 return ret;
1987         if (!buf)
1988                 return -EINVAL;
1989         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1990         kfree(buf);
1991         return ret;
1992 }
1993
1994 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1995 DEBUGFS_READ_FILE_OPS(fh_reg);
1996 DEBUGFS_READ_FILE_OPS(rx_queue);
1997 DEBUGFS_READ_FILE_OPS(tx_queue);
1998 DEBUGFS_WRITE_FILE_OPS(csr);
1999
2000 /*
2001  * Create the debugfs files and directories
2002  *
2003  */
2004 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2005                                          struct dentry *dir)
2006 {
2007         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2008         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2009         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2010         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2011         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2012         return 0;
2013
2014 err:
2015         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2016         return -ENOMEM;
2017 }
2018 #else
2019 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2020                                          struct dentry *dir)
2021 {
2022         return 0;
2023 }
2024 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2025
2026 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2027 {
2028         u32 cmdlen = 0;
2029         int i;
2030
2031         for (i = 0; i < IWL_NUM_OF_TBS; i++)
2032                 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2033
2034         return cmdlen;
2035 }
2036
2037 static const struct {
2038         u32 start, end;
2039 } iwl_prph_dump_addr[] = {
2040         { .start = 0x00a00000, .end = 0x00a00000 },
2041         { .start = 0x00a0000c, .end = 0x00a00024 },
2042         { .start = 0x00a0002c, .end = 0x00a0003c },
2043         { .start = 0x00a00410, .end = 0x00a00418 },
2044         { .start = 0x00a00420, .end = 0x00a00420 },
2045         { .start = 0x00a00428, .end = 0x00a00428 },
2046         { .start = 0x00a00430, .end = 0x00a0043c },
2047         { .start = 0x00a00444, .end = 0x00a00444 },
2048         { .start = 0x00a004c0, .end = 0x00a004cc },
2049         { .start = 0x00a004d8, .end = 0x00a004d8 },
2050         { .start = 0x00a004e0, .end = 0x00a004f0 },
2051         { .start = 0x00a00840, .end = 0x00a00840 },
2052         { .start = 0x00a00850, .end = 0x00a00858 },
2053         { .start = 0x00a01004, .end = 0x00a01008 },
2054         { .start = 0x00a01010, .end = 0x00a01010 },
2055         { .start = 0x00a01018, .end = 0x00a01018 },
2056         { .start = 0x00a01024, .end = 0x00a01024 },
2057         { .start = 0x00a0102c, .end = 0x00a01034 },
2058         { .start = 0x00a0103c, .end = 0x00a01040 },
2059         { .start = 0x00a01048, .end = 0x00a01094 },
2060         { .start = 0x00a01c00, .end = 0x00a01c20 },
2061         { .start = 0x00a01c58, .end = 0x00a01c58 },
2062         { .start = 0x00a01c7c, .end = 0x00a01c7c },
2063         { .start = 0x00a01c28, .end = 0x00a01c54 },
2064         { .start = 0x00a01c5c, .end = 0x00a01c5c },
2065         { .start = 0x00a01c60, .end = 0x00a01cdc },
2066         { .start = 0x00a01ce0, .end = 0x00a01d0c },
2067         { .start = 0x00a01d18, .end = 0x00a01d20 },
2068         { .start = 0x00a01d2c, .end = 0x00a01d30 },
2069         { .start = 0x00a01d40, .end = 0x00a01d5c },
2070         { .start = 0x00a01d80, .end = 0x00a01d80 },
2071         { .start = 0x00a01d98, .end = 0x00a01d9c },
2072         { .start = 0x00a01da8, .end = 0x00a01da8 },
2073         { .start = 0x00a01db8, .end = 0x00a01df4 },
2074         { .start = 0x00a01dc0, .end = 0x00a01dfc },
2075         { .start = 0x00a01e00, .end = 0x00a01e2c },
2076         { .start = 0x00a01e40, .end = 0x00a01e60 },
2077         { .start = 0x00a01e68, .end = 0x00a01e6c },
2078         { .start = 0x00a01e74, .end = 0x00a01e74 },
2079         { .start = 0x00a01e84, .end = 0x00a01e90 },
2080         { .start = 0x00a01e9c, .end = 0x00a01ec4 },
2081         { .start = 0x00a01ed0, .end = 0x00a01ee0 },
2082         { .start = 0x00a01f00, .end = 0x00a01f1c },
2083         { .start = 0x00a01f44, .end = 0x00a01ffc },
2084         { .start = 0x00a02000, .end = 0x00a02048 },
2085         { .start = 0x00a02068, .end = 0x00a020f0 },
2086         { .start = 0x00a02100, .end = 0x00a02118 },
2087         { .start = 0x00a02140, .end = 0x00a0214c },
2088         { .start = 0x00a02168, .end = 0x00a0218c },
2089         { .start = 0x00a021c0, .end = 0x00a021c0 },
2090         { .start = 0x00a02400, .end = 0x00a02410 },
2091         { .start = 0x00a02418, .end = 0x00a02420 },
2092         { .start = 0x00a02428, .end = 0x00a0242c },
2093         { .start = 0x00a02434, .end = 0x00a02434 },
2094         { .start = 0x00a02440, .end = 0x00a02460 },
2095         { .start = 0x00a02468, .end = 0x00a024b0 },
2096         { .start = 0x00a024c8, .end = 0x00a024cc },
2097         { .start = 0x00a02500, .end = 0x00a02504 },
2098         { .start = 0x00a0250c, .end = 0x00a02510 },
2099         { .start = 0x00a02540, .end = 0x00a02554 },
2100         { .start = 0x00a02580, .end = 0x00a025f4 },
2101         { .start = 0x00a02600, .end = 0x00a0260c },
2102         { .start = 0x00a02648, .end = 0x00a02650 },
2103         { .start = 0x00a02680, .end = 0x00a02680 },
2104         { .start = 0x00a026c0, .end = 0x00a026d0 },
2105         { .start = 0x00a02700, .end = 0x00a0270c },
2106         { .start = 0x00a02804, .end = 0x00a02804 },
2107         { .start = 0x00a02818, .end = 0x00a0281c },
2108         { .start = 0x00a02c00, .end = 0x00a02db4 },
2109         { .start = 0x00a02df4, .end = 0x00a02fb0 },
2110         { .start = 0x00a03000, .end = 0x00a03014 },
2111         { .start = 0x00a0301c, .end = 0x00a0302c },
2112         { .start = 0x00a03034, .end = 0x00a03038 },
2113         { .start = 0x00a03040, .end = 0x00a03048 },
2114         { .start = 0x00a03060, .end = 0x00a03068 },
2115         { .start = 0x00a03070, .end = 0x00a03074 },
2116         { .start = 0x00a0307c, .end = 0x00a0307c },
2117         { .start = 0x00a03080, .end = 0x00a03084 },
2118         { .start = 0x00a0308c, .end = 0x00a03090 },
2119         { .start = 0x00a03098, .end = 0x00a03098 },
2120         { .start = 0x00a030a0, .end = 0x00a030a0 },
2121         { .start = 0x00a030a8, .end = 0x00a030b4 },
2122         { .start = 0x00a030bc, .end = 0x00a030bc },
2123         { .start = 0x00a030c0, .end = 0x00a0312c },
2124         { .start = 0x00a03c00, .end = 0x00a03c5c },
2125         { .start = 0x00a04400, .end = 0x00a04454 },
2126         { .start = 0x00a04460, .end = 0x00a04474 },
2127         { .start = 0x00a044c0, .end = 0x00a044ec },
2128         { .start = 0x00a04500, .end = 0x00a04504 },
2129         { .start = 0x00a04510, .end = 0x00a04538 },
2130         { .start = 0x00a04540, .end = 0x00a04548 },
2131         { .start = 0x00a04560, .end = 0x00a0457c },
2132         { .start = 0x00a04590, .end = 0x00a04598 },
2133         { .start = 0x00a045c0, .end = 0x00a045f4 },
2134 };
2135
2136 static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
2137                                     struct iwl_fw_error_dump_data **data)
2138 {
2139         struct iwl_fw_error_dump_prph *prph;
2140         unsigned long flags;
2141         u32 prph_len = 0, i;
2142
2143         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2144                 return 0;
2145
2146         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2147                 /* The range includes both boundaries */
2148                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2149                          iwl_prph_dump_addr[i].start + 4;
2150                 int reg;
2151                 __le32 *val;
2152
2153                 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
2154
2155                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
2156                 (*data)->len = cpu_to_le32(sizeof(*prph) +
2157                                         num_bytes_in_chunk);
2158                 prph = (void *)(*data)->data;
2159                 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
2160                 val = (void *)prph->data;
2161
2162                 for (reg = iwl_prph_dump_addr[i].start;
2163                      reg <= iwl_prph_dump_addr[i].end;
2164                      reg += 4)
2165                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2166                                                                       reg));
2167                 *data = iwl_fw_error_next_data(*data);
2168         }
2169
2170         iwl_trans_release_nic_access(trans, &flags);
2171
2172         return prph_len;
2173 }
2174
2175 #define IWL_CSR_TO_DUMP (0x250)
2176
2177 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2178                                    struct iwl_fw_error_dump_data **data)
2179 {
2180         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2181         __le32 *val;
2182         int i;
2183
2184         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2185         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2186         val = (void *)(*data)->data;
2187
2188         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2189                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2190
2191         *data = iwl_fw_error_next_data(*data);
2192
2193         return csr_len;
2194 }
2195
2196 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2197                                        struct iwl_fw_error_dump_data **data)
2198 {
2199         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2200         unsigned long flags;
2201         __le32 *val;
2202         int i;
2203
2204         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2205                 return 0;
2206
2207         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2208         (*data)->len = cpu_to_le32(fh_regs_len);
2209         val = (void *)(*data)->data;
2210
2211         for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2212                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2213
2214         iwl_trans_release_nic_access(trans, &flags);
2215
2216         *data = iwl_fw_error_next_data(*data);
2217
2218         return sizeof(**data) + fh_regs_len;
2219 }
2220
2221 static u32
2222 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2223                                  struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2224                                  u32 monitor_len)
2225 {
2226         u32 buf_size_in_dwords = (monitor_len >> 2);
2227         u32 *buffer = (u32 *)fw_mon_data->data;
2228         unsigned long flags;
2229         u32 i;
2230
2231         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2232                 return 0;
2233
2234         __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2235         for (i = 0; i < buf_size_in_dwords; i++)
2236                 buffer[i] = __iwl_read_prph(trans, MON_DMARB_RD_DATA_ADDR);
2237         __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2238
2239         iwl_trans_release_nic_access(trans, &flags);
2240
2241         return monitor_len;
2242 }
2243
2244 static
2245 struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
2246 {
2247         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2248         struct iwl_fw_error_dump_data *data;
2249         struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2250         struct iwl_fw_error_dump_txcmd *txcmd;
2251         struct iwl_trans_dump_data *dump_data;
2252         u32 len;
2253         u32 monitor_len;
2254         int i, ptr;
2255
2256         /* transport dump header */
2257         len = sizeof(*dump_data);
2258
2259         /* host commands */
2260         len += sizeof(*data) +
2261                 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2262
2263         /* CSR registers */
2264         len += sizeof(*data) + IWL_CSR_TO_DUMP;
2265
2266         /* PRPH registers */
2267         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2268                 /* The range includes both boundaries */
2269                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2270                         iwl_prph_dump_addr[i].start + 4;
2271
2272                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2273                         num_bytes_in_chunk;
2274         }
2275
2276         /* FH registers */
2277         len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2278
2279         /* FW monitor */
2280         if (trans_pcie->fw_mon_page) {
2281                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2282                        trans_pcie->fw_mon_size;
2283                 monitor_len = trans_pcie->fw_mon_size;
2284         } else if (trans->dbg_dest_tlv) {
2285                 u32 base, end;
2286
2287                 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2288                 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2289
2290                 base = iwl_read_prph(trans, base) <<
2291                        trans->dbg_dest_tlv->base_shift;
2292                 end = iwl_read_prph(trans, end) <<
2293                       trans->dbg_dest_tlv->end_shift;
2294
2295                 /* Make "end" point to the actual end */
2296                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2297                     trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2298                         end += (1 << trans->dbg_dest_tlv->end_shift);
2299                 monitor_len = end - base;
2300                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2301                        monitor_len;
2302         } else {
2303                 monitor_len = 0;
2304         }
2305
2306         dump_data = vzalloc(len);
2307         if (!dump_data)
2308                 return NULL;
2309
2310         len = 0;
2311         data = (void *)dump_data->data;
2312         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2313         txcmd = (void *)data->data;
2314         spin_lock_bh(&cmdq->lock);
2315         ptr = cmdq->q.write_ptr;
2316         for (i = 0; i < cmdq->q.n_window; i++) {
2317                 u8 idx = get_cmd_index(&cmdq->q, ptr);
2318                 u32 caplen, cmdlen;
2319
2320                 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2321                 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2322
2323                 if (cmdlen) {
2324                         len += sizeof(*txcmd) + caplen;
2325                         txcmd->cmdlen = cpu_to_le32(cmdlen);
2326                         txcmd->caplen = cpu_to_le32(caplen);
2327                         memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2328                         txcmd = (void *)((u8 *)txcmd->data + caplen);
2329                 }
2330
2331                 ptr = iwl_queue_dec_wrap(ptr);
2332         }
2333         spin_unlock_bh(&cmdq->lock);
2334
2335         data->len = cpu_to_le32(len);
2336         len += sizeof(*data);
2337         data = iwl_fw_error_next_data(data);
2338
2339         len += iwl_trans_pcie_dump_prph(trans, &data);
2340         len += iwl_trans_pcie_dump_csr(trans, &data);
2341         len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2342         /* data is already pointing to the next section */
2343
2344         if ((trans_pcie->fw_mon_page &&
2345              trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2346             trans->dbg_dest_tlv) {
2347                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2348                 u32 base, write_ptr, wrap_cnt;
2349
2350                 /* If there was a dest TLV - use the values from there */
2351                 if (trans->dbg_dest_tlv) {
2352                         write_ptr =
2353                                 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2354                         wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2355                         base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2356                 } else {
2357                         base = MON_BUFF_BASE_ADDR;
2358                         write_ptr = MON_BUFF_WRPTR;
2359                         wrap_cnt = MON_BUFF_CYCLE_CNT;
2360                 }
2361
2362                 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2363                 fw_mon_data = (void *)data->data;
2364                 fw_mon_data->fw_mon_wr_ptr =
2365                         cpu_to_le32(iwl_read_prph(trans, write_ptr));
2366                 fw_mon_data->fw_mon_cycle_cnt =
2367                         cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2368                 fw_mon_data->fw_mon_base_ptr =
2369                         cpu_to_le32(iwl_read_prph(trans, base));
2370
2371                 len += sizeof(*data) + sizeof(*fw_mon_data);
2372                 if (trans_pcie->fw_mon_page) {
2373                         /*
2374                          * The firmware is now asserted, it won't write anything
2375                          * to the buffer. CPU can take ownership to fetch the
2376                          * data. The buffer will be handed back to the device
2377                          * before the firmware will be restarted.
2378                          */
2379                         dma_sync_single_for_cpu(trans->dev,
2380                                                 trans_pcie->fw_mon_phys,
2381                                                 trans_pcie->fw_mon_size,
2382                                                 DMA_FROM_DEVICE);
2383                         memcpy(fw_mon_data->data,
2384                                page_address(trans_pcie->fw_mon_page),
2385                                trans_pcie->fw_mon_size);
2386
2387                         monitor_len = trans_pcie->fw_mon_size;
2388                 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2389                         /*
2390                          * Update pointers to reflect actual values after
2391                          * shifting
2392                          */
2393                         base = iwl_read_prph(trans, base) <<
2394                                trans->dbg_dest_tlv->base_shift;
2395                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
2396                                            monitor_len / sizeof(u32));
2397                 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2398                         monitor_len =
2399                                 iwl_trans_pci_dump_marbh_monitor(trans,
2400                                                                  fw_mon_data,
2401                                                                  monitor_len);
2402                 } else {
2403                         /* Didn't match anything - output no monitor data */
2404                         monitor_len = 0;
2405                 }
2406
2407                 len += monitor_len;
2408                 data->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2409         }
2410
2411         dump_data->len = len;
2412
2413         return dump_data;
2414 }
2415
2416 static const struct iwl_trans_ops trans_ops_pcie = {
2417         .start_hw = iwl_trans_pcie_start_hw,
2418         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2419         .fw_alive = iwl_trans_pcie_fw_alive,
2420         .start_fw = iwl_trans_pcie_start_fw,
2421         .stop_device = iwl_trans_pcie_stop_device,
2422
2423         .d3_suspend = iwl_trans_pcie_d3_suspend,
2424         .d3_resume = iwl_trans_pcie_d3_resume,
2425
2426         .send_cmd = iwl_trans_pcie_send_hcmd,
2427
2428         .tx = iwl_trans_pcie_tx,
2429         .reclaim = iwl_trans_pcie_reclaim,
2430
2431         .txq_disable = iwl_trans_pcie_txq_disable,
2432         .txq_enable = iwl_trans_pcie_txq_enable,
2433
2434         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2435
2436         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2437         .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2438
2439         .write8 = iwl_trans_pcie_write8,
2440         .write32 = iwl_trans_pcie_write32,
2441         .read32 = iwl_trans_pcie_read32,
2442         .read_prph = iwl_trans_pcie_read_prph,
2443         .write_prph = iwl_trans_pcie_write_prph,
2444         .read_mem = iwl_trans_pcie_read_mem,
2445         .write_mem = iwl_trans_pcie_write_mem,
2446         .configure = iwl_trans_pcie_configure,
2447         .set_pmi = iwl_trans_pcie_set_pmi,
2448         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2449         .release_nic_access = iwl_trans_pcie_release_nic_access,
2450         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2451
2452         .ref = iwl_trans_pcie_ref,
2453         .unref = iwl_trans_pcie_unref,
2454
2455         .dump_data = iwl_trans_pcie_dump_data,
2456 };
2457
2458 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2459                                        const struct pci_device_id *ent,
2460                                        const struct iwl_cfg *cfg)
2461 {
2462         struct iwl_trans_pcie *trans_pcie;
2463         struct iwl_trans *trans;
2464         u16 pci_cmd;
2465         int err;
2466
2467         trans = kzalloc(sizeof(struct iwl_trans) +
2468                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2469         if (!trans) {
2470                 err = -ENOMEM;
2471                 goto out;
2472         }
2473
2474         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2475
2476         trans->ops = &trans_ops_pcie;
2477         trans->cfg = cfg;
2478         trans_lockdep_init(trans);
2479         trans_pcie->trans = trans;
2480         spin_lock_init(&trans_pcie->irq_lock);
2481         spin_lock_init(&trans_pcie->reg_lock);
2482         spin_lock_init(&trans_pcie->ref_lock);
2483         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2484
2485         err = pci_enable_device(pdev);
2486         if (err)
2487                 goto out_no_pci;
2488
2489         if (!cfg->base_params->pcie_l1_allowed) {
2490                 /*
2491                  * W/A - seems to solve weird behavior. We need to remove this
2492                  * if we don't want to stay in L1 all the time. This wastes a
2493                  * lot of power.
2494                  */
2495                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2496                                        PCIE_LINK_STATE_L1 |
2497                                        PCIE_LINK_STATE_CLKPM);
2498         }
2499
2500         pci_set_master(pdev);
2501
2502         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2503         if (!err)
2504                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2505         if (err) {
2506                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2507                 if (!err)
2508                         err = pci_set_consistent_dma_mask(pdev,
2509                                                           DMA_BIT_MASK(32));
2510                 /* both attempts failed: */
2511                 if (err) {
2512                         dev_err(&pdev->dev, "No suitable DMA available\n");
2513                         goto out_pci_disable_device;
2514                 }
2515         }
2516
2517         err = pci_request_regions(pdev, DRV_NAME);
2518         if (err) {
2519                 dev_err(&pdev->dev, "pci_request_regions failed\n");
2520                 goto out_pci_disable_device;
2521         }
2522
2523         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2524         if (!trans_pcie->hw_base) {
2525                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2526                 err = -ENODEV;
2527                 goto out_pci_release_regions;
2528         }
2529
2530         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2531          * PCI Tx retries from interfering with C3 CPU state */
2532         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2533
2534         trans->dev = &pdev->dev;
2535         trans_pcie->pci_dev = pdev;
2536         iwl_disable_interrupts(trans);
2537
2538         err = pci_enable_msi(pdev);
2539         if (err) {
2540                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
2541                 /* enable rfkill interrupt: hw bug w/a */
2542                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2543                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2544                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2545                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2546                 }
2547         }
2548
2549         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2550         /*
2551          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2552          * changed, and now the revision step also includes bit 0-1 (no more
2553          * "dash" value). To keep hw_rev backwards compatible - we'll store it
2554          * in the old format.
2555          */
2556         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2557                 unsigned long flags;
2558                 int ret;
2559
2560                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2561                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2562
2563                 /*
2564                  * in-order to recognize C step driver should read chip version
2565                  * id located at the AUX bus MISC address space.
2566                  */
2567                 iwl_set_bit(trans, CSR_GP_CNTRL,
2568                             CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2569                 udelay(2);
2570
2571                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2572                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2573                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2574                                    25000);
2575                 if (ret < 0) {
2576                         IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2577                         goto out_pci_disable_msi;
2578                 }
2579
2580                 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
2581                         u32 hw_step;
2582
2583                         hw_step = __iwl_read_prph(trans, WFPM_CTRL_REG);
2584                         hw_step |= ENABLE_WFPM;
2585                         __iwl_write_prph(trans, WFPM_CTRL_REG, hw_step);
2586                         hw_step = __iwl_read_prph(trans, AUX_MISC_REG);
2587                         hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2588                         if (hw_step == 0x3)
2589                                 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2590                                                 (SILICON_C_STEP << 2);
2591                         iwl_trans_release_nic_access(trans, &flags);
2592                 }
2593         }
2594
2595         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2596         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2597                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2598
2599         /* Initialize the wait queue for commands */
2600         init_waitqueue_head(&trans_pcie->wait_command_queue);
2601
2602         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2603                  "iwl_cmd_pool:%s", dev_name(trans->dev));
2604
2605         trans->dev_cmd_headroom = 0;
2606         trans->dev_cmd_pool =
2607                 kmem_cache_create(trans->dev_cmd_pool_name,
2608                                   sizeof(struct iwl_device_cmd)
2609                                   + trans->dev_cmd_headroom,
2610                                   sizeof(void *),
2611                                   SLAB_HWCACHE_ALIGN,
2612                                   NULL);
2613
2614         if (!trans->dev_cmd_pool) {
2615                 err = -ENOMEM;
2616                 goto out_pci_disable_msi;
2617         }
2618
2619         if (iwl_pcie_alloc_ict(trans))
2620                 goto out_free_cmd_pool;
2621
2622         err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2623                                    iwl_pcie_irq_handler,
2624                                    IRQF_SHARED, DRV_NAME, trans);
2625         if (err) {
2626                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2627                 goto out_free_ict;
2628         }
2629
2630         trans_pcie->inta_mask = CSR_INI_SET_MASK;
2631         trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND;
2632
2633         return trans;
2634
2635 out_free_ict:
2636         iwl_pcie_free_ict(trans);
2637 out_free_cmd_pool:
2638         kmem_cache_destroy(trans->dev_cmd_pool);
2639 out_pci_disable_msi:
2640         pci_disable_msi(pdev);
2641 out_pci_release_regions:
2642         pci_release_regions(pdev);
2643 out_pci_disable_device:
2644         pci_disable_device(pdev);
2645 out_no_pci:
2646         kfree(trans);
2647 out:
2648         return ERR_PTR(err);
2649 }