drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of version 2 of the GNU General Public License as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  23  * USA
  24  *
  25  * The full GNU General Public License is included in this distribution
  26  * in the file called COPYING.
  27  *
  28  * Contact Information:
  29  *  Intel Linux Wireless <ilw@linux.intel.com>
  30  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  31  *
  32  * BSD LICENSE
  33  *
  34  * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
  35  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  36  * All rights reserved.
  37  *
  38  * Redistribution and use in source and binary forms, with or without
  39  * modification, are permitted provided that the following conditions
  40  * are met:
  41  *
  42  *  * Redistributions of source code must retain the above copyright
  43  *    notice, this list of conditions and the following disclaimer.
  44  *  * Redistributions in binary form must reproduce the above copyright
  45  *    notice, this list of conditions and the following disclaimer in
  46  *    the documentation and/or other materials provided with the
  47  *    distribution.
  48  *  * Neither the name Intel Corporation nor the names of its
  49  *    contributors may be used to endorse or promote products derived
  50  *    from this software without specific prior written permission.
  51  *
  52  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  53  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  54  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  55  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  56  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  57  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  58  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  59  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  60  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  61  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  62  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  63  *
  64  *****************************************************************************/
  65 #include <linux/pci.h>
  66 #include <linux/pci-aspm.h>
  67 #include <linux/interrupt.h>
  68 #include <linux/debugfs.h>
  69 #include <linux/sched.h>
  70 #include <linux/bitops.h>
  71 #include <linux/gfp.h>
  72 #include <linux/vmalloc.h>
  73
  74 #include "iwl-drv.h"
  75 #include "iwl-trans.h"
  76 #include "iwl-csr.h"
  77 #include "iwl-prph.h"
  78 #include "iwl-scd.h"
  79 #include "iwl-agn-hw.h"
  80 #include "iwl-fw-error-dump.h"
  81 #include "internal.h"
  82 #include "iwl-fh.h"
  83
  84 /* extended range in FW SRAM */
  85 #define IWL_FW_MEM_EXTENDED_START       0x40000
  86 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  87
  88 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
  89 {
  90         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  91
  92         if (!trans_pcie->fw_mon_page)
  93                 return;
  94
  95         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
  96                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
  97         __free_pages(trans_pcie->fw_mon_page,
  98                      get_order(trans_pcie->fw_mon_size));
  99         trans_pcie->fw_mon_page = NULL;
 100         trans_pcie->fw_mon_phys = 0;
 101         trans_pcie->fw_mon_size = 0;
 102 }
 103
 104 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
 105 {
 106         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 107         struct page *page = NULL;
 108         dma_addr_t phys;
 109         u32 size = 0;
 110         u8 power;
 111
 112         if (!max_power) {
 113                 /* default max_power is maximum */
 114                 max_power = 26;
 115         } else {
 116                 max_power += 11;
 117         }
 118
 119         if (WARN(max_power > 26,
 120                  "External buffer size for monitor is too big %d, check the FW TLV\n",
 121                  max_power))
 122                 return;
 123
 124         if (trans_pcie->fw_mon_page) {
 125                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 126                                            trans_pcie->fw_mon_size,
 127                                            DMA_FROM_DEVICE);
 128                 return;
 129         }
 130
 131         phys = 0;
 132         for (power = max_power; power >= 11; power--) {
 133                 int order;
 134
 135                 size = BIT(power);
 136                 order = get_order(size);
 137                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 138                                    order);
 139                 if (!page)
 140                         continue;
 141
 142                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 143                                     DMA_FROM_DEVICE);
 144                 if (dma_mapping_error(trans->dev, phys)) {
 145                         __free_pages(page, order);
 146                         page = NULL;
 147                         continue;
 148                 }
 149                 IWL_INFO(trans,
 150                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 151                          size, order);
 152                 break;
 153         }
 154
 155         if (WARN_ON_ONCE(!page))
 156                 return;
 157
 158         if (power != max_power)
 159                 IWL_ERR(trans,
 160                         "Sorry - debug buffer is only %luK while you requested %luK\n",
 161                         (unsigned long)BIT(power - 10),
 162                         (unsigned long)BIT(max_power - 10));
 163
 164         trans_pcie->fw_mon_page = page;
 165         trans_pcie->fw_mon_phys = phys;
 166         trans_pcie->fw_mon_size = size;
 167 }
 168
 169 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 170 {
 171         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 172                     ((reg & 0x0000ffff) | (2 << 28)));
 173         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 174 }
 175
 176 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 177 {
 178         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 179         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 180                     ((reg & 0x0000ffff) | (3 << 28)));
 181 }
 182
 183 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 184 {
 185         if (trans->cfg->apmg_not_supported)
 186                 return;
 187
 188         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 189                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 190                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 191                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 192         else
 193                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 194                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 195                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 196 }
 197
 198 /* PCI registers */
 199 #define PCI_CFG_RETRY_TIMEOUT   0x041
 200
 201 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 202 {
 203         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 204         u16 lctl;
 205         u16 cap;
 206
 207         /*
 208          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 209          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 210          * If so (likely), disable L0S, so device moves directly L0->L1;
 211          *    costs negligible amount of power savings.
 212          * If not (unlikely), enable L0S, so there is at least some
 213          *    power savings, even without L1.
 214          */
 215         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 216         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 217                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 218         else
 219                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 220         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 221
 222         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 223         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 224         dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
 225                  (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 226                  trans->ltr_enabled ? "En" : "Dis");
 227 }
 228
 229 /*
 230  * Start up NIC's basic functionality after it has been reset
 231  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 232  * NOTE:  This does not load uCode nor start the embedded processor
 233  */
 234 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 235 {
 236         int ret = 0;
 237         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 238
 239         /*
 240          * Use "set_bit" below rather than "write", to preserve any hardware
 241          * bits already set by default after reset.
 242          */
 243
 244         /* Disable L0S exit timer (platform NMI Work/Around) */
 245         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 246                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 247                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 248
 249         /*
 250          * Disable L0s without affecting L1;
 251          *  don't wait for ICH L0s (ICH bug W/A)
 252          */
 253         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 254                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 255
 256         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 257         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 258
 259         /*
 260          * Enable HAP INTA (interrupt from management bus) to
 261          * wake device's PCI Express link L1a -> L0s
 262          */
 263         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 264                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 265
 266         iwl_pcie_apm_config(trans);
 267
 268         /* Configure analog phase-lock-loop before activating to D0A */
 269         if (trans->cfg->base_params->pll_cfg_val)
 270                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 271                             trans->cfg->base_params->pll_cfg_val);
 272
 273         /*
 274          * Set "initialization complete" bit to move adapter from
 275          * D0U* --> D0A* (powered-up active) state.
 276          */
 277         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 278
 279         /*
 280          * Wait for clock stabilization; once stabilized, access to
 281          * device-internal resources is supported, e.g. iwl_write_prph()
 282          * and accesses to uCode SRAM.
 283          */
 284         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 285                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 286                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 287         if (ret < 0) {
 288                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 289                 goto out;
 290         }
 291
 292         if (trans->cfg->host_interrupt_operation_mode) {
 293                 /*
 294                  * This is a bit of an abuse - This is needed for 7260 / 3160
 295                  * only check host_interrupt_operation_mode even if this is
 296                  * not related to host_interrupt_operation_mode.
 297                  *
 298                  * Enable the oscillator to count wake up time for L1 exit. This
 299                  * consumes slightly more power (100uA) - but allows to be sure
 300                  * that we wake up from L1 on time.
 301                  *
 302                  * This looks weird: read twice the same register, discard the
 303                  * value, set a bit, and yet again, read that same register
 304                  * just to discard the value. But that's the way the hardware
 305                  * seems to like it.
 306                  */
 307                 iwl_read_prph(trans, OSC_CLK);
 308                 iwl_read_prph(trans, OSC_CLK);
 309                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 310                 iwl_read_prph(trans, OSC_CLK);
 311                 iwl_read_prph(trans, OSC_CLK);
 312         }
 313
 314         /*
 315          * Enable DMA clock and wait for it to stabilize.
 316          *
 317          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 318          * bits do not disable clocks.  This preserves any hardware
 319          * bits already set by default in "CLK_CTRL_REG" after reset.
 320          */
 321         if (!trans->cfg->apmg_not_supported) {
 322                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 323                                APMG_CLK_VAL_DMA_CLK_RQT);
 324                 udelay(20);
 325
 326                 /* Disable L1-Active */
 327                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 328                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 329
 330                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 331                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 332                                APMG_RTC_INT_STT_RFKILL);
 333         }
 334
 335         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 336
 337 out:
 338         return ret;
 339 }
 340
 341 /*
 342  * Enable LP XTAL to avoid HW bug where device may consume much power if
 343  * FW is not loaded after device reset. LP XTAL is disabled by default
 344  * after device HW reset. Do it only if XTAL is fed by internal source.
 345  * Configure device's "persistence" mode to avoid resetting XTAL again when
 346  * SHRD_HW_RST occurs in S3.
 347  */
 348 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 349 {
 350         int ret;
 351         u32 apmg_gp1_reg;
 352         u32 apmg_xtal_cfg_reg;
 353         u32 dl_cfg_reg;
 354
 355         /* Force XTAL ON */
 356         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 357                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 358
 359         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 360         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 361
 362         udelay(10);
 363
 364         /*
 365          * Set "initialization complete" bit to move adapter from
 366          * D0U* --> D0A* (powered-up active) state.
 367          */
 368         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 369
 370         /*
 371          * Wait for clock stabilization; once stabilized, access to
 372          * device-internal resources is possible.
 373          */
 374         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 375                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 376                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 377                            25000);
 378         if (WARN_ON(ret < 0)) {
 379                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 380                 /* Release XTAL ON request */
 381                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 382                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 383                 return;
 384         }
 385
 386         /*
 387          * Clear "disable persistence" to avoid LP XTAL resetting when
 388          * SHRD_HW_RST is applied in S3.
 389          */
 390         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 391                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 392
 393         /*
 394          * Force APMG XTAL to be active to prevent its disabling by HW
 395          * caused by APMG idle state.
 396          */
 397         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 398                                                     SHR_APMG_XTAL_CFG_REG);
 399         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 400                                  apmg_xtal_cfg_reg |
 401                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 402
 403         /*
 404          * Reset entire device again - do controller reset (results in
 405          * SHRD_HW_RST). Turn MAC off before proceeding.
 406          */
 407         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 408
 409         udelay(10);
 410
 411         /* Enable LP XTAL by indirect access through CSR */
 412         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 413         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 414                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 415                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 416
 417         /* Clear delay line clock power up */
 418         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 419         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 420                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 421
 422         /*
 423          * Enable persistence mode to avoid LP XTAL resetting when
 424          * SHRD_HW_RST is applied in S3.
 425          */
 426         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 427                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 428
 429         /*
 430          * Clear "initialization complete" bit to move adapter from
 431          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 432          */
 433         iwl_clear_bit(trans, CSR_GP_CNTRL,
 434                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 435
 436         /* Activates XTAL resources monitor */
 437         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 438                                  CSR_MONITOR_XTAL_RESOURCES);
 439
 440         /* Release XTAL ON request */
 441         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 442                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 443         udelay(10);
 444
 445         /* Release APMG XTAL */
 446         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 447                                  apmg_xtal_cfg_reg &
 448                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 449 }
 450
 451 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 452 {
 453         int ret = 0;
 454
 455         /* stop device's busmaster DMA activity */
 456         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 457
 458         ret = iwl_poll_bit(trans, CSR_RESET,
 459                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 460                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 461         if (ret < 0)
 462                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 463
 464         IWL_DEBUG_INFO(trans, "stop master\n");
 465
 466         return ret;
 467 }
 468
 469 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 470 {
 471         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 472
 473         if (op_mode_leave) {
 474                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 475                         iwl_pcie_apm_init(trans);
 476
 477                 /* inform ME that we are leaving */
 478                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 479                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 480                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 481                 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
 482                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 483                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 484                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 485                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 486                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 487                         mdelay(1);
 488                         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 489                                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 490                 }
 491                 mdelay(5);
 492         }
 493
 494         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 495
 496         /* Stop device's DMA activity */
 497         iwl_pcie_apm_stop_master(trans);
 498
 499         if (trans->cfg->lp_xtal_workaround) {
 500                 iwl_pcie_apm_lp_xtal_enable(trans);
 501                 return;
 502         }
 503
 504         /* Reset the entire device */
 505         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 506
 507         udelay(10);
 508
 509         /*
 510          * Clear "initialization complete" bit to move adapter from
 511          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 512          */
 513         iwl_clear_bit(trans, CSR_GP_CNTRL,
 514                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 515 }
 516
 517 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 518 {
 519         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 520
 521         /* nic_init */
 522         spin_lock(&trans_pcie->irq_lock);
 523         iwl_pcie_apm_init(trans);
 524
 525         spin_unlock(&trans_pcie->irq_lock);
 526
 527         iwl_pcie_set_pwr(trans, false);
 528
 529         iwl_op_mode_nic_config(trans->op_mode);
 530
 531         /* Allocate the RX queue, or reset if it is already allocated */
 532         iwl_pcie_rx_init(trans);
 533
 534         /* Allocate or reset and init all Tx and Command queues */
 535         if (iwl_pcie_tx_init(trans))
 536                 return -ENOMEM;
 537
 538         if (trans->cfg->base_params->shadow_reg_enable) {
 539                 /* enable shadow regs in HW */
 540                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 541                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 542         }
 543
 544         return 0;
 545 }
 546
 547 #define HW_READY_TIMEOUT (50)
 548
 549 /* Note: returns poll_bit return value, which is >= 0 if success */
 550 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 551 {
 552         int ret;
 553
 554         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 555                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 556
 557         /* See if we got it */
 558         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 559                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 560                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 561                            HW_READY_TIMEOUT);
 562
 563         if (ret >= 0)
 564                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 565
 566         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 567         return ret;
 568 }
 569
 570 /* Note: returns standard 0/-ERROR code */
 571 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 572 {
 573         int ret;
 574         int t = 0;
 575         int iter;
 576
 577         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 578
 579         ret = iwl_pcie_set_hw_ready(trans);
 580         /* If the card is ready, exit 0 */
 581         if (ret >= 0)
 582                 return 0;
 583
 584         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 585                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 586         msleep(1);
 587
 588         for (iter = 0; iter < 10; iter++) {
 589                 /* If HW is not ready, prepare the conditions to check again */
 590                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 591                             CSR_HW_IF_CONFIG_REG_PREPARE);
 592
 593                 do {
 594                         ret = iwl_pcie_set_hw_ready(trans);
 595                         if (ret >= 0) {
 596                                 ret = 0;
 597                                 goto out;
 598                         }
 599
 600                         usleep_range(200, 1000);
 601                         t += 200;
 602                 } while (t < 150000);
 603                 msleep(25);
 604         }
 605
 606         IWL_ERR(trans, "Couldn't prepare the card\n");
 607
 608 out:
 609         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 610                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 611
 612         return ret;
 613 }
 614
 615 /*
 616  * ucode
 617  */
 618 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 619                                    dma_addr_t phy_addr, u32 byte_cnt)
 620 {
 621         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 622         int ret;
 623
 624         trans_pcie->ucode_write_complete = false;
 625
 626         iwl_write_direct32(trans,
 627                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 628                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 629
 630         iwl_write_direct32(trans,
 631                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 632                            dst_addr);
 633
 634         iwl_write_direct32(trans,
 635                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 636                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 637
 638         iwl_write_direct32(trans,
 639                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 640                            (iwl_get_dma_hi_addr(phy_addr)
 641                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 642
 643         iwl_write_direct32(trans,
 644                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 645                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 646                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 647                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 648
 649         iwl_write_direct32(trans,
 650                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 651                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 652                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 653                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 654
 655         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 656                                  trans_pcie->ucode_write_complete, 5 * HZ);
 657         if (!ret) {
 658                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 659                 return -ETIMEDOUT;
 660         }
 661
 662         return 0;
 663 }
 664
 665 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 666                             const struct fw_desc *section)
 667 {
 668         u8 *v_addr;
 669         dma_addr_t p_addr;
 670         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 671         int ret = 0;
 672
 673         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 674                      section_num);
 675
 676         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 677                                     GFP_KERNEL | __GFP_NOWARN);
 678         if (!v_addr) {
 679                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 680                 chunk_sz = PAGE_SIZE;
 681                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 682                                             &p_addr, GFP_KERNEL);
 683                 if (!v_addr)
 684                         return -ENOMEM;
 685         }
 686
 687         for (offset = 0; offset < section->len; offset += chunk_sz) {
 688                 u32 copy_size, dst_addr;
 689                 bool extended_addr = false;
 690
 691                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 692                 dst_addr = section->offset + offset;
 693
 694                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 695                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 696                         extended_addr = true;
 697
 698                 if (extended_addr)
 699                         iwl_set_bits_prph(trans, LMPM_CHICK,
 700                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 701
 702                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 703                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 704                                                    copy_size);
 705
 706                 if (extended_addr)
 707                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 708                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 709
 710                 if (ret) {
 711                         IWL_ERR(trans,
 712                                 "Could not load the [%d] uCode section\n",
 713                                 section_num);
 714                         break;
 715                 }
 716         }
 717
 718         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 719         return ret;
 720 }
 721
 722 /*
 723  * Driver Takes the ownership on secure machine before FW load
 724  * and prevent race with the BT load.
 725  * W/A for ROM bug. (should be remove in the next Si step)
 726  */
 727 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
 728 {
 729         u32 val, loop = 1000;
 730
 731         /*
 732          * Check the RSA semaphore is accessible.
 733          * If the HW isn't locked and the rsa semaphore isn't accessible,
 734          * we are in trouble.
 735          */
 736         val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
 737         if (val & (BIT(1) | BIT(17))) {
 738                 IWL_INFO(trans,
 739                          "can't access the RSA semaphore it is write protected\n");
 740                 return 0;
 741         }
 742
 743         /* take ownership on the AUX IF */
 744         iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
 745         iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
 746
 747         do {
 748                 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
 749                 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
 750                 if (val == 0x1) {
 751                         iwl_write_prph(trans, RSA_ENABLE, 0);
 752                         return 0;
 753                 }
 754
 755                 udelay(10);
 756                 loop--;
 757         } while (loop > 0);
 758
 759         IWL_ERR(trans, "Failed to take ownership on secure machine\n");
 760         return -EIO;
 761 }
 762
 763 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 764                                            const struct fw_img *image,
 765                                            int cpu,
 766                                            int *first_ucode_section)
 767 {
 768         int shift_param;
 769         int i, ret = 0, sec_num = 0x1;
 770         u32 val, last_read_idx = 0;
 771
 772         if (cpu == 1) {
 773                 shift_param = 0;
 774                 *first_ucode_section = 0;
 775         } else {
 776                 shift_param = 16;
 777                 (*first_ucode_section)++;
 778         }
 779
 780         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 781                 last_read_idx = i;
 782
 783                 if (!image->sec[i].data ||
 784                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 785                         IWL_DEBUG_FW(trans,
 786                                      "Break since Data not valid or Empty section, sec = %d\n",
 787                                      i);
 788                         break;
 789                 }
 790
 791                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 792                 if (ret)
 793                         return ret;
 794
 795                 /* Notify the ucode of the loaded section number and status */
 796                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 797                 val = val | (sec_num << shift_param);
 798                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 799                 sec_num = (sec_num << 1) | 0x1;
 800         }
 801
 802         *first_ucode_section = last_read_idx;
 803
 804         if (cpu == 1)
 805                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
 806         else
 807                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
 808
 809         return 0;
 810 }
 811
 812 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 813                                       const struct fw_img *image,
 814                                       int cpu,
 815                                       int *first_ucode_section)
 816 {
 817         int shift_param;
 818         int i, ret = 0;
 819         u32 last_read_idx = 0;
 820
 821         if (cpu == 1) {
 822                 shift_param = 0;
 823                 *first_ucode_section = 0;
 824         } else {
 825                 shift_param = 16;
 826                 (*first_ucode_section)++;
 827         }
 828
 829         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 830                 last_read_idx = i;
 831
 832                 if (!image->sec[i].data ||
 833                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 834                         IWL_DEBUG_FW(trans,
 835                                      "Break since Data not valid or Empty section, sec = %d\n",
 836                                      i);
 837                         break;
 838                 }
 839
 840                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 841                 if (ret)
 842                         return ret;
 843         }
 844
 845         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 846                 iwl_set_bits_prph(trans,
 847                                   CSR_UCODE_LOAD_STATUS_ADDR,
 848                                   (LMPM_CPU_UCODE_LOADING_COMPLETED |
 849                                    LMPM_CPU_HDRS_LOADING_COMPLETED |
 850                                    LMPM_CPU_UCODE_LOADING_STARTED) <<
 851                                         shift_param);
 852
 853         *first_ucode_section = last_read_idx;
 854
 855         return 0;
 856 }
 857
 858 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
 859 {
 860         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 861         const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
 862         int i;
 863
 864         if (dest->version)
 865                 IWL_ERR(trans,
 866                         "DBG DEST version is %d - expect issues\n",
 867                         dest->version);
 868
 869         IWL_INFO(trans, "Applying debug destination %s\n",
 870                  get_fw_dbg_mode_string(dest->monitor_mode));
 871
 872         if (dest->monitor_mode == EXTERNAL_MODE)
 873                 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
 874         else
 875                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 876
 877         for (i = 0; i < trans->dbg_dest_reg_num; i++) {
 878                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 879                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 880
 881                 switch (dest->reg_ops[i].op) {
 882                 case CSR_ASSIGN:
 883                         iwl_write32(trans, addr, val);
 884                         break;
 885                 case CSR_SETBIT:
 886                         iwl_set_bit(trans, addr, BIT(val));
 887                         break;
 888                 case CSR_CLEARBIT:
 889                         iwl_clear_bit(trans, addr, BIT(val));
 890                         break;
 891                 case PRPH_ASSIGN:
 892                         iwl_write_prph(trans, addr, val);
 893                         break;
 894                 case PRPH_SETBIT:
 895                         iwl_set_bits_prph(trans, addr, BIT(val));
 896                         break;
 897                 case PRPH_CLEARBIT:
 898                         iwl_clear_bits_prph(trans, addr, BIT(val));
 899                         break;
 900                 default:
 901                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 902                                 dest->reg_ops[i].op);
 903                         break;
 904                 }
 905         }
 906
 907         if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
 908                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 909                                trans_pcie->fw_mon_phys >> dest->base_shift);
 910                 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 911                                (trans_pcie->fw_mon_phys +
 912                                 trans_pcie->fw_mon_size) >> dest->end_shift);
 913         }
 914 }
 915
 916 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 917                                 const struct fw_img *image)
 918 {
 919         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 920         int ret = 0;
 921         int first_ucode_section;
 922
 923         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 924                      image->is_dual_cpus ? "Dual" : "Single");
 925
 926         /* load to FW the binary non secured sections of CPU1 */
 927         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
 928         if (ret)
 929                 return ret;
 930
 931         if (image->is_dual_cpus) {
 932                 /* set CPU2 header address */
 933                 iwl_write_prph(trans,
 934                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
 935                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
 936
 937                 /* load to FW the binary sections of CPU2 */
 938                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
 939                                                  &first_ucode_section);
 940                 if (ret)
 941                         return ret;
 942         }
 943
 944         /* supported for 7000 only for the moment */
 945         if (iwlwifi_mod_params.fw_monitor &&
 946             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
 947                 iwl_pcie_alloc_fw_monitor(trans, 0);
 948
 949                 if (trans_pcie->fw_mon_size) {
 950                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
 951                                        trans_pcie->fw_mon_phys >> 4);
 952                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
 953                                        (trans_pcie->fw_mon_phys +
 954                                         trans_pcie->fw_mon_size) >> 4);
 955                 }
 956         } else if (trans->dbg_dest_tlv) {
 957                 iwl_pcie_apply_destination(trans);
 958         }
 959
 960         /* release CPU reset */
 961         iwl_write32(trans, CSR_RESET, 0);
 962
 963         return 0;
 964 }
 965
 966 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
 967                                           const struct fw_img *image)
 968 {
 969         int ret = 0;
 970         int first_ucode_section;
 971
 972         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 973                      image->is_dual_cpus ? "Dual" : "Single");
 974
 975         if (trans->dbg_dest_tlv)
 976                 iwl_pcie_apply_destination(trans);
 977
 978         /* TODO: remove in the next Si step */
 979         ret = iwl_pcie_rsa_race_bug_wa(trans);
 980         if (ret)
 981                 return ret;
 982
 983         /* configure the ucode to be ready to get the secured image */
 984         /* release CPU reset */
 985         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
 986
 987         /* load to FW the binary Secured sections of CPU1 */
 988         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
 989                                               &first_ucode_section);
 990         if (ret)
 991                 return ret;
 992
 993         /* load to FW the binary sections of CPU2 */
 994         return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
 995                                                &first_ucode_section);
 996 }
 997
 998 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 999                                    const struct fw_img *fw, bool run_in_rfkill)
1000 {
1001         int ret;
1002         bool hw_rfkill;
1003
1004         /* This may fail if AMT took ownership of the device */
1005         if (iwl_pcie_prepare_card_hw(trans)) {
1006                 IWL_WARN(trans, "Exit HW not ready\n");
1007                 return -EIO;
1008         }
1009
1010         iwl_enable_rfkill_int(trans);
1011
1012         /* If platform's RF_KILL switch is NOT set to KILL */
1013         hw_rfkill = iwl_is_rfkill_set(trans);
1014         if (hw_rfkill)
1015                 set_bit(STATUS_RFKILL, &trans->status);
1016         else
1017                 clear_bit(STATUS_RFKILL, &trans->status);
1018         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1019         if (hw_rfkill && !run_in_rfkill)
1020                 return -ERFKILL;
1021
1022         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1023
1024         ret = iwl_pcie_nic_init(trans);
1025         if (ret) {
1026                 IWL_ERR(trans, "Unable to init nic\n");
1027                 return ret;
1028         }
1029
1030         /* make sure rfkill handshake bits are cleared */
1031         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1032         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1033                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1034
1035         /* clear (again), then enable host interrupts */
1036         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1037         iwl_enable_interrupts(trans);
1038
1039         /* really make sure rfkill handshake bits are cleared */
1040         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1041         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1042
1043         /* Load the given image to the HW */
1044         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1045                 return iwl_pcie_load_given_ucode_8000(trans, fw);
1046         else
1047                 return iwl_pcie_load_given_ucode(trans, fw);
1048 }
1049
1050 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1051 {
1052         iwl_pcie_reset_ict(trans);
1053         iwl_pcie_tx_start(trans, scd_addr);
1054 }
1055
1056 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1057 {
1058         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1059         bool hw_rfkill, was_hw_rfkill;
1060
1061         was_hw_rfkill = iwl_is_rfkill_set(trans);
1062
1063         /* tell the device to stop sending interrupts */
1064         spin_lock(&trans_pcie->irq_lock);
1065         iwl_disable_interrupts(trans);
1066         spin_unlock(&trans_pcie->irq_lock);
1067
1068         /* device going down, Stop using ICT table */
1069         iwl_pcie_disable_ict(trans);
1070
1071         /*
1072          * If a HW restart happens during firmware loading,
1073          * then the firmware loading might call this function
1074          * and later it might be called again due to the
1075          * restart. So don't process again if the device is
1076          * already dead.
1077          */
1078         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1079                 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
1080                 iwl_pcie_tx_stop(trans);
1081                 iwl_pcie_rx_stop(trans);
1082
1083                 /* Power-down device's busmaster DMA clocks */
1084                 if (!trans->cfg->apmg_not_supported) {
1085                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1086                                        APMG_CLK_VAL_DMA_CLK_RQT);
1087                         udelay(5);
1088                 }
1089         }
1090
1091         /* Make sure (redundant) we've released our request to stay awake */
1092         iwl_clear_bit(trans, CSR_GP_CNTRL,
1093                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1094
1095         /* Stop the device, and put it in low power state */
1096         iwl_pcie_apm_stop(trans, false);
1097
1098         /* stop and reset the on-board processor */
1099         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1100         udelay(20);
1101
1102         /*
1103          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1104          * This is a bug in certain verions of the hardware.
1105          * Certain devices also keep sending HW RF kill interrupt all
1106          * the time, unless the interrupt is ACKed even if the interrupt
1107          * should be masked. Re-ACK all the interrupts here.
1108          */
1109         spin_lock(&trans_pcie->irq_lock);
1110         iwl_disable_interrupts(trans);
1111         spin_unlock(&trans_pcie->irq_lock);
1112
1113
1114         /* clear all status bits */
1115         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1116         clear_bit(STATUS_INT_ENABLED, &trans->status);
1117         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1118         clear_bit(STATUS_RFKILL, &trans->status);
1119
1120         /*
1121          * Even if we stop the HW, we still want the RF kill
1122          * interrupt
1123          */
1124         iwl_enable_rfkill_int(trans);
1125
1126         /*
1127          * Check again since the RF kill state may have changed while
1128          * all the interrupts were disabled, in this case we couldn't
1129          * receive the RF kill interrupt and update the state in the
1130          * op_mode.
1131          * Don't call the op_mode if the rkfill state hasn't changed.
1132          * This allows the op_mode to call stop_device from the rfkill
1133          * notification without endless recursion. Under very rare
1134          * circumstances, we might have a small recursion if the rfkill
1135          * state changed exactly now while we were called from stop_device.
1136          * This is very unlikely but can happen and is supported.
1137          */
1138         hw_rfkill = iwl_is_rfkill_set(trans);
1139         if (hw_rfkill)
1140                 set_bit(STATUS_RFKILL, &trans->status);
1141         else
1142                 clear_bit(STATUS_RFKILL, &trans->status);
1143         if (hw_rfkill != was_hw_rfkill)
1144                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1145
1146         /* re-take ownership to prevent other users from stealing the deivce */
1147         iwl_pcie_prepare_card_hw(trans);
1148 }
1149
1150 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1151 {
1152         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1153                 iwl_trans_pcie_stop_device(trans, true);
1154 }
1155
1156 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
1157 {
1158         iwl_disable_interrupts(trans);
1159
1160         /*
1161          * in testing mode, the host stays awake and the
1162          * hardware won't be reset (not even partially)
1163          */
1164         if (test)
1165                 return;
1166
1167         iwl_pcie_disable_ict(trans);
1168
1169         iwl_clear_bit(trans, CSR_GP_CNTRL,
1170                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1171         iwl_clear_bit(trans, CSR_GP_CNTRL,
1172                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1173
1174         /*
1175          * reset TX queues -- some of their registers reset during S3
1176          * so if we don't reset everything here the D3 image would try
1177          * to execute some invalid memory upon resume
1178          */
1179         iwl_trans_pcie_tx_reset(trans);
1180
1181         iwl_pcie_set_pwr(trans, true);
1182 }
1183
1184 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1185                                     enum iwl_d3_status *status,
1186                                     bool test)
1187 {
1188         u32 val;
1189         int ret;
1190
1191         if (test) {
1192                 iwl_enable_interrupts(trans);
1193                 *status = IWL_D3_STATUS_ALIVE;
1194                 return 0;
1195         }
1196
1197         /*
1198          * Also enables interrupts - none will happen as the device doesn't
1199          * know we're waking it up, only when the opmode actually tells it
1200          * after this call.
1201          */
1202         iwl_pcie_reset_ict(trans);
1203
1204         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1205         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1206
1207         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1208                 udelay(2);
1209
1210         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1211                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1212                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1213                            25000);
1214         if (ret < 0) {
1215                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1216                 return ret;
1217         }
1218
1219         iwl_pcie_set_pwr(trans, false);
1220
1221         iwl_trans_pcie_tx_reset(trans);
1222
1223         ret = iwl_pcie_rx_init(trans);
1224         if (ret) {
1225                 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1226                 return ret;
1227         }
1228
1229         val = iwl_read32(trans, CSR_RESET);
1230         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1231                 *status = IWL_D3_STATUS_RESET;
1232         else
1233                 *status = IWL_D3_STATUS_ALIVE;
1234
1235         return 0;
1236 }
1237
1238 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1239 {
1240         bool hw_rfkill;
1241         int err;
1242
1243         err = iwl_pcie_prepare_card_hw(trans);
1244         if (err) {
1245                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1246                 return err;
1247         }
1248
1249         /* Reset the entire device */
1250         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1251
1252         usleep_range(10, 15);
1253
1254         iwl_pcie_apm_init(trans);
1255
1256         /* From now on, the op_mode will be kept updated about RF kill state */
1257         iwl_enable_rfkill_int(trans);
1258
1259         hw_rfkill = iwl_is_rfkill_set(trans);
1260         if (hw_rfkill)
1261                 set_bit(STATUS_RFKILL, &trans->status);
1262         else
1263                 clear_bit(STATUS_RFKILL, &trans->status);
1264         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1265
1266         return 0;
1267 }
1268
1269 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1270 {
1271         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1272
1273         /* disable interrupts - don't enable HW RF kill interrupt */
1274         spin_lock(&trans_pcie->irq_lock);
1275         iwl_disable_interrupts(trans);
1276         spin_unlock(&trans_pcie->irq_lock);
1277
1278         iwl_pcie_apm_stop(trans, true);
1279
1280         spin_lock(&trans_pcie->irq_lock);
1281         iwl_disable_interrupts(trans);
1282         spin_unlock(&trans_pcie->irq_lock);
1283
1284         iwl_pcie_disable_ict(trans);
1285 }
1286
1287 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1288 {
1289         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1290 }
1291
1292 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1293 {
1294         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1295 }
1296
1297 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1298 {
1299         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1300 }
1301
1302 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1303 {
1304         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1305                                ((reg & 0x000FFFFF) | (3 << 24)));
1306         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1307 }
1308
1309 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1310                                       u32 val)
1311 {
1312         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1313                                ((addr & 0x000FFFFF) | (3 << 24)));
1314         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1315 }
1316
1317 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1318 {
1319         WARN_ON(1);
1320         return 0;
1321 }
1322
1323 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1324                                      const struct iwl_trans_config *trans_cfg)
1325 {
1326         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1327
1328         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1329         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1330         trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1331         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1332                 trans_pcie->n_no_reclaim_cmds = 0;
1333         else
1334                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1335         if (trans_pcie->n_no_reclaim_cmds)
1336                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1337                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1338
1339         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1340         if (trans_pcie->rx_buf_size_8k)
1341                 trans_pcie->rx_page_order = get_order(8 * 1024);
1342         else
1343                 trans_pcie->rx_page_order = get_order(4 * 1024);
1344
1345         trans_pcie->command_names = trans_cfg->command_names;
1346         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1347         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1348
1349         /* init ref_count to 1 (should be cleared when ucode is loaded) */
1350         trans_pcie->ref_count = 1;
1351
1352         /* Initialize NAPI here - it should be before registering to mac80211
1353          * in the opmode but after the HW struct is allocated.
1354          * As this function may be called again in some corner cases don't
1355          * do anything if NAPI was already initialized.
1356          */
1357         if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1358                 init_dummy_netdev(&trans_pcie->napi_dev);
1359                 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1360                                      &trans_pcie->napi_dev,
1361                                      iwl_pcie_dummy_napi_poll, 64);
1362         }
1363 }
1364
1365 void iwl_trans_pcie_free(struct iwl_trans *trans)
1366 {
1367         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1368
1369         synchronize_irq(trans_pcie->pci_dev->irq);
1370
1371         iwl_pcie_tx_free(trans);
1372         iwl_pcie_rx_free(trans);
1373
1374         free_irq(trans_pcie->pci_dev->irq, trans);
1375         iwl_pcie_free_ict(trans);
1376
1377         pci_disable_msi(trans_pcie->pci_dev);
1378         iounmap(trans_pcie->hw_base);
1379         pci_release_regions(trans_pcie->pci_dev);
1380         pci_disable_device(trans_pcie->pci_dev);
1381
1382         if (trans_pcie->napi.poll)
1383                 netif_napi_del(&trans_pcie->napi);
1384
1385         iwl_pcie_free_fw_monitor(trans);
1386
1387         iwl_trans_free(trans);
1388 }
1389
1390 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1391 {
1392         if (state)
1393                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1394         else
1395                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1396 }
1397
1398 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1399                                                 unsigned long *flags)
1400 {
1401         int ret;
1402         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1403
1404         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1405
1406         if (trans_pcie->cmd_hold_nic_awake)
1407                 goto out;
1408
1409         /* this bit wakes up the NIC */
1410         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1411                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1412         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1413                 udelay(2);
1414
1415         /*
1416          * These bits say the device is running, and should keep running for
1417          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1418          * but they do not indicate that embedded SRAM is restored yet;
1419          * 3945 and 4965 have volatile SRAM, and must save/restore contents
1420          * to/from host DRAM when sleeping/waking for power-saving.
1421          * Each direction takes approximately 1/4 millisecond; with this
1422          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1423          * series of register accesses are expected (e.g. reading Event Log),
1424          * to keep device from sleeping.
1425          *
1426          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1427          * SRAM is okay/restored.  We don't check that here because this call
1428          * is just for hardware register access; but GP1 MAC_SLEEP check is a
1429          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1430          *
1431          * 5000 series and later (including 1000 series) have non-volatile SRAM,
1432          * and do not save/restore SRAM when power cycling.
1433          */
1434         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1435                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1436                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1437                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1438         if (unlikely(ret < 0)) {
1439                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1440                 if (!silent) {
1441                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1442                         WARN_ONCE(1,
1443                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1444                                   val);
1445                         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1446                         return false;
1447                 }
1448         }
1449
1450 out:
1451         /*
1452          * Fool sparse by faking we release the lock - sparse will
1453          * track nic_access anyway.
1454          */
1455         __release(&trans_pcie->reg_lock);
1456         return true;
1457 }
1458
1459 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1460                                               unsigned long *flags)
1461 {
1462         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1463
1464         lockdep_assert_held(&trans_pcie->reg_lock);
1465
1466         /*
1467          * Fool sparse by faking we acquiring the lock - sparse will
1468          * track nic_access anyway.
1469          */
1470         __acquire(&trans_pcie->reg_lock);
1471
1472         if (trans_pcie->cmd_hold_nic_awake)
1473                 goto out;
1474
1475         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1476                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1477         /*
1478          * Above we read the CSR_GP_CNTRL register, which will flush
1479          * any previous writes, but we need the write that clears the
1480          * MAC_ACCESS_REQ bit to be performed before any other writes
1481          * scheduled on different CPUs (after we drop reg_lock).
1482          */
1483         mmiowb();
1484 out:
1485         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1486 }
1487
1488 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1489                                    void *buf, int dwords)
1490 {
1491         unsigned long flags;
1492         int offs, ret = 0;
1493         u32 *vals = buf;
1494
1495         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1496                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1497                 for (offs = 0; offs < dwords; offs++)
1498                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1499                 iwl_trans_release_nic_access(trans, &flags);
1500         } else {
1501                 ret = -EBUSY;
1502         }
1503         return ret;
1504 }
1505
1506 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1507                                     const void *buf, int dwords)
1508 {
1509         unsigned long flags;
1510         int offs, ret = 0;
1511         const u32 *vals = buf;
1512
1513         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1514                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1515                 for (offs = 0; offs < dwords; offs++)
1516                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1517                                     vals ? vals[offs] : 0);
1518                 iwl_trans_release_nic_access(trans, &flags);
1519         } else {
1520                 ret = -EBUSY;
1521         }
1522         return ret;
1523 }
1524
1525 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1526                                             unsigned long txqs,
1527                                             bool freeze)
1528 {
1529         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1530         int queue;
1531
1532         for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1533                 struct iwl_txq *txq = &trans_pcie->txq[queue];
1534                 unsigned long now;
1535
1536                 spin_lock_bh(&txq->lock);
1537
1538                 now = jiffies;
1539
1540                 if (txq->frozen == freeze)
1541                         goto next_queue;
1542
1543                 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1544                                     freeze ? "Freezing" : "Waking", queue);
1545
1546                 txq->frozen = freeze;
1547
1548                 if (txq->q.read_ptr == txq->q.write_ptr)
1549                         goto next_queue;
1550
1551                 if (freeze) {
1552                         if (unlikely(time_after(now,
1553                                                 txq->stuck_timer.expires))) {
1554                                 /*
1555                                  * The timer should have fired, maybe it is
1556                                  * spinning right now on the lock.
1557                                  */
1558                                 goto next_queue;
1559                         }
1560                         /* remember how long until the timer fires */
1561                         txq->frozen_expiry_remainder =
1562                                 txq->stuck_timer.expires - now;
1563                         del_timer(&txq->stuck_timer);
1564                         goto next_queue;
1565                 }
1566
1567                 /*
1568                  * Wake a non-empty queue -> arm timer with the
1569                  * remainder before it froze
1570                  */
1571                 mod_timer(&txq->stuck_timer,
1572                           now + txq->frozen_expiry_remainder);
1573
1574 next_queue:
1575                 spin_unlock_bh(&txq->lock);
1576         }
1577 }
1578
1579 #define IWL_FLUSH_WAIT_MS       2000
1580
1581 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1582 {
1583         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1584         struct iwl_txq *txq;
1585         struct iwl_queue *q;
1586         int cnt;
1587         unsigned long now = jiffies;
1588         u32 scd_sram_addr;
1589         u8 buf[16];
1590         int ret = 0;
1591
1592         /* waiting for all the tx frames complete might take a while */
1593         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1594                 u8 wr_ptr;
1595
1596                 if (cnt == trans_pcie->cmd_queue)
1597                         continue;
1598                 if (!test_bit(cnt, trans_pcie->queue_used))
1599                         continue;
1600                 if (!(BIT(cnt) & txq_bm))
1601                         continue;
1602
1603                 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1604                 txq = &trans_pcie->txq[cnt];
1605                 q = &txq->q;
1606                 wr_ptr = ACCESS_ONCE(q->write_ptr);
1607
1608                 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1609                        !time_after(jiffies,
1610                                    now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1611                         u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1612
1613                         if (WARN_ONCE(wr_ptr != write_ptr,
1614                                       "WR pointer moved while flushing %d -> %d\n",
1615                                       wr_ptr, write_ptr))
1616                                 return -ETIMEDOUT;
1617                         msleep(1);
1618                 }
1619
1620                 if (q->read_ptr != q->write_ptr) {
1621                         IWL_ERR(trans,
1622                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1623                         ret = -ETIMEDOUT;
1624                         break;
1625                 }
1626                 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1627         }
1628
1629         if (!ret)
1630                 return 0;
1631
1632         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1633                 txq->q.read_ptr, txq->q.write_ptr);
1634
1635         scd_sram_addr = trans_pcie->scd_base_addr +
1636                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1637         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1638
1639         iwl_print_hex_error(trans, buf, sizeof(buf));
1640
1641         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1642                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1643                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1644
1645         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1646                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1647                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1648                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1649                 u32 tbl_dw =
1650                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1651                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1652
1653                 if (cnt & 0x1)
1654                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1655                 else
1656                         tbl_dw = tbl_dw & 0x0000FFFF;
1657
1658                 IWL_ERR(trans,
1659                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1660                         cnt, active ? "" : "in", fifo, tbl_dw,
1661                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1662                                 (TFD_QUEUE_SIZE_MAX - 1),
1663                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1664         }
1665
1666         return ret;
1667 }
1668
1669 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1670                                          u32 mask, u32 value)
1671 {
1672         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1673         unsigned long flags;
1674
1675         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1676         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1677         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1678 }
1679
1680 void iwl_trans_pcie_ref(struct iwl_trans *trans)
1681 {
1682         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1683         unsigned long flags;
1684
1685         if (iwlwifi_mod_params.d0i3_disable)
1686                 return;
1687
1688         spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1689         IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1690         trans_pcie->ref_count++;
1691         spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1692 }
1693
1694 void iwl_trans_pcie_unref(struct iwl_trans *trans)
1695 {
1696         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1697         unsigned long flags;
1698
1699         if (iwlwifi_mod_params.d0i3_disable)
1700                 return;
1701
1702         spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1703         IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1704         if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1705                 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1706                 return;
1707         }
1708         trans_pcie->ref_count--;
1709         spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1710 }
1711
1712 static const char *get_csr_string(int cmd)
1713 {
1714 #define IWL_CMD(x) case x: return #x
1715         switch (cmd) {
1716         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1717         IWL_CMD(CSR_INT_COALESCING);
1718         IWL_CMD(CSR_INT);
1719         IWL_CMD(CSR_INT_MASK);
1720         IWL_CMD(CSR_FH_INT_STATUS);
1721         IWL_CMD(CSR_GPIO_IN);
1722         IWL_CMD(CSR_RESET);
1723         IWL_CMD(CSR_GP_CNTRL);
1724         IWL_CMD(CSR_HW_REV);
1725         IWL_CMD(CSR_EEPROM_REG);
1726         IWL_CMD(CSR_EEPROM_GP);
1727         IWL_CMD(CSR_OTP_GP_REG);
1728         IWL_CMD(CSR_GIO_REG);
1729         IWL_CMD(CSR_GP_UCODE_REG);
1730         IWL_CMD(CSR_GP_DRIVER_REG);
1731         IWL_CMD(CSR_UCODE_DRV_GP1);
1732         IWL_CMD(CSR_UCODE_DRV_GP2);
1733         IWL_CMD(CSR_LED_REG);
1734         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1735         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1736         IWL_CMD(CSR_ANA_PLL_CFG);
1737         IWL_CMD(CSR_HW_REV_WA_REG);
1738         IWL_CMD(CSR_MONITOR_STATUS_REG);
1739         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1740         default:
1741                 return "UNKNOWN";
1742         }
1743 #undef IWL_CMD
1744 }
1745
1746 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1747 {
1748         int i;
1749         static const u32 csr_tbl[] = {
1750                 CSR_HW_IF_CONFIG_REG,
1751                 CSR_INT_COALESCING,
1752                 CSR_INT,
1753                 CSR_INT_MASK,
1754                 CSR_FH_INT_STATUS,
1755                 CSR_GPIO_IN,
1756                 CSR_RESET,
1757                 CSR_GP_CNTRL,
1758                 CSR_HW_REV,
1759                 CSR_EEPROM_REG,
1760                 CSR_EEPROM_GP,
1761                 CSR_OTP_GP_REG,
1762                 CSR_GIO_REG,
1763                 CSR_GP_UCODE_REG,
1764                 CSR_GP_DRIVER_REG,
1765                 CSR_UCODE_DRV_GP1,
1766                 CSR_UCODE_DRV_GP2,
1767                 CSR_LED_REG,
1768                 CSR_DRAM_INT_TBL_REG,
1769                 CSR_GIO_CHICKEN_BITS,
1770                 CSR_ANA_PLL_CFG,
1771                 CSR_MONITOR_STATUS_REG,
1772                 CSR_HW_REV_WA_REG,
1773                 CSR_DBG_HPET_MEM_REG
1774         };
1775         IWL_ERR(trans, "CSR values:\n");
1776         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1777                 "CSR_INT_PERIODIC_REG)\n");
1778         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1779                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1780                         get_csr_string(csr_tbl[i]),
1781                         iwl_read32(trans, csr_tbl[i]));
1782         }
1783 }
1784
1785 #ifdef CONFIG_IWLWIFI_DEBUGFS
1786 /* create and remove of files */
1787 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1788         if (!debugfs_create_file(#name, mode, parent, trans,            \
1789                                  &iwl_dbgfs_##name##_ops))              \
1790                 goto err;                                               \
1791 } while (0)
1792
1793 /* file operation */
1794 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1795 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1796         .read = iwl_dbgfs_##name##_read,                                \
1797         .open = simple_open,                                            \
1798         .llseek = generic_file_llseek,                                  \
1799 };
1800
1801 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1802 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1803         .write = iwl_dbgfs_##name##_write,                              \
1804         .open = simple_open,                                            \
1805         .llseek = generic_file_llseek,                                  \
1806 };
1807
1808 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1809 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1810         .write = iwl_dbgfs_##name##_write,                              \
1811         .read = iwl_dbgfs_##name##_read,                                \
1812         .open = simple_open,                                            \
1813         .llseek = generic_file_llseek,                                  \
1814 };
1815
1816 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1817                                        char __user *user_buf,
1818                                        size_t count, loff_t *ppos)
1819 {
1820         struct iwl_trans *trans = file->private_data;
1821         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1822         struct iwl_txq *txq;
1823         struct iwl_queue *q;
1824         char *buf;
1825         int pos = 0;
1826         int cnt;
1827         int ret;
1828         size_t bufsz;
1829
1830         bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
1831
1832         if (!trans_pcie->txq)
1833                 return -EAGAIN;
1834
1835         buf = kzalloc(bufsz, GFP_KERNEL);
1836         if (!buf)
1837                 return -ENOMEM;
1838
1839         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1840                 txq = &trans_pcie->txq[cnt];
1841                 q = &txq->q;
1842                 pos += scnprintf(buf + pos, bufsz - pos,
1843                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
1844                                 cnt, q->read_ptr, q->write_ptr,
1845                                 !!test_bit(cnt, trans_pcie->queue_used),
1846                                  !!test_bit(cnt, trans_pcie->queue_stopped),
1847                                  txq->need_update, txq->frozen,
1848                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
1849         }
1850         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1851         kfree(buf);
1852         return ret;
1853 }
1854
1855 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1856                                        char __user *user_buf,
1857                                        size_t count, loff_t *ppos)
1858 {
1859         struct iwl_trans *trans = file->private_data;
1860         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1861         struct iwl_rxq *rxq = &trans_pcie->rxq;
1862         char buf[256];
1863         int pos = 0;
1864         const size_t bufsz = sizeof(buf);
1865
1866         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1867                                                 rxq->read);
1868         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1869                                                 rxq->write);
1870         pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1871                                                 rxq->write_actual);
1872         pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1873                                                 rxq->need_update);
1874         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1875                                                 rxq->free_count);
1876         if (rxq->rb_stts) {
1877                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1878                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1879         } else {
1880                 pos += scnprintf(buf + pos, bufsz - pos,
1881                                         "closed_rb_num: Not Allocated\n");
1882         }
1883         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1884 }
1885
1886 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1887                                         char __user *user_buf,
1888                                         size_t count, loff_t *ppos)
1889 {
1890         struct iwl_trans *trans = file->private_data;
1891         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1892         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1893
1894         int pos = 0;
1895         char *buf;
1896         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1897         ssize_t ret;
1898
1899         buf = kzalloc(bufsz, GFP_KERNEL);
1900         if (!buf)
1901                 return -ENOMEM;
1902
1903         pos += scnprintf(buf + pos, bufsz - pos,
1904                         "Interrupt Statistics Report:\n");
1905
1906         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1907                 isr_stats->hw);
1908         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1909                 isr_stats->sw);
1910         if (isr_stats->sw || isr_stats->hw) {
1911                 pos += scnprintf(buf + pos, bufsz - pos,
1912                         "\tLast Restarting Code:  0x%X\n",
1913                         isr_stats->err_code);
1914         }
1915 #ifdef CONFIG_IWLWIFI_DEBUG
1916         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1917                 isr_stats->sch);
1918         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1919                 isr_stats->alive);
1920 #endif
1921         pos += scnprintf(buf + pos, bufsz - pos,
1922                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1923
1924         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1925                 isr_stats->ctkill);
1926
1927         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1928                 isr_stats->wakeup);
1929
1930         pos += scnprintf(buf + pos, bufsz - pos,
1931                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1932
1933         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1934                 isr_stats->tx);
1935
1936         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1937                 isr_stats->unhandled);
1938
1939         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1940         kfree(buf);
1941         return ret;
1942 }
1943
1944 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1945                                          const char __user *user_buf,
1946                                          size_t count, loff_t *ppos)
1947 {
1948         struct iwl_trans *trans = file->private_data;
1949         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1950         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1951
1952         char buf[8];
1953         int buf_size;
1954         u32 reset_flag;
1955
1956         memset(buf, 0, sizeof(buf));
1957         buf_size = min(count, sizeof(buf) -  1);
1958         if (copy_from_user(buf, user_buf, buf_size))
1959                 return -EFAULT;
1960         if (sscanf(buf, "%x", &reset_flag) != 1)
1961                 return -EFAULT;
1962         if (reset_flag == 0)
1963                 memset(isr_stats, 0, sizeof(*isr_stats));
1964
1965         return count;
1966 }
1967
1968 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1969                                    const char __user *user_buf,
1970                                    size_t count, loff_t *ppos)
1971 {
1972         struct iwl_trans *trans = file->private_data;
1973         char buf[8];
1974         int buf_size;
1975         int csr;
1976
1977         memset(buf, 0, sizeof(buf));
1978         buf_size = min(count, sizeof(buf) -  1);
1979         if (copy_from_user(buf, user_buf, buf_size))
1980                 return -EFAULT;
1981         if (sscanf(buf, "%d", &csr) != 1)
1982                 return -EFAULT;
1983
1984         iwl_pcie_dump_csr(trans);
1985
1986         return count;
1987 }
1988
1989 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1990                                      char __user *user_buf,
1991                                      size_t count, loff_t *ppos)
1992 {
1993         struct iwl_trans *trans = file->private_data;
1994         char *buf = NULL;
1995         ssize_t ret;
1996
1997         ret = iwl_dump_fh(trans, &buf);
1998         if (ret < 0)
1999                 return ret;
2000         if (!buf)
2001                 return -EINVAL;
2002         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2003         kfree(buf);
2004         return ret;
2005 }
2006
2007 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2008 DEBUGFS_READ_FILE_OPS(fh_reg);
2009 DEBUGFS_READ_FILE_OPS(rx_queue);
2010 DEBUGFS_READ_FILE_OPS(tx_queue);
2011 DEBUGFS_WRITE_FILE_OPS(csr);
2012
2013 /*
2014  * Create the debugfs files and directories
2015  *
2016  */
2017 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2018                                          struct dentry *dir)
2019 {
2020         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2021         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2022         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2023         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2024         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2025         return 0;
2026
2027 err:
2028         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2029         return -ENOMEM;
2030 }
2031 #else
2032 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2033                                          struct dentry *dir)
2034 {
2035         return 0;
2036 }
2037 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2038
2039 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2040 {
2041         u32 cmdlen = 0;
2042         int i;
2043
2044         for (i = 0; i < IWL_NUM_OF_TBS; i++)
2045                 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2046
2047         return cmdlen;
2048 }
2049
2050 static const struct {
2051         u32 start, end;
2052 } iwl_prph_dump_addr[] = {
2053         { .start = 0x00a00000, .end = 0x00a00000 },
2054         { .start = 0x00a0000c, .end = 0x00a00024 },
2055         { .start = 0x00a0002c, .end = 0x00a0003c },
2056         { .start = 0x00a00410, .end = 0x00a00418 },
2057         { .start = 0x00a00420, .end = 0x00a00420 },
2058         { .start = 0x00a00428, .end = 0x00a00428 },
2059         { .start = 0x00a00430, .end = 0x00a0043c },
2060         { .start = 0x00a00444, .end = 0x00a00444 },
2061         { .start = 0x00a004c0, .end = 0x00a004cc },
2062         { .start = 0x00a004d8, .end = 0x00a004d8 },
2063         { .start = 0x00a004e0, .end = 0x00a004f0 },
2064         { .start = 0x00a00840, .end = 0x00a00840 },
2065         { .start = 0x00a00850, .end = 0x00a00858 },
2066         { .start = 0x00a01004, .end = 0x00a01008 },
2067         { .start = 0x00a01010, .end = 0x00a01010 },
2068         { .start = 0x00a01018, .end = 0x00a01018 },
2069         { .start = 0x00a01024, .end = 0x00a01024 },
2070         { .start = 0x00a0102c, .end = 0x00a01034 },
2071         { .start = 0x00a0103c, .end = 0x00a01040 },
2072         { .start = 0x00a01048, .end = 0x00a01094 },
2073         { .start = 0x00a01c00, .end = 0x00a01c20 },
2074         { .start = 0x00a01c58, .end = 0x00a01c58 },
2075         { .start = 0x00a01c7c, .end = 0x00a01c7c },
2076         { .start = 0x00a01c28, .end = 0x00a01c54 },
2077         { .start = 0x00a01c5c, .end = 0x00a01c5c },
2078         { .start = 0x00a01c60, .end = 0x00a01cdc },
2079         { .start = 0x00a01ce0, .end = 0x00a01d0c },
2080         { .start = 0x00a01d18, .end = 0x00a01d20 },
2081         { .start = 0x00a01d2c, .end = 0x00a01d30 },
2082         { .start = 0x00a01d40, .end = 0x00a01d5c },
2083         { .start = 0x00a01d80, .end = 0x00a01d80 },
2084         { .start = 0x00a01d98, .end = 0x00a01d9c },
2085         { .start = 0x00a01da8, .end = 0x00a01da8 },
2086         { .start = 0x00a01db8, .end = 0x00a01df4 },
2087         { .start = 0x00a01dc0, .end = 0x00a01dfc },
2088         { .start = 0x00a01e00, .end = 0x00a01e2c },
2089         { .start = 0x00a01e40, .end = 0x00a01e60 },
2090         { .start = 0x00a01e68, .end = 0x00a01e6c },
2091         { .start = 0x00a01e74, .end = 0x00a01e74 },
2092         { .start = 0x00a01e84, .end = 0x00a01e90 },
2093         { .start = 0x00a01e9c, .end = 0x00a01ec4 },
2094         { .start = 0x00a01ed0, .end = 0x00a01ee0 },
2095         { .start = 0x00a01f00, .end = 0x00a01f1c },
2096         { .start = 0x00a01f44, .end = 0x00a01ffc },
2097         { .start = 0x00a02000, .end = 0x00a02048 },
2098         { .start = 0x00a02068, .end = 0x00a020f0 },
2099         { .start = 0x00a02100, .end = 0x00a02118 },
2100         { .start = 0x00a02140, .end = 0x00a0214c },
2101         { .start = 0x00a02168, .end = 0x00a0218c },
2102         { .start = 0x00a021c0, .end = 0x00a021c0 },
2103         { .start = 0x00a02400, .end = 0x00a02410 },
2104         { .start = 0x00a02418, .end = 0x00a02420 },
2105         { .start = 0x00a02428, .end = 0x00a0242c },
2106         { .start = 0x00a02434, .end = 0x00a02434 },
2107         { .start = 0x00a02440, .end = 0x00a02460 },
2108         { .start = 0x00a02468, .end = 0x00a024b0 },
2109         { .start = 0x00a024c8, .end = 0x00a024cc },
2110         { .start = 0x00a02500, .end = 0x00a02504 },
2111         { .start = 0x00a0250c, .end = 0x00a02510 },
2112         { .start = 0x00a02540, .end = 0x00a02554 },
2113         { .start = 0x00a02580, .end = 0x00a025f4 },
2114         { .start = 0x00a02600, .end = 0x00a0260c },
2115         { .start = 0x00a02648, .end = 0x00a02650 },
2116         { .start = 0x00a02680, .end = 0x00a02680 },
2117         { .start = 0x00a026c0, .end = 0x00a026d0 },
2118         { .start = 0x00a02700, .end = 0x00a0270c },
2119         { .start = 0x00a02804, .end = 0x00a02804 },
2120         { .start = 0x00a02818, .end = 0x00a0281c },
2121         { .start = 0x00a02c00, .end = 0x00a02db4 },
2122         { .start = 0x00a02df4, .end = 0x00a02fb0 },
2123         { .start = 0x00a03000, .end = 0x00a03014 },
2124         { .start = 0x00a0301c, .end = 0x00a0302c },
2125         { .start = 0x00a03034, .end = 0x00a03038 },
2126         { .start = 0x00a03040, .end = 0x00a03048 },
2127         { .start = 0x00a03060, .end = 0x00a03068 },
2128         { .start = 0x00a03070, .end = 0x00a03074 },
2129         { .start = 0x00a0307c, .end = 0x00a0307c },
2130         { .start = 0x00a03080, .end = 0x00a03084 },
2131         { .start = 0x00a0308c, .end = 0x00a03090 },
2132         { .start = 0x00a03098, .end = 0x00a03098 },
2133         { .start = 0x00a030a0, .end = 0x00a030a0 },
2134         { .start = 0x00a030a8, .end = 0x00a030b4 },
2135         { .start = 0x00a030bc, .end = 0x00a030bc },
2136         { .start = 0x00a030c0, .end = 0x00a0312c },
2137         { .start = 0x00a03c00, .end = 0x00a03c5c },
2138         { .start = 0x00a04400, .end = 0x00a04454 },
2139         { .start = 0x00a04460, .end = 0x00a04474 },
2140         { .start = 0x00a044c0, .end = 0x00a044ec },
2141         { .start = 0x00a04500, .end = 0x00a04504 },
2142         { .start = 0x00a04510, .end = 0x00a04538 },
2143         { .start = 0x00a04540, .end = 0x00a04548 },
2144         { .start = 0x00a04560, .end = 0x00a0457c },
2145         { .start = 0x00a04590, .end = 0x00a04598 },
2146         { .start = 0x00a045c0, .end = 0x00a045f4 },
2147 };
2148
2149 static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
2150                                     struct iwl_fw_error_dump_data **data)
2151 {
2152         struct iwl_fw_error_dump_prph *prph;
2153         unsigned long flags;
2154         u32 prph_len = 0, i;
2155
2156         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2157                 return 0;
2158
2159         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2160                 /* The range includes both boundaries */
2161                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2162                          iwl_prph_dump_addr[i].start + 4;
2163                 int reg;
2164                 __le32 *val;
2165
2166                 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
2167
2168                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
2169                 (*data)->len = cpu_to_le32(sizeof(*prph) +
2170                                         num_bytes_in_chunk);
2171                 prph = (void *)(*data)->data;
2172                 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
2173                 val = (void *)prph->data;
2174
2175                 for (reg = iwl_prph_dump_addr[i].start;
2176                      reg <= iwl_prph_dump_addr[i].end;
2177                      reg += 4)
2178                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2179                                                                       reg));
2180                 *data = iwl_fw_error_next_data(*data);
2181         }
2182
2183         iwl_trans_release_nic_access(trans, &flags);
2184
2185         return prph_len;
2186 }
2187
2188 #define IWL_CSR_TO_DUMP (0x250)
2189
2190 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2191                                    struct iwl_fw_error_dump_data **data)
2192 {
2193         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2194         __le32 *val;
2195         int i;
2196
2197         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2198         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2199         val = (void *)(*data)->data;
2200
2201         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2202                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2203
2204         *data = iwl_fw_error_next_data(*data);
2205
2206         return csr_len;
2207 }
2208
2209 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2210                                        struct iwl_fw_error_dump_data **data)
2211 {
2212         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2213         unsigned long flags;
2214         __le32 *val;
2215         int i;
2216
2217         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2218                 return 0;
2219
2220         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2221         (*data)->len = cpu_to_le32(fh_regs_len);
2222         val = (void *)(*data)->data;
2223
2224         for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2225                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2226
2227         iwl_trans_release_nic_access(trans, &flags);
2228
2229         *data = iwl_fw_error_next_data(*data);
2230
2231         return sizeof(**data) + fh_regs_len;
2232 }
2233
2234 static u32
2235 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2236                                  struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2237                                  u32 monitor_len)
2238 {
2239         u32 buf_size_in_dwords = (monitor_len >> 2);
2240         u32 *buffer = (u32 *)fw_mon_data->data;
2241         unsigned long flags;
2242         u32 i;
2243
2244         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2245                 return 0;
2246
2247         __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2248         for (i = 0; i < buf_size_in_dwords; i++)
2249                 buffer[i] = __iwl_read_prph(trans, MON_DMARB_RD_DATA_ADDR);
2250         __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2251
2252         iwl_trans_release_nic_access(trans, &flags);
2253
2254         return monitor_len;
2255 }
2256
2257 static
2258 struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
2259 {
2260         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2261         struct iwl_fw_error_dump_data *data;
2262         struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2263         struct iwl_fw_error_dump_txcmd *txcmd;
2264         struct iwl_trans_dump_data *dump_data;
2265         u32 len;
2266         u32 monitor_len;
2267         int i, ptr;
2268
2269         /* transport dump header */
2270         len = sizeof(*dump_data);
2271
2272         /* host commands */
2273         len += sizeof(*data) +
2274                 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2275
2276         /* CSR registers */
2277         len += sizeof(*data) + IWL_CSR_TO_DUMP;
2278
2279         /* PRPH registers */
2280         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2281                 /* The range includes both boundaries */
2282                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2283                         iwl_prph_dump_addr[i].start + 4;
2284
2285                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2286                         num_bytes_in_chunk;
2287         }
2288
2289         /* FH registers */
2290         len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2291
2292         /* FW monitor */
2293         if (trans_pcie->fw_mon_page) {
2294                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2295                        trans_pcie->fw_mon_size;
2296                 monitor_len = trans_pcie->fw_mon_size;
2297         } else if (trans->dbg_dest_tlv) {
2298                 u32 base, end;
2299
2300                 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2301                 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2302
2303                 base = iwl_read_prph(trans, base) <<
2304                        trans->dbg_dest_tlv->base_shift;
2305                 end = iwl_read_prph(trans, end) <<
2306                       trans->dbg_dest_tlv->end_shift;
2307
2308                 /* Make "end" point to the actual end */
2309                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2310                     trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2311                         end += (1 << trans->dbg_dest_tlv->end_shift);
2312                 monitor_len = end - base;
2313                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2314                        monitor_len;
2315         } else {
2316                 monitor_len = 0;
2317         }
2318
2319         dump_data = vzalloc(len);
2320         if (!dump_data)
2321                 return NULL;
2322
2323         len = 0;
2324         data = (void *)dump_data->data;
2325         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2326         txcmd = (void *)data->data;
2327         spin_lock_bh(&cmdq->lock);
2328         ptr = cmdq->q.write_ptr;
2329         for (i = 0; i < cmdq->q.n_window; i++) {
2330                 u8 idx = get_cmd_index(&cmdq->q, ptr);
2331                 u32 caplen, cmdlen;
2332
2333                 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2334                 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2335
2336                 if (cmdlen) {
2337                         len += sizeof(*txcmd) + caplen;
2338                         txcmd->cmdlen = cpu_to_le32(cmdlen);
2339                         txcmd->caplen = cpu_to_le32(caplen);
2340                         memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2341                         txcmd = (void *)((u8 *)txcmd->data + caplen);
2342                 }
2343
2344                 ptr = iwl_queue_dec_wrap(ptr);
2345         }
2346         spin_unlock_bh(&cmdq->lock);
2347
2348         data->len = cpu_to_le32(len);
2349         len += sizeof(*data);
2350         data = iwl_fw_error_next_data(data);
2351
2352         len += iwl_trans_pcie_dump_prph(trans, &data);
2353         len += iwl_trans_pcie_dump_csr(trans, &data);
2354         len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2355         /* data is already pointing to the next section */
2356
2357         if ((trans_pcie->fw_mon_page &&
2358              trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2359             trans->dbg_dest_tlv) {
2360                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2361                 u32 base, write_ptr, wrap_cnt;
2362
2363                 /* If there was a dest TLV - use the values from there */
2364                 if (trans->dbg_dest_tlv) {
2365                         write_ptr =
2366                                 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2367                         wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2368                         base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2369                 } else {
2370                         base = MON_BUFF_BASE_ADDR;
2371                         write_ptr = MON_BUFF_WRPTR;
2372                         wrap_cnt = MON_BUFF_CYCLE_CNT;
2373                 }
2374
2375                 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2376                 fw_mon_data = (void *)data->data;
2377                 fw_mon_data->fw_mon_wr_ptr =
2378                         cpu_to_le32(iwl_read_prph(trans, write_ptr));
2379                 fw_mon_data->fw_mon_cycle_cnt =
2380                         cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2381                 fw_mon_data->fw_mon_base_ptr =
2382                         cpu_to_le32(iwl_read_prph(trans, base));
2383
2384                 len += sizeof(*data) + sizeof(*fw_mon_data);
2385                 if (trans_pcie->fw_mon_page) {
2386                         /*
2387                          * The firmware is now asserted, it won't write anything
2388                          * to the buffer. CPU can take ownership to fetch the
2389                          * data. The buffer will be handed back to the device
2390                          * before the firmware will be restarted.
2391                          */
2392                         dma_sync_single_for_cpu(trans->dev,
2393                                                 trans_pcie->fw_mon_phys,
2394                                                 trans_pcie->fw_mon_size,
2395                                                 DMA_FROM_DEVICE);
2396                         memcpy(fw_mon_data->data,
2397                                page_address(trans_pcie->fw_mon_page),
2398                                trans_pcie->fw_mon_size);
2399
2400                         monitor_len = trans_pcie->fw_mon_size;
2401                 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2402                         /*
2403                          * Update pointers to reflect actual values after
2404                          * shifting
2405                          */
2406                         base = iwl_read_prph(trans, base) <<
2407                                trans->dbg_dest_tlv->base_shift;
2408                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
2409                                            monitor_len / sizeof(u32));
2410                 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2411                         monitor_len =
2412                                 iwl_trans_pci_dump_marbh_monitor(trans,
2413                                                                  fw_mon_data,
2414                                                                  monitor_len);
2415                 } else {
2416                         /* Didn't match anything - output no monitor data */
2417                         monitor_len = 0;
2418                 }
2419
2420                 len += monitor_len;
2421                 data->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2422         }
2423
2424         dump_data->len = len;
2425
2426         return dump_data;
2427 }
2428
2429 static const struct iwl_trans_ops trans_ops_pcie = {
2430         .start_hw = iwl_trans_pcie_start_hw,
2431         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2432         .fw_alive = iwl_trans_pcie_fw_alive,
2433         .start_fw = iwl_trans_pcie_start_fw,
2434         .stop_device = iwl_trans_pcie_stop_device,
2435
2436         .d3_suspend = iwl_trans_pcie_d3_suspend,
2437         .d3_resume = iwl_trans_pcie_d3_resume,
2438
2439         .send_cmd = iwl_trans_pcie_send_hcmd,
2440
2441         .tx = iwl_trans_pcie_tx,
2442         .reclaim = iwl_trans_pcie_reclaim,
2443
2444         .txq_disable = iwl_trans_pcie_txq_disable,
2445         .txq_enable = iwl_trans_pcie_txq_enable,
2446
2447         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2448
2449         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2450         .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2451
2452         .write8 = iwl_trans_pcie_write8,
2453         .write32 = iwl_trans_pcie_write32,
2454         .read32 = iwl_trans_pcie_read32,
2455         .read_prph = iwl_trans_pcie_read_prph,
2456         .write_prph = iwl_trans_pcie_write_prph,
2457         .read_mem = iwl_trans_pcie_read_mem,
2458         .write_mem = iwl_trans_pcie_write_mem,
2459         .configure = iwl_trans_pcie_configure,
2460         .set_pmi = iwl_trans_pcie_set_pmi,
2461         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2462         .release_nic_access = iwl_trans_pcie_release_nic_access,
2463         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2464
2465         .ref = iwl_trans_pcie_ref,
2466         .unref = iwl_trans_pcie_unref,
2467
2468         .dump_data = iwl_trans_pcie_dump_data,
2469 };
2470
2471 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2472                                        const struct pci_device_id *ent,
2473                                        const struct iwl_cfg *cfg)
2474 {
2475         struct iwl_trans_pcie *trans_pcie;
2476         struct iwl_trans *trans;
2477         u16 pci_cmd;
2478         int ret;
2479
2480         trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2481                                 &pdev->dev, cfg, &trans_ops_pcie, 0);
2482         if (!trans)
2483                 return ERR_PTR(-ENOMEM);
2484
2485         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2486
2487         trans_pcie->trans = trans;
2488         spin_lock_init(&trans_pcie->irq_lock);
2489         spin_lock_init(&trans_pcie->reg_lock);
2490         spin_lock_init(&trans_pcie->ref_lock);
2491         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2492
2493         ret = pci_enable_device(pdev);
2494         if (ret)
2495                 goto out_no_pci;
2496
2497         if (!cfg->base_params->pcie_l1_allowed) {
2498                 /*
2499                  * W/A - seems to solve weird behavior. We need to remove this
2500                  * if we don't want to stay in L1 all the time. This wastes a
2501                  * lot of power.
2502                  */
2503                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2504                                        PCIE_LINK_STATE_L1 |
2505                                        PCIE_LINK_STATE_CLKPM);
2506         }
2507
2508         pci_set_master(pdev);
2509
2510         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2511         if (!ret)
2512                 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2513         if (ret) {
2514                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2515                 if (!ret)
2516                         ret = pci_set_consistent_dma_mask(pdev,
2517                                                           DMA_BIT_MASK(32));
2518                 /* both attempts failed: */
2519                 if (ret) {
2520                         dev_err(&pdev->dev, "No suitable DMA available\n");
2521                         goto out_pci_disable_device;
2522                 }
2523         }
2524
2525         ret = pci_request_regions(pdev, DRV_NAME);
2526         if (ret) {
2527                 dev_err(&pdev->dev, "pci_request_regions failed\n");
2528                 goto out_pci_disable_device;
2529         }
2530
2531         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2532         if (!trans_pcie->hw_base) {
2533                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2534                 ret = -ENODEV;
2535                 goto out_pci_release_regions;
2536         }
2537
2538         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2539          * PCI Tx retries from interfering with C3 CPU state */
2540         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2541
2542         trans->dev = &pdev->dev;
2543         trans_pcie->pci_dev = pdev;
2544         iwl_disable_interrupts(trans);
2545
2546         ret = pci_enable_msi(pdev);
2547         if (ret) {
2548                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", ret);
2549                 /* enable rfkill interrupt: hw bug w/a */
2550                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2551                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2552                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2553                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2554                 }
2555         }
2556
2557         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2558         /*
2559          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2560          * changed, and now the revision step also includes bit 0-1 (no more
2561          * "dash" value). To keep hw_rev backwards compatible - we'll store it
2562          * in the old format.
2563          */
2564         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2565                 unsigned long flags;
2566
2567                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2568                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2569
2570                 ret = iwl_pcie_prepare_card_hw(trans);
2571                 if (ret) {
2572                         IWL_WARN(trans, "Exit HW not ready\n");
2573                         goto out_pci_disable_msi;
2574                 }
2575
2576                 /*
2577                  * in-order to recognize C step driver should read chip version
2578                  * id located at the AUX bus MISC address space.
2579                  */
2580                 iwl_set_bit(trans, CSR_GP_CNTRL,
2581                             CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2582                 udelay(2);
2583
2584                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2585                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2586                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2587                                    25000);
2588                 if (ret < 0) {
2589                         IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2590                         goto out_pci_disable_msi;
2591                 }
2592
2593                 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
2594                         u32 hw_step;
2595
2596                         hw_step = __iwl_read_prph(trans, WFPM_CTRL_REG);
2597                         hw_step |= ENABLE_WFPM;
2598                         __iwl_write_prph(trans, WFPM_CTRL_REG, hw_step);
2599                         hw_step = __iwl_read_prph(trans, AUX_MISC_REG);
2600                         hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2601                         if (hw_step == 0x3)
2602                                 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2603                                                 (SILICON_C_STEP << 2);
2604                         iwl_trans_release_nic_access(trans, &flags);
2605                 }
2606         }
2607
2608         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2609         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2610                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2611
2612         /* Initialize the wait queue for commands */
2613         init_waitqueue_head(&trans_pcie->wait_command_queue);
2614
2615         ret = iwl_pcie_alloc_ict(trans);
2616         if (ret)
2617                 goto out_pci_disable_msi;
2618
2619         ret = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2620                                    iwl_pcie_irq_handler,
2621                                    IRQF_SHARED, DRV_NAME, trans);
2622         if (ret) {
2623                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2624                 goto out_free_ict;
2625         }
2626
2627         trans_pcie->inta_mask = CSR_INI_SET_MASK;
2628         trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND;
2629
2630         return trans;
2631
2632 out_free_ict:
2633         iwl_pcie_free_ict(trans);
2634 out_pci_disable_msi:
2635         pci_disable_msi(pdev);
2636 out_pci_release_regions:
2637         pci_release_regions(pdev);
2638 out_pci_disable_device:
2639         pci_disable_device(pdev);
2640 out_no_pci:
2641         iwl_trans_free(trans);
2642         return ERR_PTR(ret);
2643 }