drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
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   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of version 2 of the GNU General Public License as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
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  34  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
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  43  *    notice, this list of conditions and the following disclaimer.
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  46  *    the documentation and/or other materials provided with the
  47  *    distribution.
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  49  *    contributors may be used to endorse or promote products derived
  50  *    from this software without specific prior written permission.
  51  *
  52  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  53  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  54  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  55  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  56  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  62  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  63  *
  64  *****************************************************************************/
  65 #include <linux/pci.h>
  66 #include <linux/pci-aspm.h>
  67 #include <linux/interrupt.h>
  68 #include <linux/debugfs.h>
  69 #include <linux/sched.h>
  70 #include <linux/bitops.h>
  71 #include <linux/gfp.h>
  72 #include <linux/vmalloc.h>
  73
  74 #include "iwl-drv.h"
  75 #include "iwl-trans.h"
  76 #include "iwl-csr.h"
  77 #include "iwl-prph.h"
  78 #include "iwl-agn-hw.h"
  79 #include "iwl-fw-error-dump.h"
  80 #include "internal.h"
  81
  82 /* extended range in FW SRAM */
  83 #define IWL_FW_MEM_EXTENDED_START       0x40000
  84 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  85
  86 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
  87 {
  88         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  89
  90         if (!trans_pcie->fw_mon_page)
  91                 return;
  92
  93         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
  94                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
  95         __free_pages(trans_pcie->fw_mon_page,
  96                      get_order(trans_pcie->fw_mon_size));
  97         trans_pcie->fw_mon_page = NULL;
  98         trans_pcie->fw_mon_phys = 0;
  99         trans_pcie->fw_mon_size = 0;
 100 }
 101
 102 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans)
 103 {
 104         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 105         struct page *page;
 106         dma_addr_t phys;
 107         u32 size;
 108         u8 power;
 109
 110         if (trans_pcie->fw_mon_page) {
 111                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 112                                            trans_pcie->fw_mon_size,
 113                                            DMA_FROM_DEVICE);
 114                 return;
 115         }
 116
 117         phys = 0;
 118         for (power = 26; power >= 11; power--) {
 119                 int order;
 120
 121                 size = BIT(power);
 122                 order = get_order(size);
 123                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 124                                    order);
 125                 if (!page)
 126                         continue;
 127
 128                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 129                                     DMA_FROM_DEVICE);
 130                 if (dma_mapping_error(trans->dev, phys)) {
 131                         __free_pages(page, order);
 132                         continue;
 133                 }
 134                 IWL_INFO(trans,
 135                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 136                          size, order);
 137                 break;
 138         }
 139
 140         if (WARN_ON_ONCE(!page))
 141                 return;
 142
 143         trans_pcie->fw_mon_page = page;
 144         trans_pcie->fw_mon_phys = phys;
 145         trans_pcie->fw_mon_size = size;
 146 }
 147
 148 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 149 {
 150         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 151                     ((reg & 0x0000ffff) | (2 << 28)));
 152         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 153 }
 154
 155 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 156 {
 157         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 158         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 159                     ((reg & 0x0000ffff) | (3 << 28)));
 160 }
 161
 162 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 163 {
 164         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 165                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 166                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 167                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 168         else
 169                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 170                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 171                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 172 }
 173
 174 /* PCI registers */
 175 #define PCI_CFG_RETRY_TIMEOUT   0x041
 176
 177 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 178 {
 179         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 180         u16 lctl;
 181         u16 cap;
 182
 183         /*
 184          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 185          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 186          * If so (likely), disable L0S, so device moves directly L0->L1;
 187          *    costs negligible amount of power savings.
 188          * If not (unlikely), enable L0S, so there is at least some
 189          *    power savings, even without L1.
 190          */
 191         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 192         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 193                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 194         else
 195                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 196         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 197
 198         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 199         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 200         dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
 201                  (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 202                  trans->ltr_enabled ? "En" : "Dis");
 203 }
 204
 205 /*
 206  * Start up NIC's basic functionality after it has been reset
 207  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 208  * NOTE:  This does not load uCode nor start the embedded processor
 209  */
 210 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 211 {
 212         int ret = 0;
 213         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 214
 215         /*
 216          * Use "set_bit" below rather than "write", to preserve any hardware
 217          * bits already set by default after reset.
 218          */
 219
 220         /* Disable L0S exit timer (platform NMI Work/Around) */
 221         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 222                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 223                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 224
 225         /*
 226          * Disable L0s without affecting L1;
 227          *  don't wait for ICH L0s (ICH bug W/A)
 228          */
 229         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 230                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 231
 232         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 233         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 234
 235         /*
 236          * Enable HAP INTA (interrupt from management bus) to
 237          * wake device's PCI Express link L1a -> L0s
 238          */
 239         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 240                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 241
 242         iwl_pcie_apm_config(trans);
 243
 244         /* Configure analog phase-lock-loop before activating to D0A */
 245         if (trans->cfg->base_params->pll_cfg_val)
 246                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 247                             trans->cfg->base_params->pll_cfg_val);
 248
 249         /*
 250          * Set "initialization complete" bit to move adapter from
 251          * D0U* --> D0A* (powered-up active) state.
 252          */
 253         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 254
 255         /*
 256          * Wait for clock stabilization; once stabilized, access to
 257          * device-internal resources is supported, e.g. iwl_write_prph()
 258          * and accesses to uCode SRAM.
 259          */
 260         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 261                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 262                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 263         if (ret < 0) {
 264                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 265                 goto out;
 266         }
 267
 268         if (trans->cfg->host_interrupt_operation_mode) {
 269                 /*
 270                  * This is a bit of an abuse - This is needed for 7260 / 3160
 271                  * only check host_interrupt_operation_mode even if this is
 272                  * not related to host_interrupt_operation_mode.
 273                  *
 274                  * Enable the oscillator to count wake up time for L1 exit. This
 275                  * consumes slightly more power (100uA) - but allows to be sure
 276                  * that we wake up from L1 on time.
 277                  *
 278                  * This looks weird: read twice the same register, discard the
 279                  * value, set a bit, and yet again, read that same register
 280                  * just to discard the value. But that's the way the hardware
 281                  * seems to like it.
 282                  */
 283                 iwl_read_prph(trans, OSC_CLK);
 284                 iwl_read_prph(trans, OSC_CLK);
 285                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 286                 iwl_read_prph(trans, OSC_CLK);
 287                 iwl_read_prph(trans, OSC_CLK);
 288         }
 289
 290         /*
 291          * Enable DMA clock and wait for it to stabilize.
 292          *
 293          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 294          * bits do not disable clocks.  This preserves any hardware
 295          * bits already set by default in "CLK_CTRL_REG" after reset.
 296          */
 297         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
 298                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 299                                APMG_CLK_VAL_DMA_CLK_RQT);
 300                 udelay(20);
 301
 302                 /* Disable L1-Active */
 303                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 304                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 305
 306                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 307                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 308                                APMG_RTC_INT_STT_RFKILL);
 309         }
 310
 311         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 312
 313 out:
 314         return ret;
 315 }
 316
 317 /*
 318  * Enable LP XTAL to avoid HW bug where device may consume much power if
 319  * FW is not loaded after device reset. LP XTAL is disabled by default
 320  * after device HW reset. Do it only if XTAL is fed by internal source.
 321  * Configure device's "persistence" mode to avoid resetting XTAL again when
 322  * SHRD_HW_RST occurs in S3.
 323  */
 324 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 325 {
 326         int ret;
 327         u32 apmg_gp1_reg;
 328         u32 apmg_xtal_cfg_reg;
 329         u32 dl_cfg_reg;
 330
 331         /* Force XTAL ON */
 332         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 333                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 334
 335         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 336         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 337
 338         udelay(10);
 339
 340         /*
 341          * Set "initialization complete" bit to move adapter from
 342          * D0U* --> D0A* (powered-up active) state.
 343          */
 344         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 345
 346         /*
 347          * Wait for clock stabilization; once stabilized, access to
 348          * device-internal resources is possible.
 349          */
 350         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 351                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 352                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 353                            25000);
 354         if (WARN_ON(ret < 0)) {
 355                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 356                 /* Release XTAL ON request */
 357                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 358                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 359                 return;
 360         }
 361
 362         /*
 363          * Clear "disable persistence" to avoid LP XTAL resetting when
 364          * SHRD_HW_RST is applied in S3.
 365          */
 366         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 367                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 368
 369         /*
 370          * Force APMG XTAL to be active to prevent its disabling by HW
 371          * caused by APMG idle state.
 372          */
 373         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 374                                                     SHR_APMG_XTAL_CFG_REG);
 375         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 376                                  apmg_xtal_cfg_reg |
 377                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 378
 379         /*
 380          * Reset entire device again - do controller reset (results in
 381          * SHRD_HW_RST). Turn MAC off before proceeding.
 382          */
 383         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 384
 385         udelay(10);
 386
 387         /* Enable LP XTAL by indirect access through CSR */
 388         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 389         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 390                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 391                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 392
 393         /* Clear delay line clock power up */
 394         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 395         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 396                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 397
 398         /*
 399          * Enable persistence mode to avoid LP XTAL resetting when
 400          * SHRD_HW_RST is applied in S3.
 401          */
 402         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 403                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 404
 405         /*
 406          * Clear "initialization complete" bit to move adapter from
 407          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 408          */
 409         iwl_clear_bit(trans, CSR_GP_CNTRL,
 410                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 411
 412         /* Activates XTAL resources monitor */
 413         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 414                                  CSR_MONITOR_XTAL_RESOURCES);
 415
 416         /* Release XTAL ON request */
 417         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 418                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 419         udelay(10);
 420
 421         /* Release APMG XTAL */
 422         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 423                                  apmg_xtal_cfg_reg &
 424                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 425 }
 426
 427 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 428 {
 429         int ret = 0;
 430
 431         /* stop device's busmaster DMA activity */
 432         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 433
 434         ret = iwl_poll_bit(trans, CSR_RESET,
 435                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 436                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 437         if (ret < 0)
 438                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 439
 440         IWL_DEBUG_INFO(trans, "stop master\n");
 441
 442         return ret;
 443 }
 444
 445 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
 446 {
 447         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 448
 449         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 450
 451         /* Stop device's DMA activity */
 452         iwl_pcie_apm_stop_master(trans);
 453
 454         if (trans->cfg->lp_xtal_workaround) {
 455                 iwl_pcie_apm_lp_xtal_enable(trans);
 456                 return;
 457         }
 458
 459         /* Reset the entire device */
 460         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 461
 462         udelay(10);
 463
 464         /*
 465          * Clear "initialization complete" bit to move adapter from
 466          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 467          */
 468         iwl_clear_bit(trans, CSR_GP_CNTRL,
 469                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 470 }
 471
 472 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 473 {
 474         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 475
 476         /* nic_init */
 477         spin_lock(&trans_pcie->irq_lock);
 478         iwl_pcie_apm_init(trans);
 479
 480         spin_unlock(&trans_pcie->irq_lock);
 481
 482         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 483                 iwl_pcie_set_pwr(trans, false);
 484
 485         iwl_op_mode_nic_config(trans->op_mode);
 486
 487         /* Allocate the RX queue, or reset if it is already allocated */
 488         iwl_pcie_rx_init(trans);
 489
 490         /* Allocate or reset and init all Tx and Command queues */
 491         if (iwl_pcie_tx_init(trans))
 492                 return -ENOMEM;
 493
 494         if (trans->cfg->base_params->shadow_reg_enable) {
 495                 /* enable shadow regs in HW */
 496                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 497                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 498         }
 499
 500         return 0;
 501 }
 502
 503 #define HW_READY_TIMEOUT (50)
 504
 505 /* Note: returns poll_bit return value, which is >= 0 if success */
 506 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 507 {
 508         int ret;
 509
 510         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 511                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 512
 513         /* See if we got it */
 514         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 515                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 516                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 517                            HW_READY_TIMEOUT);
 518
 519         if (ret >= 0)
 520                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 521
 522         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 523         return ret;
 524 }
 525
 526 /* Note: returns standard 0/-ERROR code */
 527 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 528 {
 529         int ret;
 530         int t = 0;
 531         int iter;
 532
 533         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 534
 535         ret = iwl_pcie_set_hw_ready(trans);
 536         /* If the card is ready, exit 0 */
 537         if (ret >= 0)
 538                 return 0;
 539
 540         for (iter = 0; iter < 10; iter++) {
 541                 /* If HW is not ready, prepare the conditions to check again */
 542                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 543                             CSR_HW_IF_CONFIG_REG_PREPARE);
 544
 545                 do {
 546                         ret = iwl_pcie_set_hw_ready(trans);
 547                         if (ret >= 0)
 548                                 return 0;
 549
 550                         usleep_range(200, 1000);
 551                         t += 200;
 552                 } while (t < 150000);
 553                 msleep(25);
 554         }
 555
 556         IWL_ERR(trans, "Couldn't prepare the card\n");
 557
 558         return ret;
 559 }
 560
 561 /*
 562  * ucode
 563  */
 564 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 565                                    dma_addr_t phy_addr, u32 byte_cnt)
 566 {
 567         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 568         int ret;
 569
 570         trans_pcie->ucode_write_complete = false;
 571
 572         iwl_write_direct32(trans,
 573                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 574                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 575
 576         iwl_write_direct32(trans,
 577                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 578                            dst_addr);
 579
 580         iwl_write_direct32(trans,
 581                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 582                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 583
 584         iwl_write_direct32(trans,
 585                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 586                            (iwl_get_dma_hi_addr(phy_addr)
 587                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 588
 589         iwl_write_direct32(trans,
 590                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 591                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 592                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 593                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 594
 595         iwl_write_direct32(trans,
 596                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 597                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 598                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 599                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 600
 601         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 602                                  trans_pcie->ucode_write_complete, 5 * HZ);
 603         if (!ret) {
 604                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 605                 return -ETIMEDOUT;
 606         }
 607
 608         return 0;
 609 }
 610
 611 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 612                             const struct fw_desc *section)
 613 {
 614         u8 *v_addr;
 615         dma_addr_t p_addr;
 616         u32 offset, chunk_sz = section->len;
 617         int ret = 0;
 618
 619         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 620                      section_num);
 621
 622         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 623                                     GFP_KERNEL | __GFP_NOWARN);
 624         if (!v_addr) {
 625                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 626                 chunk_sz = PAGE_SIZE;
 627                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 628                                             &p_addr, GFP_KERNEL);
 629                 if (!v_addr)
 630                         return -ENOMEM;
 631         }
 632
 633         for (offset = 0; offset < section->len; offset += chunk_sz) {
 634                 u32 copy_size, dst_addr;
 635                 bool extended_addr = false;
 636
 637                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 638                 dst_addr = section->offset + offset;
 639
 640                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 641                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 642                         extended_addr = true;
 643
 644                 if (extended_addr)
 645                         iwl_set_bits_prph(trans, LMPM_CHICK,
 646                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 647
 648                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 649                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 650                                                    copy_size);
 651
 652                 if (extended_addr)
 653                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 654                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 655
 656                 if (ret) {
 657                         IWL_ERR(trans,
 658                                 "Could not load the [%d] uCode section\n",
 659                                 section_num);
 660                         break;
 661                 }
 662         }
 663
 664         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 665         return ret;
 666 }
 667
 668 static int iwl_pcie_load_cpu_secured_sections(struct iwl_trans *trans,
 669                                               const struct fw_img *image,
 670                                               int cpu,
 671                                               int *first_ucode_section)
 672 {
 673         int shift_param;
 674         int i, ret = 0;
 675         u32 last_read_idx = 0;
 676
 677         if (cpu == 1) {
 678                 shift_param = 0;
 679                 *first_ucode_section = 0;
 680         } else {
 681                 shift_param = 16;
 682                 (*first_ucode_section)++;
 683         }
 684
 685         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 686                 last_read_idx = i;
 687
 688                 if (!image->sec[i].data ||
 689                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 690                         IWL_DEBUG_FW(trans,
 691                                      "Break since Data not valid or Empty section, sec = %d\n",
 692                                      i);
 693                         break;
 694                 }
 695
 696                 if (i == (*first_ucode_section) + 1)
 697                         /* set CPU to started */
 698                         iwl_set_bits_prph(trans,
 699                                           CSR_UCODE_LOAD_STATUS_ADDR,
 700                                           LMPM_CPU_HDRS_LOADING_COMPLETED
 701                                           << shift_param);
 702
 703                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 704                 if (ret)
 705                         return ret;
 706         }
 707         /* image loading complete */
 708         iwl_set_bits_prph(trans,
 709                           CSR_UCODE_LOAD_STATUS_ADDR,
 710                           LMPM_CPU_UCODE_LOADING_COMPLETED << shift_param);
 711
 712         *first_ucode_section = last_read_idx;
 713
 714         return 0;
 715 }
 716
 717 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 718                                       const struct fw_img *image,
 719                                       int cpu,
 720                                       int *first_ucode_section)
 721 {
 722         int shift_param;
 723         int i, ret = 0;
 724         u32 last_read_idx = 0;
 725
 726         if (cpu == 1) {
 727                 shift_param = 0;
 728                 *first_ucode_section = 0;
 729         } else {
 730                 shift_param = 16;
 731                 (*first_ucode_section)++;
 732         }
 733
 734         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 735                 last_read_idx = i;
 736
 737                 if (!image->sec[i].data ||
 738                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 739                         IWL_DEBUG_FW(trans,
 740                                      "Break since Data not valid or Empty section, sec = %d\n",
 741                                      i);
 742                         break;
 743                 }
 744
 745                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 746                 if (ret)
 747                         return ret;
 748         }
 749
 750         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 751                 iwl_set_bits_prph(trans,
 752                                   CSR_UCODE_LOAD_STATUS_ADDR,
 753                                   (LMPM_CPU_UCODE_LOADING_COMPLETED |
 754                                    LMPM_CPU_HDRS_LOADING_COMPLETED |
 755                                    LMPM_CPU_UCODE_LOADING_STARTED) <<
 756                                         shift_param);
 757
 758         *first_ucode_section = last_read_idx;
 759
 760         return 0;
 761 }
 762
 763 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 764                                 const struct fw_img *image)
 765 {
 766         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 767         int ret = 0;
 768         int first_ucode_section;
 769
 770         IWL_DEBUG_FW(trans,
 771                      "working with %s CPU\n",
 772                      image->is_dual_cpus ? "Dual" : "Single");
 773
 774         /* configure the ucode to be ready to get the secured image */
 775         if (iwl_has_secure_boot(trans->hw_rev, trans->cfg->device_family)) {
 776                 /* set secure boot inspector addresses */
 777                 iwl_write_prph(trans,
 778                                LMPM_SECURE_INSPECTOR_CODE_ADDR,
 779                                LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE);
 780
 781                 iwl_write_prph(trans,
 782                                LMPM_SECURE_INSPECTOR_DATA_ADDR,
 783                                LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE);
 784
 785                 /* set CPU1 header address */
 786                 iwl_write_prph(trans,
 787                                LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR,
 788                                LMPM_SECURE_CPU1_HDR_MEM_SPACE);
 789
 790                 /* load to FW the binary Secured sections of CPU1 */
 791                 ret = iwl_pcie_load_cpu_secured_sections(trans, image, 1,
 792                                                          &first_ucode_section);
 793                 if (ret)
 794                         return ret;
 795
 796         } else {
 797                 /* load to FW the binary Non secured sections of CPU1 */
 798                 ret = iwl_pcie_load_cpu_sections(trans, image, 1,
 799                                                  &first_ucode_section);
 800                 if (ret)
 801                         return ret;
 802         }
 803
 804         if (image->is_dual_cpus) {
 805                 /* set CPU2 header address */
 806                 iwl_write_prph(trans,
 807                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
 808                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
 809
 810                 /* load to FW the binary sections of CPU2 */
 811                 if (iwl_has_secure_boot(trans->hw_rev,
 812                                         trans->cfg->device_family))
 813                         ret = iwl_pcie_load_cpu_secured_sections(
 814                                                         trans, image, 2,
 815                                                         &first_ucode_section);
 816                 else
 817                         ret = iwl_pcie_load_cpu_sections(trans, image, 2,
 818                                                          &first_ucode_section);
 819                 if (ret)
 820                         return ret;
 821         }
 822
 823         /* supported for 7000 only for the moment */
 824         if (iwlwifi_mod_params.fw_monitor &&
 825             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
 826                 iwl_pcie_alloc_fw_monitor(trans);
 827
 828                 if (trans_pcie->fw_mon_size) {
 829                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
 830                                        trans_pcie->fw_mon_phys >> 4);
 831                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
 832                                        (trans_pcie->fw_mon_phys +
 833                                         trans_pcie->fw_mon_size) >> 4);
 834                 }
 835         }
 836
 837         /* release CPU reset */
 838         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 839                 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
 840         else
 841                 iwl_write32(trans, CSR_RESET, 0);
 842
 843         if (iwl_has_secure_boot(trans->hw_rev, trans->cfg->device_family)) {
 844                 /* wait for image verification to complete  */
 845                 ret = iwl_poll_prph_bit(trans,
 846                                         LMPM_SECURE_BOOT_CPU1_STATUS_ADDR,
 847                                         LMPM_SECURE_BOOT_STATUS_SUCCESS,
 848                                         LMPM_SECURE_BOOT_STATUS_SUCCESS,
 849                                         LMPM_SECURE_TIME_OUT);
 850
 851                 if (ret < 0) {
 852                         IWL_ERR(trans, "Time out on secure boot process\n");
 853                         return ret;
 854                 }
 855         }
 856
 857         return 0;
 858 }
 859
 860 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 861                                    const struct fw_img *fw, bool run_in_rfkill)
 862 {
 863         int ret;
 864         bool hw_rfkill;
 865
 866         /* This may fail if AMT took ownership of the device */
 867         if (iwl_pcie_prepare_card_hw(trans)) {
 868                 IWL_WARN(trans, "Exit HW not ready\n");
 869                 return -EIO;
 870         }
 871
 872         iwl_enable_rfkill_int(trans);
 873
 874         /* If platform's RF_KILL switch is NOT set to KILL */
 875         hw_rfkill = iwl_is_rfkill_set(trans);
 876         if (hw_rfkill)
 877                 set_bit(STATUS_RFKILL, &trans->status);
 878         else
 879                 clear_bit(STATUS_RFKILL, &trans->status);
 880         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
 881         if (hw_rfkill && !run_in_rfkill)
 882                 return -ERFKILL;
 883
 884         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 885
 886         ret = iwl_pcie_nic_init(trans);
 887         if (ret) {
 888                 IWL_ERR(trans, "Unable to init nic\n");
 889                 return ret;
 890         }
 891
 892         /* make sure rfkill handshake bits are cleared */
 893         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 894         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
 895                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 896
 897         /* clear (again), then enable host interrupts */
 898         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 899         iwl_enable_interrupts(trans);
 900
 901         /* really make sure rfkill handshake bits are cleared */
 902         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 903         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 904
 905         /* Load the given image to the HW */
 906         return iwl_pcie_load_given_ucode(trans, fw);
 907 }
 908
 909 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
 910 {
 911         iwl_pcie_reset_ict(trans);
 912         iwl_pcie_tx_start(trans, scd_addr);
 913 }
 914
 915 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 916 {
 917         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 918         bool hw_rfkill, was_hw_rfkill;
 919
 920         was_hw_rfkill = iwl_is_rfkill_set(trans);
 921
 922         /* tell the device to stop sending interrupts */
 923         spin_lock(&trans_pcie->irq_lock);
 924         iwl_disable_interrupts(trans);
 925         spin_unlock(&trans_pcie->irq_lock);
 926
 927         /* device going down, Stop using ICT table */
 928         iwl_pcie_disable_ict(trans);
 929
 930         /*
 931          * If a HW restart happens during firmware loading,
 932          * then the firmware loading might call this function
 933          * and later it might be called again due to the
 934          * restart. So don't process again if the device is
 935          * already dead.
 936          */
 937         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
 938                 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
 939                 iwl_pcie_tx_stop(trans);
 940                 iwl_pcie_rx_stop(trans);
 941
 942                 /* Power-down device's busmaster DMA clocks */
 943                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
 944                                APMG_CLK_VAL_DMA_CLK_RQT);
 945                 udelay(5);
 946         }
 947
 948         /* Make sure (redundant) we've released our request to stay awake */
 949         iwl_clear_bit(trans, CSR_GP_CNTRL,
 950                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 951
 952         /* Stop the device, and put it in low power state */
 953         iwl_pcie_apm_stop(trans);
 954
 955         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
 956          * Clean again the interrupt here
 957          */
 958         spin_lock(&trans_pcie->irq_lock);
 959         iwl_disable_interrupts(trans);
 960         spin_unlock(&trans_pcie->irq_lock);
 961
 962         /* stop and reset the on-board processor */
 963         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 964         udelay(20);
 965
 966         /* clear all status bits */
 967         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
 968         clear_bit(STATUS_INT_ENABLED, &trans->status);
 969         clear_bit(STATUS_TPOWER_PMI, &trans->status);
 970         clear_bit(STATUS_RFKILL, &trans->status);
 971
 972         /*
 973          * Even if we stop the HW, we still want the RF kill
 974          * interrupt
 975          */
 976         iwl_enable_rfkill_int(trans);
 977
 978         /*
 979          * Check again since the RF kill state may have changed while
 980          * all the interrupts were disabled, in this case we couldn't
 981          * receive the RF kill interrupt and update the state in the
 982          * op_mode.
 983          * Don't call the op_mode if the rkfill state hasn't changed.
 984          * This allows the op_mode to call stop_device from the rfkill
 985          * notification without endless recursion. Under very rare
 986          * circumstances, we might have a small recursion if the rfkill
 987          * state changed exactly now while we were called from stop_device.
 988          * This is very unlikely but can happen and is supported.
 989          */
 990         hw_rfkill = iwl_is_rfkill_set(trans);
 991         if (hw_rfkill)
 992                 set_bit(STATUS_RFKILL, &trans->status);
 993         else
 994                 clear_bit(STATUS_RFKILL, &trans->status);
 995         if (hw_rfkill != was_hw_rfkill)
 996                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
 997 }
 998
 999 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1000 {
1001         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1002                 iwl_trans_pcie_stop_device(trans);
1003 }
1004
1005 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
1006 {
1007         iwl_disable_interrupts(trans);
1008
1009         /*
1010          * in testing mode, the host stays awake and the
1011          * hardware won't be reset (not even partially)
1012          */
1013         if (test)
1014                 return;
1015
1016         iwl_pcie_disable_ict(trans);
1017
1018         iwl_clear_bit(trans, CSR_GP_CNTRL,
1019                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1020         iwl_clear_bit(trans, CSR_GP_CNTRL,
1021                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1022
1023         /*
1024          * reset TX queues -- some of their registers reset during S3
1025          * so if we don't reset everything here the D3 image would try
1026          * to execute some invalid memory upon resume
1027          */
1028         iwl_trans_pcie_tx_reset(trans);
1029
1030         iwl_pcie_set_pwr(trans, true);
1031 }
1032
1033 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1034                                     enum iwl_d3_status *status,
1035                                     bool test)
1036 {
1037         u32 val;
1038         int ret;
1039
1040         if (test) {
1041                 iwl_enable_interrupts(trans);
1042                 *status = IWL_D3_STATUS_ALIVE;
1043                 return 0;
1044         }
1045
1046         /*
1047          * Also enables interrupts - none will happen as the device doesn't
1048          * know we're waking it up, only when the opmode actually tells it
1049          * after this call.
1050          */
1051         iwl_pcie_reset_ict(trans);
1052
1053         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1054         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1055
1056         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1057                 udelay(2);
1058
1059         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1060                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1061                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1062                            25000);
1063         if (ret < 0) {
1064                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1065                 return ret;
1066         }
1067
1068         iwl_pcie_set_pwr(trans, false);
1069
1070         iwl_trans_pcie_tx_reset(trans);
1071
1072         ret = iwl_pcie_rx_init(trans);
1073         if (ret) {
1074                 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1075                 return ret;
1076         }
1077
1078         val = iwl_read32(trans, CSR_RESET);
1079         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1080                 *status = IWL_D3_STATUS_RESET;
1081         else
1082                 *status = IWL_D3_STATUS_ALIVE;
1083
1084         return 0;
1085 }
1086
1087 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1088 {
1089         bool hw_rfkill;
1090         int err;
1091
1092         err = iwl_pcie_prepare_card_hw(trans);
1093         if (err) {
1094                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1095                 return err;
1096         }
1097
1098         /* Reset the entire device */
1099         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1100
1101         usleep_range(10, 15);
1102
1103         iwl_pcie_apm_init(trans);
1104
1105         /* From now on, the op_mode will be kept updated about RF kill state */
1106         iwl_enable_rfkill_int(trans);
1107
1108         hw_rfkill = iwl_is_rfkill_set(trans);
1109         if (hw_rfkill)
1110                 set_bit(STATUS_RFKILL, &trans->status);
1111         else
1112                 clear_bit(STATUS_RFKILL, &trans->status);
1113         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1114
1115         return 0;
1116 }
1117
1118 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1119 {
1120         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1121
1122         /* disable interrupts - don't enable HW RF kill interrupt */
1123         spin_lock(&trans_pcie->irq_lock);
1124         iwl_disable_interrupts(trans);
1125         spin_unlock(&trans_pcie->irq_lock);
1126
1127         iwl_pcie_apm_stop(trans);
1128
1129         spin_lock(&trans_pcie->irq_lock);
1130         iwl_disable_interrupts(trans);
1131         spin_unlock(&trans_pcie->irq_lock);
1132
1133         iwl_pcie_disable_ict(trans);
1134 }
1135
1136 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1137 {
1138         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1139 }
1140
1141 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1142 {
1143         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1144 }
1145
1146 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1147 {
1148         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1149 }
1150
1151 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1152 {
1153         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1154                                ((reg & 0x000FFFFF) | (3 << 24)));
1155         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1156 }
1157
1158 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1159                                       u32 val)
1160 {
1161         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1162                                ((addr & 0x000FFFFF) | (3 << 24)));
1163         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1164 }
1165
1166 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1167 {
1168         WARN_ON(1);
1169         return 0;
1170 }
1171
1172 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1173                                      const struct iwl_trans_config *trans_cfg)
1174 {
1175         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1176
1177         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1178         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1179         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1180                 trans_pcie->n_no_reclaim_cmds = 0;
1181         else
1182                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1183         if (trans_pcie->n_no_reclaim_cmds)
1184                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1185                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1186
1187         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1188         if (trans_pcie->rx_buf_size_8k)
1189                 trans_pcie->rx_page_order = get_order(8 * 1024);
1190         else
1191                 trans_pcie->rx_page_order = get_order(4 * 1024);
1192
1193         trans_pcie->wd_timeout =
1194                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1195
1196         trans_pcie->command_names = trans_cfg->command_names;
1197         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1198         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1199
1200         /* Initialize NAPI here - it should be before registering to mac80211
1201          * in the opmode but after the HW struct is allocated.
1202          * As this function may be called again in some corner cases don't
1203          * do anything if NAPI was already initialized.
1204          */
1205         if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1206                 init_dummy_netdev(&trans_pcie->napi_dev);
1207                 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1208                                      &trans_pcie->napi_dev,
1209                                      iwl_pcie_dummy_napi_poll, 64);
1210         }
1211 }
1212
1213 void iwl_trans_pcie_free(struct iwl_trans *trans)
1214 {
1215         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1216
1217         synchronize_irq(trans_pcie->pci_dev->irq);
1218
1219         iwl_pcie_tx_free(trans);
1220         iwl_pcie_rx_free(trans);
1221
1222         free_irq(trans_pcie->pci_dev->irq, trans);
1223         iwl_pcie_free_ict(trans);
1224
1225         pci_disable_msi(trans_pcie->pci_dev);
1226         iounmap(trans_pcie->hw_base);
1227         pci_release_regions(trans_pcie->pci_dev);
1228         pci_disable_device(trans_pcie->pci_dev);
1229         kmem_cache_destroy(trans->dev_cmd_pool);
1230
1231         if (trans_pcie->napi.poll)
1232                 netif_napi_del(&trans_pcie->napi);
1233
1234         iwl_pcie_free_fw_monitor(trans);
1235
1236         kfree(trans);
1237 }
1238
1239 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1240 {
1241         if (state)
1242                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1243         else
1244                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1245 }
1246
1247 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1248                                                 unsigned long *flags)
1249 {
1250         int ret;
1251         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1252
1253         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1254
1255         if (trans_pcie->cmd_in_flight)
1256                 goto out;
1257
1258         /* this bit wakes up the NIC */
1259         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1260                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1261         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1262                 udelay(2);
1263
1264         /*
1265          * These bits say the device is running, and should keep running for
1266          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1267          * but they do not indicate that embedded SRAM is restored yet;
1268          * 3945 and 4965 have volatile SRAM, and must save/restore contents
1269          * to/from host DRAM when sleeping/waking for power-saving.
1270          * Each direction takes approximately 1/4 millisecond; with this
1271          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1272          * series of register accesses are expected (e.g. reading Event Log),
1273          * to keep device from sleeping.
1274          *
1275          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1276          * SRAM is okay/restored.  We don't check that here because this call
1277          * is just for hardware register access; but GP1 MAC_SLEEP check is a
1278          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1279          *
1280          * 5000 series and later (including 1000 series) have non-volatile SRAM,
1281          * and do not save/restore SRAM when power cycling.
1282          */
1283         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1284                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1285                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1286                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1287         if (unlikely(ret < 0)) {
1288                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1289                 if (!silent) {
1290                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1291                         WARN_ONCE(1,
1292                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1293                                   val);
1294                         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1295                         return false;
1296                 }
1297         }
1298
1299 out:
1300         /*
1301          * Fool sparse by faking we release the lock - sparse will
1302          * track nic_access anyway.
1303          */
1304         __release(&trans_pcie->reg_lock);
1305         return true;
1306 }
1307
1308 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1309                                               unsigned long *flags)
1310 {
1311         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1312
1313         lockdep_assert_held(&trans_pcie->reg_lock);
1314
1315         /*
1316          * Fool sparse by faking we acquiring the lock - sparse will
1317          * track nic_access anyway.
1318          */
1319         __acquire(&trans_pcie->reg_lock);
1320
1321         if (trans_pcie->cmd_in_flight)
1322                 goto out;
1323
1324         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1325                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1326         /*
1327          * Above we read the CSR_GP_CNTRL register, which will flush
1328          * any previous writes, but we need the write that clears the
1329          * MAC_ACCESS_REQ bit to be performed before any other writes
1330          * scheduled on different CPUs (after we drop reg_lock).
1331          */
1332         mmiowb();
1333 out:
1334         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1335 }
1336
1337 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1338                                    void *buf, int dwords)
1339 {
1340         unsigned long flags;
1341         int offs, ret = 0;
1342         u32 *vals = buf;
1343
1344         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1345                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1346                 for (offs = 0; offs < dwords; offs++)
1347                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1348                 iwl_trans_release_nic_access(trans, &flags);
1349         } else {
1350                 ret = -EBUSY;
1351         }
1352         return ret;
1353 }
1354
1355 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1356                                     const void *buf, int dwords)
1357 {
1358         unsigned long flags;
1359         int offs, ret = 0;
1360         const u32 *vals = buf;
1361
1362         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1363                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1364                 for (offs = 0; offs < dwords; offs++)
1365                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1366                                     vals ? vals[offs] : 0);
1367                 iwl_trans_release_nic_access(trans, &flags);
1368         } else {
1369                 ret = -EBUSY;
1370         }
1371         return ret;
1372 }
1373
1374 #define IWL_FLUSH_WAIT_MS       2000
1375
1376 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1377 {
1378         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1379         struct iwl_txq *txq;
1380         struct iwl_queue *q;
1381         int cnt;
1382         unsigned long now = jiffies;
1383         u32 scd_sram_addr;
1384         u8 buf[16];
1385         int ret = 0;
1386
1387         /* waiting for all the tx frames complete might take a while */
1388         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1389                 u8 wr_ptr;
1390
1391                 if (cnt == trans_pcie->cmd_queue)
1392                         continue;
1393                 if (!test_bit(cnt, trans_pcie->queue_used))
1394                         continue;
1395                 if (!(BIT(cnt) & txq_bm))
1396                         continue;
1397
1398                 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1399                 txq = &trans_pcie->txq[cnt];
1400                 q = &txq->q;
1401                 wr_ptr = ACCESS_ONCE(q->write_ptr);
1402
1403                 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1404                        !time_after(jiffies,
1405                                    now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1406                         u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1407
1408                         if (WARN_ONCE(wr_ptr != write_ptr,
1409                                       "WR pointer moved while flushing %d -> %d\n",
1410                                       wr_ptr, write_ptr))
1411                                 return -ETIMEDOUT;
1412                         msleep(1);
1413                 }
1414
1415                 if (q->read_ptr != q->write_ptr) {
1416                         IWL_ERR(trans,
1417                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1418                         ret = -ETIMEDOUT;
1419                         break;
1420                 }
1421                 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1422         }
1423
1424         if (!ret)
1425                 return 0;
1426
1427         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1428                 txq->q.read_ptr, txq->q.write_ptr);
1429
1430         scd_sram_addr = trans_pcie->scd_base_addr +
1431                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1432         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1433
1434         iwl_print_hex_error(trans, buf, sizeof(buf));
1435
1436         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1437                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1438                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1439
1440         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1441                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1442                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1443                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1444                 u32 tbl_dw =
1445                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1446                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1447
1448                 if (cnt & 0x1)
1449                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1450                 else
1451                         tbl_dw = tbl_dw & 0x0000FFFF;
1452
1453                 IWL_ERR(trans,
1454                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1455                         cnt, active ? "" : "in", fifo, tbl_dw,
1456                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1457                                 (TFD_QUEUE_SIZE_MAX - 1),
1458                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1459         }
1460
1461         return ret;
1462 }
1463
1464 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1465                                          u32 mask, u32 value)
1466 {
1467         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1468         unsigned long flags;
1469
1470         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1471         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1472         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1473 }
1474
1475 static const char *get_csr_string(int cmd)
1476 {
1477 #define IWL_CMD(x) case x: return #x
1478         switch (cmd) {
1479         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1480         IWL_CMD(CSR_INT_COALESCING);
1481         IWL_CMD(CSR_INT);
1482         IWL_CMD(CSR_INT_MASK);
1483         IWL_CMD(CSR_FH_INT_STATUS);
1484         IWL_CMD(CSR_GPIO_IN);
1485         IWL_CMD(CSR_RESET);
1486         IWL_CMD(CSR_GP_CNTRL);
1487         IWL_CMD(CSR_HW_REV);
1488         IWL_CMD(CSR_EEPROM_REG);
1489         IWL_CMD(CSR_EEPROM_GP);
1490         IWL_CMD(CSR_OTP_GP_REG);
1491         IWL_CMD(CSR_GIO_REG);
1492         IWL_CMD(CSR_GP_UCODE_REG);
1493         IWL_CMD(CSR_GP_DRIVER_REG);
1494         IWL_CMD(CSR_UCODE_DRV_GP1);
1495         IWL_CMD(CSR_UCODE_DRV_GP2);
1496         IWL_CMD(CSR_LED_REG);
1497         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1498         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1499         IWL_CMD(CSR_ANA_PLL_CFG);
1500         IWL_CMD(CSR_HW_REV_WA_REG);
1501         IWL_CMD(CSR_MONITOR_STATUS_REG);
1502         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1503         default:
1504                 return "UNKNOWN";
1505         }
1506 #undef IWL_CMD
1507 }
1508
1509 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1510 {
1511         int i;
1512         static const u32 csr_tbl[] = {
1513                 CSR_HW_IF_CONFIG_REG,
1514                 CSR_INT_COALESCING,
1515                 CSR_INT,
1516                 CSR_INT_MASK,
1517                 CSR_FH_INT_STATUS,
1518                 CSR_GPIO_IN,
1519                 CSR_RESET,
1520                 CSR_GP_CNTRL,
1521                 CSR_HW_REV,
1522                 CSR_EEPROM_REG,
1523                 CSR_EEPROM_GP,
1524                 CSR_OTP_GP_REG,
1525                 CSR_GIO_REG,
1526                 CSR_GP_UCODE_REG,
1527                 CSR_GP_DRIVER_REG,
1528                 CSR_UCODE_DRV_GP1,
1529                 CSR_UCODE_DRV_GP2,
1530                 CSR_LED_REG,
1531                 CSR_DRAM_INT_TBL_REG,
1532                 CSR_GIO_CHICKEN_BITS,
1533                 CSR_ANA_PLL_CFG,
1534                 CSR_MONITOR_STATUS_REG,
1535                 CSR_HW_REV_WA_REG,
1536                 CSR_DBG_HPET_MEM_REG
1537         };
1538         IWL_ERR(trans, "CSR values:\n");
1539         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1540                 "CSR_INT_PERIODIC_REG)\n");
1541         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1542                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1543                         get_csr_string(csr_tbl[i]),
1544                         iwl_read32(trans, csr_tbl[i]));
1545         }
1546 }
1547
1548 #ifdef CONFIG_IWLWIFI_DEBUGFS
1549 /* create and remove of files */
1550 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1551         if (!debugfs_create_file(#name, mode, parent, trans,            \
1552                                  &iwl_dbgfs_##name##_ops))              \
1553                 goto err;                                               \
1554 } while (0)
1555
1556 /* file operation */
1557 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1558 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1559         .read = iwl_dbgfs_##name##_read,                                \
1560         .open = simple_open,                                            \
1561         .llseek = generic_file_llseek,                                  \
1562 };
1563
1564 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1565 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1566         .write = iwl_dbgfs_##name##_write,                              \
1567         .open = simple_open,                                            \
1568         .llseek = generic_file_llseek,                                  \
1569 };
1570
1571 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1572 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1573         .write = iwl_dbgfs_##name##_write,                              \
1574         .read = iwl_dbgfs_##name##_read,                                \
1575         .open = simple_open,                                            \
1576         .llseek = generic_file_llseek,                                  \
1577 };
1578
1579 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1580                                        char __user *user_buf,
1581                                        size_t count, loff_t *ppos)
1582 {
1583         struct iwl_trans *trans = file->private_data;
1584         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1585         struct iwl_txq *txq;
1586         struct iwl_queue *q;
1587         char *buf;
1588         int pos = 0;
1589         int cnt;
1590         int ret;
1591         size_t bufsz;
1592
1593         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1594
1595         if (!trans_pcie->txq)
1596                 return -EAGAIN;
1597
1598         buf = kzalloc(bufsz, GFP_KERNEL);
1599         if (!buf)
1600                 return -ENOMEM;
1601
1602         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1603                 txq = &trans_pcie->txq[cnt];
1604                 q = &txq->q;
1605                 pos += scnprintf(buf + pos, bufsz - pos,
1606                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d%s\n",
1607                                 cnt, q->read_ptr, q->write_ptr,
1608                                 !!test_bit(cnt, trans_pcie->queue_used),
1609                                  !!test_bit(cnt, trans_pcie->queue_stopped),
1610                                  txq->need_update,
1611                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
1612         }
1613         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1614         kfree(buf);
1615         return ret;
1616 }
1617
1618 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1619                                        char __user *user_buf,
1620                                        size_t count, loff_t *ppos)
1621 {
1622         struct iwl_trans *trans = file->private_data;
1623         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1624         struct iwl_rxq *rxq = &trans_pcie->rxq;
1625         char buf[256];
1626         int pos = 0;
1627         const size_t bufsz = sizeof(buf);
1628
1629         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1630                                                 rxq->read);
1631         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1632                                                 rxq->write);
1633         pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1634                                                 rxq->write_actual);
1635         pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1636                                                 rxq->need_update);
1637         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1638                                                 rxq->free_count);
1639         if (rxq->rb_stts) {
1640                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1641                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1642         } else {
1643                 pos += scnprintf(buf + pos, bufsz - pos,
1644                                         "closed_rb_num: Not Allocated\n");
1645         }
1646         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1647 }
1648
1649 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1650                                         char __user *user_buf,
1651                                         size_t count, loff_t *ppos)
1652 {
1653         struct iwl_trans *trans = file->private_data;
1654         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1655         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1656
1657         int pos = 0;
1658         char *buf;
1659         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1660         ssize_t ret;
1661
1662         buf = kzalloc(bufsz, GFP_KERNEL);
1663         if (!buf)
1664                 return -ENOMEM;
1665
1666         pos += scnprintf(buf + pos, bufsz - pos,
1667                         "Interrupt Statistics Report:\n");
1668
1669         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1670                 isr_stats->hw);
1671         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1672                 isr_stats->sw);
1673         if (isr_stats->sw || isr_stats->hw) {
1674                 pos += scnprintf(buf + pos, bufsz - pos,
1675                         "\tLast Restarting Code:  0x%X\n",
1676                         isr_stats->err_code);
1677         }
1678 #ifdef CONFIG_IWLWIFI_DEBUG
1679         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1680                 isr_stats->sch);
1681         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1682                 isr_stats->alive);
1683 #endif
1684         pos += scnprintf(buf + pos, bufsz - pos,
1685                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1686
1687         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1688                 isr_stats->ctkill);
1689
1690         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1691                 isr_stats->wakeup);
1692
1693         pos += scnprintf(buf + pos, bufsz - pos,
1694                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1695
1696         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1697                 isr_stats->tx);
1698
1699         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1700                 isr_stats->unhandled);
1701
1702         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1703         kfree(buf);
1704         return ret;
1705 }
1706
1707 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1708                                          const char __user *user_buf,
1709                                          size_t count, loff_t *ppos)
1710 {
1711         struct iwl_trans *trans = file->private_data;
1712         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1713         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1714
1715         char buf[8];
1716         int buf_size;
1717         u32 reset_flag;
1718
1719         memset(buf, 0, sizeof(buf));
1720         buf_size = min(count, sizeof(buf) -  1);
1721         if (copy_from_user(buf, user_buf, buf_size))
1722                 return -EFAULT;
1723         if (sscanf(buf, "%x", &reset_flag) != 1)
1724                 return -EFAULT;
1725         if (reset_flag == 0)
1726                 memset(isr_stats, 0, sizeof(*isr_stats));
1727
1728         return count;
1729 }
1730
1731 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1732                                    const char __user *user_buf,
1733                                    size_t count, loff_t *ppos)
1734 {
1735         struct iwl_trans *trans = file->private_data;
1736         char buf[8];
1737         int buf_size;
1738         int csr;
1739
1740         memset(buf, 0, sizeof(buf));
1741         buf_size = min(count, sizeof(buf) -  1);
1742         if (copy_from_user(buf, user_buf, buf_size))
1743                 return -EFAULT;
1744         if (sscanf(buf, "%d", &csr) != 1)
1745                 return -EFAULT;
1746
1747         iwl_pcie_dump_csr(trans);
1748
1749         return count;
1750 }
1751
1752 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1753                                      char __user *user_buf,
1754                                      size_t count, loff_t *ppos)
1755 {
1756         struct iwl_trans *trans = file->private_data;
1757         char *buf = NULL;
1758         ssize_t ret;
1759
1760         ret = iwl_dump_fh(trans, &buf);
1761         if (ret < 0)
1762                 return ret;
1763         if (!buf)
1764                 return -EINVAL;
1765         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1766         kfree(buf);
1767         return ret;
1768 }
1769
1770 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1771 DEBUGFS_READ_FILE_OPS(fh_reg);
1772 DEBUGFS_READ_FILE_OPS(rx_queue);
1773 DEBUGFS_READ_FILE_OPS(tx_queue);
1774 DEBUGFS_WRITE_FILE_OPS(csr);
1775
1776 /*
1777  * Create the debugfs files and directories
1778  *
1779  */
1780 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1781                                          struct dentry *dir)
1782 {
1783         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1784         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1785         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1786         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1787         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1788         return 0;
1789
1790 err:
1791         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1792         return -ENOMEM;
1793 }
1794 #else
1795 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1796                                          struct dentry *dir)
1797 {
1798         return 0;
1799 }
1800 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1801
1802 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
1803 {
1804         u32 cmdlen = 0;
1805         int i;
1806
1807         for (i = 0; i < IWL_NUM_OF_TBS; i++)
1808                 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
1809
1810         return cmdlen;
1811 }
1812
1813 static const struct {
1814         u32 start, end;
1815 } iwl_prph_dump_addr[] = {
1816         { .start = 0x00a00000, .end = 0x00a00000 },
1817         { .start = 0x00a0000c, .end = 0x00a00024 },
1818         { .start = 0x00a0002c, .end = 0x00a0003c },
1819         { .start = 0x00a00410, .end = 0x00a00418 },
1820         { .start = 0x00a00420, .end = 0x00a00420 },
1821         { .start = 0x00a00428, .end = 0x00a00428 },
1822         { .start = 0x00a00430, .end = 0x00a0043c },
1823         { .start = 0x00a00444, .end = 0x00a00444 },
1824         { .start = 0x00a004c0, .end = 0x00a004cc },
1825         { .start = 0x00a004d8, .end = 0x00a004d8 },
1826         { .start = 0x00a004e0, .end = 0x00a004f0 },
1827         { .start = 0x00a00840, .end = 0x00a00840 },
1828         { .start = 0x00a00850, .end = 0x00a00858 },
1829         { .start = 0x00a01004, .end = 0x00a01008 },
1830         { .start = 0x00a01010, .end = 0x00a01010 },
1831         { .start = 0x00a01018, .end = 0x00a01018 },
1832         { .start = 0x00a01024, .end = 0x00a01024 },
1833         { .start = 0x00a0102c, .end = 0x00a01034 },
1834         { .start = 0x00a0103c, .end = 0x00a01040 },
1835         { .start = 0x00a01048, .end = 0x00a01094 },
1836         { .start = 0x00a01c00, .end = 0x00a01c20 },
1837         { .start = 0x00a01c58, .end = 0x00a01c58 },
1838         { .start = 0x00a01c7c, .end = 0x00a01c7c },
1839         { .start = 0x00a01c28, .end = 0x00a01c54 },
1840         { .start = 0x00a01c5c, .end = 0x00a01c5c },
1841         { .start = 0x00a01c84, .end = 0x00a01c84 },
1842         { .start = 0x00a01ce0, .end = 0x00a01d0c },
1843         { .start = 0x00a01d18, .end = 0x00a01d20 },
1844         { .start = 0x00a01d2c, .end = 0x00a01d30 },
1845         { .start = 0x00a01d40, .end = 0x00a01d5c },
1846         { .start = 0x00a01d80, .end = 0x00a01d80 },
1847         { .start = 0x00a01d98, .end = 0x00a01d98 },
1848         { .start = 0x00a01dc0, .end = 0x00a01dfc },
1849         { .start = 0x00a01e00, .end = 0x00a01e2c },
1850         { .start = 0x00a01e40, .end = 0x00a01e60 },
1851         { .start = 0x00a01e84, .end = 0x00a01e90 },
1852         { .start = 0x00a01e9c, .end = 0x00a01ec4 },
1853         { .start = 0x00a01ed0, .end = 0x00a01ed0 },
1854         { .start = 0x00a01f00, .end = 0x00a01f14 },
1855         { .start = 0x00a01f44, .end = 0x00a01f58 },
1856         { .start = 0x00a01f80, .end = 0x00a01fa8 },
1857         { .start = 0x00a01fb0, .end = 0x00a01fbc },
1858         { .start = 0x00a01ff8, .end = 0x00a01ffc },
1859         { .start = 0x00a02000, .end = 0x00a02048 },
1860         { .start = 0x00a02068, .end = 0x00a020f0 },
1861         { .start = 0x00a02100, .end = 0x00a02118 },
1862         { .start = 0x00a02140, .end = 0x00a0214c },
1863         { .start = 0x00a02168, .end = 0x00a0218c },
1864         { .start = 0x00a021c0, .end = 0x00a021c0 },
1865         { .start = 0x00a02400, .end = 0x00a02410 },
1866         { .start = 0x00a02418, .end = 0x00a02420 },
1867         { .start = 0x00a02428, .end = 0x00a0242c },
1868         { .start = 0x00a02434, .end = 0x00a02434 },
1869         { .start = 0x00a02440, .end = 0x00a02460 },
1870         { .start = 0x00a02468, .end = 0x00a024b0 },
1871         { .start = 0x00a024c8, .end = 0x00a024cc },
1872         { .start = 0x00a02500, .end = 0x00a02504 },
1873         { .start = 0x00a0250c, .end = 0x00a02510 },
1874         { .start = 0x00a02540, .end = 0x00a02554 },
1875         { .start = 0x00a02580, .end = 0x00a025f4 },
1876         { .start = 0x00a02600, .end = 0x00a0260c },
1877         { .start = 0x00a02648, .end = 0x00a02650 },
1878         { .start = 0x00a02680, .end = 0x00a02680 },
1879         { .start = 0x00a026c0, .end = 0x00a026d0 },
1880         { .start = 0x00a02700, .end = 0x00a0270c },
1881         { .start = 0x00a02804, .end = 0x00a02804 },
1882         { .start = 0x00a02818, .end = 0x00a0281c },
1883         { .start = 0x00a02c00, .end = 0x00a02db4 },
1884         { .start = 0x00a02df4, .end = 0x00a02fb0 },
1885         { .start = 0x00a03000, .end = 0x00a03014 },
1886         { .start = 0x00a0301c, .end = 0x00a0302c },
1887         { .start = 0x00a03034, .end = 0x00a03038 },
1888         { .start = 0x00a03040, .end = 0x00a03048 },
1889         { .start = 0x00a03060, .end = 0x00a03068 },
1890         { .start = 0x00a03070, .end = 0x00a03074 },
1891         { .start = 0x00a0307c, .end = 0x00a0307c },
1892         { .start = 0x00a03080, .end = 0x00a03084 },
1893         { .start = 0x00a0308c, .end = 0x00a03090 },
1894         { .start = 0x00a03098, .end = 0x00a03098 },
1895         { .start = 0x00a030a0, .end = 0x00a030a0 },
1896         { .start = 0x00a030a8, .end = 0x00a030b4 },
1897         { .start = 0x00a030bc, .end = 0x00a030bc },
1898         { .start = 0x00a030c0, .end = 0x00a0312c },
1899         { .start = 0x00a03c00, .end = 0x00a03c5c },
1900         { .start = 0x00a04400, .end = 0x00a04454 },
1901         { .start = 0x00a04460, .end = 0x00a04474 },
1902         { .start = 0x00a044c0, .end = 0x00a044ec },
1903         { .start = 0x00a04500, .end = 0x00a04504 },
1904         { .start = 0x00a04510, .end = 0x00a04538 },
1905         { .start = 0x00a04540, .end = 0x00a04548 },
1906         { .start = 0x00a04560, .end = 0x00a0457c },
1907         { .start = 0x00a04590, .end = 0x00a04598 },
1908         { .start = 0x00a045c0, .end = 0x00a045f4 },
1909 };
1910
1911 static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
1912                                     struct iwl_fw_error_dump_data **data)
1913 {
1914         struct iwl_fw_error_dump_prph *prph;
1915         unsigned long flags;
1916         u32 prph_len = 0, i;
1917
1918         if (!iwl_trans_grab_nic_access(trans, false, &flags))
1919                 return 0;
1920
1921         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
1922                 /* The range includes both boundaries */
1923                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
1924                          iwl_prph_dump_addr[i].start + 4;
1925                 int reg;
1926                 __le32 *val;
1927
1928                 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
1929
1930                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
1931                 (*data)->len = cpu_to_le32(sizeof(*prph) +
1932                                         num_bytes_in_chunk);
1933                 prph = (void *)(*data)->data;
1934                 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
1935                 val = (void *)prph->data;
1936
1937                 for (reg = iwl_prph_dump_addr[i].start;
1938                      reg <= iwl_prph_dump_addr[i].end;
1939                      reg += 4)
1940                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
1941                                                                       reg));
1942                 *data = iwl_fw_error_next_data(*data);
1943         }
1944
1945         iwl_trans_release_nic_access(trans, &flags);
1946
1947         return prph_len;
1948 }
1949
1950 #define IWL_CSR_TO_DUMP (0x250)
1951
1952 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
1953                                    struct iwl_fw_error_dump_data **data)
1954 {
1955         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
1956         __le32 *val;
1957         int i;
1958
1959         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
1960         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
1961         val = (void *)(*data)->data;
1962
1963         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
1964                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
1965
1966         *data = iwl_fw_error_next_data(*data);
1967
1968         return csr_len;
1969 }
1970
1971 static
1972 struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
1973 {
1974         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1975         struct iwl_fw_error_dump_data *data;
1976         struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
1977         struct iwl_fw_error_dump_txcmd *txcmd;
1978         struct iwl_trans_dump_data *dump_data;
1979         u32 len;
1980         int i, ptr;
1981
1982         /* transport dump header */
1983         len = sizeof(*dump_data);
1984
1985         /* host commands */
1986         len += sizeof(*data) +
1987                 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
1988
1989         /* CSR registers */
1990         len += sizeof(*data) + IWL_CSR_TO_DUMP;
1991
1992         /* PRPH registers */
1993         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
1994                 /* The range includes both boundaries */
1995                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
1996                         iwl_prph_dump_addr[i].start + 4;
1997
1998                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
1999                         num_bytes_in_chunk;
2000         }
2001
2002         /* FW monitor */
2003         if (trans_pcie->fw_mon_page)
2004                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2005                         trans_pcie->fw_mon_size;
2006
2007         dump_data = vzalloc(len);
2008         if (!dump_data)
2009                 return NULL;
2010
2011         len = 0;
2012         data = (void *)dump_data->data;
2013         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2014         txcmd = (void *)data->data;
2015         spin_lock_bh(&cmdq->lock);
2016         ptr = cmdq->q.write_ptr;
2017         for (i = 0; i < cmdq->q.n_window; i++) {
2018                 u8 idx = get_cmd_index(&cmdq->q, ptr);
2019                 u32 caplen, cmdlen;
2020
2021                 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2022                 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2023
2024                 if (cmdlen) {
2025                         len += sizeof(*txcmd) + caplen;
2026                         txcmd->cmdlen = cpu_to_le32(cmdlen);
2027                         txcmd->caplen = cpu_to_le32(caplen);
2028                         memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2029                         txcmd = (void *)((u8 *)txcmd->data + caplen);
2030                 }
2031
2032                 ptr = iwl_queue_dec_wrap(ptr);
2033         }
2034         spin_unlock_bh(&cmdq->lock);
2035
2036         data->len = cpu_to_le32(len);
2037         len += sizeof(*data);
2038         data = iwl_fw_error_next_data(data);
2039
2040         len += iwl_trans_pcie_dump_prph(trans, &data);
2041         len += iwl_trans_pcie_dump_csr(trans, &data);
2042         /* data is already pointing to the next section */
2043
2044         if (trans_pcie->fw_mon_page) {
2045                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2046
2047                 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2048                 data->len = cpu_to_le32(trans_pcie->fw_mon_size +
2049                                         sizeof(*fw_mon_data));
2050                 fw_mon_data = (void *)data->data;
2051                 fw_mon_data->fw_mon_wr_ptr =
2052                         cpu_to_le32(iwl_read_prph(trans, MON_BUFF_WRPTR));
2053                 fw_mon_data->fw_mon_cycle_cnt =
2054                         cpu_to_le32(iwl_read_prph(trans, MON_BUFF_CYCLE_CNT));
2055                 fw_mon_data->fw_mon_base_ptr =
2056                         cpu_to_le32(iwl_read_prph(trans, MON_BUFF_BASE_ADDR));
2057
2058                 /*
2059                  * The firmware is now asserted, it won't write anything to
2060                  * the buffer. CPU can take ownership to fetch the data.
2061                  * The buffer will be handed back to the device before the
2062                  * firmware will be restarted.
2063                  */
2064                 dma_sync_single_for_cpu(trans->dev, trans_pcie->fw_mon_phys,
2065                                         trans_pcie->fw_mon_size,
2066                                         DMA_FROM_DEVICE);
2067                 memcpy(fw_mon_data->data, page_address(trans_pcie->fw_mon_page),
2068                        trans_pcie->fw_mon_size);
2069
2070                 len += sizeof(*data) + sizeof(*fw_mon_data) +
2071                         trans_pcie->fw_mon_size;
2072         }
2073
2074         dump_data->len = len;
2075
2076         return dump_data;
2077 }
2078
2079 static const struct iwl_trans_ops trans_ops_pcie = {
2080         .start_hw = iwl_trans_pcie_start_hw,
2081         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2082         .fw_alive = iwl_trans_pcie_fw_alive,
2083         .start_fw = iwl_trans_pcie_start_fw,
2084         .stop_device = iwl_trans_pcie_stop_device,
2085
2086         .d3_suspend = iwl_trans_pcie_d3_suspend,
2087         .d3_resume = iwl_trans_pcie_d3_resume,
2088
2089         .send_cmd = iwl_trans_pcie_send_hcmd,
2090
2091         .tx = iwl_trans_pcie_tx,
2092         .reclaim = iwl_trans_pcie_reclaim,
2093
2094         .txq_disable = iwl_trans_pcie_txq_disable,
2095         .txq_enable = iwl_trans_pcie_txq_enable,
2096
2097         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2098
2099         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2100
2101         .write8 = iwl_trans_pcie_write8,
2102         .write32 = iwl_trans_pcie_write32,
2103         .read32 = iwl_trans_pcie_read32,
2104         .read_prph = iwl_trans_pcie_read_prph,
2105         .write_prph = iwl_trans_pcie_write_prph,
2106         .read_mem = iwl_trans_pcie_read_mem,
2107         .write_mem = iwl_trans_pcie_write_mem,
2108         .configure = iwl_trans_pcie_configure,
2109         .set_pmi = iwl_trans_pcie_set_pmi,
2110         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2111         .release_nic_access = iwl_trans_pcie_release_nic_access,
2112         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2113
2114         .dump_data = iwl_trans_pcie_dump_data,
2115 };
2116
2117 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2118                                        const struct pci_device_id *ent,
2119                                        const struct iwl_cfg *cfg)
2120 {
2121         struct iwl_trans_pcie *trans_pcie;
2122         struct iwl_trans *trans;
2123         u16 pci_cmd;
2124         int err;
2125
2126         trans = kzalloc(sizeof(struct iwl_trans) +
2127                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2128         if (!trans) {
2129                 err = -ENOMEM;
2130                 goto out;
2131         }
2132
2133         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2134
2135         trans->ops = &trans_ops_pcie;
2136         trans->cfg = cfg;
2137         trans_lockdep_init(trans);
2138         trans_pcie->trans = trans;
2139         spin_lock_init(&trans_pcie->irq_lock);
2140         spin_lock_init(&trans_pcie->reg_lock);
2141         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2142
2143         err = pci_enable_device(pdev);
2144         if (err)
2145                 goto out_no_pci;
2146
2147         if (!cfg->base_params->pcie_l1_allowed) {
2148                 /*
2149                  * W/A - seems to solve weird behavior. We need to remove this
2150                  * if we don't want to stay in L1 all the time. This wastes a
2151                  * lot of power.
2152                  */
2153                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2154                                        PCIE_LINK_STATE_L1 |
2155                                        PCIE_LINK_STATE_CLKPM);
2156         }
2157
2158         pci_set_master(pdev);
2159
2160         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2161         if (!err)
2162                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2163         if (err) {
2164                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2165                 if (!err)
2166                         err = pci_set_consistent_dma_mask(pdev,
2167                                                           DMA_BIT_MASK(32));
2168                 /* both attempts failed: */
2169                 if (err) {
2170                         dev_err(&pdev->dev, "No suitable DMA available\n");
2171                         goto out_pci_disable_device;
2172                 }
2173         }
2174
2175         err = pci_request_regions(pdev, DRV_NAME);
2176         if (err) {
2177                 dev_err(&pdev->dev, "pci_request_regions failed\n");
2178                 goto out_pci_disable_device;
2179         }
2180
2181         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2182         if (!trans_pcie->hw_base) {
2183                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2184                 err = -ENODEV;
2185                 goto out_pci_release_regions;
2186         }
2187
2188         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2189          * PCI Tx retries from interfering with C3 CPU state */
2190         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2191
2192         trans->dev = &pdev->dev;
2193         trans_pcie->pci_dev = pdev;
2194         iwl_disable_interrupts(trans);
2195
2196         err = pci_enable_msi(pdev);
2197         if (err) {
2198                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
2199                 /* enable rfkill interrupt: hw bug w/a */
2200                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2201                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2202                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2203                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2204                 }
2205         }
2206
2207         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2208         /*
2209          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2210          * changed, and now the revision step also includes bit 0-1 (no more
2211          * "dash" value). To keep hw_rev backwards compatible - we'll store it
2212          * in the old format.
2213          */
2214         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2215                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2216                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2217
2218         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2219         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2220                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2221
2222         /* Initialize the wait queue for commands */
2223         init_waitqueue_head(&trans_pcie->wait_command_queue);
2224
2225         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2226                  "iwl_cmd_pool:%s", dev_name(trans->dev));
2227
2228         trans->dev_cmd_headroom = 0;
2229         trans->dev_cmd_pool =
2230                 kmem_cache_create(trans->dev_cmd_pool_name,
2231                                   sizeof(struct iwl_device_cmd)
2232                                   + trans->dev_cmd_headroom,
2233                                   sizeof(void *),
2234                                   SLAB_HWCACHE_ALIGN,
2235                                   NULL);
2236
2237         if (!trans->dev_cmd_pool) {
2238                 err = -ENOMEM;
2239                 goto out_pci_disable_msi;
2240         }
2241
2242         if (iwl_pcie_alloc_ict(trans))
2243                 goto out_free_cmd_pool;
2244
2245         err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2246                                    iwl_pcie_irq_handler,
2247                                    IRQF_SHARED, DRV_NAME, trans);
2248         if (err) {
2249                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2250                 goto out_free_ict;
2251         }
2252
2253         trans_pcie->inta_mask = CSR_INI_SET_MASK;
2254
2255         return trans;
2256
2257 out_free_ict:
2258         iwl_pcie_free_ict(trans);
2259 out_free_cmd_pool:
2260         kmem_cache_destroy(trans->dev_cmd_pool);
2261 out_pci_disable_msi:
2262         pci_disable_msi(pdev);
2263 out_pci_release_regions:
2264         pci_release_regions(pdev);
2265 out_pci_disable_device:
2266         pci_disable_device(pdev);
2267 out_no_pci:
2268         kfree(trans);
2269 out:
2270         return ERR_PTR(err);
2271 }