drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of version 2 of the GNU General Public License as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  23  * USA
  24  *
  25  * The full GNU General Public License is included in this distribution
  26  * in the file called COPYING.
  27  *
  28  * Contact Information:
  29  *  Intel Linux Wireless <ilw@linux.intel.com>
  30  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  31  *
  32  * BSD LICENSE
  33  *
  34  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
  35  * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
  36  * All rights reserved.
  37  *
  38  * Redistribution and use in source and binary forms, with or without
  39  * modification, are permitted provided that the following conditions
  40  * are met:
  41  *
  42  *  * Redistributions of source code must retain the above copyright
  43  *    notice, this list of conditions and the following disclaimer.
  44  *  * Redistributions in binary form must reproduce the above copyright
  45  *    notice, this list of conditions and the following disclaimer in
  46  *    the documentation and/or other materials provided with the
  47  *    distribution.
  48  *  * Neither the name Intel Corporation nor the names of its
  49  *    contributors may be used to endorse or promote products derived
  50  *    from this software without specific prior written permission.
  51  *
  52  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  53  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  54  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  55  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  56  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  57  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  58  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  59  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  60  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  61  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  62  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  63  *
  64  *****************************************************************************/
  65 #include <linux/pci.h>
  66 #include <linux/pci-aspm.h>
  67 #include <linux/interrupt.h>
  68 #include <linux/debugfs.h>
  69 #include <linux/sched.h>
  70 #include <linux/bitops.h>
  71 #include <linux/gfp.h>
  72 #include <linux/vmalloc.h>
  73
  74 #include "iwl-drv.h"
  75 #include "iwl-trans.h"
  76 #include "iwl-csr.h"
  77 #include "iwl-prph.h"
  78 #include "iwl-agn-hw.h"
  79 #include "iwl-fw-error-dump.h"
  80 #include "internal.h"
  81 #include "iwl-fh.h"
  82
  83 /* extended range in FW SRAM */
  84 #define IWL_FW_MEM_EXTENDED_START       0x40000
  85 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  86
  87 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
  88 {
  89         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  90
  91         if (!trans_pcie->fw_mon_page)
  92                 return;
  93
  94         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
  95                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
  96         __free_pages(trans_pcie->fw_mon_page,
  97                      get_order(trans_pcie->fw_mon_size));
  98         trans_pcie->fw_mon_page = NULL;
  99         trans_pcie->fw_mon_phys = 0;
 100         trans_pcie->fw_mon_size = 0;
 101 }
 102
 103 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans)
 104 {
 105         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 106         struct page *page;
 107         dma_addr_t phys;
 108         u32 size;
 109         u8 power;
 110
 111         if (trans_pcie->fw_mon_page) {
 112                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 113                                            trans_pcie->fw_mon_size,
 114                                            DMA_FROM_DEVICE);
 115                 return;
 116         }
 117
 118         phys = 0;
 119         for (power = 26; power >= 11; power--) {
 120                 int order;
 121
 122                 size = BIT(power);
 123                 order = get_order(size);
 124                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 125                                    order);
 126                 if (!page)
 127                         continue;
 128
 129                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 130                                     DMA_FROM_DEVICE);
 131                 if (dma_mapping_error(trans->dev, phys)) {
 132                         __free_pages(page, order);
 133                         continue;
 134                 }
 135                 IWL_INFO(trans,
 136                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 137                          size, order);
 138                 break;
 139         }
 140
 141         if (WARN_ON_ONCE(!page))
 142                 return;
 143
 144         trans_pcie->fw_mon_page = page;
 145         trans_pcie->fw_mon_phys = phys;
 146         trans_pcie->fw_mon_size = size;
 147 }
 148
 149 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 150 {
 151         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 152                     ((reg & 0x0000ffff) | (2 << 28)));
 153         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 154 }
 155
 156 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 157 {
 158         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 159         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 160                     ((reg & 0x0000ffff) | (3 << 28)));
 161 }
 162
 163 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 164 {
 165         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 166                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 167                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 168                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 169         else
 170                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 171                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 172                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 173 }
 174
 175 /* PCI registers */
 176 #define PCI_CFG_RETRY_TIMEOUT   0x041
 177
 178 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 179 {
 180         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 181         u16 lctl;
 182         u16 cap;
 183
 184         /*
 185          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 186          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 187          * If so (likely), disable L0S, so device moves directly L0->L1;
 188          *    costs negligible amount of power savings.
 189          * If not (unlikely), enable L0S, so there is at least some
 190          *    power savings, even without L1.
 191          */
 192         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 193         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 194                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 195         else
 196                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 197         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 198
 199         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 200         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 201         dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
 202                  (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 203                  trans->ltr_enabled ? "En" : "Dis");
 204 }
 205
 206 /*
 207  * Start up NIC's basic functionality after it has been reset
 208  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 209  * NOTE:  This does not load uCode nor start the embedded processor
 210  */
 211 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 212 {
 213         int ret = 0;
 214         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 215
 216         /*
 217          * Use "set_bit" below rather than "write", to preserve any hardware
 218          * bits already set by default after reset.
 219          */
 220
 221         /* Disable L0S exit timer (platform NMI Work/Around) */
 222         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 223                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 224                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 225
 226         /*
 227          * Disable L0s without affecting L1;
 228          *  don't wait for ICH L0s (ICH bug W/A)
 229          */
 230         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 231                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 232
 233         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 234         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 235
 236         /*
 237          * Enable HAP INTA (interrupt from management bus) to
 238          * wake device's PCI Express link L1a -> L0s
 239          */
 240         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 241                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 242
 243         iwl_pcie_apm_config(trans);
 244
 245         /* Configure analog phase-lock-loop before activating to D0A */
 246         if (trans->cfg->base_params->pll_cfg_val)
 247                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 248                             trans->cfg->base_params->pll_cfg_val);
 249
 250         /*
 251          * Set "initialization complete" bit to move adapter from
 252          * D0U* --> D0A* (powered-up active) state.
 253          */
 254         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 255
 256         /*
 257          * Wait for clock stabilization; once stabilized, access to
 258          * device-internal resources is supported, e.g. iwl_write_prph()
 259          * and accesses to uCode SRAM.
 260          */
 261         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 262                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 263                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 264         if (ret < 0) {
 265                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 266                 goto out;
 267         }
 268
 269         if (trans->cfg->host_interrupt_operation_mode) {
 270                 /*
 271                  * This is a bit of an abuse - This is needed for 7260 / 3160
 272                  * only check host_interrupt_operation_mode even if this is
 273                  * not related to host_interrupt_operation_mode.
 274                  *
 275                  * Enable the oscillator to count wake up time for L1 exit. This
 276                  * consumes slightly more power (100uA) - but allows to be sure
 277                  * that we wake up from L1 on time.
 278                  *
 279                  * This looks weird: read twice the same register, discard the
 280                  * value, set a bit, and yet again, read that same register
 281                  * just to discard the value. But that's the way the hardware
 282                  * seems to like it.
 283                  */
 284                 iwl_read_prph(trans, OSC_CLK);
 285                 iwl_read_prph(trans, OSC_CLK);
 286                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 287                 iwl_read_prph(trans, OSC_CLK);
 288                 iwl_read_prph(trans, OSC_CLK);
 289         }
 290
 291         /*
 292          * Enable DMA clock and wait for it to stabilize.
 293          *
 294          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 295          * bits do not disable clocks.  This preserves any hardware
 296          * bits already set by default in "CLK_CTRL_REG" after reset.
 297          */
 298         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
 299                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 300                                APMG_CLK_VAL_DMA_CLK_RQT);
 301                 udelay(20);
 302
 303                 /* Disable L1-Active */
 304                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 305                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 306
 307                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 308                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 309                                APMG_RTC_INT_STT_RFKILL);
 310         }
 311
 312         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 313
 314 out:
 315         return ret;
 316 }
 317
 318 /*
 319  * Enable LP XTAL to avoid HW bug where device may consume much power if
 320  * FW is not loaded after device reset. LP XTAL is disabled by default
 321  * after device HW reset. Do it only if XTAL is fed by internal source.
 322  * Configure device's "persistence" mode to avoid resetting XTAL again when
 323  * SHRD_HW_RST occurs in S3.
 324  */
 325 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 326 {
 327         int ret;
 328         u32 apmg_gp1_reg;
 329         u32 apmg_xtal_cfg_reg;
 330         u32 dl_cfg_reg;
 331
 332         /* Force XTAL ON */
 333         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 334                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 335
 336         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 337         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 338
 339         udelay(10);
 340
 341         /*
 342          * Set "initialization complete" bit to move adapter from
 343          * D0U* --> D0A* (powered-up active) state.
 344          */
 345         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 346
 347         /*
 348          * Wait for clock stabilization; once stabilized, access to
 349          * device-internal resources is possible.
 350          */
 351         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 352                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 353                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 354                            25000);
 355         if (WARN_ON(ret < 0)) {
 356                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 357                 /* Release XTAL ON request */
 358                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 359                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 360                 return;
 361         }
 362
 363         /*
 364          * Clear "disable persistence" to avoid LP XTAL resetting when
 365          * SHRD_HW_RST is applied in S3.
 366          */
 367         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 368                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 369
 370         /*
 371          * Force APMG XTAL to be active to prevent its disabling by HW
 372          * caused by APMG idle state.
 373          */
 374         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 375                                                     SHR_APMG_XTAL_CFG_REG);
 376         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 377                                  apmg_xtal_cfg_reg |
 378                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 379
 380         /*
 381          * Reset entire device again - do controller reset (results in
 382          * SHRD_HW_RST). Turn MAC off before proceeding.
 383          */
 384         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 385
 386         udelay(10);
 387
 388         /* Enable LP XTAL by indirect access through CSR */
 389         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 390         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 391                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 392                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 393
 394         /* Clear delay line clock power up */
 395         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 396         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 397                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 398
 399         /*
 400          * Enable persistence mode to avoid LP XTAL resetting when
 401          * SHRD_HW_RST is applied in S3.
 402          */
 403         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 404                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 405
 406         /*
 407          * Clear "initialization complete" bit to move adapter from
 408          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 409          */
 410         iwl_clear_bit(trans, CSR_GP_CNTRL,
 411                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 412
 413         /* Activates XTAL resources monitor */
 414         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 415                                  CSR_MONITOR_XTAL_RESOURCES);
 416
 417         /* Release XTAL ON request */
 418         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 419                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 420         udelay(10);
 421
 422         /* Release APMG XTAL */
 423         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 424                                  apmg_xtal_cfg_reg &
 425                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 426 }
 427
 428 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 429 {
 430         int ret = 0;
 431
 432         /* stop device's busmaster DMA activity */
 433         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 434
 435         ret = iwl_poll_bit(trans, CSR_RESET,
 436                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 437                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 438         if (ret < 0)
 439                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 440
 441         IWL_DEBUG_INFO(trans, "stop master\n");
 442
 443         return ret;
 444 }
 445
 446 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
 447 {
 448         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 449
 450         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 451
 452         /* Stop device's DMA activity */
 453         iwl_pcie_apm_stop_master(trans);
 454
 455         if (trans->cfg->lp_xtal_workaround) {
 456                 iwl_pcie_apm_lp_xtal_enable(trans);
 457                 return;
 458         }
 459
 460         /* Reset the entire device */
 461         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 462
 463         udelay(10);
 464
 465         /*
 466          * Clear "initialization complete" bit to move adapter from
 467          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 468          */
 469         iwl_clear_bit(trans, CSR_GP_CNTRL,
 470                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 471 }
 472
 473 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 474 {
 475         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 476
 477         /* nic_init */
 478         spin_lock(&trans_pcie->irq_lock);
 479         iwl_pcie_apm_init(trans);
 480
 481         spin_unlock(&trans_pcie->irq_lock);
 482
 483         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 484                 iwl_pcie_set_pwr(trans, false);
 485
 486         iwl_op_mode_nic_config(trans->op_mode);
 487
 488         /* Allocate the RX queue, or reset if it is already allocated */
 489         iwl_pcie_rx_init(trans);
 490
 491         /* Allocate or reset and init all Tx and Command queues */
 492         if (iwl_pcie_tx_init(trans))
 493                 return -ENOMEM;
 494
 495         if (trans->cfg->base_params->shadow_reg_enable) {
 496                 /* enable shadow regs in HW */
 497                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 498                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 499         }
 500
 501         return 0;
 502 }
 503
 504 #define HW_READY_TIMEOUT (50)
 505
 506 /* Note: returns poll_bit return value, which is >= 0 if success */
 507 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 508 {
 509         int ret;
 510
 511         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 512                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 513
 514         /* See if we got it */
 515         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 516                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 517                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 518                            HW_READY_TIMEOUT);
 519
 520         if (ret >= 0)
 521                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 522
 523         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 524         return ret;
 525 }
 526
 527 /* Note: returns standard 0/-ERROR code */
 528 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 529 {
 530         int ret;
 531         int t = 0;
 532         int iter;
 533
 534         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 535
 536         ret = iwl_pcie_set_hw_ready(trans);
 537         /* If the card is ready, exit 0 */
 538         if (ret >= 0)
 539                 return 0;
 540
 541         for (iter = 0; iter < 10; iter++) {
 542                 /* If HW is not ready, prepare the conditions to check again */
 543                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 544                             CSR_HW_IF_CONFIG_REG_PREPARE);
 545
 546                 do {
 547                         ret = iwl_pcie_set_hw_ready(trans);
 548                         if (ret >= 0)
 549                                 return 0;
 550
 551                         usleep_range(200, 1000);
 552                         t += 200;
 553                 } while (t < 150000);
 554                 msleep(25);
 555         }
 556
 557         IWL_ERR(trans, "Couldn't prepare the card\n");
 558
 559         return ret;
 560 }
 561
 562 /*
 563  * ucode
 564  */
 565 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 566                                    dma_addr_t phy_addr, u32 byte_cnt)
 567 {
 568         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 569         int ret;
 570
 571         trans_pcie->ucode_write_complete = false;
 572
 573         iwl_write_direct32(trans,
 574                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 575                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 576
 577         iwl_write_direct32(trans,
 578                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 579                            dst_addr);
 580
 581         iwl_write_direct32(trans,
 582                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 583                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 584
 585         iwl_write_direct32(trans,
 586                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 587                            (iwl_get_dma_hi_addr(phy_addr)
 588                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 589
 590         iwl_write_direct32(trans,
 591                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 592                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 593                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 594                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 595
 596         iwl_write_direct32(trans,
 597                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 598                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 599                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 600                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 601
 602         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 603                                  trans_pcie->ucode_write_complete, 5 * HZ);
 604         if (!ret) {
 605                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 606                 return -ETIMEDOUT;
 607         }
 608
 609         return 0;
 610 }
 611
 612 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 613                             const struct fw_desc *section)
 614 {
 615         u8 *v_addr;
 616         dma_addr_t p_addr;
 617         u32 offset, chunk_sz = section->len;
 618         int ret = 0;
 619
 620         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 621                      section_num);
 622
 623         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 624                                     GFP_KERNEL | __GFP_NOWARN);
 625         if (!v_addr) {
 626                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 627                 chunk_sz = PAGE_SIZE;
 628                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 629                                             &p_addr, GFP_KERNEL);
 630                 if (!v_addr)
 631                         return -ENOMEM;
 632         }
 633
 634         for (offset = 0; offset < section->len; offset += chunk_sz) {
 635                 u32 copy_size, dst_addr;
 636                 bool extended_addr = false;
 637
 638                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 639                 dst_addr = section->offset + offset;
 640
 641                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 642                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 643                         extended_addr = true;
 644
 645                 if (extended_addr)
 646                         iwl_set_bits_prph(trans, LMPM_CHICK,
 647                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 648
 649                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 650                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 651                                                    copy_size);
 652
 653                 if (extended_addr)
 654                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 655                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 656
 657                 if (ret) {
 658                         IWL_ERR(trans,
 659                                 "Could not load the [%d] uCode section\n",
 660                                 section_num);
 661                         break;
 662                 }
 663         }
 664
 665         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 666         return ret;
 667 }
 668
 669 static int iwl_pcie_load_cpu_sections_8000b(struct iwl_trans *trans,
 670                                             const struct fw_img *image,
 671                                             int cpu,
 672                                             int *first_ucode_section)
 673 {
 674         int shift_param;
 675         int i, ret = 0, sec_num = 0x1;
 676         u32 val, last_read_idx = 0;
 677
 678         if (cpu == 1) {
 679                 shift_param = 0;
 680                 *first_ucode_section = 0;
 681         } else {
 682                 shift_param = 16;
 683                 (*first_ucode_section)++;
 684         }
 685
 686         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 687                 last_read_idx = i;
 688
 689                 if (!image->sec[i].data ||
 690                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 691                         IWL_DEBUG_FW(trans,
 692                                      "Break since Data not valid or Empty section, sec = %d\n",
 693                                      i);
 694                         break;
 695                 }
 696
 697                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 698                 if (ret)
 699                         return ret;
 700
 701                 /* Notify the ucode of the loaded section number and status */
 702                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 703                 val = val | (sec_num << shift_param);
 704                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 705                 sec_num = (sec_num << 1) | 0x1;
 706         }
 707
 708         *first_ucode_section = last_read_idx;
 709
 710         return 0;
 711 }
 712
 713 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 714                                       const struct fw_img *image,
 715                                       int cpu,
 716                                       int *first_ucode_section)
 717 {
 718         int shift_param;
 719         int i, ret = 0;
 720         u32 last_read_idx = 0;
 721
 722         if (cpu == 1) {
 723                 shift_param = 0;
 724                 *first_ucode_section = 0;
 725         } else {
 726                 shift_param = 16;
 727                 (*first_ucode_section)++;
 728         }
 729
 730         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 731                 last_read_idx = i;
 732
 733                 if (!image->sec[i].data ||
 734                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 735                         IWL_DEBUG_FW(trans,
 736                                      "Break since Data not valid or Empty section, sec = %d\n",
 737                                      i);
 738                         break;
 739                 }
 740
 741                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 742                 if (ret)
 743                         return ret;
 744         }
 745
 746         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 747                 iwl_set_bits_prph(trans,
 748                                   CSR_UCODE_LOAD_STATUS_ADDR,
 749                                   (LMPM_CPU_UCODE_LOADING_COMPLETED |
 750                                    LMPM_CPU_HDRS_LOADING_COMPLETED |
 751                                    LMPM_CPU_UCODE_LOADING_STARTED) <<
 752                                         shift_param);
 753
 754         *first_ucode_section = last_read_idx;
 755
 756         return 0;
 757 }
 758
 759 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 760                                 const struct fw_img *image)
 761 {
 762         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 763         int ret = 0;
 764         int first_ucode_section;
 765
 766         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 767                      image->is_dual_cpus ? "Dual" : "Single");
 768
 769         /* load to FW the binary non secured sections of CPU1 */
 770         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
 771         if (ret)
 772                 return ret;
 773
 774         if (image->is_dual_cpus) {
 775                 /* set CPU2 header address */
 776                 iwl_write_prph(trans,
 777                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
 778                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
 779
 780                 /* load to FW the binary sections of CPU2 */
 781                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
 782                                                  &first_ucode_section);
 783                 if (ret)
 784                         return ret;
 785         }
 786
 787         /* supported for 7000 only for the moment */
 788         if (iwlwifi_mod_params.fw_monitor &&
 789             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
 790                 iwl_pcie_alloc_fw_monitor(trans);
 791
 792                 if (trans_pcie->fw_mon_size) {
 793                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
 794                                        trans_pcie->fw_mon_phys >> 4);
 795                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
 796                                        (trans_pcie->fw_mon_phys +
 797                                         trans_pcie->fw_mon_size) >> 4);
 798                 }
 799         }
 800
 801         /* release CPU reset */
 802         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 803                 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
 804         else
 805                 iwl_write32(trans, CSR_RESET, 0);
 806
 807         return 0;
 808 }
 809
 810 static int iwl_pcie_load_given_ucode_8000b(struct iwl_trans *trans,
 811                                            const struct fw_img *image)
 812 {
 813         int ret = 0;
 814         int first_ucode_section;
 815         u32 reg;
 816
 817         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 818                      image->is_dual_cpus ? "Dual" : "Single");
 819
 820         /* configure the ucode to be ready to get the secured image */
 821         /* release CPU reset */
 822         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
 823
 824         /* load to FW the binary Secured sections of CPU1 */
 825         ret = iwl_pcie_load_cpu_sections_8000b(trans, image, 1,
 826                                                &first_ucode_section);
 827         if (ret)
 828                 return ret;
 829
 830         /* load to FW the binary sections of CPU2 */
 831         ret = iwl_pcie_load_cpu_sections_8000b(trans, image, 2,
 832                                                &first_ucode_section);
 833         if (ret)
 834                 return ret;
 835
 836         /* Notify FW loading is done */
 837         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
 838
 839         /* wait for image verification to complete  */
 840         ret = iwl_poll_prph_bit(trans, LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0,
 841                                 LMPM_SECURE_BOOT_STATUS_SUCCESS,
 842                                 LMPM_SECURE_BOOT_STATUS_SUCCESS,
 843                                 LMPM_SECURE_TIME_OUT);
 844         if (ret < 0) {
 845                 reg = iwl_read_prph(trans,
 846                                     LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0);
 847
 848                 IWL_ERR(trans, "Timeout on secure boot process, reg = %x\n",
 849                         reg);
 850                 return ret;
 851         }
 852
 853         return 0;
 854 }
 855
 856 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 857                                    const struct fw_img *fw, bool run_in_rfkill)
 858 {
 859         int ret;
 860         bool hw_rfkill;
 861
 862         /* This may fail if AMT took ownership of the device */
 863         if (iwl_pcie_prepare_card_hw(trans)) {
 864                 IWL_WARN(trans, "Exit HW not ready\n");
 865                 return -EIO;
 866         }
 867
 868         iwl_enable_rfkill_int(trans);
 869
 870         /* If platform's RF_KILL switch is NOT set to KILL */
 871         hw_rfkill = iwl_is_rfkill_set(trans);
 872         if (hw_rfkill)
 873                 set_bit(STATUS_RFKILL, &trans->status);
 874         else
 875                 clear_bit(STATUS_RFKILL, &trans->status);
 876         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
 877         if (hw_rfkill && !run_in_rfkill)
 878                 return -ERFKILL;
 879
 880         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 881
 882         ret = iwl_pcie_nic_init(trans);
 883         if (ret) {
 884                 IWL_ERR(trans, "Unable to init nic\n");
 885                 return ret;
 886         }
 887
 888         /* make sure rfkill handshake bits are cleared */
 889         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 890         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
 891                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 892
 893         /* clear (again), then enable host interrupts */
 894         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 895         iwl_enable_interrupts(trans);
 896
 897         /* really make sure rfkill handshake bits are cleared */
 898         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 899         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 900
 901         /* Load the given image to the HW */
 902         if ((trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) &&
 903             (CSR_HW_REV_STEP(trans->hw_rev) == SILICON_B_STEP))
 904                 return iwl_pcie_load_given_ucode_8000b(trans, fw);
 905         else
 906                 return iwl_pcie_load_given_ucode(trans, fw);
 907 }
 908
 909 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
 910 {
 911         iwl_pcie_reset_ict(trans);
 912         iwl_pcie_tx_start(trans, scd_addr);
 913 }
 914
 915 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 916 {
 917         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 918         bool hw_rfkill, was_hw_rfkill;
 919
 920         was_hw_rfkill = iwl_is_rfkill_set(trans);
 921
 922         /* tell the device to stop sending interrupts */
 923         spin_lock(&trans_pcie->irq_lock);
 924         iwl_disable_interrupts(trans);
 925         spin_unlock(&trans_pcie->irq_lock);
 926
 927         /* device going down, Stop using ICT table */
 928         iwl_pcie_disable_ict(trans);
 929
 930         /*
 931          * If a HW restart happens during firmware loading,
 932          * then the firmware loading might call this function
 933          * and later it might be called again due to the
 934          * restart. So don't process again if the device is
 935          * already dead.
 936          */
 937         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
 938                 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
 939                 iwl_pcie_tx_stop(trans);
 940                 iwl_pcie_rx_stop(trans);
 941
 942                 /* Power-down device's busmaster DMA clocks */
 943                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
 944                                APMG_CLK_VAL_DMA_CLK_RQT);
 945                 udelay(5);
 946         }
 947
 948         /* Make sure (redundant) we've released our request to stay awake */
 949         iwl_clear_bit(trans, CSR_GP_CNTRL,
 950                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 951
 952         /* Stop the device, and put it in low power state */
 953         iwl_pcie_apm_stop(trans);
 954
 955         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
 956          * Clean again the interrupt here
 957          */
 958         spin_lock(&trans_pcie->irq_lock);
 959         iwl_disable_interrupts(trans);
 960         spin_unlock(&trans_pcie->irq_lock);
 961
 962         /* stop and reset the on-board processor */
 963         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 964         udelay(20);
 965
 966         /* clear all status bits */
 967         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
 968         clear_bit(STATUS_INT_ENABLED, &trans->status);
 969         clear_bit(STATUS_TPOWER_PMI, &trans->status);
 970         clear_bit(STATUS_RFKILL, &trans->status);
 971
 972         /*
 973          * Even if we stop the HW, we still want the RF kill
 974          * interrupt
 975          */
 976         iwl_enable_rfkill_int(trans);
 977
 978         /*
 979          * Check again since the RF kill state may have changed while
 980          * all the interrupts were disabled, in this case we couldn't
 981          * receive the RF kill interrupt and update the state in the
 982          * op_mode.
 983          * Don't call the op_mode if the rkfill state hasn't changed.
 984          * This allows the op_mode to call stop_device from the rfkill
 985          * notification without endless recursion. Under very rare
 986          * circumstances, we might have a small recursion if the rfkill
 987          * state changed exactly now while we were called from stop_device.
 988          * This is very unlikely but can happen and is supported.
 989          */
 990         hw_rfkill = iwl_is_rfkill_set(trans);
 991         if (hw_rfkill)
 992                 set_bit(STATUS_RFKILL, &trans->status);
 993         else
 994                 clear_bit(STATUS_RFKILL, &trans->status);
 995         if (hw_rfkill != was_hw_rfkill)
 996                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
 997
 998         /* re-take ownership to prevent other users from stealing the deivce */
 999         iwl_pcie_prepare_card_hw(trans);
1000 }
1001
1002 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1003 {
1004         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1005                 iwl_trans_pcie_stop_device(trans);
1006 }
1007
1008 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
1009 {
1010         iwl_disable_interrupts(trans);
1011
1012         /*
1013          * in testing mode, the host stays awake and the
1014          * hardware won't be reset (not even partially)
1015          */
1016         if (test)
1017                 return;
1018
1019         iwl_pcie_disable_ict(trans);
1020
1021         iwl_clear_bit(trans, CSR_GP_CNTRL,
1022                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1023         iwl_clear_bit(trans, CSR_GP_CNTRL,
1024                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1025
1026         /*
1027          * reset TX queues -- some of their registers reset during S3
1028          * so if we don't reset everything here the D3 image would try
1029          * to execute some invalid memory upon resume
1030          */
1031         iwl_trans_pcie_tx_reset(trans);
1032
1033         iwl_pcie_set_pwr(trans, true);
1034 }
1035
1036 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1037                                     enum iwl_d3_status *status,
1038                                     bool test)
1039 {
1040         u32 val;
1041         int ret;
1042
1043         if (test) {
1044                 iwl_enable_interrupts(trans);
1045                 *status = IWL_D3_STATUS_ALIVE;
1046                 return 0;
1047         }
1048
1049         /*
1050          * Also enables interrupts - none will happen as the device doesn't
1051          * know we're waking it up, only when the opmode actually tells it
1052          * after this call.
1053          */
1054         iwl_pcie_reset_ict(trans);
1055
1056         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1057         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1058
1059         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1060                 udelay(2);
1061
1062         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1063                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1064                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1065                            25000);
1066         if (ret < 0) {
1067                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1068                 return ret;
1069         }
1070
1071         iwl_pcie_set_pwr(trans, false);
1072
1073         iwl_trans_pcie_tx_reset(trans);
1074
1075         ret = iwl_pcie_rx_init(trans);
1076         if (ret) {
1077                 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1078                 return ret;
1079         }
1080
1081         val = iwl_read32(trans, CSR_RESET);
1082         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1083                 *status = IWL_D3_STATUS_RESET;
1084         else
1085                 *status = IWL_D3_STATUS_ALIVE;
1086
1087         return 0;
1088 }
1089
1090 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1091 {
1092         bool hw_rfkill;
1093         int err;
1094
1095         err = iwl_pcie_prepare_card_hw(trans);
1096         if (err) {
1097                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1098                 return err;
1099         }
1100
1101         /* Reset the entire device */
1102         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1103
1104         usleep_range(10, 15);
1105
1106         iwl_pcie_apm_init(trans);
1107
1108         /* From now on, the op_mode will be kept updated about RF kill state */
1109         iwl_enable_rfkill_int(trans);
1110
1111         hw_rfkill = iwl_is_rfkill_set(trans);
1112         if (hw_rfkill)
1113                 set_bit(STATUS_RFKILL, &trans->status);
1114         else
1115                 clear_bit(STATUS_RFKILL, &trans->status);
1116         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1117
1118         return 0;
1119 }
1120
1121 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1122 {
1123         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1124
1125         /* disable interrupts - don't enable HW RF kill interrupt */
1126         spin_lock(&trans_pcie->irq_lock);
1127         iwl_disable_interrupts(trans);
1128         spin_unlock(&trans_pcie->irq_lock);
1129
1130         iwl_pcie_apm_stop(trans);
1131
1132         spin_lock(&trans_pcie->irq_lock);
1133         iwl_disable_interrupts(trans);
1134         spin_unlock(&trans_pcie->irq_lock);
1135
1136         iwl_pcie_disable_ict(trans);
1137 }
1138
1139 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1140 {
1141         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1142 }
1143
1144 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1145 {
1146         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1147 }
1148
1149 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1150 {
1151         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1152 }
1153
1154 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1155 {
1156         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1157                                ((reg & 0x000FFFFF) | (3 << 24)));
1158         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1159 }
1160
1161 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1162                                       u32 val)
1163 {
1164         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1165                                ((addr & 0x000FFFFF) | (3 << 24)));
1166         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1167 }
1168
1169 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1170 {
1171         WARN_ON(1);
1172         return 0;
1173 }
1174
1175 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1176                                      const struct iwl_trans_config *trans_cfg)
1177 {
1178         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1179
1180         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1181         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1182         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1183                 trans_pcie->n_no_reclaim_cmds = 0;
1184         else
1185                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1186         if (trans_pcie->n_no_reclaim_cmds)
1187                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1188                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1189
1190         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1191         if (trans_pcie->rx_buf_size_8k)
1192                 trans_pcie->rx_page_order = get_order(8 * 1024);
1193         else
1194                 trans_pcie->rx_page_order = get_order(4 * 1024);
1195
1196         trans_pcie->wd_timeout =
1197                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1198
1199         trans_pcie->command_names = trans_cfg->command_names;
1200         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1201         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1202
1203         /* Initialize NAPI here - it should be before registering to mac80211
1204          * in the opmode but after the HW struct is allocated.
1205          * As this function may be called again in some corner cases don't
1206          * do anything if NAPI was already initialized.
1207          */
1208         if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1209                 init_dummy_netdev(&trans_pcie->napi_dev);
1210                 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1211                                      &trans_pcie->napi_dev,
1212                                      iwl_pcie_dummy_napi_poll, 64);
1213         }
1214 }
1215
1216 void iwl_trans_pcie_free(struct iwl_trans *trans)
1217 {
1218         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1219
1220         synchronize_irq(trans_pcie->pci_dev->irq);
1221
1222         iwl_pcie_tx_free(trans);
1223         iwl_pcie_rx_free(trans);
1224
1225         free_irq(trans_pcie->pci_dev->irq, trans);
1226         iwl_pcie_free_ict(trans);
1227
1228         pci_disable_msi(trans_pcie->pci_dev);
1229         iounmap(trans_pcie->hw_base);
1230         pci_release_regions(trans_pcie->pci_dev);
1231         pci_disable_device(trans_pcie->pci_dev);
1232         kmem_cache_destroy(trans->dev_cmd_pool);
1233
1234         if (trans_pcie->napi.poll)
1235                 netif_napi_del(&trans_pcie->napi);
1236
1237         iwl_pcie_free_fw_monitor(trans);
1238
1239         kfree(trans);
1240 }
1241
1242 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1243 {
1244         if (state)
1245                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1246         else
1247                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1248 }
1249
1250 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1251                                                 unsigned long *flags)
1252 {
1253         int ret;
1254         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1255
1256         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1257
1258         if (trans_pcie->cmd_in_flight)
1259                 goto out;
1260
1261         /* this bit wakes up the NIC */
1262         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1263                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1264         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1265                 udelay(2);
1266
1267         /*
1268          * These bits say the device is running, and should keep running for
1269          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1270          * but they do not indicate that embedded SRAM is restored yet;
1271          * 3945 and 4965 have volatile SRAM, and must save/restore contents
1272          * to/from host DRAM when sleeping/waking for power-saving.
1273          * Each direction takes approximately 1/4 millisecond; with this
1274          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1275          * series of register accesses are expected (e.g. reading Event Log),
1276          * to keep device from sleeping.
1277          *
1278          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1279          * SRAM is okay/restored.  We don't check that here because this call
1280          * is just for hardware register access; but GP1 MAC_SLEEP check is a
1281          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1282          *
1283          * 5000 series and later (including 1000 series) have non-volatile SRAM,
1284          * and do not save/restore SRAM when power cycling.
1285          */
1286         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1287                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1288                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1289                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1290         if (unlikely(ret < 0)) {
1291                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1292                 if (!silent) {
1293                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1294                         WARN_ONCE(1,
1295                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1296                                   val);
1297                         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1298                         return false;
1299                 }
1300         }
1301
1302 out:
1303         /*
1304          * Fool sparse by faking we release the lock - sparse will
1305          * track nic_access anyway.
1306          */
1307         __release(&trans_pcie->reg_lock);
1308         return true;
1309 }
1310
1311 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1312                                               unsigned long *flags)
1313 {
1314         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1315
1316         lockdep_assert_held(&trans_pcie->reg_lock);
1317
1318         /*
1319          * Fool sparse by faking we acquiring the lock - sparse will
1320          * track nic_access anyway.
1321          */
1322         __acquire(&trans_pcie->reg_lock);
1323
1324         if (trans_pcie->cmd_in_flight)
1325                 goto out;
1326
1327         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1328                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1329         /*
1330          * Above we read the CSR_GP_CNTRL register, which will flush
1331          * any previous writes, but we need the write that clears the
1332          * MAC_ACCESS_REQ bit to be performed before any other writes
1333          * scheduled on different CPUs (after we drop reg_lock).
1334          */
1335         mmiowb();
1336 out:
1337         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1338 }
1339
1340 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1341                                    void *buf, int dwords)
1342 {
1343         unsigned long flags;
1344         int offs, ret = 0;
1345         u32 *vals = buf;
1346
1347         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1348                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1349                 for (offs = 0; offs < dwords; offs++)
1350                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1351                 iwl_trans_release_nic_access(trans, &flags);
1352         } else {
1353                 ret = -EBUSY;
1354         }
1355         return ret;
1356 }
1357
1358 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1359                                     const void *buf, int dwords)
1360 {
1361         unsigned long flags;
1362         int offs, ret = 0;
1363         const u32 *vals = buf;
1364
1365         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1366                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1367                 for (offs = 0; offs < dwords; offs++)
1368                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1369                                     vals ? vals[offs] : 0);
1370                 iwl_trans_release_nic_access(trans, &flags);
1371         } else {
1372                 ret = -EBUSY;
1373         }
1374         return ret;
1375 }
1376
1377 #define IWL_FLUSH_WAIT_MS       2000
1378
1379 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1380 {
1381         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1382         struct iwl_txq *txq;
1383         struct iwl_queue *q;
1384         int cnt;
1385         unsigned long now = jiffies;
1386         u32 scd_sram_addr;
1387         u8 buf[16];
1388         int ret = 0;
1389
1390         /* waiting for all the tx frames complete might take a while */
1391         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1392                 u8 wr_ptr;
1393
1394                 if (cnt == trans_pcie->cmd_queue)
1395                         continue;
1396                 if (!test_bit(cnt, trans_pcie->queue_used))
1397                         continue;
1398                 if (!(BIT(cnt) & txq_bm))
1399                         continue;
1400
1401                 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1402                 txq = &trans_pcie->txq[cnt];
1403                 q = &txq->q;
1404                 wr_ptr = ACCESS_ONCE(q->write_ptr);
1405
1406                 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1407                        !time_after(jiffies,
1408                                    now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1409                         u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1410
1411                         if (WARN_ONCE(wr_ptr != write_ptr,
1412                                       "WR pointer moved while flushing %d -> %d\n",
1413                                       wr_ptr, write_ptr))
1414                                 return -ETIMEDOUT;
1415                         msleep(1);
1416                 }
1417
1418                 if (q->read_ptr != q->write_ptr) {
1419                         IWL_ERR(trans,
1420                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1421                         ret = -ETIMEDOUT;
1422                         break;
1423                 }
1424                 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1425         }
1426
1427         if (!ret)
1428                 return 0;
1429
1430         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1431                 txq->q.read_ptr, txq->q.write_ptr);
1432
1433         scd_sram_addr = trans_pcie->scd_base_addr +
1434                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1435         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1436
1437         iwl_print_hex_error(trans, buf, sizeof(buf));
1438
1439         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1440                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1441                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1442
1443         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1444                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1445                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1446                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1447                 u32 tbl_dw =
1448                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1449                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1450
1451                 if (cnt & 0x1)
1452                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1453                 else
1454                         tbl_dw = tbl_dw & 0x0000FFFF;
1455
1456                 IWL_ERR(trans,
1457                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1458                         cnt, active ? "" : "in", fifo, tbl_dw,
1459                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1460                                 (TFD_QUEUE_SIZE_MAX - 1),
1461                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1462         }
1463
1464         return ret;
1465 }
1466
1467 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1468                                          u32 mask, u32 value)
1469 {
1470         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1471         unsigned long flags;
1472
1473         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1474         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1475         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1476 }
1477
1478 static const char *get_csr_string(int cmd)
1479 {
1480 #define IWL_CMD(x) case x: return #x
1481         switch (cmd) {
1482         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1483         IWL_CMD(CSR_INT_COALESCING);
1484         IWL_CMD(CSR_INT);
1485         IWL_CMD(CSR_INT_MASK);
1486         IWL_CMD(CSR_FH_INT_STATUS);
1487         IWL_CMD(CSR_GPIO_IN);
1488         IWL_CMD(CSR_RESET);
1489         IWL_CMD(CSR_GP_CNTRL);
1490         IWL_CMD(CSR_HW_REV);
1491         IWL_CMD(CSR_EEPROM_REG);
1492         IWL_CMD(CSR_EEPROM_GP);
1493         IWL_CMD(CSR_OTP_GP_REG);
1494         IWL_CMD(CSR_GIO_REG);
1495         IWL_CMD(CSR_GP_UCODE_REG);
1496         IWL_CMD(CSR_GP_DRIVER_REG);
1497         IWL_CMD(CSR_UCODE_DRV_GP1);
1498         IWL_CMD(CSR_UCODE_DRV_GP2);
1499         IWL_CMD(CSR_LED_REG);
1500         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1501         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1502         IWL_CMD(CSR_ANA_PLL_CFG);
1503         IWL_CMD(CSR_HW_REV_WA_REG);
1504         IWL_CMD(CSR_MONITOR_STATUS_REG);
1505         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1506         default:
1507                 return "UNKNOWN";
1508         }
1509 #undef IWL_CMD
1510 }
1511
1512 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1513 {
1514         int i;
1515         static const u32 csr_tbl[] = {
1516                 CSR_HW_IF_CONFIG_REG,
1517                 CSR_INT_COALESCING,
1518                 CSR_INT,
1519                 CSR_INT_MASK,
1520                 CSR_FH_INT_STATUS,
1521                 CSR_GPIO_IN,
1522                 CSR_RESET,
1523                 CSR_GP_CNTRL,
1524                 CSR_HW_REV,
1525                 CSR_EEPROM_REG,
1526                 CSR_EEPROM_GP,
1527                 CSR_OTP_GP_REG,
1528                 CSR_GIO_REG,
1529                 CSR_GP_UCODE_REG,
1530                 CSR_GP_DRIVER_REG,
1531                 CSR_UCODE_DRV_GP1,
1532                 CSR_UCODE_DRV_GP2,
1533                 CSR_LED_REG,
1534                 CSR_DRAM_INT_TBL_REG,
1535                 CSR_GIO_CHICKEN_BITS,
1536                 CSR_ANA_PLL_CFG,
1537                 CSR_MONITOR_STATUS_REG,
1538                 CSR_HW_REV_WA_REG,
1539                 CSR_DBG_HPET_MEM_REG
1540         };
1541         IWL_ERR(trans, "CSR values:\n");
1542         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1543                 "CSR_INT_PERIODIC_REG)\n");
1544         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1545                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1546                         get_csr_string(csr_tbl[i]),
1547                         iwl_read32(trans, csr_tbl[i]));
1548         }
1549 }
1550
1551 #ifdef CONFIG_IWLWIFI_DEBUGFS
1552 /* create and remove of files */
1553 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1554         if (!debugfs_create_file(#name, mode, parent, trans,            \
1555                                  &iwl_dbgfs_##name##_ops))              \
1556                 goto err;                                               \
1557 } while (0)
1558
1559 /* file operation */
1560 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1561 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1562         .read = iwl_dbgfs_##name##_read,                                \
1563         .open = simple_open,                                            \
1564         .llseek = generic_file_llseek,                                  \
1565 };
1566
1567 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1568 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1569         .write = iwl_dbgfs_##name##_write,                              \
1570         .open = simple_open,                                            \
1571         .llseek = generic_file_llseek,                                  \
1572 };
1573
1574 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1575 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1576         .write = iwl_dbgfs_##name##_write,                              \
1577         .read = iwl_dbgfs_##name##_read,                                \
1578         .open = simple_open,                                            \
1579         .llseek = generic_file_llseek,                                  \
1580 };
1581
1582 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1583                                        char __user *user_buf,
1584                                        size_t count, loff_t *ppos)
1585 {
1586         struct iwl_trans *trans = file->private_data;
1587         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1588         struct iwl_txq *txq;
1589         struct iwl_queue *q;
1590         char *buf;
1591         int pos = 0;
1592         int cnt;
1593         int ret;
1594         size_t bufsz;
1595
1596         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1597
1598         if (!trans_pcie->txq)
1599                 return -EAGAIN;
1600
1601         buf = kzalloc(bufsz, GFP_KERNEL);
1602         if (!buf)
1603                 return -ENOMEM;
1604
1605         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1606                 txq = &trans_pcie->txq[cnt];
1607                 q = &txq->q;
1608                 pos += scnprintf(buf + pos, bufsz - pos,
1609                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d%s\n",
1610                                 cnt, q->read_ptr, q->write_ptr,
1611                                 !!test_bit(cnt, trans_pcie->queue_used),
1612                                  !!test_bit(cnt, trans_pcie->queue_stopped),
1613                                  txq->need_update,
1614                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
1615         }
1616         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1617         kfree(buf);
1618         return ret;
1619 }
1620
1621 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1622                                        char __user *user_buf,
1623                                        size_t count, loff_t *ppos)
1624 {
1625         struct iwl_trans *trans = file->private_data;
1626         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1627         struct iwl_rxq *rxq = &trans_pcie->rxq;
1628         char buf[256];
1629         int pos = 0;
1630         const size_t bufsz = sizeof(buf);
1631
1632         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1633                                                 rxq->read);
1634         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1635                                                 rxq->write);
1636         pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1637                                                 rxq->write_actual);
1638         pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1639                                                 rxq->need_update);
1640         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1641                                                 rxq->free_count);
1642         if (rxq->rb_stts) {
1643                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1644                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1645         } else {
1646                 pos += scnprintf(buf + pos, bufsz - pos,
1647                                         "closed_rb_num: Not Allocated\n");
1648         }
1649         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1650 }
1651
1652 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1653                                         char __user *user_buf,
1654                                         size_t count, loff_t *ppos)
1655 {
1656         struct iwl_trans *trans = file->private_data;
1657         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1658         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1659
1660         int pos = 0;
1661         char *buf;
1662         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1663         ssize_t ret;
1664
1665         buf = kzalloc(bufsz, GFP_KERNEL);
1666         if (!buf)
1667                 return -ENOMEM;
1668
1669         pos += scnprintf(buf + pos, bufsz - pos,
1670                         "Interrupt Statistics Report:\n");
1671
1672         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1673                 isr_stats->hw);
1674         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1675                 isr_stats->sw);
1676         if (isr_stats->sw || isr_stats->hw) {
1677                 pos += scnprintf(buf + pos, bufsz - pos,
1678                         "\tLast Restarting Code:  0x%X\n",
1679                         isr_stats->err_code);
1680         }
1681 #ifdef CONFIG_IWLWIFI_DEBUG
1682         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1683                 isr_stats->sch);
1684         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1685                 isr_stats->alive);
1686 #endif
1687         pos += scnprintf(buf + pos, bufsz - pos,
1688                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1689
1690         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1691                 isr_stats->ctkill);
1692
1693         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1694                 isr_stats->wakeup);
1695
1696         pos += scnprintf(buf + pos, bufsz - pos,
1697                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1698
1699         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1700                 isr_stats->tx);
1701
1702         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1703                 isr_stats->unhandled);
1704
1705         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1706         kfree(buf);
1707         return ret;
1708 }
1709
1710 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1711                                          const char __user *user_buf,
1712                                          size_t count, loff_t *ppos)
1713 {
1714         struct iwl_trans *trans = file->private_data;
1715         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1716         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1717
1718         char buf[8];
1719         int buf_size;
1720         u32 reset_flag;
1721
1722         memset(buf, 0, sizeof(buf));
1723         buf_size = min(count, sizeof(buf) -  1);
1724         if (copy_from_user(buf, user_buf, buf_size))
1725                 return -EFAULT;
1726         if (sscanf(buf, "%x", &reset_flag) != 1)
1727                 return -EFAULT;
1728         if (reset_flag == 0)
1729                 memset(isr_stats, 0, sizeof(*isr_stats));
1730
1731         return count;
1732 }
1733
1734 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1735                                    const char __user *user_buf,
1736                                    size_t count, loff_t *ppos)
1737 {
1738         struct iwl_trans *trans = file->private_data;
1739         char buf[8];
1740         int buf_size;
1741         int csr;
1742
1743         memset(buf, 0, sizeof(buf));
1744         buf_size = min(count, sizeof(buf) -  1);
1745         if (copy_from_user(buf, user_buf, buf_size))
1746                 return -EFAULT;
1747         if (sscanf(buf, "%d", &csr) != 1)
1748                 return -EFAULT;
1749
1750         iwl_pcie_dump_csr(trans);
1751
1752         return count;
1753 }
1754
1755 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1756                                      char __user *user_buf,
1757                                      size_t count, loff_t *ppos)
1758 {
1759         struct iwl_trans *trans = file->private_data;
1760         char *buf = NULL;
1761         ssize_t ret;
1762
1763         ret = iwl_dump_fh(trans, &buf);
1764         if (ret < 0)
1765                 return ret;
1766         if (!buf)
1767                 return -EINVAL;
1768         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1769         kfree(buf);
1770         return ret;
1771 }
1772
1773 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1774 DEBUGFS_READ_FILE_OPS(fh_reg);
1775 DEBUGFS_READ_FILE_OPS(rx_queue);
1776 DEBUGFS_READ_FILE_OPS(tx_queue);
1777 DEBUGFS_WRITE_FILE_OPS(csr);
1778
1779 /*
1780  * Create the debugfs files and directories
1781  *
1782  */
1783 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1784                                          struct dentry *dir)
1785 {
1786         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1787         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1788         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1789         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1790         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1791         return 0;
1792
1793 err:
1794         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1795         return -ENOMEM;
1796 }
1797 #else
1798 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1799                                          struct dentry *dir)
1800 {
1801         return 0;
1802 }
1803 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1804
1805 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
1806 {
1807         u32 cmdlen = 0;
1808         int i;
1809
1810         for (i = 0; i < IWL_NUM_OF_TBS; i++)
1811                 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
1812
1813         return cmdlen;
1814 }
1815
1816 static const struct {
1817         u32 start, end;
1818 } iwl_prph_dump_addr[] = {
1819         { .start = 0x00a00000, .end = 0x00a00000 },
1820         { .start = 0x00a0000c, .end = 0x00a00024 },
1821         { .start = 0x00a0002c, .end = 0x00a0003c },
1822         { .start = 0x00a00410, .end = 0x00a00418 },
1823         { .start = 0x00a00420, .end = 0x00a00420 },
1824         { .start = 0x00a00428, .end = 0x00a00428 },
1825         { .start = 0x00a00430, .end = 0x00a0043c },
1826         { .start = 0x00a00444, .end = 0x00a00444 },
1827         { .start = 0x00a004c0, .end = 0x00a004cc },
1828         { .start = 0x00a004d8, .end = 0x00a004d8 },
1829         { .start = 0x00a004e0, .end = 0x00a004f0 },
1830         { .start = 0x00a00840, .end = 0x00a00840 },
1831         { .start = 0x00a00850, .end = 0x00a00858 },
1832         { .start = 0x00a01004, .end = 0x00a01008 },
1833         { .start = 0x00a01010, .end = 0x00a01010 },
1834         { .start = 0x00a01018, .end = 0x00a01018 },
1835         { .start = 0x00a01024, .end = 0x00a01024 },
1836         { .start = 0x00a0102c, .end = 0x00a01034 },
1837         { .start = 0x00a0103c, .end = 0x00a01040 },
1838         { .start = 0x00a01048, .end = 0x00a01094 },
1839         { .start = 0x00a01c00, .end = 0x00a01c20 },
1840         { .start = 0x00a01c58, .end = 0x00a01c58 },
1841         { .start = 0x00a01c7c, .end = 0x00a01c7c },
1842         { .start = 0x00a01c28, .end = 0x00a01c54 },
1843         { .start = 0x00a01c5c, .end = 0x00a01c5c },
1844         { .start = 0x00a01c84, .end = 0x00a01c84 },
1845         { .start = 0x00a01ce0, .end = 0x00a01d0c },
1846         { .start = 0x00a01d18, .end = 0x00a01d20 },
1847         { .start = 0x00a01d2c, .end = 0x00a01d30 },
1848         { .start = 0x00a01d40, .end = 0x00a01d5c },
1849         { .start = 0x00a01d80, .end = 0x00a01d80 },
1850         { .start = 0x00a01d98, .end = 0x00a01d98 },
1851         { .start = 0x00a01dc0, .end = 0x00a01dfc },
1852         { .start = 0x00a01e00, .end = 0x00a01e2c },
1853         { .start = 0x00a01e40, .end = 0x00a01e60 },
1854         { .start = 0x00a01e84, .end = 0x00a01e90 },
1855         { .start = 0x00a01e9c, .end = 0x00a01ec4 },
1856         { .start = 0x00a01ed0, .end = 0x00a01ed0 },
1857         { .start = 0x00a01f00, .end = 0x00a01f14 },
1858         { .start = 0x00a01f44, .end = 0x00a01f58 },
1859         { .start = 0x00a01f80, .end = 0x00a01fa8 },
1860         { .start = 0x00a01fb0, .end = 0x00a01fbc },
1861         { .start = 0x00a01ff8, .end = 0x00a01ffc },
1862         { .start = 0x00a02000, .end = 0x00a02048 },
1863         { .start = 0x00a02068, .end = 0x00a020f0 },
1864         { .start = 0x00a02100, .end = 0x00a02118 },
1865         { .start = 0x00a02140, .end = 0x00a0214c },
1866         { .start = 0x00a02168, .end = 0x00a0218c },
1867         { .start = 0x00a021c0, .end = 0x00a021c0 },
1868         { .start = 0x00a02400, .end = 0x00a02410 },
1869         { .start = 0x00a02418, .end = 0x00a02420 },
1870         { .start = 0x00a02428, .end = 0x00a0242c },
1871         { .start = 0x00a02434, .end = 0x00a02434 },
1872         { .start = 0x00a02440, .end = 0x00a02460 },
1873         { .start = 0x00a02468, .end = 0x00a024b0 },
1874         { .start = 0x00a024c8, .end = 0x00a024cc },
1875         { .start = 0x00a02500, .end = 0x00a02504 },
1876         { .start = 0x00a0250c, .end = 0x00a02510 },
1877         { .start = 0x00a02540, .end = 0x00a02554 },
1878         { .start = 0x00a02580, .end = 0x00a025f4 },
1879         { .start = 0x00a02600, .end = 0x00a0260c },
1880         { .start = 0x00a02648, .end = 0x00a02650 },
1881         { .start = 0x00a02680, .end = 0x00a02680 },
1882         { .start = 0x00a026c0, .end = 0x00a026d0 },
1883         { .start = 0x00a02700, .end = 0x00a0270c },
1884         { .start = 0x00a02804, .end = 0x00a02804 },
1885         { .start = 0x00a02818, .end = 0x00a0281c },
1886         { .start = 0x00a02c00, .end = 0x00a02db4 },
1887         { .start = 0x00a02df4, .end = 0x00a02fb0 },
1888         { .start = 0x00a03000, .end = 0x00a03014 },
1889         { .start = 0x00a0301c, .end = 0x00a0302c },
1890         { .start = 0x00a03034, .end = 0x00a03038 },
1891         { .start = 0x00a03040, .end = 0x00a03048 },
1892         { .start = 0x00a03060, .end = 0x00a03068 },
1893         { .start = 0x00a03070, .end = 0x00a03074 },
1894         { .start = 0x00a0307c, .end = 0x00a0307c },
1895         { .start = 0x00a03080, .end = 0x00a03084 },
1896         { .start = 0x00a0308c, .end = 0x00a03090 },
1897         { .start = 0x00a03098, .end = 0x00a03098 },
1898         { .start = 0x00a030a0, .end = 0x00a030a0 },
1899         { .start = 0x00a030a8, .end = 0x00a030b4 },
1900         { .start = 0x00a030bc, .end = 0x00a030bc },
1901         { .start = 0x00a030c0, .end = 0x00a0312c },
1902         { .start = 0x00a03c00, .end = 0x00a03c5c },
1903         { .start = 0x00a04400, .end = 0x00a04454 },
1904         { .start = 0x00a04460, .end = 0x00a04474 },
1905         { .start = 0x00a044c0, .end = 0x00a044ec },
1906         { .start = 0x00a04500, .end = 0x00a04504 },
1907         { .start = 0x00a04510, .end = 0x00a04538 },
1908         { .start = 0x00a04540, .end = 0x00a04548 },
1909         { .start = 0x00a04560, .end = 0x00a0457c },
1910         { .start = 0x00a04590, .end = 0x00a04598 },
1911         { .start = 0x00a045c0, .end = 0x00a045f4 },
1912 };
1913
1914 static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
1915                                     struct iwl_fw_error_dump_data **data)
1916 {
1917         struct iwl_fw_error_dump_prph *prph;
1918         unsigned long flags;
1919         u32 prph_len = 0, i;
1920
1921         if (!iwl_trans_grab_nic_access(trans, false, &flags))
1922                 return 0;
1923
1924         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
1925                 /* The range includes both boundaries */
1926                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
1927                          iwl_prph_dump_addr[i].start + 4;
1928                 int reg;
1929                 __le32 *val;
1930
1931                 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
1932
1933                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
1934                 (*data)->len = cpu_to_le32(sizeof(*prph) +
1935                                         num_bytes_in_chunk);
1936                 prph = (void *)(*data)->data;
1937                 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
1938                 val = (void *)prph->data;
1939
1940                 for (reg = iwl_prph_dump_addr[i].start;
1941                      reg <= iwl_prph_dump_addr[i].end;
1942                      reg += 4)
1943                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
1944                                                                       reg));
1945                 *data = iwl_fw_error_next_data(*data);
1946         }
1947
1948         iwl_trans_release_nic_access(trans, &flags);
1949
1950         return prph_len;
1951 }
1952
1953 #define IWL_CSR_TO_DUMP (0x250)
1954
1955 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
1956                                    struct iwl_fw_error_dump_data **data)
1957 {
1958         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
1959         __le32 *val;
1960         int i;
1961
1962         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
1963         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
1964         val = (void *)(*data)->data;
1965
1966         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
1967                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
1968
1969         *data = iwl_fw_error_next_data(*data);
1970
1971         return csr_len;
1972 }
1973
1974 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
1975                                        struct iwl_fw_error_dump_data **data)
1976 {
1977         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
1978         unsigned long flags;
1979         __le32 *val;
1980         int i;
1981
1982         if (!iwl_trans_grab_nic_access(trans, false, &flags))
1983                 return 0;
1984
1985         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
1986         (*data)->len = cpu_to_le32(fh_regs_len);
1987         val = (void *)(*data)->data;
1988
1989         for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
1990                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
1991
1992         iwl_trans_release_nic_access(trans, &flags);
1993
1994         *data = iwl_fw_error_next_data(*data);
1995
1996         return sizeof(**data) + fh_regs_len;
1997 }
1998
1999 static
2000 struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
2001 {
2002         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2003         struct iwl_fw_error_dump_data *data;
2004         struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2005         struct iwl_fw_error_dump_txcmd *txcmd;
2006         struct iwl_trans_dump_data *dump_data;
2007         u32 len;
2008         int i, ptr;
2009
2010         /* transport dump header */
2011         len = sizeof(*dump_data);
2012
2013         /* host commands */
2014         len += sizeof(*data) +
2015                 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2016
2017         /* CSR registers */
2018         len += sizeof(*data) + IWL_CSR_TO_DUMP;
2019
2020         /* PRPH registers */
2021         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2022                 /* The range includes both boundaries */
2023                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2024                         iwl_prph_dump_addr[i].start + 4;
2025
2026                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2027                         num_bytes_in_chunk;
2028         }
2029
2030         /* FH registers */
2031         len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2032
2033         /* FW monitor */
2034         if (trans_pcie->fw_mon_page)
2035                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2036                         trans_pcie->fw_mon_size;
2037
2038         dump_data = vzalloc(len);
2039         if (!dump_data)
2040                 return NULL;
2041
2042         len = 0;
2043         data = (void *)dump_data->data;
2044         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2045         txcmd = (void *)data->data;
2046         spin_lock_bh(&cmdq->lock);
2047         ptr = cmdq->q.write_ptr;
2048         for (i = 0; i < cmdq->q.n_window; i++) {
2049                 u8 idx = get_cmd_index(&cmdq->q, ptr);
2050                 u32 caplen, cmdlen;
2051
2052                 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2053                 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2054
2055                 if (cmdlen) {
2056                         len += sizeof(*txcmd) + caplen;
2057                         txcmd->cmdlen = cpu_to_le32(cmdlen);
2058                         txcmd->caplen = cpu_to_le32(caplen);
2059                         memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2060                         txcmd = (void *)((u8 *)txcmd->data + caplen);
2061                 }
2062
2063                 ptr = iwl_queue_dec_wrap(ptr);
2064         }
2065         spin_unlock_bh(&cmdq->lock);
2066
2067         data->len = cpu_to_le32(len);
2068         len += sizeof(*data);
2069         data = iwl_fw_error_next_data(data);
2070
2071         len += iwl_trans_pcie_dump_prph(trans, &data);
2072         len += iwl_trans_pcie_dump_csr(trans, &data);
2073         len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2074         /* data is already pointing to the next section */
2075
2076         if (trans_pcie->fw_mon_page) {
2077                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2078
2079                 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2080                 data->len = cpu_to_le32(trans_pcie->fw_mon_size +
2081                                         sizeof(*fw_mon_data));
2082                 fw_mon_data = (void *)data->data;
2083                 fw_mon_data->fw_mon_wr_ptr =
2084                         cpu_to_le32(iwl_read_prph(trans, MON_BUFF_WRPTR));
2085                 fw_mon_data->fw_mon_cycle_cnt =
2086                         cpu_to_le32(iwl_read_prph(trans, MON_BUFF_CYCLE_CNT));
2087                 fw_mon_data->fw_mon_base_ptr =
2088                         cpu_to_le32(iwl_read_prph(trans, MON_BUFF_BASE_ADDR));
2089
2090                 /*
2091                  * The firmware is now asserted, it won't write anything to
2092                  * the buffer. CPU can take ownership to fetch the data.
2093                  * The buffer will be handed back to the device before the
2094                  * firmware will be restarted.
2095                  */
2096                 dma_sync_single_for_cpu(trans->dev, trans_pcie->fw_mon_phys,
2097                                         trans_pcie->fw_mon_size,
2098                                         DMA_FROM_DEVICE);
2099                 memcpy(fw_mon_data->data, page_address(trans_pcie->fw_mon_page),
2100                        trans_pcie->fw_mon_size);
2101
2102                 len += sizeof(*data) + sizeof(*fw_mon_data) +
2103                         trans_pcie->fw_mon_size;
2104         }
2105
2106         dump_data->len = len;
2107
2108         return dump_data;
2109 }
2110
2111 static const struct iwl_trans_ops trans_ops_pcie = {
2112         .start_hw = iwl_trans_pcie_start_hw,
2113         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2114         .fw_alive = iwl_trans_pcie_fw_alive,
2115         .start_fw = iwl_trans_pcie_start_fw,
2116         .stop_device = iwl_trans_pcie_stop_device,
2117
2118         .d3_suspend = iwl_trans_pcie_d3_suspend,
2119         .d3_resume = iwl_trans_pcie_d3_resume,
2120
2121         .send_cmd = iwl_trans_pcie_send_hcmd,
2122
2123         .tx = iwl_trans_pcie_tx,
2124         .reclaim = iwl_trans_pcie_reclaim,
2125
2126         .txq_disable = iwl_trans_pcie_txq_disable,
2127         .txq_enable = iwl_trans_pcie_txq_enable,
2128
2129         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2130
2131         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2132
2133         .write8 = iwl_trans_pcie_write8,
2134         .write32 = iwl_trans_pcie_write32,
2135         .read32 = iwl_trans_pcie_read32,
2136         .read_prph = iwl_trans_pcie_read_prph,
2137         .write_prph = iwl_trans_pcie_write_prph,
2138         .read_mem = iwl_trans_pcie_read_mem,
2139         .write_mem = iwl_trans_pcie_write_mem,
2140         .configure = iwl_trans_pcie_configure,
2141         .set_pmi = iwl_trans_pcie_set_pmi,
2142         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2143         .release_nic_access = iwl_trans_pcie_release_nic_access,
2144         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2145
2146         .dump_data = iwl_trans_pcie_dump_data,
2147 };
2148
2149 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2150                                        const struct pci_device_id *ent,
2151                                        const struct iwl_cfg *cfg)
2152 {
2153         struct iwl_trans_pcie *trans_pcie;
2154         struct iwl_trans *trans;
2155         u16 pci_cmd;
2156         int err;
2157
2158         trans = kzalloc(sizeof(struct iwl_trans) +
2159                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2160         if (!trans) {
2161                 err = -ENOMEM;
2162                 goto out;
2163         }
2164
2165         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2166
2167         trans->ops = &trans_ops_pcie;
2168         trans->cfg = cfg;
2169         trans_lockdep_init(trans);
2170         trans_pcie->trans = trans;
2171         spin_lock_init(&trans_pcie->irq_lock);
2172         spin_lock_init(&trans_pcie->reg_lock);
2173         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2174
2175         err = pci_enable_device(pdev);
2176         if (err)
2177                 goto out_no_pci;
2178
2179         if (!cfg->base_params->pcie_l1_allowed) {
2180                 /*
2181                  * W/A - seems to solve weird behavior. We need to remove this
2182                  * if we don't want to stay in L1 all the time. This wastes a
2183                  * lot of power.
2184                  */
2185                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2186                                        PCIE_LINK_STATE_L1 |
2187                                        PCIE_LINK_STATE_CLKPM);
2188         }
2189
2190         pci_set_master(pdev);
2191
2192         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2193         if (!err)
2194                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2195         if (err) {
2196                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2197                 if (!err)
2198                         err = pci_set_consistent_dma_mask(pdev,
2199                                                           DMA_BIT_MASK(32));
2200                 /* both attempts failed: */
2201                 if (err) {
2202                         dev_err(&pdev->dev, "No suitable DMA available\n");
2203                         goto out_pci_disable_device;
2204                 }
2205         }
2206
2207         err = pci_request_regions(pdev, DRV_NAME);
2208         if (err) {
2209                 dev_err(&pdev->dev, "pci_request_regions failed\n");
2210                 goto out_pci_disable_device;
2211         }
2212
2213         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2214         if (!trans_pcie->hw_base) {
2215                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2216                 err = -ENODEV;
2217                 goto out_pci_release_regions;
2218         }
2219
2220         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2221          * PCI Tx retries from interfering with C3 CPU state */
2222         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2223
2224         trans->dev = &pdev->dev;
2225         trans_pcie->pci_dev = pdev;
2226         iwl_disable_interrupts(trans);
2227
2228         err = pci_enable_msi(pdev);
2229         if (err) {
2230                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
2231                 /* enable rfkill interrupt: hw bug w/a */
2232                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2233                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2234                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2235                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2236                 }
2237         }
2238
2239         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2240         /*
2241          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2242          * changed, and now the revision step also includes bit 0-1 (no more
2243          * "dash" value). To keep hw_rev backwards compatible - we'll store it
2244          * in the old format.
2245          */
2246         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2247                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2248                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2249
2250         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2251         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2252                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2253
2254         /* Initialize the wait queue for commands */
2255         init_waitqueue_head(&trans_pcie->wait_command_queue);
2256
2257         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2258                  "iwl_cmd_pool:%s", dev_name(trans->dev));
2259
2260         trans->dev_cmd_headroom = 0;
2261         trans->dev_cmd_pool =
2262                 kmem_cache_create(trans->dev_cmd_pool_name,
2263                                   sizeof(struct iwl_device_cmd)
2264                                   + trans->dev_cmd_headroom,
2265                                   sizeof(void *),
2266                                   SLAB_HWCACHE_ALIGN,
2267                                   NULL);
2268
2269         if (!trans->dev_cmd_pool) {
2270                 err = -ENOMEM;
2271                 goto out_pci_disable_msi;
2272         }
2273
2274         if (iwl_pcie_alloc_ict(trans))
2275                 goto out_free_cmd_pool;
2276
2277         err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2278                                    iwl_pcie_irq_handler,
2279                                    IRQF_SHARED, DRV_NAME, trans);
2280         if (err) {
2281                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2282                 goto out_free_ict;
2283         }
2284
2285         trans_pcie->inta_mask = CSR_INI_SET_MASK;
2286
2287         return trans;
2288
2289 out_free_ict:
2290         iwl_pcie_free_ict(trans);
2291 out_free_cmd_pool:
2292         kmem_cache_destroy(trans->dev_cmd_pool);
2293 out_pci_disable_msi:
2294         pci_disable_msi(pdev);
2295 out_pci_release_regions:
2296         pci_release_regions(pdev);
2297 out_pci_disable_device:
2298         pci_disable_device(pdev);
2299 out_no_pci:
2300         kfree(trans);
2301 out:
2302         return ERR_PTR(err);
2303 }