drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
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   4  * redistributing this file, you may do so under either license.
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   6  * GPL LICENSE SUMMARY
   7  *
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  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
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  13  *
  14  * This program is distributed in the hope that it will be useful, but
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  44  *    the documentation and/or other materials provided with the
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
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  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-drv.h"
  72 #include "iwl-trans.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-agn-hw.h"
  76 #include "internal.h"
  77
  78 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
  79 {
  80         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
  81                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
  82                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  83                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
  84         else
  85                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
  86                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  87                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
  88 }
  89
  90 /* PCI registers */
  91 #define PCI_CFG_RETRY_TIMEOUT   0x041
  92
  93 static void iwl_pcie_apm_config(struct iwl_trans *trans)
  94 {
  95         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  96         u16 lctl;
  97
  98         /*
  99          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 100          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 101          * If so (likely), disable L0S, so device moves directly L0->L1;
 102          *    costs negligible amount of power savings.
 103          * If not (unlikely), enable L0S, so there is at least some
 104          *    power savings, even without L1.
 105          */
 106         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 107         if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
 108                 /* L1-ASPM enabled; disable(!) L0S */
 109                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 110                 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
 111         } else {
 112                 /* L1-ASPM disabled; enable(!) L0S */
 113                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 114                 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
 115         }
 116         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 117 }
 118
 119 /*
 120  * Start up NIC's basic functionality after it has been reset
 121  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 122  * NOTE:  This does not load uCode nor start the embedded processor
 123  */
 124 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 125 {
 126         int ret = 0;
 127         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 128
 129         /*
 130          * Use "set_bit" below rather than "write", to preserve any hardware
 131          * bits already set by default after reset.
 132          */
 133
 134         /* Disable L0S exit timer (platform NMI Work/Around) */
 135         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 136                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 137                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 138
 139         /*
 140          * Disable L0s without affecting L1;
 141          *  don't wait for ICH L0s (ICH bug W/A)
 142          */
 143         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 144                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 145
 146         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 147         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 148
 149         /*
 150          * Enable HAP INTA (interrupt from management bus) to
 151          * wake device's PCI Express link L1a -> L0s
 152          */
 153         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 154                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 155
 156         iwl_pcie_apm_config(trans);
 157
 158         /* Configure analog phase-lock-loop before activating to D0A */
 159         if (trans->cfg->base_params->pll_cfg_val)
 160                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 161                             trans->cfg->base_params->pll_cfg_val);
 162
 163         /*
 164          * Set "initialization complete" bit to move adapter from
 165          * D0U* --> D0A* (powered-up active) state.
 166          */
 167         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 168
 169         /*
 170          * Wait for clock stabilization; once stabilized, access to
 171          * device-internal resources is supported, e.g. iwl_write_prph()
 172          * and accesses to uCode SRAM.
 173          */
 174         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 175                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 176                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 177         if (ret < 0) {
 178                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 179                 goto out;
 180         }
 181
 182         if (trans->cfg->host_interrupt_operation_mode) {
 183                 /*
 184                  * This is a bit of an abuse - This is needed for 7260 / 3160
 185                  * only check host_interrupt_operation_mode even if this is
 186                  * not related to host_interrupt_operation_mode.
 187                  *
 188                  * Enable the oscillator to count wake up time for L1 exit. This
 189                  * consumes slightly more power (100uA) - but allows to be sure
 190                  * that we wake up from L1 on time.
 191                  *
 192                  * This looks weird: read twice the same register, discard the
 193                  * value, set a bit, and yet again, read that same register
 194                  * just to discard the value. But that's the way the hardware
 195                  * seems to like it.
 196                  */
 197                 iwl_read_prph(trans, OSC_CLK);
 198                 iwl_read_prph(trans, OSC_CLK);
 199                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 200                 iwl_read_prph(trans, OSC_CLK);
 201                 iwl_read_prph(trans, OSC_CLK);
 202         }
 203
 204         /*
 205          * Enable DMA clock and wait for it to stabilize.
 206          *
 207          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 208          * bits do not disable clocks.  This preserves any hardware
 209          * bits already set by default in "CLK_CTRL_REG" after reset.
 210          */
 211         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
 212                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 213                                APMG_CLK_VAL_DMA_CLK_RQT);
 214                 udelay(20);
 215
 216                 /* Disable L1-Active */
 217                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 218                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 219
 220                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 221                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 222                                APMG_RTC_INT_STT_RFKILL);
 223         }
 224
 225         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 226
 227 out:
 228         return ret;
 229 }
 230
 231 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 232 {
 233         int ret = 0;
 234
 235         /* stop device's busmaster DMA activity */
 236         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 237
 238         ret = iwl_poll_bit(trans, CSR_RESET,
 239                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 240                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 241         if (ret)
 242                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 243
 244         IWL_DEBUG_INFO(trans, "stop master\n");
 245
 246         return ret;
 247 }
 248
 249 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
 250 {
 251         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 252
 253         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 254
 255         /* Stop device's DMA activity */
 256         iwl_pcie_apm_stop_master(trans);
 257
 258         /* Reset the entire device */
 259         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 260
 261         udelay(10);
 262
 263         /*
 264          * Clear "initialization complete" bit to move adapter from
 265          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 266          */
 267         iwl_clear_bit(trans, CSR_GP_CNTRL,
 268                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 269 }
 270
 271 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 272 {
 273         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 274
 275         /* nic_init */
 276         spin_lock(&trans_pcie->irq_lock);
 277         iwl_pcie_apm_init(trans);
 278
 279         spin_unlock(&trans_pcie->irq_lock);
 280
 281         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 282                 iwl_pcie_set_pwr(trans, false);
 283
 284         iwl_op_mode_nic_config(trans->op_mode);
 285
 286         /* Allocate the RX queue, or reset if it is already allocated */
 287         iwl_pcie_rx_init(trans);
 288
 289         /* Allocate or reset and init all Tx and Command queues */
 290         if (iwl_pcie_tx_init(trans))
 291                 return -ENOMEM;
 292
 293         if (trans->cfg->base_params->shadow_reg_enable) {
 294                 /* enable shadow regs in HW */
 295                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 296                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 297         }
 298
 299         return 0;
 300 }
 301
 302 #define HW_READY_TIMEOUT (50)
 303
 304 /* Note: returns poll_bit return value, which is >= 0 if success */
 305 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 306 {
 307         int ret;
 308
 309         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 310                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 311
 312         /* See if we got it */
 313         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 314                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 315                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 316                            HW_READY_TIMEOUT);
 317
 318         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 319         return ret;
 320 }
 321
 322 /* Note: returns standard 0/-ERROR code */
 323 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 324 {
 325         int ret;
 326         int t = 0;
 327
 328         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 329
 330         ret = iwl_pcie_set_hw_ready(trans);
 331         /* If the card is ready, exit 0 */
 332         if (ret >= 0)
 333                 return 0;
 334
 335         /* If HW is not ready, prepare the conditions to check again */
 336         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 337                     CSR_HW_IF_CONFIG_REG_PREPARE);
 338
 339         do {
 340                 ret = iwl_pcie_set_hw_ready(trans);
 341                 if (ret >= 0)
 342                         return 0;
 343
 344                 usleep_range(200, 1000);
 345                 t += 200;
 346         } while (t < 150000);
 347
 348         return ret;
 349 }
 350
 351 /*
 352  * ucode
 353  */
 354 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 355                                    dma_addr_t phy_addr, u32 byte_cnt)
 356 {
 357         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 358         int ret;
 359
 360         trans_pcie->ucode_write_complete = false;
 361
 362         iwl_write_direct32(trans,
 363                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 364                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 365
 366         iwl_write_direct32(trans,
 367                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 368                            dst_addr);
 369
 370         iwl_write_direct32(trans,
 371                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 372                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 373
 374         iwl_write_direct32(trans,
 375                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 376                            (iwl_get_dma_hi_addr(phy_addr)
 377                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 378
 379         iwl_write_direct32(trans,
 380                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 381                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 382                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 383                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 384
 385         iwl_write_direct32(trans,
 386                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 387                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 388                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 389                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 390
 391         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 392                                  trans_pcie->ucode_write_complete, 5 * HZ);
 393         if (!ret) {
 394                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 395                 return -ETIMEDOUT;
 396         }
 397
 398         return 0;
 399 }
 400
 401 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 402                             const struct fw_desc *section)
 403 {
 404         u8 *v_addr;
 405         dma_addr_t p_addr;
 406         u32 offset, chunk_sz = section->len;
 407         int ret = 0;
 408
 409         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 410                      section_num);
 411
 412         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 413                                     GFP_KERNEL | __GFP_NOWARN);
 414         if (!v_addr) {
 415                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 416                 chunk_sz = PAGE_SIZE;
 417                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 418                                             &p_addr, GFP_KERNEL);
 419                 if (!v_addr)
 420                         return -ENOMEM;
 421         }
 422
 423         for (offset = 0; offset < section->len; offset += chunk_sz) {
 424                 u32 copy_size;
 425
 426                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 427
 428                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 429                 ret = iwl_pcie_load_firmware_chunk(trans,
 430                                                    section->offset + offset,
 431                                                    p_addr, copy_size);
 432                 if (ret) {
 433                         IWL_ERR(trans,
 434                                 "Could not load the [%d] uCode section\n",
 435                                 section_num);
 436                         break;
 437                 }
 438         }
 439
 440         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 441         return ret;
 442 }
 443
 444 static int iwl_pcie_secure_set(struct iwl_trans *trans, int cpu)
 445 {
 446         int shift_param;
 447         u32 address;
 448         int ret = 0;
 449
 450         if (cpu == 1) {
 451                 shift_param = 0;
 452                 address = CSR_SECURE_BOOT_CPU1_STATUS_ADDR;
 453         } else {
 454                 shift_param = 16;
 455                 address = CSR_SECURE_BOOT_CPU2_STATUS_ADDR;
 456         }
 457
 458         /* set CPU to started */
 459         iwl_trans_set_bits_mask(trans,
 460                                 CSR_UCODE_LOAD_STATUS_ADDR,
 461                                 CSR_CPU_STATUS_LOADING_STARTED << shift_param,
 462                                 1);
 463
 464         /* set last complete descriptor number */
 465         iwl_trans_set_bits_mask(trans,
 466                                 CSR_UCODE_LOAD_STATUS_ADDR,
 467                                 CSR_CPU_STATUS_NUM_OF_LAST_COMPLETED
 468                                 << shift_param,
 469                                 1);
 470
 471         /* set last loaded block */
 472         iwl_trans_set_bits_mask(trans,
 473                                 CSR_UCODE_LOAD_STATUS_ADDR,
 474                                 CSR_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK
 475                                 << shift_param,
 476                                 1);
 477
 478         /* image loading complete */
 479         iwl_trans_set_bits_mask(trans,
 480                                 CSR_UCODE_LOAD_STATUS_ADDR,
 481                                 CSR_CPU_STATUS_LOADING_COMPLETED
 482                                 << shift_param,
 483                                 1);
 484
 485         /* set FH_TCSR_0_REG  */
 486         iwl_trans_set_bits_mask(trans, FH_TCSR_0_REG0, 0x00400000, 1);
 487
 488         /* verify image verification started  */
 489         ret = iwl_poll_bit(trans, address,
 490                            CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS,
 491                            CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS,
 492                            CSR_SECURE_TIME_OUT);
 493         if (ret < 0) {
 494                 IWL_ERR(trans, "secure boot process didn't start\n");
 495                 return ret;
 496         }
 497
 498         /* wait for image verification to complete  */
 499         ret = iwl_poll_bit(trans, address,
 500                            CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED,
 501                            CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED,
 502                            CSR_SECURE_TIME_OUT);
 503
 504         if (ret < 0) {
 505                 IWL_ERR(trans, "Time out on secure boot process\n");
 506                 return ret;
 507         }
 508
 509         return 0;
 510 }
 511
 512 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 513                                 const struct fw_img *image)
 514 {
 515         int i, ret = 0;
 516
 517         IWL_DEBUG_FW(trans,
 518                      "working with %s image\n",
 519                      image->is_secure ? "Secured" : "Non Secured");
 520         IWL_DEBUG_FW(trans,
 521                      "working with %s CPU\n",
 522                      image->is_dual_cpus ? "Dual" : "Single");
 523
 524         /* configure the ucode to be ready to get the secured image */
 525         if (image->is_secure) {
 526                 /* set secure boot inspector addresses */
 527                 iwl_write32(trans, CSR_SECURE_INSPECTOR_CODE_ADDR, 0);
 528                 iwl_write32(trans, CSR_SECURE_INSPECTOR_DATA_ADDR, 0);
 529
 530                 /* release CPU1 reset if secure inspector image burned in OTP */
 531                 iwl_write32(trans, CSR_RESET, 0);
 532         }
 533
 534         /* load to FW the binary sections of CPU1 */
 535         IWL_DEBUG_INFO(trans, "Loading CPU1\n");
 536         for (i = 0;
 537              i < IWL_UCODE_FIRST_SECTION_OF_SECOND_CPU;
 538              i++) {
 539                 if (!image->sec[i].data)
 540                         break;
 541                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 542                 if (ret)
 543                         return ret;
 544         }
 545
 546         /* configure the ucode to start secure process on CPU1 */
 547         if (image->is_secure) {
 548                 /* config CPU1 to start secure protocol */
 549                 ret = iwl_pcie_secure_set(trans, 1);
 550                 if (ret)
 551                         return ret;
 552         } else {
 553                 /* Remove all resets to allow NIC to operate */
 554                 iwl_write32(trans, CSR_RESET, 0);
 555         }
 556
 557         if (image->is_dual_cpus) {
 558                 /* load to FW the binary sections of CPU2 */
 559                 IWL_DEBUG_INFO(trans, "working w/ DUAL CPUs - Loading CPU2\n");
 560                 for (i = IWL_UCODE_FIRST_SECTION_OF_SECOND_CPU;
 561                         i < IWL_UCODE_SECTION_MAX; i++) {
 562                         if (!image->sec[i].data)
 563                                 break;
 564                         ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 565                         if (ret)
 566                                 return ret;
 567                 }
 568
 569                 if (image->is_secure) {
 570                         /* set CPU2 for secure protocol */
 571                         ret = iwl_pcie_secure_set(trans, 2);
 572                         if (ret)
 573                                 return ret;
 574                 }
 575         }
 576
 577         /* release CPU reset */
 578         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 579                 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
 580         else
 581                 iwl_write32(trans, CSR_RESET, 0);
 582
 583         return 0;
 584 }
 585
 586 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 587                                    const struct fw_img *fw, bool run_in_rfkill)
 588 {
 589         int ret;
 590         bool hw_rfkill;
 591
 592         /* This may fail if AMT took ownership of the device */
 593         if (iwl_pcie_prepare_card_hw(trans)) {
 594                 IWL_WARN(trans, "Exit HW not ready\n");
 595                 return -EIO;
 596         }
 597
 598         iwl_enable_rfkill_int(trans);
 599
 600         /* If platform's RF_KILL switch is NOT set to KILL */
 601         hw_rfkill = iwl_is_rfkill_set(trans);
 602         if (hw_rfkill)
 603                 set_bit(STATUS_RFKILL, &trans->status);
 604         else
 605                 clear_bit(STATUS_RFKILL, &trans->status);
 606         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 607         if (hw_rfkill && !run_in_rfkill)
 608                 return -ERFKILL;
 609
 610         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 611
 612         ret = iwl_pcie_nic_init(trans);
 613         if (ret) {
 614                 IWL_ERR(trans, "Unable to init nic\n");
 615                 return ret;
 616         }
 617
 618         /* make sure rfkill handshake bits are cleared */
 619         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 620         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
 621                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 622
 623         /* clear (again), then enable host interrupts */
 624         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 625         iwl_enable_interrupts(trans);
 626
 627         /* really make sure rfkill handshake bits are cleared */
 628         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 629         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 630
 631         /* Load the given image to the HW */
 632         return iwl_pcie_load_given_ucode(trans, fw);
 633 }
 634
 635 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
 636 {
 637         iwl_pcie_reset_ict(trans);
 638         iwl_pcie_tx_start(trans, scd_addr);
 639 }
 640
 641 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 642 {
 643         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 644         bool hw_rfkill, was_hw_rfkill;
 645
 646         was_hw_rfkill = iwl_is_rfkill_set(trans);
 647
 648         /* tell the device to stop sending interrupts */
 649         spin_lock(&trans_pcie->irq_lock);
 650         iwl_disable_interrupts(trans);
 651         spin_unlock(&trans_pcie->irq_lock);
 652
 653         /* device going down, Stop using ICT table */
 654         iwl_pcie_disable_ict(trans);
 655
 656         /*
 657          * If a HW restart happens during firmware loading,
 658          * then the firmware loading might call this function
 659          * and later it might be called again due to the
 660          * restart. So don't process again if the device is
 661          * already dead.
 662          */
 663         if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
 664                 iwl_pcie_tx_stop(trans);
 665                 iwl_pcie_rx_stop(trans);
 666
 667                 /* Power-down device's busmaster DMA clocks */
 668                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
 669                                APMG_CLK_VAL_DMA_CLK_RQT);
 670                 udelay(5);
 671         }
 672
 673         /* Make sure (redundant) we've released our request to stay awake */
 674         iwl_clear_bit(trans, CSR_GP_CNTRL,
 675                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 676
 677         /* Stop the device, and put it in low power state */
 678         iwl_pcie_apm_stop(trans);
 679
 680         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
 681          * Clean again the interrupt here
 682          */
 683         spin_lock(&trans_pcie->irq_lock);
 684         iwl_disable_interrupts(trans);
 685         spin_unlock(&trans_pcie->irq_lock);
 686
 687         /* stop and reset the on-board processor */
 688         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
 689
 690         /* clear all status bits */
 691         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
 692         clear_bit(STATUS_INT_ENABLED, &trans->status);
 693         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 694         clear_bit(STATUS_TPOWER_PMI, &trans->status);
 695         clear_bit(STATUS_RFKILL, &trans->status);
 696
 697         /*
 698          * Even if we stop the HW, we still want the RF kill
 699          * interrupt
 700          */
 701         iwl_enable_rfkill_int(trans);
 702
 703         /*
 704          * Check again since the RF kill state may have changed while
 705          * all the interrupts were disabled, in this case we couldn't
 706          * receive the RF kill interrupt and update the state in the
 707          * op_mode.
 708          * Don't call the op_mode if the rkfill state hasn't changed.
 709          * This allows the op_mode to call stop_device from the rfkill
 710          * notification without endless recursion. Under very rare
 711          * circumstances, we might have a small recursion if the rfkill
 712          * state changed exactly now while we were called from stop_device.
 713          * This is very unlikely but can happen and is supported.
 714          */
 715         hw_rfkill = iwl_is_rfkill_set(trans);
 716         if (hw_rfkill)
 717                 set_bit(STATUS_RFKILL, &trans->status);
 718         else
 719                 clear_bit(STATUS_RFKILL, &trans->status);
 720         if (hw_rfkill != was_hw_rfkill)
 721                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 722 }
 723
 724 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
 725 {
 726         iwl_disable_interrupts(trans);
 727
 728         /*
 729          * in testing mode, the host stays awake and the
 730          * hardware won't be reset (not even partially)
 731          */
 732         if (test)
 733                 return;
 734
 735         iwl_pcie_disable_ict(trans);
 736
 737         iwl_clear_bit(trans, CSR_GP_CNTRL,
 738                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 739         iwl_clear_bit(trans, CSR_GP_CNTRL,
 740                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 741
 742         /*
 743          * reset TX queues -- some of their registers reset during S3
 744          * so if we don't reset everything here the D3 image would try
 745          * to execute some invalid memory upon resume
 746          */
 747         iwl_trans_pcie_tx_reset(trans);
 748
 749         iwl_pcie_set_pwr(trans, true);
 750 }
 751
 752 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
 753                                     enum iwl_d3_status *status,
 754                                     bool test)
 755 {
 756         u32 val;
 757         int ret;
 758
 759         if (test) {
 760                 iwl_enable_interrupts(trans);
 761                 *status = IWL_D3_STATUS_ALIVE;
 762                 return 0;
 763         }
 764
 765         iwl_pcie_set_pwr(trans, false);
 766
 767         val = iwl_read32(trans, CSR_RESET);
 768         if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
 769                 *status = IWL_D3_STATUS_RESET;
 770                 return 0;
 771         }
 772
 773         /*
 774          * Also enables interrupts - none will happen as the device doesn't
 775          * know we're waking it up, only when the opmode actually tells it
 776          * after this call.
 777          */
 778         iwl_pcie_reset_ict(trans);
 779
 780         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 781         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 782
 783         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 784                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 785                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 786                            25000);
 787         if (ret) {
 788                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
 789                 return ret;
 790         }
 791
 792         iwl_trans_pcie_tx_reset(trans);
 793
 794         ret = iwl_pcie_rx_init(trans);
 795         if (ret) {
 796                 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
 797                 return ret;
 798         }
 799
 800         *status = IWL_D3_STATUS_ALIVE;
 801         return 0;
 802 }
 803
 804 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
 805 {
 806         bool hw_rfkill;
 807         int err;
 808
 809         err = iwl_pcie_prepare_card_hw(trans);
 810         if (err) {
 811                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
 812                 return err;
 813         }
 814
 815         /* Reset the entire device */
 816         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 817
 818         usleep_range(10, 15);
 819
 820         iwl_pcie_apm_init(trans);
 821
 822         /* From now on, the op_mode will be kept updated about RF kill state */
 823         iwl_enable_rfkill_int(trans);
 824
 825         hw_rfkill = iwl_is_rfkill_set(trans);
 826         if (hw_rfkill)
 827                 set_bit(STATUS_RFKILL, &trans->status);
 828         else
 829                 clear_bit(STATUS_RFKILL, &trans->status);
 830         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 831
 832         return 0;
 833 }
 834
 835 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
 836 {
 837         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 838
 839         /* disable interrupts - don't enable HW RF kill interrupt */
 840         spin_lock(&trans_pcie->irq_lock);
 841         iwl_disable_interrupts(trans);
 842         spin_unlock(&trans_pcie->irq_lock);
 843
 844         iwl_pcie_apm_stop(trans);
 845
 846         spin_lock(&trans_pcie->irq_lock);
 847         iwl_disable_interrupts(trans);
 848         spin_unlock(&trans_pcie->irq_lock);
 849
 850         iwl_pcie_disable_ict(trans);
 851 }
 852
 853 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
 854 {
 855         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 856 }
 857
 858 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
 859 {
 860         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 861 }
 862
 863 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
 864 {
 865         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 866 }
 867
 868 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
 869 {
 870         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
 871                                ((reg & 0x000FFFFF) | (3 << 24)));
 872         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
 873 }
 874
 875 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
 876                                       u32 val)
 877 {
 878         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
 879                                ((addr & 0x000FFFFF) | (3 << 24)));
 880         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
 881 }
 882
 883 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
 884                                      const struct iwl_trans_config *trans_cfg)
 885 {
 886         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 887
 888         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
 889         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
 890         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
 891                 trans_pcie->n_no_reclaim_cmds = 0;
 892         else
 893                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
 894         if (trans_pcie->n_no_reclaim_cmds)
 895                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
 896                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
 897
 898         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
 899         if (trans_pcie->rx_buf_size_8k)
 900                 trans_pcie->rx_page_order = get_order(8 * 1024);
 901         else
 902                 trans_pcie->rx_page_order = get_order(4 * 1024);
 903
 904         trans_pcie->wd_timeout =
 905                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
 906
 907         trans_pcie->command_names = trans_cfg->command_names;
 908         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
 909 }
 910
 911 void iwl_trans_pcie_free(struct iwl_trans *trans)
 912 {
 913         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 914
 915         synchronize_irq(trans_pcie->pci_dev->irq);
 916
 917         iwl_pcie_tx_free(trans);
 918         iwl_pcie_rx_free(trans);
 919
 920         free_irq(trans_pcie->pci_dev->irq, trans);
 921         iwl_pcie_free_ict(trans);
 922
 923         pci_disable_msi(trans_pcie->pci_dev);
 924         iounmap(trans_pcie->hw_base);
 925         pci_release_regions(trans_pcie->pci_dev);
 926         pci_disable_device(trans_pcie->pci_dev);
 927         kmem_cache_destroy(trans->dev_cmd_pool);
 928
 929         kfree(trans);
 930 }
 931
 932 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
 933 {
 934         if (state)
 935                 set_bit(STATUS_TPOWER_PMI, &trans->status);
 936         else
 937                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
 938 }
 939
 940 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
 941                                                 unsigned long *flags)
 942 {
 943         int ret;
 944         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 945
 946         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
 947
 948         if (trans_pcie->cmd_in_flight)
 949                 goto out;
 950
 951         /* this bit wakes up the NIC */
 952         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 953                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 954
 955         /*
 956          * These bits say the device is running, and should keep running for
 957          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
 958          * but they do not indicate that embedded SRAM is restored yet;
 959          * 3945 and 4965 have volatile SRAM, and must save/restore contents
 960          * to/from host DRAM when sleeping/waking for power-saving.
 961          * Each direction takes approximately 1/4 millisecond; with this
 962          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
 963          * series of register accesses are expected (e.g. reading Event Log),
 964          * to keep device from sleeping.
 965          *
 966          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
 967          * SRAM is okay/restored.  We don't check that here because this call
 968          * is just for hardware register access; but GP1 MAC_SLEEP check is a
 969          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
 970          *
 971          * 5000 series and later (including 1000 series) have non-volatile SRAM,
 972          * and do not save/restore SRAM when power cycling.
 973          */
 974         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 975                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
 976                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
 977                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
 978         if (unlikely(ret < 0)) {
 979                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
 980                 if (!silent) {
 981                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
 982                         WARN_ONCE(1,
 983                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
 984                                   val);
 985                         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
 986                         return false;
 987                 }
 988         }
 989
 990 out:
 991         /*
 992          * Fool sparse by faking we release the lock - sparse will
 993          * track nic_access anyway.
 994          */
 995         __release(&trans_pcie->reg_lock);
 996         return true;
 997 }
 998
 999 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1000                                               unsigned long *flags)
1001 {
1002         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1003
1004         lockdep_assert_held(&trans_pcie->reg_lock);
1005
1006         /*
1007          * Fool sparse by faking we acquiring the lock - sparse will
1008          * track nic_access anyway.
1009          */
1010         __acquire(&trans_pcie->reg_lock);
1011
1012         if (trans_pcie->cmd_in_flight)
1013                 goto out;
1014
1015         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1016                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1017         /*
1018          * Above we read the CSR_GP_CNTRL register, which will flush
1019          * any previous writes, but we need the write that clears the
1020          * MAC_ACCESS_REQ bit to be performed before any other writes
1021          * scheduled on different CPUs (after we drop reg_lock).
1022          */
1023         mmiowb();
1024 out:
1025         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1026 }
1027
1028 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1029                                    void *buf, int dwords)
1030 {
1031         unsigned long flags;
1032         int offs, ret = 0;
1033         u32 *vals = buf;
1034
1035         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1036                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1037                 for (offs = 0; offs < dwords; offs++)
1038                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1039                 iwl_trans_release_nic_access(trans, &flags);
1040         } else {
1041                 ret = -EBUSY;
1042         }
1043         return ret;
1044 }
1045
1046 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1047                                     const void *buf, int dwords)
1048 {
1049         unsigned long flags;
1050         int offs, ret = 0;
1051         const u32 *vals = buf;
1052
1053         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1054                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1055                 for (offs = 0; offs < dwords; offs++)
1056                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1057                                     vals ? vals[offs] : 0);
1058                 iwl_trans_release_nic_access(trans, &flags);
1059         } else {
1060                 ret = -EBUSY;
1061         }
1062         return ret;
1063 }
1064
1065 #define IWL_FLUSH_WAIT_MS       2000
1066
1067 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
1068 {
1069         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1070         struct iwl_txq *txq;
1071         struct iwl_queue *q;
1072         int cnt;
1073         unsigned long now = jiffies;
1074         u32 scd_sram_addr;
1075         u8 buf[16];
1076         int ret = 0;
1077
1078         /* waiting for all the tx frames complete might take a while */
1079         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1080                 if (cnt == trans_pcie->cmd_queue)
1081                         continue;
1082                 txq = &trans_pcie->txq[cnt];
1083                 q = &txq->q;
1084                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1085                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1086                         msleep(1);
1087
1088                 if (q->read_ptr != q->write_ptr) {
1089                         IWL_ERR(trans,
1090                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1091                         ret = -ETIMEDOUT;
1092                         break;
1093                 }
1094         }
1095
1096         if (!ret)
1097                 return 0;
1098
1099         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1100                 txq->q.read_ptr, txq->q.write_ptr);
1101
1102         scd_sram_addr = trans_pcie->scd_base_addr +
1103                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1104         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1105
1106         iwl_print_hex_error(trans, buf, sizeof(buf));
1107
1108         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1109                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1110                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1111
1112         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1113                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1114                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1115                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1116                 u32 tbl_dw =
1117                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1118                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1119
1120                 if (cnt & 0x1)
1121                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1122                 else
1123                         tbl_dw = tbl_dw & 0x0000FFFF;
1124
1125                 IWL_ERR(trans,
1126                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1127                         cnt, active ? "" : "in", fifo, tbl_dw,
1128                         iwl_read_prph(trans,
1129                                       SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1),
1130                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1131         }
1132
1133         return ret;
1134 }
1135
1136 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1137                                          u32 mask, u32 value)
1138 {
1139         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1140         unsigned long flags;
1141
1142         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1143         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1144         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1145 }
1146
1147 static const char *get_csr_string(int cmd)
1148 {
1149 #define IWL_CMD(x) case x: return #x
1150         switch (cmd) {
1151         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1152         IWL_CMD(CSR_INT_COALESCING);
1153         IWL_CMD(CSR_INT);
1154         IWL_CMD(CSR_INT_MASK);
1155         IWL_CMD(CSR_FH_INT_STATUS);
1156         IWL_CMD(CSR_GPIO_IN);
1157         IWL_CMD(CSR_RESET);
1158         IWL_CMD(CSR_GP_CNTRL);
1159         IWL_CMD(CSR_HW_REV);
1160         IWL_CMD(CSR_EEPROM_REG);
1161         IWL_CMD(CSR_EEPROM_GP);
1162         IWL_CMD(CSR_OTP_GP_REG);
1163         IWL_CMD(CSR_GIO_REG);
1164         IWL_CMD(CSR_GP_UCODE_REG);
1165         IWL_CMD(CSR_GP_DRIVER_REG);
1166         IWL_CMD(CSR_UCODE_DRV_GP1);
1167         IWL_CMD(CSR_UCODE_DRV_GP2);
1168         IWL_CMD(CSR_LED_REG);
1169         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1170         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1171         IWL_CMD(CSR_ANA_PLL_CFG);
1172         IWL_CMD(CSR_HW_REV_WA_REG);
1173         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1174         default:
1175                 return "UNKNOWN";
1176         }
1177 #undef IWL_CMD
1178 }
1179
1180 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1181 {
1182         int i;
1183         static const u32 csr_tbl[] = {
1184                 CSR_HW_IF_CONFIG_REG,
1185                 CSR_INT_COALESCING,
1186                 CSR_INT,
1187                 CSR_INT_MASK,
1188                 CSR_FH_INT_STATUS,
1189                 CSR_GPIO_IN,
1190                 CSR_RESET,
1191                 CSR_GP_CNTRL,
1192                 CSR_HW_REV,
1193                 CSR_EEPROM_REG,
1194                 CSR_EEPROM_GP,
1195                 CSR_OTP_GP_REG,
1196                 CSR_GIO_REG,
1197                 CSR_GP_UCODE_REG,
1198                 CSR_GP_DRIVER_REG,
1199                 CSR_UCODE_DRV_GP1,
1200                 CSR_UCODE_DRV_GP2,
1201                 CSR_LED_REG,
1202                 CSR_DRAM_INT_TBL_REG,
1203                 CSR_GIO_CHICKEN_BITS,
1204                 CSR_ANA_PLL_CFG,
1205                 CSR_HW_REV_WA_REG,
1206                 CSR_DBG_HPET_MEM_REG
1207         };
1208         IWL_ERR(trans, "CSR values:\n");
1209         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1210                 "CSR_INT_PERIODIC_REG)\n");
1211         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1212                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1213                         get_csr_string(csr_tbl[i]),
1214                         iwl_read32(trans, csr_tbl[i]));
1215         }
1216 }
1217
1218 #ifdef CONFIG_IWLWIFI_DEBUGFS
1219 /* create and remove of files */
1220 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1221         if (!debugfs_create_file(#name, mode, parent, trans,            \
1222                                  &iwl_dbgfs_##name##_ops))              \
1223                 goto err;                                               \
1224 } while (0)
1225
1226 /* file operation */
1227 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1228 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1229         .read = iwl_dbgfs_##name##_read,                                \
1230         .open = simple_open,                                            \
1231         .llseek = generic_file_llseek,                                  \
1232 };
1233
1234 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1235 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1236         .write = iwl_dbgfs_##name##_write,                              \
1237         .open = simple_open,                                            \
1238         .llseek = generic_file_llseek,                                  \
1239 };
1240
1241 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1242 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1243         .write = iwl_dbgfs_##name##_write,                              \
1244         .read = iwl_dbgfs_##name##_read,                                \
1245         .open = simple_open,                                            \
1246         .llseek = generic_file_llseek,                                  \
1247 };
1248
1249 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1250                                        char __user *user_buf,
1251                                        size_t count, loff_t *ppos)
1252 {
1253         struct iwl_trans *trans = file->private_data;
1254         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1255         struct iwl_txq *txq;
1256         struct iwl_queue *q;
1257         char *buf;
1258         int pos = 0;
1259         int cnt;
1260         int ret;
1261         size_t bufsz;
1262
1263         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1264
1265         if (!trans_pcie->txq)
1266                 return -EAGAIN;
1267
1268         buf = kzalloc(bufsz, GFP_KERNEL);
1269         if (!buf)
1270                 return -ENOMEM;
1271
1272         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1273                 txq = &trans_pcie->txq[cnt];
1274                 q = &txq->q;
1275                 pos += scnprintf(buf + pos, bufsz - pos,
1276                                 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1277                                 cnt, q->read_ptr, q->write_ptr,
1278                                 !!test_bit(cnt, trans_pcie->queue_used),
1279                                 !!test_bit(cnt, trans_pcie->queue_stopped));
1280         }
1281         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1282         kfree(buf);
1283         return ret;
1284 }
1285
1286 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1287                                        char __user *user_buf,
1288                                        size_t count, loff_t *ppos)
1289 {
1290         struct iwl_trans *trans = file->private_data;
1291         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1292         struct iwl_rxq *rxq = &trans_pcie->rxq;
1293         char buf[256];
1294         int pos = 0;
1295         const size_t bufsz = sizeof(buf);
1296
1297         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1298                                                 rxq->read);
1299         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1300                                                 rxq->write);
1301         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1302                                                 rxq->free_count);
1303         if (rxq->rb_stts) {
1304                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1305                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1306         } else {
1307                 pos += scnprintf(buf + pos, bufsz - pos,
1308                                         "closed_rb_num: Not Allocated\n");
1309         }
1310         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1311 }
1312
1313 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1314                                         char __user *user_buf,
1315                                         size_t count, loff_t *ppos)
1316 {
1317         struct iwl_trans *trans = file->private_data;
1318         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1319         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1320
1321         int pos = 0;
1322         char *buf;
1323         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1324         ssize_t ret;
1325
1326         buf = kzalloc(bufsz, GFP_KERNEL);
1327         if (!buf)
1328                 return -ENOMEM;
1329
1330         pos += scnprintf(buf + pos, bufsz - pos,
1331                         "Interrupt Statistics Report:\n");
1332
1333         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1334                 isr_stats->hw);
1335         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1336                 isr_stats->sw);
1337         if (isr_stats->sw || isr_stats->hw) {
1338                 pos += scnprintf(buf + pos, bufsz - pos,
1339                         "\tLast Restarting Code:  0x%X\n",
1340                         isr_stats->err_code);
1341         }
1342 #ifdef CONFIG_IWLWIFI_DEBUG
1343         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1344                 isr_stats->sch);
1345         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1346                 isr_stats->alive);
1347 #endif
1348         pos += scnprintf(buf + pos, bufsz - pos,
1349                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1350
1351         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1352                 isr_stats->ctkill);
1353
1354         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1355                 isr_stats->wakeup);
1356
1357         pos += scnprintf(buf + pos, bufsz - pos,
1358                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1359
1360         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1361                 isr_stats->tx);
1362
1363         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1364                 isr_stats->unhandled);
1365
1366         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1367         kfree(buf);
1368         return ret;
1369 }
1370
1371 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1372                                          const char __user *user_buf,
1373                                          size_t count, loff_t *ppos)
1374 {
1375         struct iwl_trans *trans = file->private_data;
1376         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1377         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1378
1379         char buf[8];
1380         int buf_size;
1381         u32 reset_flag;
1382
1383         memset(buf, 0, sizeof(buf));
1384         buf_size = min(count, sizeof(buf) -  1);
1385         if (copy_from_user(buf, user_buf, buf_size))
1386                 return -EFAULT;
1387         if (sscanf(buf, "%x", &reset_flag) != 1)
1388                 return -EFAULT;
1389         if (reset_flag == 0)
1390                 memset(isr_stats, 0, sizeof(*isr_stats));
1391
1392         return count;
1393 }
1394
1395 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1396                                    const char __user *user_buf,
1397                                    size_t count, loff_t *ppos)
1398 {
1399         struct iwl_trans *trans = file->private_data;
1400         char buf[8];
1401         int buf_size;
1402         int csr;
1403
1404         memset(buf, 0, sizeof(buf));
1405         buf_size = min(count, sizeof(buf) -  1);
1406         if (copy_from_user(buf, user_buf, buf_size))
1407                 return -EFAULT;
1408         if (sscanf(buf, "%d", &csr) != 1)
1409                 return -EFAULT;
1410
1411         iwl_pcie_dump_csr(trans);
1412
1413         return count;
1414 }
1415
1416 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1417                                      char __user *user_buf,
1418                                      size_t count, loff_t *ppos)
1419 {
1420         struct iwl_trans *trans = file->private_data;
1421         char *buf = NULL;
1422         int pos = 0;
1423         ssize_t ret = -EFAULT;
1424
1425         ret = pos = iwl_dump_fh(trans, &buf);
1426         if (buf) {
1427                 ret = simple_read_from_buffer(user_buf,
1428                                               count, ppos, buf, pos);
1429                 kfree(buf);
1430         }
1431
1432         return ret;
1433 }
1434
1435 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1436 DEBUGFS_READ_FILE_OPS(fh_reg);
1437 DEBUGFS_READ_FILE_OPS(rx_queue);
1438 DEBUGFS_READ_FILE_OPS(tx_queue);
1439 DEBUGFS_WRITE_FILE_OPS(csr);
1440
1441 /*
1442  * Create the debugfs files and directories
1443  *
1444  */
1445 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1446                                          struct dentry *dir)
1447 {
1448         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1449         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1450         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1451         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1452         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1453         return 0;
1454
1455 err:
1456         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1457         return -ENOMEM;
1458 }
1459 #else
1460 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1461                                          struct dentry *dir)
1462 {
1463         return 0;
1464 }
1465 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1466
1467 static const struct iwl_trans_ops trans_ops_pcie = {
1468         .start_hw = iwl_trans_pcie_start_hw,
1469         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
1470         .fw_alive = iwl_trans_pcie_fw_alive,
1471         .start_fw = iwl_trans_pcie_start_fw,
1472         .stop_device = iwl_trans_pcie_stop_device,
1473
1474         .d3_suspend = iwl_trans_pcie_d3_suspend,
1475         .d3_resume = iwl_trans_pcie_d3_resume,
1476
1477         .send_cmd = iwl_trans_pcie_send_hcmd,
1478
1479         .tx = iwl_trans_pcie_tx,
1480         .reclaim = iwl_trans_pcie_reclaim,
1481
1482         .txq_disable = iwl_trans_pcie_txq_disable,
1483         .txq_enable = iwl_trans_pcie_txq_enable,
1484
1485         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1486
1487         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
1488
1489         .write8 = iwl_trans_pcie_write8,
1490         .write32 = iwl_trans_pcie_write32,
1491         .read32 = iwl_trans_pcie_read32,
1492         .read_prph = iwl_trans_pcie_read_prph,
1493         .write_prph = iwl_trans_pcie_write_prph,
1494         .read_mem = iwl_trans_pcie_read_mem,
1495         .write_mem = iwl_trans_pcie_write_mem,
1496         .configure = iwl_trans_pcie_configure,
1497         .set_pmi = iwl_trans_pcie_set_pmi,
1498         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
1499         .release_nic_access = iwl_trans_pcie_release_nic_access,
1500         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
1501 };
1502
1503 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
1504                                        const struct pci_device_id *ent,
1505                                        const struct iwl_cfg *cfg)
1506 {
1507         struct iwl_trans_pcie *trans_pcie;
1508         struct iwl_trans *trans;
1509         u16 pci_cmd;
1510         int err;
1511
1512         trans = kzalloc(sizeof(struct iwl_trans) +
1513                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
1514         if (!trans) {
1515                 err = -ENOMEM;
1516                 goto out;
1517         }
1518
1519         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1520
1521         trans->ops = &trans_ops_pcie;
1522         trans->cfg = cfg;
1523         trans_lockdep_init(trans);
1524         trans_pcie->trans = trans;
1525         spin_lock_init(&trans_pcie->irq_lock);
1526         spin_lock_init(&trans_pcie->reg_lock);
1527         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
1528
1529         err = pci_enable_device(pdev);
1530         if (err)
1531                 goto out_no_pci;
1532
1533         if (!cfg->base_params->pcie_l1_allowed) {
1534                 /*
1535                  * W/A - seems to solve weird behavior. We need to remove this
1536                  * if we don't want to stay in L1 all the time. This wastes a
1537                  * lot of power.
1538                  */
1539                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
1540                                        PCIE_LINK_STATE_L1 |
1541                                        PCIE_LINK_STATE_CLKPM);
1542         }
1543
1544         pci_set_master(pdev);
1545
1546         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
1547         if (!err)
1548                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
1549         if (err) {
1550                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1551                 if (!err)
1552                         err = pci_set_consistent_dma_mask(pdev,
1553                                                           DMA_BIT_MASK(32));
1554                 /* both attempts failed: */
1555                 if (err) {
1556                         dev_err(&pdev->dev, "No suitable DMA available\n");
1557                         goto out_pci_disable_device;
1558                 }
1559         }
1560
1561         err = pci_request_regions(pdev, DRV_NAME);
1562         if (err) {
1563                 dev_err(&pdev->dev, "pci_request_regions failed\n");
1564                 goto out_pci_disable_device;
1565         }
1566
1567         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
1568         if (!trans_pcie->hw_base) {
1569                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
1570                 err = -ENODEV;
1571                 goto out_pci_release_regions;
1572         }
1573
1574         /* We disable the RETRY_TIMEOUT register (0x41) to keep
1575          * PCI Tx retries from interfering with C3 CPU state */
1576         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
1577
1578         err = pci_enable_msi(pdev);
1579         if (err) {
1580                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
1581                 /* enable rfkill interrupt: hw bug w/a */
1582                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1583                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1584                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1585                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1586                 }
1587         }
1588
1589         trans->dev = &pdev->dev;
1590         trans_pcie->pci_dev = pdev;
1591         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
1592         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
1593         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
1594                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
1595
1596         /* Initialize the wait queue for commands */
1597         init_waitqueue_head(&trans_pcie->wait_command_queue);
1598
1599         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
1600                  "iwl_cmd_pool:%s", dev_name(trans->dev));
1601
1602         trans->dev_cmd_headroom = 0;
1603         trans->dev_cmd_pool =
1604                 kmem_cache_create(trans->dev_cmd_pool_name,
1605                                   sizeof(struct iwl_device_cmd)
1606                                   + trans->dev_cmd_headroom,
1607                                   sizeof(void *),
1608                                   SLAB_HWCACHE_ALIGN,
1609                                   NULL);
1610
1611         if (!trans->dev_cmd_pool) {
1612                 err = -ENOMEM;
1613                 goto out_pci_disable_msi;
1614         }
1615
1616         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1617
1618         if (iwl_pcie_alloc_ict(trans))
1619                 goto out_free_cmd_pool;
1620
1621         err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
1622                                    iwl_pcie_irq_handler,
1623                                    IRQF_SHARED, DRV_NAME, trans);
1624         if (err) {
1625                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
1626                 goto out_free_ict;
1627         }
1628
1629         return trans;
1630
1631 out_free_ict:
1632         iwl_pcie_free_ict(trans);
1633 out_free_cmd_pool:
1634         kmem_cache_destroy(trans->dev_cmd_pool);
1635 out_pci_disable_msi:
1636         pci_disable_msi(pdev);
1637 out_pci_release_regions:
1638         pci_release_regions(pdev);
1639 out_pci_disable_device:
1640         pci_disable_device(pdev);
1641 out_no_pci:
1642         kfree(trans);
1643 out:
1644         return ERR_PTR(err);
1645 }