drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
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   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of version 2 of the GNU General Public License as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
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  29  *  Intel Linux Wireless <ilw@linux.intel.com>
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  33  *
  34  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
  35  * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
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  39  * modification, are permitted provided that the following conditions
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  43  *    notice, this list of conditions and the following disclaimer.
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  46  *    the documentation and/or other materials provided with the
  47  *    distribution.
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  49  *    contributors may be used to endorse or promote products derived
  50  *    from this software without specific prior written permission.
  51  *
  52  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  53  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  54  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  55  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  56  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  61  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  62  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  63  *
  64  *****************************************************************************/
  65 #include <linux/pci.h>
  66 #include <linux/pci-aspm.h>
  67 #include <linux/interrupt.h>
  68 #include <linux/debugfs.h>
  69 #include <linux/sched.h>
  70 #include <linux/bitops.h>
  71 #include <linux/gfp.h>
  72 #include <linux/vmalloc.h>
  73
  74 #include "iwl-drv.h"
  75 #include "iwl-trans.h"
  76 #include "iwl-csr.h"
  77 #include "iwl-prph.h"
  78 #include "iwl-agn-hw.h"
  79 #include "iwl-fw-error-dump.h"
  80 #include "internal.h"
  81
  82 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
  83 {
  84         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  85
  86         if (!trans_pcie->fw_mon_page)
  87                 return;
  88
  89         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
  90                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
  91         __free_pages(trans_pcie->fw_mon_page,
  92                      get_order(trans_pcie->fw_mon_size));
  93         trans_pcie->fw_mon_page = NULL;
  94         trans_pcie->fw_mon_phys = 0;
  95         trans_pcie->fw_mon_size = 0;
  96 }
  97
  98 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans)
  99 {
 100         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 101         struct page *page;
 102         dma_addr_t phys;
 103         u32 size;
 104         u8 power;
 105
 106         if (trans_pcie->fw_mon_page) {
 107                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 108                                            trans_pcie->fw_mon_size,
 109                                            DMA_FROM_DEVICE);
 110                 return;
 111         }
 112
 113         phys = 0;
 114         for (power = 26; power >= 11; power--) {
 115                 int order;
 116
 117                 size = BIT(power);
 118                 order = get_order(size);
 119                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 120                                    order);
 121                 if (!page)
 122                         continue;
 123
 124                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 125                                     DMA_FROM_DEVICE);
 126                 if (dma_mapping_error(trans->dev, phys)) {
 127                         __free_pages(page, order);
 128                         continue;
 129                 }
 130                 IWL_INFO(trans,
 131                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 132                          size, order);
 133                 break;
 134         }
 135
 136         if (!page)
 137                 return;
 138
 139         trans_pcie->fw_mon_page = page;
 140         trans_pcie->fw_mon_phys = phys;
 141         trans_pcie->fw_mon_size = size;
 142 }
 143
 144 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 145 {
 146         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 147                     ((reg & 0x0000ffff) | (2 << 28)));
 148         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 149 }
 150
 151 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 152 {
 153         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 154         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 155                     ((reg & 0x0000ffff) | (3 << 28)));
 156 }
 157
 158 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 159 {
 160         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 161                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 162                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 163                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 164         else
 165                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 166                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 167                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 168 }
 169
 170 /* PCI registers */
 171 #define PCI_CFG_RETRY_TIMEOUT   0x041
 172
 173 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 174 {
 175         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 176         u16 lctl;
 177
 178         /*
 179          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 180          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 181          * If so (likely), disable L0S, so device moves directly L0->L1;
 182          *    costs negligible amount of power savings.
 183          * If not (unlikely), enable L0S, so there is at least some
 184          *    power savings, even without L1.
 185          */
 186         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 187         if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
 188                 /* L1-ASPM enabled; disable(!) L0S */
 189                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 190                 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
 191         } else {
 192                 /* L1-ASPM disabled; enable(!) L0S */
 193                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 194                 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
 195         }
 196         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 197 }
 198
 199 /*
 200  * Start up NIC's basic functionality after it has been reset
 201  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 202  * NOTE:  This does not load uCode nor start the embedded processor
 203  */
 204 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 205 {
 206         int ret = 0;
 207         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 208
 209         /*
 210          * Use "set_bit" below rather than "write", to preserve any hardware
 211          * bits already set by default after reset.
 212          */
 213
 214         /* Disable L0S exit timer (platform NMI Work/Around) */
 215         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 216                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 217                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 218
 219         /*
 220          * Disable L0s without affecting L1;
 221          *  don't wait for ICH L0s (ICH bug W/A)
 222          */
 223         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 224                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 225
 226         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 227         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 228
 229         /*
 230          * Enable HAP INTA (interrupt from management bus) to
 231          * wake device's PCI Express link L1a -> L0s
 232          */
 233         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 234                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 235
 236         iwl_pcie_apm_config(trans);
 237
 238         /* Configure analog phase-lock-loop before activating to D0A */
 239         if (trans->cfg->base_params->pll_cfg_val)
 240                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 241                             trans->cfg->base_params->pll_cfg_val);
 242
 243         /*
 244          * Set "initialization complete" bit to move adapter from
 245          * D0U* --> D0A* (powered-up active) state.
 246          */
 247         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 248
 249         /*
 250          * Wait for clock stabilization; once stabilized, access to
 251          * device-internal resources is supported, e.g. iwl_write_prph()
 252          * and accesses to uCode SRAM.
 253          */
 254         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 255                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 256                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 257         if (ret < 0) {
 258                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 259                 goto out;
 260         }
 261
 262         if (trans->cfg->host_interrupt_operation_mode) {
 263                 /*
 264                  * This is a bit of an abuse - This is needed for 7260 / 3160
 265                  * only check host_interrupt_operation_mode even if this is
 266                  * not related to host_interrupt_operation_mode.
 267                  *
 268                  * Enable the oscillator to count wake up time for L1 exit. This
 269                  * consumes slightly more power (100uA) - but allows to be sure
 270                  * that we wake up from L1 on time.
 271                  *
 272                  * This looks weird: read twice the same register, discard the
 273                  * value, set a bit, and yet again, read that same register
 274                  * just to discard the value. But that's the way the hardware
 275                  * seems to like it.
 276                  */
 277                 iwl_read_prph(trans, OSC_CLK);
 278                 iwl_read_prph(trans, OSC_CLK);
 279                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 280                 iwl_read_prph(trans, OSC_CLK);
 281                 iwl_read_prph(trans, OSC_CLK);
 282         }
 283
 284         /*
 285          * Enable DMA clock and wait for it to stabilize.
 286          *
 287          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 288          * bits do not disable clocks.  This preserves any hardware
 289          * bits already set by default in "CLK_CTRL_REG" after reset.
 290          */
 291         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
 292                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 293                                APMG_CLK_VAL_DMA_CLK_RQT);
 294                 udelay(20);
 295
 296                 /* Disable L1-Active */
 297                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 298                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 299
 300                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 301                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 302                                APMG_RTC_INT_STT_RFKILL);
 303         }
 304
 305         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 306
 307 out:
 308         return ret;
 309 }
 310
 311 /*
 312  * Enable LP XTAL to avoid HW bug where device may consume much power if
 313  * FW is not loaded after device reset. LP XTAL is disabled by default
 314  * after device HW reset. Do it only if XTAL is fed by internal source.
 315  * Configure device's "persistence" mode to avoid resetting XTAL again when
 316  * SHRD_HW_RST occurs in S3.
 317  */
 318 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 319 {
 320         int ret;
 321         u32 apmg_gp1_reg;
 322         u32 apmg_xtal_cfg_reg;
 323         u32 dl_cfg_reg;
 324
 325         /* Force XTAL ON */
 326         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 327                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 328
 329         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 330         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 331
 332         udelay(10);
 333
 334         /*
 335          * Set "initialization complete" bit to move adapter from
 336          * D0U* --> D0A* (powered-up active) state.
 337          */
 338         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 339
 340         /*
 341          * Wait for clock stabilization; once stabilized, access to
 342          * device-internal resources is possible.
 343          */
 344         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 345                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 346                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 347                            25000);
 348         if (WARN_ON(ret < 0)) {
 349                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 350                 /* Release XTAL ON request */
 351                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 352                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 353                 return;
 354         }
 355
 356         /*
 357          * Clear "disable persistence" to avoid LP XTAL resetting when
 358          * SHRD_HW_RST is applied in S3.
 359          */
 360         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 361                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 362
 363         /*
 364          * Force APMG XTAL to be active to prevent its disabling by HW
 365          * caused by APMG idle state.
 366          */
 367         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 368                                                     SHR_APMG_XTAL_CFG_REG);
 369         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 370                                  apmg_xtal_cfg_reg |
 371                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 372
 373         /*
 374          * Reset entire device again - do controller reset (results in
 375          * SHRD_HW_RST). Turn MAC off before proceeding.
 376          */
 377         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 378
 379         udelay(10);
 380
 381         /* Enable LP XTAL by indirect access through CSR */
 382         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 383         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 384                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 385                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 386
 387         /* Clear delay line clock power up */
 388         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 389         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 390                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 391
 392         /*
 393          * Enable persistence mode to avoid LP XTAL resetting when
 394          * SHRD_HW_RST is applied in S3.
 395          */
 396         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 397                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 398
 399         /*
 400          * Clear "initialization complete" bit to move adapter from
 401          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 402          */
 403         iwl_clear_bit(trans, CSR_GP_CNTRL,
 404                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 405
 406         /* Activates XTAL resources monitor */
 407         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 408                                  CSR_MONITOR_XTAL_RESOURCES);
 409
 410         /* Release XTAL ON request */
 411         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 412                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 413         udelay(10);
 414
 415         /* Release APMG XTAL */
 416         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 417                                  apmg_xtal_cfg_reg &
 418                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 419 }
 420
 421 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 422 {
 423         int ret = 0;
 424
 425         /* stop device's busmaster DMA activity */
 426         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 427
 428         ret = iwl_poll_bit(trans, CSR_RESET,
 429                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 430                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 431         if (ret)
 432                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 433
 434         IWL_DEBUG_INFO(trans, "stop master\n");
 435
 436         return ret;
 437 }
 438
 439 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
 440 {
 441         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 442
 443         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 444
 445         /* Stop device's DMA activity */
 446         iwl_pcie_apm_stop_master(trans);
 447
 448         if (trans->cfg->lp_xtal_workaround) {
 449                 iwl_pcie_apm_lp_xtal_enable(trans);
 450                 return;
 451         }
 452
 453         /* Reset the entire device */
 454         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 455
 456         udelay(10);
 457
 458         /*
 459          * Clear "initialization complete" bit to move adapter from
 460          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 461          */
 462         iwl_clear_bit(trans, CSR_GP_CNTRL,
 463                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 464 }
 465
 466 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 467 {
 468         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 469
 470         /* nic_init */
 471         spin_lock(&trans_pcie->irq_lock);
 472         iwl_pcie_apm_init(trans);
 473
 474         spin_unlock(&trans_pcie->irq_lock);
 475
 476         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 477                 iwl_pcie_set_pwr(trans, false);
 478
 479         iwl_op_mode_nic_config(trans->op_mode);
 480
 481         /* Allocate the RX queue, or reset if it is already allocated */
 482         iwl_pcie_rx_init(trans);
 483
 484         /* Allocate or reset and init all Tx and Command queues */
 485         if (iwl_pcie_tx_init(trans))
 486                 return -ENOMEM;
 487
 488         if (trans->cfg->base_params->shadow_reg_enable) {
 489                 /* enable shadow regs in HW */
 490                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 491                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 492         }
 493
 494         return 0;
 495 }
 496
 497 #define HW_READY_TIMEOUT (50)
 498
 499 /* Note: returns poll_bit return value, which is >= 0 if success */
 500 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 501 {
 502         int ret;
 503
 504         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 505                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 506
 507         /* See if we got it */
 508         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 509                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 510                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 511                            HW_READY_TIMEOUT);
 512
 513         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 514         return ret;
 515 }
 516
 517 /* Note: returns standard 0/-ERROR code */
 518 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 519 {
 520         int ret;
 521         int t = 0;
 522         int iter;
 523
 524         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 525
 526         ret = iwl_pcie_set_hw_ready(trans);
 527         /* If the card is ready, exit 0 */
 528         if (ret >= 0)
 529                 return 0;
 530
 531         for (iter = 0; iter < 10; iter++) {
 532                 /* If HW is not ready, prepare the conditions to check again */
 533                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 534                             CSR_HW_IF_CONFIG_REG_PREPARE);
 535
 536                 do {
 537                         ret = iwl_pcie_set_hw_ready(trans);
 538                         if (ret >= 0)
 539                                 return 0;
 540
 541                         usleep_range(200, 1000);
 542                         t += 200;
 543                 } while (t < 150000);
 544                 msleep(25);
 545         }
 546
 547         IWL_DEBUG_INFO(trans, "got NIC after %d iterations\n", iter);
 548
 549         return ret;
 550 }
 551
 552 /*
 553  * ucode
 554  */
 555 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 556                                    dma_addr_t phy_addr, u32 byte_cnt)
 557 {
 558         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 559         int ret;
 560
 561         trans_pcie->ucode_write_complete = false;
 562
 563         iwl_write_direct32(trans,
 564                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 565                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 566
 567         iwl_write_direct32(trans,
 568                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 569                            dst_addr);
 570
 571         iwl_write_direct32(trans,
 572                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 573                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 574
 575         iwl_write_direct32(trans,
 576                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 577                            (iwl_get_dma_hi_addr(phy_addr)
 578                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 579
 580         iwl_write_direct32(trans,
 581                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 582                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 583                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 584                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 585
 586         iwl_write_direct32(trans,
 587                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 588                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 589                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 590                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 591
 592         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 593                                  trans_pcie->ucode_write_complete, 5 * HZ);
 594         if (!ret) {
 595                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 596                 return -ETIMEDOUT;
 597         }
 598
 599         return 0;
 600 }
 601
 602 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 603                             const struct fw_desc *section)
 604 {
 605         u8 *v_addr;
 606         dma_addr_t p_addr;
 607         u32 offset, chunk_sz = section->len;
 608         int ret = 0;
 609
 610         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 611                      section_num);
 612
 613         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 614                                     GFP_KERNEL | __GFP_NOWARN);
 615         if (!v_addr) {
 616                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 617                 chunk_sz = PAGE_SIZE;
 618                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 619                                             &p_addr, GFP_KERNEL);
 620                 if (!v_addr)
 621                         return -ENOMEM;
 622         }
 623
 624         for (offset = 0; offset < section->len; offset += chunk_sz) {
 625                 u32 copy_size;
 626
 627                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 628
 629                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 630                 ret = iwl_pcie_load_firmware_chunk(trans,
 631                                                    section->offset + offset,
 632                                                    p_addr, copy_size);
 633                 if (ret) {
 634                         IWL_ERR(trans,
 635                                 "Could not load the [%d] uCode section\n",
 636                                 section_num);
 637                         break;
 638                 }
 639         }
 640
 641         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 642         return ret;
 643 }
 644
 645 static int iwl_pcie_load_cpu_secured_sections(struct iwl_trans *trans,
 646                                               const struct fw_img *image,
 647                                               int cpu,
 648                                               int *first_ucode_section)
 649 {
 650         int shift_param;
 651         int i, ret = 0;
 652         u32 last_read_idx = 0;
 653
 654         if (cpu == 1) {
 655                 shift_param = 0;
 656                 *first_ucode_section = 0;
 657         } else {
 658                 shift_param = 16;
 659                 (*first_ucode_section)++;
 660         }
 661
 662         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 663                 last_read_idx = i;
 664
 665                 if (!image->sec[i].data ||
 666                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 667                         IWL_DEBUG_FW(trans,
 668                                      "Break since Data not valid or Empty section, sec = %d\n",
 669                                      i);
 670                         break;
 671                 }
 672
 673                 if (i == (*first_ucode_section) + 1)
 674                         /* set CPU to started */
 675                         iwl_set_bits_prph(trans,
 676                                           CSR_UCODE_LOAD_STATUS_ADDR,
 677                                           LMPM_CPU_HDRS_LOADING_COMPLETED
 678                                           << shift_param);
 679
 680                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 681                 if (ret)
 682                         return ret;
 683         }
 684         /* image loading complete */
 685         iwl_set_bits_prph(trans,
 686                           CSR_UCODE_LOAD_STATUS_ADDR,
 687                           LMPM_CPU_UCODE_LOADING_COMPLETED << shift_param);
 688
 689         *first_ucode_section = last_read_idx;
 690
 691         return 0;
 692 }
 693
 694 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 695                                       const struct fw_img *image,
 696                                       int cpu,
 697                                       int *first_ucode_section)
 698 {
 699         int shift_param;
 700         int i, ret = 0;
 701         u32 last_read_idx = 0;
 702
 703         if (cpu == 1) {
 704                 shift_param = 0;
 705                 *first_ucode_section = 0;
 706         } else {
 707                 shift_param = 16;
 708                 (*first_ucode_section)++;
 709         }
 710
 711         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 712                 last_read_idx = i;
 713
 714                 if (!image->sec[i].data ||
 715                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 716                         IWL_DEBUG_FW(trans,
 717                                      "Break since Data not valid or Empty section, sec = %d\n",
 718                                      i);
 719                         break;
 720                 }
 721
 722                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 723                 if (ret)
 724                         return ret;
 725         }
 726
 727         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 728                 iwl_set_bits_prph(trans,
 729                                   CSR_UCODE_LOAD_STATUS_ADDR,
 730                                   (LMPM_CPU_UCODE_LOADING_COMPLETED |
 731                                    LMPM_CPU_HDRS_LOADING_COMPLETED |
 732                                    LMPM_CPU_UCODE_LOADING_STARTED) <<
 733                                         shift_param);
 734
 735         *first_ucode_section = last_read_idx;
 736
 737         return 0;
 738 }
 739
 740 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 741                                 const struct fw_img *image)
 742 {
 743         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 744         int ret = 0;
 745         int first_ucode_section;
 746
 747         IWL_DEBUG_FW(trans,
 748                      "working with %s image\n",
 749                      image->is_secure ? "Secured" : "Non Secured");
 750         IWL_DEBUG_FW(trans,
 751                      "working with %s CPU\n",
 752                      image->is_dual_cpus ? "Dual" : "Single");
 753
 754         /* configure the ucode to be ready to get the secured image */
 755         if (image->is_secure) {
 756                 /* set secure boot inspector addresses */
 757                 iwl_write_prph(trans,
 758                                LMPM_SECURE_INSPECTOR_CODE_ADDR,
 759                                LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE);
 760
 761                 iwl_write_prph(trans,
 762                                LMPM_SECURE_INSPECTOR_DATA_ADDR,
 763                                LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE);
 764
 765                 /* set CPU1 header address */
 766                 iwl_write_prph(trans,
 767                                LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR,
 768                                LMPM_SECURE_CPU1_HDR_MEM_SPACE);
 769
 770                 /* load to FW the binary Secured sections of CPU1 */
 771                 ret = iwl_pcie_load_cpu_secured_sections(trans, image, 1,
 772                                                          &first_ucode_section);
 773                 if (ret)
 774                         return ret;
 775
 776         } else {
 777                 /* load to FW the binary Non secured sections of CPU1 */
 778                 ret = iwl_pcie_load_cpu_sections(trans, image, 1,
 779                                                  &first_ucode_section);
 780                 if (ret)
 781                         return ret;
 782         }
 783
 784         if (image->is_dual_cpus) {
 785                 /* set CPU2 header address */
 786                 iwl_write_prph(trans,
 787                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
 788                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
 789
 790                 /* load to FW the binary sections of CPU2 */
 791                 if (image->is_secure)
 792                         ret = iwl_pcie_load_cpu_secured_sections(
 793                                                         trans, image, 2,
 794                                                         &first_ucode_section);
 795                 else
 796                         ret = iwl_pcie_load_cpu_sections(trans, image, 2,
 797                                                          &first_ucode_section);
 798                 if (ret)
 799                         return ret;
 800         }
 801
 802         /* supported for 7000 only for the moment */
 803         if (iwlwifi_mod_params.fw_monitor &&
 804             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
 805                 iwl_pcie_alloc_fw_monitor(trans);
 806
 807                 if (trans_pcie->fw_mon_size) {
 808                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
 809                                        trans_pcie->fw_mon_phys >> 4);
 810                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
 811                                        (trans_pcie->fw_mon_phys +
 812                                         trans_pcie->fw_mon_size) >> 4);
 813                 }
 814         }
 815
 816         /* release CPU reset */
 817         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 818                 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
 819         else
 820                 iwl_write32(trans, CSR_RESET, 0);
 821
 822         if (image->is_secure) {
 823                 /* wait for image verification to complete  */
 824                 ret = iwl_poll_prph_bit(trans,
 825                                         LMPM_SECURE_BOOT_CPU1_STATUS_ADDR,
 826                                         LMPM_SECURE_BOOT_STATUS_SUCCESS,
 827                                         LMPM_SECURE_BOOT_STATUS_SUCCESS,
 828                                         LMPM_SECURE_TIME_OUT);
 829
 830                 if (ret < 0) {
 831                         IWL_ERR(trans, "Time out on secure boot process\n");
 832                         return ret;
 833                 }
 834         }
 835
 836         return 0;
 837 }
 838
 839 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 840                                    const struct fw_img *fw, bool run_in_rfkill)
 841 {
 842         int ret;
 843         bool hw_rfkill;
 844
 845         /* This may fail if AMT took ownership of the device */
 846         if (iwl_pcie_prepare_card_hw(trans)) {
 847                 IWL_WARN(trans, "Exit HW not ready\n");
 848                 return -EIO;
 849         }
 850
 851         iwl_enable_rfkill_int(trans);
 852
 853         /* If platform's RF_KILL switch is NOT set to KILL */
 854         hw_rfkill = iwl_is_rfkill_set(trans);
 855         if (hw_rfkill)
 856                 set_bit(STATUS_RFKILL, &trans->status);
 857         else
 858                 clear_bit(STATUS_RFKILL, &trans->status);
 859         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
 860         if (hw_rfkill && !run_in_rfkill)
 861                 return -ERFKILL;
 862
 863         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 864
 865         ret = iwl_pcie_nic_init(trans);
 866         if (ret) {
 867                 IWL_ERR(trans, "Unable to init nic\n");
 868                 return ret;
 869         }
 870
 871         /* make sure rfkill handshake bits are cleared */
 872         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 873         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
 874                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 875
 876         /* clear (again), then enable host interrupts */
 877         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 878         iwl_enable_interrupts(trans);
 879
 880         /* really make sure rfkill handshake bits are cleared */
 881         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 882         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 883
 884         /* Load the given image to the HW */
 885         return iwl_pcie_load_given_ucode(trans, fw);
 886 }
 887
 888 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
 889 {
 890         iwl_pcie_reset_ict(trans);
 891         iwl_pcie_tx_start(trans, scd_addr);
 892 }
 893
 894 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 895 {
 896         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 897         bool hw_rfkill, was_hw_rfkill;
 898
 899         was_hw_rfkill = iwl_is_rfkill_set(trans);
 900
 901         /* tell the device to stop sending interrupts */
 902         spin_lock(&trans_pcie->irq_lock);
 903         iwl_disable_interrupts(trans);
 904         spin_unlock(&trans_pcie->irq_lock);
 905
 906         /* device going down, Stop using ICT table */
 907         iwl_pcie_disable_ict(trans);
 908
 909         /*
 910          * If a HW restart happens during firmware loading,
 911          * then the firmware loading might call this function
 912          * and later it might be called again due to the
 913          * restart. So don't process again if the device is
 914          * already dead.
 915          */
 916         if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
 917                 iwl_pcie_tx_stop(trans);
 918                 iwl_pcie_rx_stop(trans);
 919
 920                 /* Power-down device's busmaster DMA clocks */
 921                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
 922                                APMG_CLK_VAL_DMA_CLK_RQT);
 923                 udelay(5);
 924         }
 925
 926         /* Make sure (redundant) we've released our request to stay awake */
 927         iwl_clear_bit(trans, CSR_GP_CNTRL,
 928                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 929
 930         /* Stop the device, and put it in low power state */
 931         iwl_pcie_apm_stop(trans);
 932
 933         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
 934          * Clean again the interrupt here
 935          */
 936         spin_lock(&trans_pcie->irq_lock);
 937         iwl_disable_interrupts(trans);
 938         spin_unlock(&trans_pcie->irq_lock);
 939
 940         /* stop and reset the on-board processor */
 941         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
 942
 943         /* clear all status bits */
 944         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
 945         clear_bit(STATUS_INT_ENABLED, &trans->status);
 946         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 947         clear_bit(STATUS_TPOWER_PMI, &trans->status);
 948         clear_bit(STATUS_RFKILL, &trans->status);
 949
 950         /*
 951          * Even if we stop the HW, we still want the RF kill
 952          * interrupt
 953          */
 954         iwl_enable_rfkill_int(trans);
 955
 956         /*
 957          * Check again since the RF kill state may have changed while
 958          * all the interrupts were disabled, in this case we couldn't
 959          * receive the RF kill interrupt and update the state in the
 960          * op_mode.
 961          * Don't call the op_mode if the rkfill state hasn't changed.
 962          * This allows the op_mode to call stop_device from the rfkill
 963          * notification without endless recursion. Under very rare
 964          * circumstances, we might have a small recursion if the rfkill
 965          * state changed exactly now while we were called from stop_device.
 966          * This is very unlikely but can happen and is supported.
 967          */
 968         hw_rfkill = iwl_is_rfkill_set(trans);
 969         if (hw_rfkill)
 970                 set_bit(STATUS_RFKILL, &trans->status);
 971         else
 972                 clear_bit(STATUS_RFKILL, &trans->status);
 973         if (hw_rfkill != was_hw_rfkill)
 974                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
 975 }
 976
 977 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
 978 {
 979         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
 980                 iwl_trans_pcie_stop_device(trans);
 981 }
 982
 983 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
 984 {
 985         iwl_disable_interrupts(trans);
 986
 987         /*
 988          * in testing mode, the host stays awake and the
 989          * hardware won't be reset (not even partially)
 990          */
 991         if (test)
 992                 return;
 993
 994         iwl_pcie_disable_ict(trans);
 995
 996         iwl_clear_bit(trans, CSR_GP_CNTRL,
 997                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 998         iwl_clear_bit(trans, CSR_GP_CNTRL,
 999                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1000
1001         /*
1002          * reset TX queues -- some of their registers reset during S3
1003          * so if we don't reset everything here the D3 image would try
1004          * to execute some invalid memory upon resume
1005          */
1006         iwl_trans_pcie_tx_reset(trans);
1007
1008         iwl_pcie_set_pwr(trans, true);
1009 }
1010
1011 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1012                                     enum iwl_d3_status *status,
1013                                     bool test)
1014 {
1015         u32 val;
1016         int ret;
1017
1018         if (test) {
1019                 iwl_enable_interrupts(trans);
1020                 *status = IWL_D3_STATUS_ALIVE;
1021                 return 0;
1022         }
1023
1024         iwl_pcie_set_pwr(trans, false);
1025
1026         val = iwl_read32(trans, CSR_RESET);
1027         if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
1028                 *status = IWL_D3_STATUS_RESET;
1029                 return 0;
1030         }
1031
1032         /*
1033          * Also enables interrupts - none will happen as the device doesn't
1034          * know we're waking it up, only when the opmode actually tells it
1035          * after this call.
1036          */
1037         iwl_pcie_reset_ict(trans);
1038
1039         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1040         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1041
1042         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1043                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1044                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1045                            25000);
1046         if (ret) {
1047                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1048                 return ret;
1049         }
1050
1051         iwl_trans_pcie_tx_reset(trans);
1052
1053         ret = iwl_pcie_rx_init(trans);
1054         if (ret) {
1055                 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1056                 return ret;
1057         }
1058
1059         *status = IWL_D3_STATUS_ALIVE;
1060         return 0;
1061 }
1062
1063 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1064 {
1065         bool hw_rfkill;
1066         int err;
1067
1068         err = iwl_pcie_prepare_card_hw(trans);
1069         if (err) {
1070                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1071                 return err;
1072         }
1073
1074         /* Reset the entire device */
1075         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1076
1077         usleep_range(10, 15);
1078
1079         iwl_pcie_apm_init(trans);
1080
1081         /* From now on, the op_mode will be kept updated about RF kill state */
1082         iwl_enable_rfkill_int(trans);
1083
1084         hw_rfkill = iwl_is_rfkill_set(trans);
1085         if (hw_rfkill)
1086                 set_bit(STATUS_RFKILL, &trans->status);
1087         else
1088                 clear_bit(STATUS_RFKILL, &trans->status);
1089         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1090
1091         return 0;
1092 }
1093
1094 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1095 {
1096         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1097
1098         /* disable interrupts - don't enable HW RF kill interrupt */
1099         spin_lock(&trans_pcie->irq_lock);
1100         iwl_disable_interrupts(trans);
1101         spin_unlock(&trans_pcie->irq_lock);
1102
1103         iwl_pcie_apm_stop(trans);
1104
1105         spin_lock(&trans_pcie->irq_lock);
1106         iwl_disable_interrupts(trans);
1107         spin_unlock(&trans_pcie->irq_lock);
1108
1109         iwl_pcie_disable_ict(trans);
1110 }
1111
1112 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1113 {
1114         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1115 }
1116
1117 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1118 {
1119         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1120 }
1121
1122 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1123 {
1124         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1125 }
1126
1127 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1128 {
1129         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1130                                ((reg & 0x000FFFFF) | (3 << 24)));
1131         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1132 }
1133
1134 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1135                                       u32 val)
1136 {
1137         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1138                                ((addr & 0x000FFFFF) | (3 << 24)));
1139         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1140 }
1141
1142 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1143 {
1144         WARN_ON(1);
1145         return 0;
1146 }
1147
1148 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1149                                      const struct iwl_trans_config *trans_cfg)
1150 {
1151         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1152
1153         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1154         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1155         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1156                 trans_pcie->n_no_reclaim_cmds = 0;
1157         else
1158                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1159         if (trans_pcie->n_no_reclaim_cmds)
1160                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1161                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1162
1163         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1164         if (trans_pcie->rx_buf_size_8k)
1165                 trans_pcie->rx_page_order = get_order(8 * 1024);
1166         else
1167                 trans_pcie->rx_page_order = get_order(4 * 1024);
1168
1169         trans_pcie->wd_timeout =
1170                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1171
1172         trans_pcie->command_names = trans_cfg->command_names;
1173         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1174         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1175
1176         /* Initialize NAPI here - it should be before registering to mac80211
1177          * in the opmode but after the HW struct is allocated.
1178          * As this function may be called again in some corner cases don't
1179          * do anything if NAPI was already initialized.
1180          */
1181         if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1182                 init_dummy_netdev(&trans_pcie->napi_dev);
1183                 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1184                                      &trans_pcie->napi_dev,
1185                                      iwl_pcie_dummy_napi_poll, 64);
1186         }
1187 }
1188
1189 void iwl_trans_pcie_free(struct iwl_trans *trans)
1190 {
1191         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1192
1193         synchronize_irq(trans_pcie->pci_dev->irq);
1194
1195         iwl_pcie_tx_free(trans);
1196         iwl_pcie_rx_free(trans);
1197
1198         free_irq(trans_pcie->pci_dev->irq, trans);
1199         iwl_pcie_free_ict(trans);
1200
1201         pci_disable_msi(trans_pcie->pci_dev);
1202         iounmap(trans_pcie->hw_base);
1203         pci_release_regions(trans_pcie->pci_dev);
1204         pci_disable_device(trans_pcie->pci_dev);
1205         kmem_cache_destroy(trans->dev_cmd_pool);
1206
1207         if (trans_pcie->napi.poll)
1208                 netif_napi_del(&trans_pcie->napi);
1209
1210         iwl_pcie_free_fw_monitor(trans);
1211
1212         kfree(trans);
1213 }
1214
1215 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1216 {
1217         if (state)
1218                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1219         else
1220                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1221 }
1222
1223 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1224                                                 unsigned long *flags)
1225 {
1226         int ret;
1227         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1228
1229         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1230
1231         if (trans_pcie->cmd_in_flight)
1232                 goto out;
1233
1234         /* this bit wakes up the NIC */
1235         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1236                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1237
1238         /*
1239          * These bits say the device is running, and should keep running for
1240          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1241          * but they do not indicate that embedded SRAM is restored yet;
1242          * 3945 and 4965 have volatile SRAM, and must save/restore contents
1243          * to/from host DRAM when sleeping/waking for power-saving.
1244          * Each direction takes approximately 1/4 millisecond; with this
1245          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1246          * series of register accesses are expected (e.g. reading Event Log),
1247          * to keep device from sleeping.
1248          *
1249          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1250          * SRAM is okay/restored.  We don't check that here because this call
1251          * is just for hardware register access; but GP1 MAC_SLEEP check is a
1252          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1253          *
1254          * 5000 series and later (including 1000 series) have non-volatile SRAM,
1255          * and do not save/restore SRAM when power cycling.
1256          */
1257         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1258                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1259                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1260                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1261         if (unlikely(ret < 0)) {
1262                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1263                 if (!silent) {
1264                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1265                         WARN_ONCE(1,
1266                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1267                                   val);
1268                         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1269                         return false;
1270                 }
1271         }
1272
1273 out:
1274         /*
1275          * Fool sparse by faking we release the lock - sparse will
1276          * track nic_access anyway.
1277          */
1278         __release(&trans_pcie->reg_lock);
1279         return true;
1280 }
1281
1282 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1283                                               unsigned long *flags)
1284 {
1285         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1286
1287         lockdep_assert_held(&trans_pcie->reg_lock);
1288
1289         /*
1290          * Fool sparse by faking we acquiring the lock - sparse will
1291          * track nic_access anyway.
1292          */
1293         __acquire(&trans_pcie->reg_lock);
1294
1295         if (trans_pcie->cmd_in_flight)
1296                 goto out;
1297
1298         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1299                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1300         /*
1301          * Above we read the CSR_GP_CNTRL register, which will flush
1302          * any previous writes, but we need the write that clears the
1303          * MAC_ACCESS_REQ bit to be performed before any other writes
1304          * scheduled on different CPUs (after we drop reg_lock).
1305          */
1306         mmiowb();
1307 out:
1308         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1309 }
1310
1311 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1312                                    void *buf, int dwords)
1313 {
1314         unsigned long flags;
1315         int offs, ret = 0;
1316         u32 *vals = buf;
1317
1318         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1319                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1320                 for (offs = 0; offs < dwords; offs++)
1321                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1322                 iwl_trans_release_nic_access(trans, &flags);
1323         } else {
1324                 ret = -EBUSY;
1325         }
1326         return ret;
1327 }
1328
1329 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1330                                     const void *buf, int dwords)
1331 {
1332         unsigned long flags;
1333         int offs, ret = 0;
1334         const u32 *vals = buf;
1335
1336         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1337                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1338                 for (offs = 0; offs < dwords; offs++)
1339                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1340                                     vals ? vals[offs] : 0);
1341                 iwl_trans_release_nic_access(trans, &flags);
1342         } else {
1343                 ret = -EBUSY;
1344         }
1345         return ret;
1346 }
1347
1348 #define IWL_FLUSH_WAIT_MS       2000
1349
1350 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1351 {
1352         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1353         struct iwl_txq *txq;
1354         struct iwl_queue *q;
1355         int cnt;
1356         unsigned long now = jiffies;
1357         u32 scd_sram_addr;
1358         u8 buf[16];
1359         int ret = 0;
1360
1361         /* waiting for all the tx frames complete might take a while */
1362         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1363                 u8 wr_ptr;
1364
1365                 if (cnt == trans_pcie->cmd_queue)
1366                         continue;
1367                 if (!test_bit(cnt, trans_pcie->queue_used))
1368                         continue;
1369                 if (!(BIT(cnt) & txq_bm))
1370                         continue;
1371
1372                 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1373                 txq = &trans_pcie->txq[cnt];
1374                 q = &txq->q;
1375                 wr_ptr = ACCESS_ONCE(q->write_ptr);
1376
1377                 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1378                        !time_after(jiffies,
1379                                    now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1380                         u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1381
1382                         if (WARN_ONCE(wr_ptr != write_ptr,
1383                                       "WR pointer moved while flushing %d -> %d\n",
1384                                       wr_ptr, write_ptr))
1385                                 return -ETIMEDOUT;
1386                         msleep(1);
1387                 }
1388
1389                 if (q->read_ptr != q->write_ptr) {
1390                         IWL_ERR(trans,
1391                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1392                         ret = -ETIMEDOUT;
1393                         break;
1394                 }
1395                 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1396         }
1397
1398         if (!ret)
1399                 return 0;
1400
1401         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1402                 txq->q.read_ptr, txq->q.write_ptr);
1403
1404         scd_sram_addr = trans_pcie->scd_base_addr +
1405                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1406         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1407
1408         iwl_print_hex_error(trans, buf, sizeof(buf));
1409
1410         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1411                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1412                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1413
1414         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1415                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1416                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1417                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1418                 u32 tbl_dw =
1419                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1420                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1421
1422                 if (cnt & 0x1)
1423                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1424                 else
1425                         tbl_dw = tbl_dw & 0x0000FFFF;
1426
1427                 IWL_ERR(trans,
1428                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1429                         cnt, active ? "" : "in", fifo, tbl_dw,
1430                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1431                                 (TFD_QUEUE_SIZE_MAX - 1),
1432                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1433         }
1434
1435         return ret;
1436 }
1437
1438 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1439                                          u32 mask, u32 value)
1440 {
1441         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1442         unsigned long flags;
1443
1444         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1445         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1446         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1447 }
1448
1449 static const char *get_csr_string(int cmd)
1450 {
1451 #define IWL_CMD(x) case x: return #x
1452         switch (cmd) {
1453         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1454         IWL_CMD(CSR_INT_COALESCING);
1455         IWL_CMD(CSR_INT);
1456         IWL_CMD(CSR_INT_MASK);
1457         IWL_CMD(CSR_FH_INT_STATUS);
1458         IWL_CMD(CSR_GPIO_IN);
1459         IWL_CMD(CSR_RESET);
1460         IWL_CMD(CSR_GP_CNTRL);
1461         IWL_CMD(CSR_HW_REV);
1462         IWL_CMD(CSR_EEPROM_REG);
1463         IWL_CMD(CSR_EEPROM_GP);
1464         IWL_CMD(CSR_OTP_GP_REG);
1465         IWL_CMD(CSR_GIO_REG);
1466         IWL_CMD(CSR_GP_UCODE_REG);
1467         IWL_CMD(CSR_GP_DRIVER_REG);
1468         IWL_CMD(CSR_UCODE_DRV_GP1);
1469         IWL_CMD(CSR_UCODE_DRV_GP2);
1470         IWL_CMD(CSR_LED_REG);
1471         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1472         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1473         IWL_CMD(CSR_ANA_PLL_CFG);
1474         IWL_CMD(CSR_HW_REV_WA_REG);
1475         IWL_CMD(CSR_MONITOR_STATUS_REG);
1476         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1477         default:
1478                 return "UNKNOWN";
1479         }
1480 #undef IWL_CMD
1481 }
1482
1483 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1484 {
1485         int i;
1486         static const u32 csr_tbl[] = {
1487                 CSR_HW_IF_CONFIG_REG,
1488                 CSR_INT_COALESCING,
1489                 CSR_INT,
1490                 CSR_INT_MASK,
1491                 CSR_FH_INT_STATUS,
1492                 CSR_GPIO_IN,
1493                 CSR_RESET,
1494                 CSR_GP_CNTRL,
1495                 CSR_HW_REV,
1496                 CSR_EEPROM_REG,
1497                 CSR_EEPROM_GP,
1498                 CSR_OTP_GP_REG,
1499                 CSR_GIO_REG,
1500                 CSR_GP_UCODE_REG,
1501                 CSR_GP_DRIVER_REG,
1502                 CSR_UCODE_DRV_GP1,
1503                 CSR_UCODE_DRV_GP2,
1504                 CSR_LED_REG,
1505                 CSR_DRAM_INT_TBL_REG,
1506                 CSR_GIO_CHICKEN_BITS,
1507                 CSR_ANA_PLL_CFG,
1508                 CSR_MONITOR_STATUS_REG,
1509                 CSR_HW_REV_WA_REG,
1510                 CSR_DBG_HPET_MEM_REG
1511         };
1512         IWL_ERR(trans, "CSR values:\n");
1513         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1514                 "CSR_INT_PERIODIC_REG)\n");
1515         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1516                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1517                         get_csr_string(csr_tbl[i]),
1518                         iwl_read32(trans, csr_tbl[i]));
1519         }
1520 }
1521
1522 #ifdef CONFIG_IWLWIFI_DEBUGFS
1523 /* create and remove of files */
1524 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1525         if (!debugfs_create_file(#name, mode, parent, trans,            \
1526                                  &iwl_dbgfs_##name##_ops))              \
1527                 goto err;                                               \
1528 } while (0)
1529
1530 /* file operation */
1531 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1532 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1533         .read = iwl_dbgfs_##name##_read,                                \
1534         .open = simple_open,                                            \
1535         .llseek = generic_file_llseek,                                  \
1536 };
1537
1538 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1539 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1540         .write = iwl_dbgfs_##name##_write,                              \
1541         .open = simple_open,                                            \
1542         .llseek = generic_file_llseek,                                  \
1543 };
1544
1545 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1546 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1547         .write = iwl_dbgfs_##name##_write,                              \
1548         .read = iwl_dbgfs_##name##_read,                                \
1549         .open = simple_open,                                            \
1550         .llseek = generic_file_llseek,                                  \
1551 };
1552
1553 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1554                                        char __user *user_buf,
1555                                        size_t count, loff_t *ppos)
1556 {
1557         struct iwl_trans *trans = file->private_data;
1558         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1559         struct iwl_txq *txq;
1560         struct iwl_queue *q;
1561         char *buf;
1562         int pos = 0;
1563         int cnt;
1564         int ret;
1565         size_t bufsz;
1566
1567         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1568
1569         if (!trans_pcie->txq)
1570                 return -EAGAIN;
1571
1572         buf = kzalloc(bufsz, GFP_KERNEL);
1573         if (!buf)
1574                 return -ENOMEM;
1575
1576         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1577                 txq = &trans_pcie->txq[cnt];
1578                 q = &txq->q;
1579                 pos += scnprintf(buf + pos, bufsz - pos,
1580                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d%s\n",
1581                                 cnt, q->read_ptr, q->write_ptr,
1582                                 !!test_bit(cnt, trans_pcie->queue_used),
1583                                  !!test_bit(cnt, trans_pcie->queue_stopped),
1584                                  txq->need_update,
1585                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
1586         }
1587         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1588         kfree(buf);
1589         return ret;
1590 }
1591
1592 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1593                                        char __user *user_buf,
1594                                        size_t count, loff_t *ppos)
1595 {
1596         struct iwl_trans *trans = file->private_data;
1597         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1598         struct iwl_rxq *rxq = &trans_pcie->rxq;
1599         char buf[256];
1600         int pos = 0;
1601         const size_t bufsz = sizeof(buf);
1602
1603         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1604                                                 rxq->read);
1605         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1606                                                 rxq->write);
1607         pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1608                                                 rxq->write_actual);
1609         pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1610                                                 rxq->need_update);
1611         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1612                                                 rxq->free_count);
1613         if (rxq->rb_stts) {
1614                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1615                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1616         } else {
1617                 pos += scnprintf(buf + pos, bufsz - pos,
1618                                         "closed_rb_num: Not Allocated\n");
1619         }
1620         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1621 }
1622
1623 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1624                                         char __user *user_buf,
1625                                         size_t count, loff_t *ppos)
1626 {
1627         struct iwl_trans *trans = file->private_data;
1628         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1629         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1630
1631         int pos = 0;
1632         char *buf;
1633         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1634         ssize_t ret;
1635
1636         buf = kzalloc(bufsz, GFP_KERNEL);
1637         if (!buf)
1638                 return -ENOMEM;
1639
1640         pos += scnprintf(buf + pos, bufsz - pos,
1641                         "Interrupt Statistics Report:\n");
1642
1643         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1644                 isr_stats->hw);
1645         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1646                 isr_stats->sw);
1647         if (isr_stats->sw || isr_stats->hw) {
1648                 pos += scnprintf(buf + pos, bufsz - pos,
1649                         "\tLast Restarting Code:  0x%X\n",
1650                         isr_stats->err_code);
1651         }
1652 #ifdef CONFIG_IWLWIFI_DEBUG
1653         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1654                 isr_stats->sch);
1655         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1656                 isr_stats->alive);
1657 #endif
1658         pos += scnprintf(buf + pos, bufsz - pos,
1659                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1660
1661         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1662                 isr_stats->ctkill);
1663
1664         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1665                 isr_stats->wakeup);
1666
1667         pos += scnprintf(buf + pos, bufsz - pos,
1668                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1669
1670         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1671                 isr_stats->tx);
1672
1673         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1674                 isr_stats->unhandled);
1675
1676         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1677         kfree(buf);
1678         return ret;
1679 }
1680
1681 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1682                                          const char __user *user_buf,
1683                                          size_t count, loff_t *ppos)
1684 {
1685         struct iwl_trans *trans = file->private_data;
1686         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1687         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1688
1689         char buf[8];
1690         int buf_size;
1691         u32 reset_flag;
1692
1693         memset(buf, 0, sizeof(buf));
1694         buf_size = min(count, sizeof(buf) -  1);
1695         if (copy_from_user(buf, user_buf, buf_size))
1696                 return -EFAULT;
1697         if (sscanf(buf, "%x", &reset_flag) != 1)
1698                 return -EFAULT;
1699         if (reset_flag == 0)
1700                 memset(isr_stats, 0, sizeof(*isr_stats));
1701
1702         return count;
1703 }
1704
1705 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1706                                    const char __user *user_buf,
1707                                    size_t count, loff_t *ppos)
1708 {
1709         struct iwl_trans *trans = file->private_data;
1710         char buf[8];
1711         int buf_size;
1712         int csr;
1713
1714         memset(buf, 0, sizeof(buf));
1715         buf_size = min(count, sizeof(buf) -  1);
1716         if (copy_from_user(buf, user_buf, buf_size))
1717                 return -EFAULT;
1718         if (sscanf(buf, "%d", &csr) != 1)
1719                 return -EFAULT;
1720
1721         iwl_pcie_dump_csr(trans);
1722
1723         return count;
1724 }
1725
1726 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1727                                      char __user *user_buf,
1728                                      size_t count, loff_t *ppos)
1729 {
1730         struct iwl_trans *trans = file->private_data;
1731         char *buf = NULL;
1732         ssize_t ret;
1733
1734         ret = iwl_dump_fh(trans, &buf);
1735         if (ret < 0)
1736                 return ret;
1737         if (!buf)
1738                 return -EINVAL;
1739         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1740         kfree(buf);
1741         return ret;
1742 }
1743
1744 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1745 DEBUGFS_READ_FILE_OPS(fh_reg);
1746 DEBUGFS_READ_FILE_OPS(rx_queue);
1747 DEBUGFS_READ_FILE_OPS(tx_queue);
1748 DEBUGFS_WRITE_FILE_OPS(csr);
1749
1750 /*
1751  * Create the debugfs files and directories
1752  *
1753  */
1754 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1755                                          struct dentry *dir)
1756 {
1757         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1758         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1759         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1760         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1761         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1762         return 0;
1763
1764 err:
1765         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1766         return -ENOMEM;
1767 }
1768
1769 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
1770 {
1771         u32 cmdlen = 0;
1772         int i;
1773
1774         for (i = 0; i < IWL_NUM_OF_TBS; i++)
1775                 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
1776
1777         return cmdlen;
1778 }
1779
1780 static const struct {
1781         u32 start, end;
1782 } iwl_prph_dump_addr[] = {
1783         { .start = 0x00a00000, .end = 0x00a00000 },
1784         { .start = 0x00a0000c, .end = 0x00a00024 },
1785         { .start = 0x00a0002c, .end = 0x00a0003c },
1786         { .start = 0x00a00410, .end = 0x00a00418 },
1787         { .start = 0x00a00420, .end = 0x00a00420 },
1788         { .start = 0x00a00428, .end = 0x00a00428 },
1789         { .start = 0x00a00430, .end = 0x00a0043c },
1790         { .start = 0x00a00444, .end = 0x00a00444 },
1791         { .start = 0x00a004c0, .end = 0x00a004cc },
1792         { .start = 0x00a004d8, .end = 0x00a004d8 },
1793         { .start = 0x00a004e0, .end = 0x00a004f0 },
1794         { .start = 0x00a00840, .end = 0x00a00840 },
1795         { .start = 0x00a00850, .end = 0x00a00858 },
1796         { .start = 0x00a01004, .end = 0x00a01008 },
1797         { .start = 0x00a01010, .end = 0x00a01010 },
1798         { .start = 0x00a01018, .end = 0x00a01018 },
1799         { .start = 0x00a01024, .end = 0x00a01024 },
1800         { .start = 0x00a0102c, .end = 0x00a01034 },
1801         { .start = 0x00a0103c, .end = 0x00a01040 },
1802         { .start = 0x00a01048, .end = 0x00a01094 },
1803         { .start = 0x00a01c00, .end = 0x00a01c20 },
1804         { .start = 0x00a01c58, .end = 0x00a01c58 },
1805         { .start = 0x00a01c7c, .end = 0x00a01c7c },
1806         { .start = 0x00a01c28, .end = 0x00a01c54 },
1807         { .start = 0x00a01c5c, .end = 0x00a01c5c },
1808         { .start = 0x00a01c84, .end = 0x00a01c84 },
1809         { .start = 0x00a01ce0, .end = 0x00a01d0c },
1810         { .start = 0x00a01d18, .end = 0x00a01d20 },
1811         { .start = 0x00a01d2c, .end = 0x00a01d30 },
1812         { .start = 0x00a01d40, .end = 0x00a01d5c },
1813         { .start = 0x00a01d80, .end = 0x00a01d80 },
1814         { .start = 0x00a01d98, .end = 0x00a01d98 },
1815         { .start = 0x00a01dc0, .end = 0x00a01dfc },
1816         { .start = 0x00a01e00, .end = 0x00a01e2c },
1817         { .start = 0x00a01e40, .end = 0x00a01e60 },
1818         { .start = 0x00a01e84, .end = 0x00a01e90 },
1819         { .start = 0x00a01e9c, .end = 0x00a01ec4 },
1820         { .start = 0x00a01ed0, .end = 0x00a01ed0 },
1821         { .start = 0x00a01f00, .end = 0x00a01f14 },
1822         { .start = 0x00a01f44, .end = 0x00a01f58 },
1823         { .start = 0x00a01f80, .end = 0x00a01fa8 },
1824         { .start = 0x00a01fb0, .end = 0x00a01fbc },
1825         { .start = 0x00a01ff8, .end = 0x00a01ffc },
1826         { .start = 0x00a02000, .end = 0x00a02048 },
1827         { .start = 0x00a02068, .end = 0x00a020f0 },
1828         { .start = 0x00a02100, .end = 0x00a02118 },
1829         { .start = 0x00a02140, .end = 0x00a0214c },
1830         { .start = 0x00a02168, .end = 0x00a0218c },
1831         { .start = 0x00a021c0, .end = 0x00a021c0 },
1832         { .start = 0x00a02400, .end = 0x00a02410 },
1833         { .start = 0x00a02418, .end = 0x00a02420 },
1834         { .start = 0x00a02428, .end = 0x00a0242c },
1835         { .start = 0x00a02434, .end = 0x00a02434 },
1836         { .start = 0x00a02440, .end = 0x00a02460 },
1837         { .start = 0x00a02468, .end = 0x00a024b0 },
1838         { .start = 0x00a024c8, .end = 0x00a024cc },
1839         { .start = 0x00a02500, .end = 0x00a02504 },
1840         { .start = 0x00a0250c, .end = 0x00a02510 },
1841         { .start = 0x00a02540, .end = 0x00a02554 },
1842         { .start = 0x00a02580, .end = 0x00a025f4 },
1843         { .start = 0x00a02600, .end = 0x00a0260c },
1844         { .start = 0x00a02648, .end = 0x00a02650 },
1845         { .start = 0x00a02680, .end = 0x00a02680 },
1846         { .start = 0x00a026c0, .end = 0x00a026d0 },
1847         { .start = 0x00a02700, .end = 0x00a0270c },
1848         { .start = 0x00a02804, .end = 0x00a02804 },
1849         { .start = 0x00a02818, .end = 0x00a0281c },
1850         { .start = 0x00a02c00, .end = 0x00a02db4 },
1851         { .start = 0x00a02df4, .end = 0x00a02fb0 },
1852         { .start = 0x00a03000, .end = 0x00a03014 },
1853         { .start = 0x00a0301c, .end = 0x00a0302c },
1854         { .start = 0x00a03034, .end = 0x00a03038 },
1855         { .start = 0x00a03040, .end = 0x00a03048 },
1856         { .start = 0x00a03060, .end = 0x00a03068 },
1857         { .start = 0x00a03070, .end = 0x00a03074 },
1858         { .start = 0x00a0307c, .end = 0x00a0307c },
1859         { .start = 0x00a03080, .end = 0x00a03084 },
1860         { .start = 0x00a0308c, .end = 0x00a03090 },
1861         { .start = 0x00a03098, .end = 0x00a03098 },
1862         { .start = 0x00a030a0, .end = 0x00a030a0 },
1863         { .start = 0x00a030a8, .end = 0x00a030b4 },
1864         { .start = 0x00a030bc, .end = 0x00a030bc },
1865         { .start = 0x00a030c0, .end = 0x00a0312c },
1866         { .start = 0x00a03c00, .end = 0x00a03c5c },
1867         { .start = 0x00a04400, .end = 0x00a04454 },
1868         { .start = 0x00a04460, .end = 0x00a04474 },
1869         { .start = 0x00a044c0, .end = 0x00a044ec },
1870         { .start = 0x00a04500, .end = 0x00a04504 },
1871         { .start = 0x00a04510, .end = 0x00a04538 },
1872         { .start = 0x00a04540, .end = 0x00a04548 },
1873         { .start = 0x00a04560, .end = 0x00a0457c },
1874         { .start = 0x00a04590, .end = 0x00a04598 },
1875         { .start = 0x00a045c0, .end = 0x00a045f4 },
1876 };
1877
1878 static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
1879                                     struct iwl_fw_error_dump_data **data)
1880 {
1881         struct iwl_fw_error_dump_prph *prph;
1882         unsigned long flags;
1883         u32 prph_len = 0, i;
1884
1885         if (!iwl_trans_grab_nic_access(trans, false, &flags))
1886                 return 0;
1887
1888         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
1889                 /* The range includes both boundaries */
1890                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
1891                          iwl_prph_dump_addr[i].start + 4;
1892                 int reg;
1893                 __le32 *val;
1894
1895                 prph_len += sizeof(*data) + sizeof(*prph) +
1896                         num_bytes_in_chunk;
1897
1898                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
1899                 (*data)->len = cpu_to_le32(sizeof(*prph) +
1900                                         num_bytes_in_chunk);
1901                 prph = (void *)(*data)->data;
1902                 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
1903                 val = (void *)prph->data;
1904
1905                 for (reg = iwl_prph_dump_addr[i].start;
1906                      reg <= iwl_prph_dump_addr[i].end;
1907                      reg += 4)
1908                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
1909                                                                       reg));
1910                 *data = iwl_fw_error_next_data(*data);
1911         }
1912
1913         iwl_trans_release_nic_access(trans, &flags);
1914
1915         return prph_len;
1916 }
1917
1918 #define IWL_CSR_TO_DUMP (0x250)
1919
1920 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
1921                                    struct iwl_fw_error_dump_data **data)
1922 {
1923         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
1924         __le32 *val;
1925         int i;
1926
1927         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
1928         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
1929         val = (void *)(*data)->data;
1930
1931         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
1932                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
1933
1934         *data = iwl_fw_error_next_data(*data);
1935
1936         return csr_len;
1937 }
1938
1939 static
1940 struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
1941 {
1942         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1943         struct iwl_fw_error_dump_data *data;
1944         struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
1945         struct iwl_fw_error_dump_txcmd *txcmd;
1946         struct iwl_trans_dump_data *dump_data;
1947         u32 len;
1948         int i, ptr;
1949
1950         /* transport dump header */
1951         len = sizeof(*dump_data);
1952
1953         /* host commands */
1954         len += sizeof(*data) +
1955                 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
1956
1957         /* CSR registers */
1958         len += sizeof(*data) + IWL_CSR_TO_DUMP;
1959
1960         /* PRPH registers */
1961         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
1962                 /* The range includes both boundaries */
1963                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
1964                         iwl_prph_dump_addr[i].start + 4;
1965
1966                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
1967                         num_bytes_in_chunk;
1968         }
1969
1970         /* FW monitor */
1971         if (trans_pcie->fw_mon_page)
1972                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
1973                         trans_pcie->fw_mon_size;
1974
1975         dump_data = vzalloc(len);
1976         if (!dump_data)
1977                 return NULL;
1978
1979         len = 0;
1980         data = (void *)dump_data->data;
1981         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
1982         txcmd = (void *)data->data;
1983         spin_lock_bh(&cmdq->lock);
1984         ptr = cmdq->q.write_ptr;
1985         for (i = 0; i < cmdq->q.n_window; i++) {
1986                 u8 idx = get_cmd_index(&cmdq->q, ptr);
1987                 u32 caplen, cmdlen;
1988
1989                 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
1990                 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
1991
1992                 if (cmdlen) {
1993                         len += sizeof(*txcmd) + caplen;
1994                         txcmd->cmdlen = cpu_to_le32(cmdlen);
1995                         txcmd->caplen = cpu_to_le32(caplen);
1996                         memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
1997                         txcmd = (void *)((u8 *)txcmd->data + caplen);
1998                 }
1999
2000                 ptr = iwl_queue_dec_wrap(ptr);
2001         }
2002         spin_unlock_bh(&cmdq->lock);
2003
2004         data->len = cpu_to_le32(len);
2005         len += sizeof(*data);
2006         data = iwl_fw_error_next_data(data);
2007
2008         len += iwl_trans_pcie_dump_prph(trans, &data);
2009         len += iwl_trans_pcie_dump_csr(trans, &data);
2010         /* data is already pointing to the next section */
2011
2012         if (trans_pcie->fw_mon_page) {
2013                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2014
2015                 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2016                 data->len = cpu_to_le32(trans_pcie->fw_mon_size +
2017                                         sizeof(*fw_mon_data));
2018                 fw_mon_data = (void *)data->data;
2019                 fw_mon_data->fw_mon_wr_ptr =
2020                         cpu_to_le32(iwl_read_prph(trans, MON_BUFF_WRPTR));
2021                 fw_mon_data->fw_mon_cycle_cnt =
2022                         cpu_to_le32(iwl_read_prph(trans, MON_BUFF_CYCLE_CNT));
2023                 fw_mon_data->fw_mon_base_ptr =
2024                         cpu_to_le32(iwl_read_prph(trans, MON_BUFF_BASE_ADDR));
2025
2026                 /*
2027                  * The firmware is now asserted, it won't write anything to
2028                  * the buffer. CPU can take ownership to fetch the data.
2029                  * The buffer will be handed back to the device before the
2030                  * firmware will be restarted.
2031                  */
2032                 dma_sync_single_for_cpu(trans->dev, trans_pcie->fw_mon_phys,
2033                                         trans_pcie->fw_mon_size,
2034                                         DMA_FROM_DEVICE);
2035                 memcpy(fw_mon_data->data, page_address(trans_pcie->fw_mon_page),
2036                        trans_pcie->fw_mon_size);
2037
2038                 len += sizeof(*data) + sizeof(*fw_mon_data) +
2039                         trans_pcie->fw_mon_size;
2040         }
2041
2042         dump_data->len = len;
2043
2044         return dump_data;
2045 }
2046 #else
2047 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2048                                          struct dentry *dir)
2049 {
2050         return 0;
2051 }
2052 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2053
2054 static const struct iwl_trans_ops trans_ops_pcie = {
2055         .start_hw = iwl_trans_pcie_start_hw,
2056         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2057         .fw_alive = iwl_trans_pcie_fw_alive,
2058         .start_fw = iwl_trans_pcie_start_fw,
2059         .stop_device = iwl_trans_pcie_stop_device,
2060
2061         .d3_suspend = iwl_trans_pcie_d3_suspend,
2062         .d3_resume = iwl_trans_pcie_d3_resume,
2063
2064         .send_cmd = iwl_trans_pcie_send_hcmd,
2065
2066         .tx = iwl_trans_pcie_tx,
2067         .reclaim = iwl_trans_pcie_reclaim,
2068
2069         .txq_disable = iwl_trans_pcie_txq_disable,
2070         .txq_enable = iwl_trans_pcie_txq_enable,
2071
2072         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2073
2074         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2075
2076         .write8 = iwl_trans_pcie_write8,
2077         .write32 = iwl_trans_pcie_write32,
2078         .read32 = iwl_trans_pcie_read32,
2079         .read_prph = iwl_trans_pcie_read_prph,
2080         .write_prph = iwl_trans_pcie_write_prph,
2081         .read_mem = iwl_trans_pcie_read_mem,
2082         .write_mem = iwl_trans_pcie_write_mem,
2083         .configure = iwl_trans_pcie_configure,
2084         .set_pmi = iwl_trans_pcie_set_pmi,
2085         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2086         .release_nic_access = iwl_trans_pcie_release_nic_access,
2087         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2088
2089 #ifdef CONFIG_IWLWIFI_DEBUGFS
2090         .dump_data = iwl_trans_pcie_dump_data,
2091 #endif
2092 };
2093
2094 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2095                                        const struct pci_device_id *ent,
2096                                        const struct iwl_cfg *cfg)
2097 {
2098         struct iwl_trans_pcie *trans_pcie;
2099         struct iwl_trans *trans;
2100         u16 pci_cmd;
2101         int err;
2102
2103         trans = kzalloc(sizeof(struct iwl_trans) +
2104                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2105         if (!trans) {
2106                 err = -ENOMEM;
2107                 goto out;
2108         }
2109
2110         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2111
2112         trans->ops = &trans_ops_pcie;
2113         trans->cfg = cfg;
2114         trans_lockdep_init(trans);
2115         trans_pcie->trans = trans;
2116         spin_lock_init(&trans_pcie->irq_lock);
2117         spin_lock_init(&trans_pcie->reg_lock);
2118         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2119
2120         err = pci_enable_device(pdev);
2121         if (err)
2122                 goto out_no_pci;
2123
2124         if (!cfg->base_params->pcie_l1_allowed) {
2125                 /*
2126                  * W/A - seems to solve weird behavior. We need to remove this
2127                  * if we don't want to stay in L1 all the time. This wastes a
2128                  * lot of power.
2129                  */
2130                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2131                                        PCIE_LINK_STATE_L1 |
2132                                        PCIE_LINK_STATE_CLKPM);
2133         }
2134
2135         pci_set_master(pdev);
2136
2137         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2138         if (!err)
2139                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2140         if (err) {
2141                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2142                 if (!err)
2143                         err = pci_set_consistent_dma_mask(pdev,
2144                                                           DMA_BIT_MASK(32));
2145                 /* both attempts failed: */
2146                 if (err) {
2147                         dev_err(&pdev->dev, "No suitable DMA available\n");
2148                         goto out_pci_disable_device;
2149                 }
2150         }
2151
2152         err = pci_request_regions(pdev, DRV_NAME);
2153         if (err) {
2154                 dev_err(&pdev->dev, "pci_request_regions failed\n");
2155                 goto out_pci_disable_device;
2156         }
2157
2158         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2159         if (!trans_pcie->hw_base) {
2160                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2161                 err = -ENODEV;
2162                 goto out_pci_release_regions;
2163         }
2164
2165         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2166          * PCI Tx retries from interfering with C3 CPU state */
2167         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2168
2169         trans->dev = &pdev->dev;
2170         trans_pcie->pci_dev = pdev;
2171         iwl_disable_interrupts(trans);
2172
2173         err = pci_enable_msi(pdev);
2174         if (err) {
2175                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
2176                 /* enable rfkill interrupt: hw bug w/a */
2177                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2178                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2179                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2180                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2181                 }
2182         }
2183
2184         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2185         /*
2186          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2187          * changed, and now the revision step also includes bit 0-1 (no more
2188          * "dash" value). To keep hw_rev backwards compatible - we'll store it
2189          * in the old format.
2190          */
2191         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2192                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2193                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2194
2195         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2196         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2197                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2198
2199         /* Initialize the wait queue for commands */
2200         init_waitqueue_head(&trans_pcie->wait_command_queue);
2201
2202         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2203                  "iwl_cmd_pool:%s", dev_name(trans->dev));
2204
2205         trans->dev_cmd_headroom = 0;
2206         trans->dev_cmd_pool =
2207                 kmem_cache_create(trans->dev_cmd_pool_name,
2208                                   sizeof(struct iwl_device_cmd)
2209                                   + trans->dev_cmd_headroom,
2210                                   sizeof(void *),
2211                                   SLAB_HWCACHE_ALIGN,
2212                                   NULL);
2213
2214         if (!trans->dev_cmd_pool) {
2215                 err = -ENOMEM;
2216                 goto out_pci_disable_msi;
2217         }
2218
2219         if (iwl_pcie_alloc_ict(trans))
2220                 goto out_free_cmd_pool;
2221
2222         err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2223                                    iwl_pcie_irq_handler,
2224                                    IRQF_SHARED, DRV_NAME, trans);
2225         if (err) {
2226                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2227                 goto out_free_ict;
2228         }
2229
2230         trans_pcie->inta_mask = CSR_INI_SET_MASK;
2231
2232         return trans;
2233
2234 out_free_ict:
2235         iwl_pcie_free_ict(trans);
2236 out_free_cmd_pool:
2237         kmem_cache_destroy(trans->dev_cmd_pool);
2238 out_pci_disable_msi:
2239         pci_disable_msi(pdev);
2240 out_pci_release_regions:
2241         pci_release_regions(pdev);
2242 out_pci_disable_device:
2243         pci_disable_device(pdev);
2244 out_no_pci:
2245         kfree(trans);
2246 out:
2247         return ERR_PTR(err);
2248 }