drivers/net/wireless/ralink/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, see <http://www.gnu.org/licenses/>.
  28  */
  29
  30 /*
  31         Module: rt2800lib
  32         Abstract: rt2800 generic device routines.
  33  */
  34
  35 #include <linux/crc-ccitt.h>
  36 #include <linux/kernel.h>
  37 #include <linux/module.h>
  38 #include <linux/slab.h>
  39
  40 #include "rt2x00.h"
  41 #include "rt2800lib.h"
  42 #include "rt2800.h"
  43
  44 /*
  45  * Register access.
  46  * All access to the CSR registers will go through the methods
  47  * rt2800_register_read and rt2800_register_write.
  48  * BBP and RF register require indirect register access,
  49  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  50  * These indirect registers work with busy bits,
  51  * and we will try maximal REGISTER_BUSY_COUNT times to access
  52  * the register while taking a REGISTER_BUSY_DELAY us delay
  53  * between each attampt. When the busy bit is still set at that time,
  54  * the access attempt is considered to have failed,
  55  * and we will print an error.
  56  * The _lock versions must be used if you already hold the csr_mutex
  57  */
  58 #define WAIT_FOR_BBP(__dev, __reg) \
  59         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  60 #define WAIT_FOR_RFCSR(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RF(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  64 #define WAIT_FOR_MCU(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  66                             H2M_MAILBOX_CSR_OWNER, (__reg))
  67
  68 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  69 {
  70         /* check for rt2872 on SoC */
  71         if (!rt2x00_is_soc(rt2x00dev) ||
  72             !rt2x00_rt(rt2x00dev, RT2872))
  73                 return false;
  74
  75         /* we know for sure that these rf chipsets are used on rt305x boards */
  76         if (rt2x00_rf(rt2x00dev, RF3020) ||
  77             rt2x00_rf(rt2x00dev, RF3021) ||
  78             rt2x00_rf(rt2x00dev, RF3022))
  79                 return true;
  80
  81         rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
  82         return false;
  83 }
  84
  85 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  86                              const unsigned int word, const u8 value)
  87 {
  88         u32 reg;
  89
  90         mutex_lock(&rt2x00dev->csr_mutex);
  91
  92         /*
  93          * Wait until the BBP becomes available, afterwards we
  94          * can safely write the new data into the register.
  95          */
  96         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  97                 reg = 0;
  98                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  99                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 103
 104                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 105         }
 106
 107         mutex_unlock(&rt2x00dev->csr_mutex);
 108 }
 109
 110 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 111                             const unsigned int word, u8 *value)
 112 {
 113         u32 reg;
 114
 115         mutex_lock(&rt2x00dev->csr_mutex);
 116
 117         /*
 118          * Wait until the BBP becomes available, afterwards we
 119          * can safely write the read request into the register.
 120          * After the data has been written, we wait until hardware
 121          * returns the correct value, if at any time the register
 122          * doesn't become available in time, reg will be 0xffffffff
 123          * which means we return 0xff to the caller.
 124          */
 125         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 126                 reg = 0;
 127                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 128                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 131
 132                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 133
 134                 WAIT_FOR_BBP(rt2x00dev, &reg);
 135         }
 136
 137         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 138
 139         mutex_unlock(&rt2x00dev->csr_mutex);
 140 }
 141
 142 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 143                                const unsigned int word, const u8 value)
 144 {
 145         u32 reg;
 146
 147         mutex_lock(&rt2x00dev->csr_mutex);
 148
 149         /*
 150          * Wait until the RFCSR becomes available, afterwards we
 151          * can safely write the new data into the register.
 152          */
 153         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 154                 reg = 0;
 155                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 156                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 159
 160                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 161         }
 162
 163         mutex_unlock(&rt2x00dev->csr_mutex);
 164 }
 165
 166 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 167                               const unsigned int word, u8 *value)
 168 {
 169         u32 reg;
 170
 171         mutex_lock(&rt2x00dev->csr_mutex);
 172
 173         /*
 174          * Wait until the RFCSR becomes available, afterwards we
 175          * can safely write the read request into the register.
 176          * After the data has been written, we wait until hardware
 177          * returns the correct value, if at any time the register
 178          * doesn't become available in time, reg will be 0xffffffff
 179          * which means we return 0xff to the caller.
 180          */
 181         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 182                 reg = 0;
 183                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 184                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 186
 187                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 188
 189                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 190         }
 191
 192         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 193
 194         mutex_unlock(&rt2x00dev->csr_mutex);
 195 }
 196
 197 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 198                             const unsigned int word, const u32 value)
 199 {
 200         u32 reg;
 201
 202         mutex_lock(&rt2x00dev->csr_mutex);
 203
 204         /*
 205          * Wait until the RF becomes available, afterwards we
 206          * can safely write the new data into the register.
 207          */
 208         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 209                 reg = 0;
 210                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 211                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 214
 215                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 216                 rt2x00_rf_write(rt2x00dev, word, value);
 217         }
 218
 219         mutex_unlock(&rt2x00dev->csr_mutex);
 220 }
 221
 222 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
 223         [EEPROM_CHIP_ID]                = 0x0000,
 224         [EEPROM_VERSION]                = 0x0001,
 225         [EEPROM_MAC_ADDR_0]             = 0x0002,
 226         [EEPROM_MAC_ADDR_1]             = 0x0003,
 227         [EEPROM_MAC_ADDR_2]             = 0x0004,
 228         [EEPROM_NIC_CONF0]              = 0x001a,
 229         [EEPROM_NIC_CONF1]              = 0x001b,
 230         [EEPROM_FREQ]                   = 0x001d,
 231         [EEPROM_LED_AG_CONF]            = 0x001e,
 232         [EEPROM_LED_ACT_CONF]           = 0x001f,
 233         [EEPROM_LED_POLARITY]           = 0x0020,
 234         [EEPROM_NIC_CONF2]              = 0x0021,
 235         [EEPROM_LNA]                    = 0x0022,
 236         [EEPROM_RSSI_BG]                = 0x0023,
 237         [EEPROM_RSSI_BG2]               = 0x0024,
 238         [EEPROM_TXMIXER_GAIN_BG]        = 0x0024, /* overlaps with RSSI_BG2 */
 239         [EEPROM_RSSI_A]                 = 0x0025,
 240         [EEPROM_RSSI_A2]                = 0x0026,
 241         [EEPROM_TXMIXER_GAIN_A]         = 0x0026, /* overlaps with RSSI_A2 */
 242         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0027,
 243         [EEPROM_TXPOWER_DELTA]          = 0x0028,
 244         [EEPROM_TXPOWER_BG1]            = 0x0029,
 245         [EEPROM_TXPOWER_BG2]            = 0x0030,
 246         [EEPROM_TSSI_BOUND_BG1]         = 0x0037,
 247         [EEPROM_TSSI_BOUND_BG2]         = 0x0038,
 248         [EEPROM_TSSI_BOUND_BG3]         = 0x0039,
 249         [EEPROM_TSSI_BOUND_BG4]         = 0x003a,
 250         [EEPROM_TSSI_BOUND_BG5]         = 0x003b,
 251         [EEPROM_TXPOWER_A1]             = 0x003c,
 252         [EEPROM_TXPOWER_A2]             = 0x0053,
 253         [EEPROM_TSSI_BOUND_A1]          = 0x006a,
 254         [EEPROM_TSSI_BOUND_A2]          = 0x006b,
 255         [EEPROM_TSSI_BOUND_A3]          = 0x006c,
 256         [EEPROM_TSSI_BOUND_A4]          = 0x006d,
 257         [EEPROM_TSSI_BOUND_A5]          = 0x006e,
 258         [EEPROM_TXPOWER_BYRATE]         = 0x006f,
 259         [EEPROM_BBP_START]              = 0x0078,
 260 };
 261
 262 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
 263         [EEPROM_CHIP_ID]                = 0x0000,
 264         [EEPROM_VERSION]                = 0x0001,
 265         [EEPROM_MAC_ADDR_0]             = 0x0002,
 266         [EEPROM_MAC_ADDR_1]             = 0x0003,
 267         [EEPROM_MAC_ADDR_2]             = 0x0004,
 268         [EEPROM_NIC_CONF0]              = 0x001a,
 269         [EEPROM_NIC_CONF1]              = 0x001b,
 270         [EEPROM_NIC_CONF2]              = 0x001c,
 271         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0020,
 272         [EEPROM_FREQ]                   = 0x0022,
 273         [EEPROM_LED_AG_CONF]            = 0x0023,
 274         [EEPROM_LED_ACT_CONF]           = 0x0024,
 275         [EEPROM_LED_POLARITY]           = 0x0025,
 276         [EEPROM_LNA]                    = 0x0026,
 277         [EEPROM_EXT_LNA2]               = 0x0027,
 278         [EEPROM_RSSI_BG]                = 0x0028,
 279         [EEPROM_RSSI_BG2]               = 0x0029,
 280         [EEPROM_RSSI_A]                 = 0x002a,
 281         [EEPROM_RSSI_A2]                = 0x002b,
 282         [EEPROM_TXPOWER_BG1]            = 0x0030,
 283         [EEPROM_TXPOWER_BG2]            = 0x0037,
 284         [EEPROM_EXT_TXPOWER_BG3]        = 0x003e,
 285         [EEPROM_TSSI_BOUND_BG1]         = 0x0045,
 286         [EEPROM_TSSI_BOUND_BG2]         = 0x0046,
 287         [EEPROM_TSSI_BOUND_BG3]         = 0x0047,
 288         [EEPROM_TSSI_BOUND_BG4]         = 0x0048,
 289         [EEPROM_TSSI_BOUND_BG5]         = 0x0049,
 290         [EEPROM_TXPOWER_A1]             = 0x004b,
 291         [EEPROM_TXPOWER_A2]             = 0x0065,
 292         [EEPROM_EXT_TXPOWER_A3]         = 0x007f,
 293         [EEPROM_TSSI_BOUND_A1]          = 0x009a,
 294         [EEPROM_TSSI_BOUND_A2]          = 0x009b,
 295         [EEPROM_TSSI_BOUND_A3]          = 0x009c,
 296         [EEPROM_TSSI_BOUND_A4]          = 0x009d,
 297         [EEPROM_TSSI_BOUND_A5]          = 0x009e,
 298         [EEPROM_TXPOWER_BYRATE]         = 0x00a0,
 299 };
 300
 301 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
 302                                              const enum rt2800_eeprom_word word)
 303 {
 304         const unsigned int *map;
 305         unsigned int index;
 306
 307         if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
 308                       "%s: invalid EEPROM word %d\n",
 309                       wiphy_name(rt2x00dev->hw->wiphy), word))
 310                 return 0;
 311
 312         if (rt2x00_rt(rt2x00dev, RT3593))
 313                 map = rt2800_eeprom_map_ext;
 314         else
 315                 map = rt2800_eeprom_map;
 316
 317         index = map[word];
 318
 319         /* Index 0 is valid only for EEPROM_CHIP_ID.
 320          * Otherwise it means that the offset of the
 321          * given word is not initialized in the map,
 322          * or that the field is not usable on the
 323          * actual chipset.
 324          */
 325         WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
 326                   "%s: invalid access of EEPROM word %d\n",
 327                   wiphy_name(rt2x00dev->hw->wiphy), word);
 328
 329         return index;
 330 }
 331
 332 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
 333                                 const enum rt2800_eeprom_word word)
 334 {
 335         unsigned int index;
 336
 337         index = rt2800_eeprom_word_index(rt2x00dev, word);
 338         return rt2x00_eeprom_addr(rt2x00dev, index);
 339 }
 340
 341 static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
 342                                const enum rt2800_eeprom_word word, u16 *data)
 343 {
 344         unsigned int index;
 345
 346         index = rt2800_eeprom_word_index(rt2x00dev, word);
 347         rt2x00_eeprom_read(rt2x00dev, index, data);
 348 }
 349
 350 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
 351                                 const enum rt2800_eeprom_word word, u16 data)
 352 {
 353         unsigned int index;
 354
 355         index = rt2800_eeprom_word_index(rt2x00dev, word);
 356         rt2x00_eeprom_write(rt2x00dev, index, data);
 357 }
 358
 359 static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
 360                                           const enum rt2800_eeprom_word array,
 361                                           unsigned int offset,
 362                                           u16 *data)
 363 {
 364         unsigned int index;
 365
 366         index = rt2800_eeprom_word_index(rt2x00dev, array);
 367         rt2x00_eeprom_read(rt2x00dev, index + offset, data);
 368 }
 369
 370 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
 371 {
 372         u32 reg;
 373         int i, count;
 374
 375         rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 376         if (rt2x00_get_field32(reg, WLAN_EN))
 377                 return 0;
 378
 379         rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
 380         rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
 381         rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
 382         rt2x00_set_field32(&reg, WLAN_EN, 1);
 383         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 384
 385         udelay(REGISTER_BUSY_DELAY);
 386
 387         count = 0;
 388         do {
 389                 /*
 390                  * Check PLL_LD & XTAL_RDY.
 391                  */
 392                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 393                         rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
 394                         if (rt2x00_get_field32(reg, PLL_LD) &&
 395                             rt2x00_get_field32(reg, XTAL_RDY))
 396                                 break;
 397                         udelay(REGISTER_BUSY_DELAY);
 398                 }
 399
 400                 if (i >= REGISTER_BUSY_COUNT) {
 401
 402                         if (count >= 10)
 403                                 return -EIO;
 404
 405                         rt2800_register_write(rt2x00dev, 0x58, 0x018);
 406                         udelay(REGISTER_BUSY_DELAY);
 407                         rt2800_register_write(rt2x00dev, 0x58, 0x418);
 408                         udelay(REGISTER_BUSY_DELAY);
 409                         rt2800_register_write(rt2x00dev, 0x58, 0x618);
 410                         udelay(REGISTER_BUSY_DELAY);
 411                         count++;
 412                 } else {
 413                         count = 0;
 414                 }
 415
 416                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 417                 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
 418                 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
 419                 rt2x00_set_field32(&reg, WLAN_RESET, 1);
 420                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 421                 udelay(10);
 422                 rt2x00_set_field32(&reg, WLAN_RESET, 0);
 423                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 424                 udelay(10);
 425                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
 426         } while (count != 0);
 427
 428         return 0;
 429 }
 430
 431 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 432                         const u8 command, const u8 token,
 433                         const u8 arg0, const u8 arg1)
 434 {
 435         u32 reg;
 436
 437         /*
 438          * SOC devices don't support MCU requests.
 439          */
 440         if (rt2x00_is_soc(rt2x00dev))
 441                 return;
 442
 443         mutex_lock(&rt2x00dev->csr_mutex);
 444
 445         /*
 446          * Wait until the MCU becomes available, afterwards we
 447          * can safely write the new data into the register.
 448          */
 449         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 450                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 451                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 452                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 453                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 454                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 455
 456                 reg = 0;
 457                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 458                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 459         }
 460
 461         mutex_unlock(&rt2x00dev->csr_mutex);
 462 }
 463 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 464
 465 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 466 {
 467         unsigned int i = 0;
 468         u32 reg;
 469
 470         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 471                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 472                 if (reg && reg != ~0)
 473                         return 0;
 474                 msleep(1);
 475         }
 476
 477         rt2x00_err(rt2x00dev, "Unstable hardware\n");
 478         return -EBUSY;
 479 }
 480 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 481
 482 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 483 {
 484         unsigned int i;
 485         u32 reg;
 486
 487         /*
 488          * Some devices are really slow to respond here. Wait a whole second
 489          * before timing out.
 490          */
 491         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 492                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 493                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 494                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 495                         return 0;
 496
 497                 msleep(10);
 498         }
 499
 500         rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
 501         return -EACCES;
 502 }
 503 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 504
 505 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
 506 {
 507         u32 reg;
 508
 509         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 510         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 511         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 512         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 513         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 514         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 515         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 516 }
 517 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
 518
 519 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
 520                                unsigned short *txwi_size,
 521                                unsigned short *rxwi_size)
 522 {
 523         switch (rt2x00dev->chip.rt) {
 524         case RT3593:
 525                 *txwi_size = TXWI_DESC_SIZE_4WORDS;
 526                 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
 527                 break;
 528
 529         case RT5592:
 530                 *txwi_size = TXWI_DESC_SIZE_5WORDS;
 531                 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
 532                 break;
 533
 534         default:
 535                 *txwi_size = TXWI_DESC_SIZE_4WORDS;
 536                 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
 537                 break;
 538         }
 539 }
 540 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
 541
 542 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 543 {
 544         u16 fw_crc;
 545         u16 crc;
 546
 547         /*
 548          * The last 2 bytes in the firmware array are the crc checksum itself,
 549          * this means that we should never pass those 2 bytes to the crc
 550          * algorithm.
 551          */
 552         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 553
 554         /*
 555          * Use the crc ccitt algorithm.
 556          * This will return the same value as the legacy driver which
 557          * used bit ordering reversion on the both the firmware bytes
 558          * before input input as well as on the final output.
 559          * Obviously using crc ccitt directly is much more efficient.
 560          */
 561         crc = crc_ccitt(~0, data, len - 2);
 562
 563         /*
 564          * There is a small difference between the crc-itu-t + bitrev and
 565          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 566          * will be swapped, use swab16 to convert the crc to the correct
 567          * value.
 568          */
 569         crc = swab16(crc);
 570
 571         return fw_crc == crc;
 572 }
 573
 574 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 575                           const u8 *data, const size_t len)
 576 {
 577         size_t offset = 0;
 578         size_t fw_len;
 579         bool multiple;
 580
 581         /*
 582          * PCI(e) & SOC devices require firmware with a length
 583          * of 8kb. USB devices require firmware files with a length
 584          * of 4kb. Certain USB chipsets however require different firmware,
 585          * which Ralink only provides attached to the original firmware
 586          * file. Thus for USB devices, firmware files have a length
 587          * which is a multiple of 4kb. The firmware for rt3290 chip also
 588          * have a length which is a multiple of 4kb.
 589          */
 590         if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
 591                 fw_len = 4096;
 592         else
 593                 fw_len = 8192;
 594
 595         multiple = true;
 596         /*
 597          * Validate the firmware length
 598          */
 599         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 600                 return FW_BAD_LENGTH;
 601
 602         /*
 603          * Check if the chipset requires one of the upper parts
 604          * of the firmware.
 605          */
 606         if (rt2x00_is_usb(rt2x00dev) &&
 607             !rt2x00_rt(rt2x00dev, RT2860) &&
 608             !rt2x00_rt(rt2x00dev, RT2872) &&
 609             !rt2x00_rt(rt2x00dev, RT3070) &&
 610             ((len / fw_len) == 1))
 611                 return FW_BAD_VERSION;
 612
 613         /*
 614          * 8kb firmware files must be checked as if it were
 615          * 2 separate firmware files.
 616          */
 617         while (offset < len) {
 618                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 619                         return FW_BAD_CRC;
 620
 621                 offset += fw_len;
 622         }
 623
 624         return FW_OK;
 625 }
 626 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 627
 628 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 629                          const u8 *data, const size_t len)
 630 {
 631         unsigned int i;
 632         u32 reg;
 633         int retval;
 634
 635         if (rt2x00_rt(rt2x00dev, RT3290)) {
 636                 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
 637                 if (retval)
 638                         return -EBUSY;
 639         }
 640
 641         /*
 642          * If driver doesn't wake up firmware here,
 643          * rt2800_load_firmware will hang forever when interface is up again.
 644          */
 645         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 646
 647         /*
 648          * Wait for stable hardware.
 649          */
 650         if (rt2800_wait_csr_ready(rt2x00dev))
 651                 return -EBUSY;
 652
 653         if (rt2x00_is_pci(rt2x00dev)) {
 654                 if (rt2x00_rt(rt2x00dev, RT3290) ||
 655                     rt2x00_rt(rt2x00dev, RT3572) ||
 656                     rt2x00_rt(rt2x00dev, RT5390) ||
 657                     rt2x00_rt(rt2x00dev, RT5392)) {
 658                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 659                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 660                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 661                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 662                 }
 663                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 664         }
 665
 666         rt2800_disable_wpdma(rt2x00dev);
 667
 668         /*
 669          * Write firmware to the device.
 670          */
 671         rt2800_drv_write_firmware(rt2x00dev, data, len);
 672
 673         /*
 674          * Wait for device to stabilize.
 675          */
 676         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 677                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 678                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 679                         break;
 680                 msleep(1);
 681         }
 682
 683         if (i == REGISTER_BUSY_COUNT) {
 684                 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
 685                 return -EBUSY;
 686         }
 687
 688         /*
 689          * Disable DMA, will be reenabled later when enabling
 690          * the radio.
 691          */
 692         rt2800_disable_wpdma(rt2x00dev);
 693
 694         /*
 695          * Initialize firmware.
 696          */
 697         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 698         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 699         if (rt2x00_is_usb(rt2x00dev)) {
 700                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
 701                 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
 702         }
 703         msleep(1);
 704
 705         return 0;
 706 }
 707 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 708
 709 void rt2800_write_tx_data(struct queue_entry *entry,
 710                           struct txentry_desc *txdesc)
 711 {
 712         __le32 *txwi = rt2800_drv_get_txwi(entry);
 713         u32 word;
 714         int i;
 715
 716         /*
 717          * Initialize TX Info descriptor
 718          */
 719         rt2x00_desc_read(txwi, 0, &word);
 720         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 721                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 722         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 723                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 724         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 725         rt2x00_set_field32(&word, TXWI_W0_TS,
 726                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 727         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 728                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 729         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 730                            txdesc->u.ht.mpdu_density);
 731         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 732         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 733         rt2x00_set_field32(&word, TXWI_W0_BW,
 734                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 735         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 736                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 737         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 738         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 739         rt2x00_desc_write(txwi, 0, word);
 740
 741         rt2x00_desc_read(txwi, 1, &word);
 742         rt2x00_set_field32(&word, TXWI_W1_ACK,
 743                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 744         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 745                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 746         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 747         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 748                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 749                            txdesc->key_idx : txdesc->u.ht.wcid);
 750         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 751                            txdesc->length);
 752         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 753         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 754         rt2x00_desc_write(txwi, 1, word);
 755
 756         /*
 757          * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
 758          * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
 759          * When TXD_W3_WIV is set to 1 it will use the IV data
 760          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 761          * crypto entry in the registers should be used to encrypt the frame.
 762          *
 763          * Nulify all remaining words as well, we don't know how to program them.
 764          */
 765         for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
 766                 _rt2x00_desc_write(txwi, i, 0);
 767 }
 768 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 769
 770 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 771 {
 772         s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 773         s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 774         s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 775         u16 eeprom;
 776         u8 offset0;
 777         u8 offset1;
 778         u8 offset2;
 779
 780         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 781                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 782                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 783                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 784                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 785                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 786         } else {
 787                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 788                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 789                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 790                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 791                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 792         }
 793
 794         /*
 795          * Convert the value from the descriptor into the RSSI value
 796          * If the value in the descriptor is 0, it is considered invalid
 797          * and the default (extremely low) rssi value is assumed
 798          */
 799         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 800         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 801         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 802
 803         /*
 804          * mac80211 only accepts a single RSSI value. Calculating the
 805          * average doesn't deliver a fair answer either since -60:-60 would
 806          * be considered equally good as -50:-70 while the second is the one
 807          * which gives less energy...
 808          */
 809         rssi0 = max(rssi0, rssi1);
 810         return (int)max(rssi0, rssi2);
 811 }
 812
 813 void rt2800_process_rxwi(struct queue_entry *entry,
 814                          struct rxdone_entry_desc *rxdesc)
 815 {
 816         __le32 *rxwi = (__le32 *) entry->skb->data;
 817         u32 word;
 818
 819         rt2x00_desc_read(rxwi, 0, &word);
 820
 821         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 822         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 823
 824         rt2x00_desc_read(rxwi, 1, &word);
 825
 826         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 827                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 828
 829         if (rt2x00_get_field32(word, RXWI_W1_BW))
 830                 rxdesc->flags |= RX_FLAG_40MHZ;
 831
 832         /*
 833          * Detect RX rate, always use MCS as signal type.
 834          */
 835         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 836         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 837         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 838
 839         /*
 840          * Mask of 0x8 bit to remove the short preamble flag.
 841          */
 842         if (rxdesc->rate_mode == RATE_MODE_CCK)
 843                 rxdesc->signal &= ~0x8;
 844
 845         rt2x00_desc_read(rxwi, 2, &word);
 846
 847         /*
 848          * Convert descriptor AGC value to RSSI value.
 849          */
 850         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 851         /*
 852          * Remove RXWI descriptor from start of the buffer.
 853          */
 854         skb_pull(entry->skb, entry->queue->winfo_size);
 855 }
 856 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 857
 858 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
 859 {
 860         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 861         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 862         struct txdone_entry_desc txdesc;
 863         u32 word;
 864         u16 mcs, real_mcs;
 865         int aggr, ampdu;
 866
 867         /*
 868          * Obtain the status about this packet.
 869          */
 870         txdesc.flags = 0;
 871         rt2x00_desc_read(txwi, 0, &word);
 872
 873         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 874         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 875
 876         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 877         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 878
 879         /*
 880          * If a frame was meant to be sent as a single non-aggregated MPDU
 881          * but ended up in an aggregate the used tx rate doesn't correlate
 882          * with the one specified in the TXWI as the whole aggregate is sent
 883          * with the same rate.
 884          *
 885          * For example: two frames are sent to rt2x00, the first one sets
 886          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 887          * and requests MCS15. If the hw aggregates both frames into one
 888          * AMDPU the tx status for both frames will contain MCS7 although
 889          * the frame was sent successfully.
 890          *
 891          * Hence, replace the requested rate with the real tx rate to not
 892          * confuse the rate control algortihm by providing clearly wrong
 893          * data.
 894          */
 895         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
 896                 skbdesc->tx_rate_idx = real_mcs;
 897                 mcs = real_mcs;
 898         }
 899
 900         if (aggr == 1 || ampdu == 1)
 901                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
 902
 903         /*
 904          * Ralink has a retry mechanism using a global fallback
 905          * table. We setup this fallback table to try the immediate
 906          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 907          * always contains the MCS used for the last transmission, be
 908          * it successful or not.
 909          */
 910         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 911                 /*
 912                  * Transmission succeeded. The number of retries is
 913                  * mcs - real_mcs
 914                  */
 915                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 916                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 917         } else {
 918                 /*
 919                  * Transmission failed. The number of retries is
 920                  * always 7 in this case (for a total number of 8
 921                  * frames sent).
 922                  */
 923                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 924                 txdesc.retry = rt2x00dev->long_retry;
 925         }
 926
 927         /*
 928          * the frame was retried at least once
 929          * -> hw used fallback rates
 930          */
 931         if (txdesc.retry)
 932                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 933
 934         rt2x00lib_txdone(entry, &txdesc);
 935 }
 936 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 937
 938 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
 939                                           unsigned int index)
 940 {
 941         return HW_BEACON_BASE(index);
 942 }
 943
 944 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
 945                                           unsigned int index)
 946 {
 947         return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
 948 }
 949
 950 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
 951 {
 952         struct data_queue *queue = rt2x00dev->bcn;
 953         struct queue_entry *entry;
 954         int i, bcn_num = 0;
 955         u64 off, reg = 0;
 956         u32 bssid_dw1;
 957
 958         /*
 959          * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
 960          */
 961         for (i = 0; i < queue->limit; i++) {
 962                 entry = &queue->entries[i];
 963                 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
 964                         continue;
 965                 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
 966                 reg |= off << (8 * bcn_num);
 967                 bcn_num++;
 968         }
 969
 970         WARN_ON_ONCE(bcn_num != rt2x00dev->intf_beaconing);
 971
 972         rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
 973         rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
 974
 975         /*
 976          * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
 977          */
 978         rt2800_register_read(rt2x00dev, MAC_BSSID_DW1, &bssid_dw1);
 979         rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
 980                            bcn_num > 0 ? bcn_num - 1 : 0);
 981         rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
 982 }
 983
 984 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 985 {
 986         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 987         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 988         unsigned int beacon_base;
 989         unsigned int padding_len;
 990         u32 orig_reg, reg;
 991         const int txwi_desc_size = entry->queue->winfo_size;
 992
 993         /*
 994          * Disable beaconing while we are reloading the beacon data,
 995          * otherwise we might be sending out invalid data.
 996          */
 997         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 998         orig_reg = reg;
 999         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1000         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1001
1002         /*
1003          * Add space for the TXWI in front of the skb.
1004          */
1005         memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
1006
1007         /*
1008          * Register descriptor details in skb frame descriptor.
1009          */
1010         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1011         skbdesc->desc = entry->skb->data;
1012         skbdesc->desc_len = txwi_desc_size;
1013
1014         /*
1015          * Add the TXWI for the beacon to the skb.
1016          */
1017         rt2800_write_tx_data(entry, txdesc);
1018
1019         /*
1020          * Dump beacon to userspace through debugfs.
1021          */
1022         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1023
1024         /*
1025          * Write entire beacon with TXWI and padding to register.
1026          */
1027         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1028         if (padding_len && skb_pad(entry->skb, padding_len)) {
1029                 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1030                 /* skb freed by skb_pad() on failure */
1031                 entry->skb = NULL;
1032                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1033                 return;
1034         }
1035
1036         beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1037
1038         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1039                                    entry->skb->len + padding_len);
1040         __set_bit(ENTRY_BCN_ENABLED, &entry->flags);
1041
1042         /*
1043          * Change global beacons settings.
1044          */
1045         rt2800_update_beacons_setup(rt2x00dev);
1046
1047         /*
1048          * Restore beaconing state.
1049          */
1050         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1051
1052         /*
1053          * Clean up beacon skb.
1054          */
1055         dev_kfree_skb_any(entry->skb);
1056         entry->skb = NULL;
1057 }
1058 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
1059
1060 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1061                                                 unsigned int index)
1062 {
1063         int i;
1064         const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1065         unsigned int beacon_base;
1066
1067         beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1068
1069         /*
1070          * For the Beacon base registers we only need to clear
1071          * the whole TXWI which (when set to 0) will invalidate
1072          * the entire beacon.
1073          */
1074         for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1075                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1076 }
1077
1078 void rt2800_clear_beacon(struct queue_entry *entry)
1079 {
1080         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1081         u32 orig_reg, reg;
1082
1083         /*
1084          * Disable beaconing while we are reloading the beacon data,
1085          * otherwise we might be sending out invalid data.
1086          */
1087         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &orig_reg);
1088         reg = orig_reg;
1089         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1090         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1091
1092         /*
1093          * Clear beacon.
1094          */
1095         rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1096         __clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
1097
1098         /*
1099          * Change global beacons settings.
1100          */
1101         rt2800_update_beacons_setup(rt2x00dev);
1102         /*
1103          * Restore beaconing state.
1104          */
1105         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1106 }
1107 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1108
1109 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1110 const struct rt2x00debug rt2800_rt2x00debug = {
1111         .owner  = THIS_MODULE,
1112         .csr    = {
1113                 .read           = rt2800_register_read,
1114                 .write          = rt2800_register_write,
1115                 .flags          = RT2X00DEBUGFS_OFFSET,
1116                 .word_base      = CSR_REG_BASE,
1117                 .word_size      = sizeof(u32),
1118                 .word_count     = CSR_REG_SIZE / sizeof(u32),
1119         },
1120         .eeprom = {
1121                 /* NOTE: The local EEPROM access functions can't
1122                  * be used here, use the generic versions instead.
1123                  */
1124                 .read           = rt2x00_eeprom_read,
1125                 .write          = rt2x00_eeprom_write,
1126                 .word_base      = EEPROM_BASE,
1127                 .word_size      = sizeof(u16),
1128                 .word_count     = EEPROM_SIZE / sizeof(u16),
1129         },
1130         .bbp    = {
1131                 .read           = rt2800_bbp_read,
1132                 .write          = rt2800_bbp_write,
1133                 .word_base      = BBP_BASE,
1134                 .word_size      = sizeof(u8),
1135                 .word_count     = BBP_SIZE / sizeof(u8),
1136         },
1137         .rf     = {
1138                 .read           = rt2x00_rf_read,
1139                 .write          = rt2800_rf_write,
1140                 .word_base      = RF_BASE,
1141                 .word_size      = sizeof(u32),
1142                 .word_count     = RF_SIZE / sizeof(u32),
1143         },
1144         .rfcsr  = {
1145                 .read           = rt2800_rfcsr_read,
1146                 .write          = rt2800_rfcsr_write,
1147                 .word_base      = RFCSR_BASE,
1148                 .word_size      = sizeof(u8),
1149                 .word_count     = RFCSR_SIZE / sizeof(u8),
1150         },
1151 };
1152 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1153 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1154
1155 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1156 {
1157         u32 reg;
1158
1159         if (rt2x00_rt(rt2x00dev, RT3290)) {
1160                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1161                 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1162         } else {
1163                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1164                 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1165         }
1166 }
1167 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1168
1169 #ifdef CONFIG_RT2X00_LIB_LEDS
1170 static void rt2800_brightness_set(struct led_classdev *led_cdev,
1171                                   enum led_brightness brightness)
1172 {
1173         struct rt2x00_led *led =
1174             container_of(led_cdev, struct rt2x00_led, led_dev);
1175         unsigned int enabled = brightness != LED_OFF;
1176         unsigned int bg_mode =
1177             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
1178         unsigned int polarity =
1179                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1180                                    EEPROM_FREQ_LED_POLARITY);
1181         unsigned int ledmode =
1182                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1183                                    EEPROM_FREQ_LED_MODE);
1184         u32 reg;
1185
1186         /* Check for SoC (SOC devices don't support MCU requests) */
1187         if (rt2x00_is_soc(led->rt2x00dev)) {
1188                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1189
1190                 /* Set LED Polarity */
1191                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1192
1193                 /* Set LED Mode */
1194                 if (led->type == LED_TYPE_RADIO) {
1195                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1196                                            enabled ? 3 : 0);
1197                 } else if (led->type == LED_TYPE_ASSOC) {
1198                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1199                                            enabled ? 3 : 0);
1200                 } else if (led->type == LED_TYPE_QUALITY) {
1201                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1202                                            enabled ? 3 : 0);
1203                 }
1204
1205                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1206
1207         } else {
1208                 if (led->type == LED_TYPE_RADIO) {
1209                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1210                                               enabled ? 0x20 : 0);
1211                 } else if (led->type == LED_TYPE_ASSOC) {
1212                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1213                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1214                 } else if (led->type == LED_TYPE_QUALITY) {
1215                         /*
1216                          * The brightness is divided into 6 levels (0 - 5),
1217                          * The specs tell us the following levels:
1218                          *      0, 1 ,3, 7, 15, 31
1219                          * to determine the level in a simple way we can simply
1220                          * work with bitshifting:
1221                          *      (1 << level) - 1
1222                          */
1223                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1224                                               (1 << brightness / (LED_FULL / 6)) - 1,
1225                                               polarity);
1226                 }
1227         }
1228 }
1229
1230 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1231                      struct rt2x00_led *led, enum led_type type)
1232 {
1233         led->rt2x00dev = rt2x00dev;
1234         led->type = type;
1235         led->led_dev.brightness_set = rt2800_brightness_set;
1236         led->flags = LED_INITIALIZED;
1237 }
1238 #endif /* CONFIG_RT2X00_LIB_LEDS */
1239
1240 /*
1241  * Configuration handlers.
1242  */
1243 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1244                                const u8 *address,
1245                                int wcid)
1246 {
1247         struct mac_wcid_entry wcid_entry;
1248         u32 offset;
1249
1250         offset = MAC_WCID_ENTRY(wcid);
1251
1252         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1253         if (address)
1254                 memcpy(wcid_entry.mac, address, ETH_ALEN);
1255
1256         rt2800_register_multiwrite(rt2x00dev, offset,
1257                                       &wcid_entry, sizeof(wcid_entry));
1258 }
1259
1260 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1261 {
1262         u32 offset;
1263         offset = MAC_WCID_ATTR_ENTRY(wcid);
1264         rt2800_register_write(rt2x00dev, offset, 0);
1265 }
1266
1267 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1268                                            int wcid, u32 bssidx)
1269 {
1270         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1271         u32 reg;
1272
1273         /*
1274          * The BSS Idx numbers is split in a main value of 3 bits,
1275          * and a extended field for adding one additional bit to the value.
1276          */
1277         rt2800_register_read(rt2x00dev, offset, &reg);
1278         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1279         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1280                            (bssidx & 0x8) >> 3);
1281         rt2800_register_write(rt2x00dev, offset, reg);
1282 }
1283
1284 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1285                                            struct rt2x00lib_crypto *crypto,
1286                                            struct ieee80211_key_conf *key)
1287 {
1288         struct mac_iveiv_entry iveiv_entry;
1289         u32 offset;
1290         u32 reg;
1291
1292         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1293
1294         if (crypto->cmd == SET_KEY) {
1295                 rt2800_register_read(rt2x00dev, offset, &reg);
1296                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1297                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1298                 /*
1299                  * Both the cipher as the BSS Idx numbers are split in a main
1300                  * value of 3 bits, and a extended field for adding one additional
1301                  * bit to the value.
1302                  */
1303                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1304                                    (crypto->cipher & 0x7));
1305                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1306                                    (crypto->cipher & 0x8) >> 3);
1307                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1308                 rt2800_register_write(rt2x00dev, offset, reg);
1309         } else {
1310                 /* Delete the cipher without touching the bssidx */
1311                 rt2800_register_read(rt2x00dev, offset, &reg);
1312                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1313                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1314                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1315                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1316                 rt2800_register_write(rt2x00dev, offset, reg);
1317         }
1318
1319         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1320
1321         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1322         if ((crypto->cipher == CIPHER_TKIP) ||
1323             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1324             (crypto->cipher == CIPHER_AES))
1325                 iveiv_entry.iv[3] |= 0x20;
1326         iveiv_entry.iv[3] |= key->keyidx << 6;
1327         rt2800_register_multiwrite(rt2x00dev, offset,
1328                                       &iveiv_entry, sizeof(iveiv_entry));
1329 }
1330
1331 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1332                              struct rt2x00lib_crypto *crypto,
1333                              struct ieee80211_key_conf *key)
1334 {
1335         struct hw_key_entry key_entry;
1336         struct rt2x00_field32 field;
1337         u32 offset;
1338         u32 reg;
1339
1340         if (crypto->cmd == SET_KEY) {
1341                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1342
1343                 memcpy(key_entry.key, crypto->key,
1344                        sizeof(key_entry.key));
1345                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1346                        sizeof(key_entry.tx_mic));
1347                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1348                        sizeof(key_entry.rx_mic));
1349
1350                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1351                 rt2800_register_multiwrite(rt2x00dev, offset,
1352                                               &key_entry, sizeof(key_entry));
1353         }
1354
1355         /*
1356          * The cipher types are stored over multiple registers
1357          * starting with SHARED_KEY_MODE_BASE each word will have
1358          * 32 bits and contains the cipher types for 2 bssidx each.
1359          * Using the correct defines correctly will cause overhead,
1360          * so just calculate the correct offset.
1361          */
1362         field.bit_offset = 4 * (key->hw_key_idx % 8);
1363         field.bit_mask = 0x7 << field.bit_offset;
1364
1365         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1366
1367         rt2800_register_read(rt2x00dev, offset, &reg);
1368         rt2x00_set_field32(&reg, field,
1369                            (crypto->cmd == SET_KEY) * crypto->cipher);
1370         rt2800_register_write(rt2x00dev, offset, reg);
1371
1372         /*
1373          * Update WCID information
1374          */
1375         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1376         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1377                                        crypto->bssidx);
1378         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1379
1380         return 0;
1381 }
1382 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1383
1384 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1385                                struct rt2x00lib_crypto *crypto,
1386                                struct ieee80211_key_conf *key)
1387 {
1388         struct hw_key_entry key_entry;
1389         u32 offset;
1390
1391         if (crypto->cmd == SET_KEY) {
1392                 /*
1393                  * Allow key configuration only for STAs that are
1394                  * known by the hw.
1395                  */
1396                 if (crypto->wcid > WCID_END)
1397                         return -ENOSPC;
1398                 key->hw_key_idx = crypto->wcid;
1399
1400                 memcpy(key_entry.key, crypto->key,
1401                        sizeof(key_entry.key));
1402                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1403                        sizeof(key_entry.tx_mic));
1404                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1405                        sizeof(key_entry.rx_mic));
1406
1407                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1408                 rt2800_register_multiwrite(rt2x00dev, offset,
1409                                               &key_entry, sizeof(key_entry));
1410         }
1411
1412         /*
1413          * Update WCID information
1414          */
1415         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1416
1417         return 0;
1418 }
1419 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1420
1421 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1422                    struct ieee80211_sta *sta)
1423 {
1424         int wcid;
1425         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1426         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1427
1428         /*
1429          * Search for the first free WCID entry and return the corresponding
1430          * index.
1431          */
1432         wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START;
1433
1434         /*
1435          * Store selected wcid even if it is invalid so that we can
1436          * later decide if the STA is uploaded into the hw.
1437          */
1438         sta_priv->wcid = wcid;
1439
1440         /*
1441          * No space left in the device, however, we can still communicate
1442          * with the STA -> No error.
1443          */
1444         if (wcid > WCID_END)
1445                 return 0;
1446
1447         __set_bit(wcid - WCID_START, drv_data->sta_ids);
1448
1449         /*
1450          * Clean up WCID attributes and write STA address to the device.
1451          */
1452         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1453         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1454         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1455                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1456         return 0;
1457 }
1458 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1459
1460 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1461 {
1462         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1463
1464         if (wcid > WCID_END)
1465                 return 0;
1466         /*
1467          * Remove WCID entry, no need to clean the attributes as they will
1468          * get renewed when the WCID is reused.
1469          */
1470         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1471         __clear_bit(wcid - WCID_START, drv_data->sta_ids);
1472
1473         return 0;
1474 }
1475 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1476
1477 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1478                           const unsigned int filter_flags)
1479 {
1480         u32 reg;
1481
1482         /*
1483          * Start configuration steps.
1484          * Note that the version error will always be dropped
1485          * and broadcast frames will always be accepted since
1486          * there is no filter for it at this time.
1487          */
1488         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1489         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1490                            !(filter_flags & FIF_FCSFAIL));
1491         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1492                            !(filter_flags & FIF_PLCPFAIL));
1493         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME, 1);
1494         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1495         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1496         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1497                            !(filter_flags & FIF_ALLMULTI));
1498         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1499         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1500         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1501                            !(filter_flags & FIF_CONTROL));
1502         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1503                            !(filter_flags & FIF_CONTROL));
1504         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1505                            !(filter_flags & FIF_CONTROL));
1506         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1507                            !(filter_flags & FIF_CONTROL));
1508         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1509                            !(filter_flags & FIF_CONTROL));
1510         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1511                            !(filter_flags & FIF_PSPOLL));
1512         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1513         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1514                            !(filter_flags & FIF_CONTROL));
1515         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1516                            !(filter_flags & FIF_CONTROL));
1517         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1518 }
1519 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1520
1521 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1522                         struct rt2x00intf_conf *conf, const unsigned int flags)
1523 {
1524         u32 reg;
1525         bool update_bssid = false;
1526
1527         if (flags & CONFIG_UPDATE_TYPE) {
1528                 /*
1529                  * Enable synchronisation.
1530                  */
1531                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1532                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1533                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1534
1535                 if (conf->sync == TSF_SYNC_AP_NONE) {
1536                         /*
1537                          * Tune beacon queue transmit parameters for AP mode
1538                          */
1539                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1540                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1541                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1542                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1543                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1544                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1545                 } else {
1546                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1547                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1548                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1549                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1550                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1551                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1552                 }
1553         }
1554
1555         if (flags & CONFIG_UPDATE_MAC) {
1556                 if (flags & CONFIG_UPDATE_TYPE &&
1557                     conf->sync == TSF_SYNC_AP_NONE) {
1558                         /*
1559                          * The BSSID register has to be set to our own mac
1560                          * address in AP mode.
1561                          */
1562                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1563                         update_bssid = true;
1564                 }
1565
1566                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1567                         reg = le32_to_cpu(conf->mac[1]);
1568                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1569                         conf->mac[1] = cpu_to_le32(reg);
1570                 }
1571
1572                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1573                                               conf->mac, sizeof(conf->mac));
1574         }
1575
1576         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1577                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1578                         reg = le32_to_cpu(conf->bssid[1]);
1579                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1580                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
1581                         conf->bssid[1] = cpu_to_le32(reg);
1582                 }
1583
1584                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1585                                               conf->bssid, sizeof(conf->bssid));
1586         }
1587 }
1588 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1589
1590 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1591                                     struct rt2x00lib_erp *erp)
1592 {
1593         bool any_sta_nongf = !!(erp->ht_opmode &
1594                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1595         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1596         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1597         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1598         u32 reg;
1599
1600         /* default protection rate for HT20: OFDM 24M */
1601         mm20_rate = gf20_rate = 0x4004;
1602
1603         /* default protection rate for HT40: duplicate OFDM 24M */
1604         mm40_rate = gf40_rate = 0x4084;
1605
1606         switch (protection) {
1607         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1608                 /*
1609                  * All STAs in this BSS are HT20/40 but there might be
1610                  * STAs not supporting greenfield mode.
1611                  * => Disable protection for HT transmissions.
1612                  */
1613                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1614
1615                 break;
1616         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1617                 /*
1618                  * All STAs in this BSS are HT20 or HT20/40 but there
1619                  * might be STAs not supporting greenfield mode.
1620                  * => Protect all HT40 transmissions.
1621                  */
1622                 mm20_mode = gf20_mode = 0;
1623                 mm40_mode = gf40_mode = 2;
1624
1625                 break;
1626         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1627                 /*
1628                  * Nonmember protection:
1629                  * According to 802.11n we _should_ protect all
1630                  * HT transmissions (but we don't have to).
1631                  *
1632                  * But if cts_protection is enabled we _shall_ protect
1633                  * all HT transmissions using a CCK rate.
1634                  *
1635                  * And if any station is non GF we _shall_ protect
1636                  * GF transmissions.
1637                  *
1638                  * We decide to protect everything
1639                  * -> fall through to mixed mode.
1640                  */
1641         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1642                 /*
1643                  * Legacy STAs are present
1644                  * => Protect all HT transmissions.
1645                  */
1646                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1647
1648                 /*
1649                  * If erp protection is needed we have to protect HT
1650                  * transmissions with CCK 11M long preamble.
1651                  */
1652                 if (erp->cts_protection) {
1653                         /* don't duplicate RTS/CTS in CCK mode */
1654                         mm20_rate = mm40_rate = 0x0003;
1655                         gf20_rate = gf40_rate = 0x0003;
1656                 }
1657                 break;
1658         }
1659
1660         /* check for STAs not supporting greenfield mode */
1661         if (any_sta_nongf)
1662                 gf20_mode = gf40_mode = 2;
1663
1664         /* Update HT protection config */
1665         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1666         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1667         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1668         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1669
1670         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1671         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1672         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1673         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1674
1675         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1676         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1677         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1678         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1679
1680         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1681         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1682         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1683         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1684 }
1685
1686 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1687                        u32 changed)
1688 {
1689         u32 reg;
1690
1691         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1692                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1693                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1694                                    !!erp->short_preamble);
1695                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1696                                    !!erp->short_preamble);
1697                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1698         }
1699
1700         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1701                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1702                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1703                                    erp->cts_protection ? 2 : 0);
1704                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1705         }
1706
1707         if (changed & BSS_CHANGED_BASIC_RATES) {
1708                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1709                                          erp->basic_rates);
1710                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1711         }
1712
1713         if (changed & BSS_CHANGED_ERP_SLOT) {
1714                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1715                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1716                                    erp->slot_time);
1717                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1718
1719                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1720                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1721                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1722         }
1723
1724         if (changed & BSS_CHANGED_BEACON_INT) {
1725                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1726                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1727                                    erp->beacon_int * 16);
1728                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1729         }
1730
1731         if (changed & BSS_CHANGED_HT)
1732                 rt2800_config_ht_opmode(rt2x00dev, erp);
1733 }
1734 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1735
1736 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1737 {
1738         u32 reg;
1739         u16 eeprom;
1740         u8 led_ctrl, led_g_mode, led_r_mode;
1741
1742         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1743         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1744                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1745                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1746         } else {
1747                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1748                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1749         }
1750         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1751
1752         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1753         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1754         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1755         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1756             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1757                 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1758                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1759                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1760                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1761                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1762                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1763                 } else {
1764                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1765                                            (led_g_mode << 2) | led_r_mode, 1);
1766                 }
1767         }
1768 }
1769
1770 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1771                                      enum antenna ant)
1772 {
1773         u32 reg;
1774         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1775         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1776
1777         if (rt2x00_is_pci(rt2x00dev)) {
1778                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1779                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1780                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1781         } else if (rt2x00_is_usb(rt2x00dev))
1782                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1783                                    eesk_pin, 0);
1784
1785         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1786         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1787         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1788         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1789 }
1790
1791 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1792 {
1793         u8 r1;
1794         u8 r3;
1795         u16 eeprom;
1796
1797         rt2800_bbp_read(rt2x00dev, 1, &r1);
1798         rt2800_bbp_read(rt2x00dev, 3, &r3);
1799
1800         if (rt2x00_rt(rt2x00dev, RT3572) &&
1801             rt2x00_has_cap_bt_coexist(rt2x00dev))
1802                 rt2800_config_3572bt_ant(rt2x00dev);
1803
1804         /*
1805          * Configure the TX antenna.
1806          */
1807         switch (ant->tx_chain_num) {
1808         case 1:
1809                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1810                 break;
1811         case 2:
1812                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1813                     rt2x00_has_cap_bt_coexist(rt2x00dev))
1814                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1815                 else
1816                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1817                 break;
1818         case 3:
1819                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1820                 break;
1821         }
1822
1823         /*
1824          * Configure the RX antenna.
1825          */
1826         switch (ant->rx_chain_num) {
1827         case 1:
1828                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1829                     rt2x00_rt(rt2x00dev, RT3090) ||
1830                     rt2x00_rt(rt2x00dev, RT3352) ||
1831                     rt2x00_rt(rt2x00dev, RT3390)) {
1832                         rt2800_eeprom_read(rt2x00dev,
1833                                            EEPROM_NIC_CONF1, &eeprom);
1834                         if (rt2x00_get_field16(eeprom,
1835                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1836                                 rt2800_set_ant_diversity(rt2x00dev,
1837                                                 rt2x00dev->default_ant.rx);
1838                 }
1839                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1840                 break;
1841         case 2:
1842                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1843                     rt2x00_has_cap_bt_coexist(rt2x00dev)) {
1844                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1845                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1846                                 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1847                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1848                 } else {
1849                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1850                 }
1851                 break;
1852         case 3:
1853                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1854                 break;
1855         }
1856
1857         rt2800_bbp_write(rt2x00dev, 3, r3);
1858         rt2800_bbp_write(rt2x00dev, 1, r1);
1859
1860         if (rt2x00_rt(rt2x00dev, RT3593)) {
1861                 if (ant->rx_chain_num == 1)
1862                         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1863                 else
1864                         rt2800_bbp_write(rt2x00dev, 86, 0x46);
1865         }
1866 }
1867 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1868
1869 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1870                                    struct rt2x00lib_conf *libconf)
1871 {
1872         u16 eeprom;
1873         short lna_gain;
1874
1875         if (libconf->rf.channel <= 14) {
1876                 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1877                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1878         } else if (libconf->rf.channel <= 64) {
1879                 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1880                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1881         } else if (libconf->rf.channel <= 128) {
1882                 if (rt2x00_rt(rt2x00dev, RT3593)) {
1883                         rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1884                         lna_gain = rt2x00_get_field16(eeprom,
1885                                                       EEPROM_EXT_LNA2_A1);
1886                 } else {
1887                         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1888                         lna_gain = rt2x00_get_field16(eeprom,
1889                                                       EEPROM_RSSI_BG2_LNA_A1);
1890                 }
1891         } else {
1892                 if (rt2x00_rt(rt2x00dev, RT3593)) {
1893                         rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1894                         lna_gain = rt2x00_get_field16(eeprom,
1895                                                       EEPROM_EXT_LNA2_A2);
1896                 } else {
1897                         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1898                         lna_gain = rt2x00_get_field16(eeprom,
1899                                                       EEPROM_RSSI_A2_LNA_A2);
1900                 }
1901         }
1902
1903         rt2x00dev->lna_gain = lna_gain;
1904 }
1905
1906 #define FREQ_OFFSET_BOUND       0x5f
1907
1908 static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
1909 {
1910         u8 freq_offset, prev_freq_offset;
1911         u8 rfcsr, prev_rfcsr;
1912
1913         freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
1914         freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
1915
1916         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1917         prev_rfcsr = rfcsr;
1918
1919         rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
1920         if (rfcsr == prev_rfcsr)
1921                 return;
1922
1923         if (rt2x00_is_usb(rt2x00dev)) {
1924                 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
1925                                    freq_offset, prev_rfcsr);
1926                 return;
1927         }
1928
1929         prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
1930         while (prev_freq_offset != freq_offset) {
1931                 if (prev_freq_offset < freq_offset)
1932                         prev_freq_offset++;
1933                 else
1934                         prev_freq_offset--;
1935
1936                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
1937                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1938
1939                 usleep_range(1000, 1500);
1940         }
1941 }
1942
1943 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1944                                          struct ieee80211_conf *conf,
1945                                          struct rf_channel *rf,
1946                                          struct channel_info *info)
1947 {
1948         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1949
1950         if (rt2x00dev->default_ant.tx_chain_num == 1)
1951                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1952
1953         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1954                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1955                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1956         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1957                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1958
1959         if (rf->channel > 14) {
1960                 /*
1961                  * When TX power is below 0, we should increase it by 7 to
1962                  * make it a positive value (Minimum value is -7).
1963                  * However this means that values between 0 and 7 have
1964                  * double meaning, and we should set a 7DBm boost flag.
1965                  */
1966                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1967                                    (info->default_power1 >= 0));
1968
1969                 if (info->default_power1 < 0)
1970                         info->default_power1 += 7;
1971
1972                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1973
1974                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1975                                    (info->default_power2 >= 0));
1976
1977                 if (info->default_power2 < 0)
1978                         info->default_power2 += 7;
1979
1980                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1981         } else {
1982                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1983                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1984         }
1985
1986         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1987
1988         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1989         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1990         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1991         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1992
1993         udelay(200);
1994
1995         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1996         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1997         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1998         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1999
2000         udelay(200);
2001
2002         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2003         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2004         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2005         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2006 }
2007
2008 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2009                                          struct ieee80211_conf *conf,
2010                                          struct rf_channel *rf,
2011                                          struct channel_info *info)
2012 {
2013         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2014         u8 rfcsr, calib_tx, calib_rx;
2015
2016         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2017
2018         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2019         rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2020         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2021
2022         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2023         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2024         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2025
2026         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2027         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
2028         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2029
2030         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2031         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
2032         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2033
2034         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2035         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2036         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2037                           rt2x00dev->default_ant.rx_chain_num <= 1);
2038         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2039                           rt2x00dev->default_ant.rx_chain_num <= 2);
2040         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2041         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2042                           rt2x00dev->default_ant.tx_chain_num <= 1);
2043         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2044                           rt2x00dev->default_ant.tx_chain_num <= 2);
2045         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2046
2047         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2048         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2049         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2050
2051         if (rt2x00_rt(rt2x00dev, RT3390)) {
2052                 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2053                 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2054         } else {
2055                 if (conf_is_ht40(conf)) {
2056                         calib_tx = drv_data->calibration_bw40;
2057                         calib_rx = drv_data->calibration_bw40;
2058                 } else {
2059                         calib_tx = drv_data->calibration_bw20;
2060                         calib_rx = drv_data->calibration_bw20;
2061                 }
2062         }
2063
2064         rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
2065         rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2066         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2067
2068         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2069         rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2070         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2071
2072         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2073         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2074         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2075
2076         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2077         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2078         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2079         msleep(1);
2080         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2081         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2082 }
2083
2084 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2085                                          struct ieee80211_conf *conf,
2086                                          struct rf_channel *rf,
2087                                          struct channel_info *info)
2088 {
2089         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2090         u8 rfcsr;
2091         u32 reg;
2092
2093         if (rf->channel <= 14) {
2094                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2095                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2096         } else {
2097                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2098                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2099         }
2100
2101         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2102         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2103
2104         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2105         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2106         if (rf->channel <= 14)
2107                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2108         else
2109                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2110         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2111
2112         rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
2113         if (rf->channel <= 14)
2114                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2115         else
2116                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2117         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2118
2119         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2120         if (rf->channel <= 14) {
2121                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2122                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2123                                   info->default_power1);
2124         } else {
2125                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2126                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2127                                 (info->default_power1 & 0x3) |
2128                                 ((info->default_power1 & 0xC) << 1));
2129         }
2130         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2131
2132         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2133         if (rf->channel <= 14) {
2134                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2135                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2136                                   info->default_power2);
2137         } else {
2138                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2139                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2140                                 (info->default_power2 & 0x3) |
2141                                 ((info->default_power2 & 0xC) << 1));
2142         }
2143         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2144
2145         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2146         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2147         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2148         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2149         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2150         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2151         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2152         if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2153                 if (rf->channel <= 14) {
2154                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2155                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2156                 }
2157                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2158                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2159         } else {
2160                 switch (rt2x00dev->default_ant.tx_chain_num) {
2161                 case 1:
2162                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2163                 case 2:
2164                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2165                         break;
2166                 }
2167
2168                 switch (rt2x00dev->default_ant.rx_chain_num) {
2169                 case 1:
2170                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2171                 case 2:
2172                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2173                         break;
2174                 }
2175         }
2176         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2177
2178         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2179         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2180         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2181
2182         if (conf_is_ht40(conf)) {
2183                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2184                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2185         } else {
2186                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2187                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2188         }
2189
2190         if (rf->channel <= 14) {
2191                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2192                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2193                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2194                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2195                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2196                 rfcsr = 0x4c;
2197                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2198                                   drv_data->txmixer_gain_24g);
2199                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2200                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2201                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2202                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2203                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2204                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2205                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2206                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2207         } else {
2208                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2209                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2210                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2211                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2212                 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2213                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2214                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2215                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2216                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2217                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2218                 rfcsr = 0x7a;
2219                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2220                                   drv_data->txmixer_gain_5g);
2221                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2222                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2223                 if (rf->channel <= 64) {
2224                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2225                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2226                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2227                 } else if (rf->channel <= 128) {
2228                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2229                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2230                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2231                 } else {
2232                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2233                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2234                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2235                 }
2236                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2237                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2238                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2239         }
2240
2241         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2242         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
2243         if (rf->channel <= 14)
2244                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
2245         else
2246                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2247         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2248
2249         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2250         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2251         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2252 }
2253
2254 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2255                                          struct ieee80211_conf *conf,
2256                                          struct rf_channel *rf,
2257                                          struct channel_info *info)
2258 {
2259         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2260         u8 txrx_agc_fc;
2261         u8 txrx_h20m;
2262         u8 rfcsr;
2263         u8 bbp;
2264         const bool txbf_enabled = false; /* TODO */
2265
2266         /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2267         rt2800_bbp_read(rt2x00dev, 109, &bbp);
2268         rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2269         rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2270         rt2800_bbp_write(rt2x00dev, 109, bbp);
2271
2272         rt2800_bbp_read(rt2x00dev, 110, &bbp);
2273         rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2274         rt2800_bbp_write(rt2x00dev, 110, bbp);
2275
2276         if (rf->channel <= 14) {
2277                 /* Restore BBP 25 & 26 for 2.4 GHz */
2278                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2279                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2280         } else {
2281                 /* Hard code BBP 25 & 26 for 5GHz */
2282
2283                 /* Enable IQ Phase correction */
2284                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2285                 /* Setup IQ Phase correction value */
2286                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2287         }
2288
2289         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2290         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2291
2292         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2293         rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2294         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2295
2296         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2297         rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2298         if (rf->channel <= 14)
2299                 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2300         else
2301                 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2302         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2303
2304         rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr);
2305         if (rf->channel <= 14) {
2306                 rfcsr = 0;
2307                 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2308                                   info->default_power1 & 0x1f);
2309         } else {
2310                 if (rt2x00_is_usb(rt2x00dev))
2311                         rfcsr = 0x40;
2312
2313                 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2314                                   ((info->default_power1 & 0x18) << 1) |
2315                                   (info->default_power1 & 7));
2316         }
2317         rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2318
2319         rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr);
2320         if (rf->channel <= 14) {
2321                 rfcsr = 0;
2322                 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2323                                   info->default_power2 & 0x1f);
2324         } else {
2325                 if (rt2x00_is_usb(rt2x00dev))
2326                         rfcsr = 0x40;
2327
2328                 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2329                                   ((info->default_power2 & 0x18) << 1) |
2330                                   (info->default_power2 & 7));
2331         }
2332         rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2333
2334         rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr);
2335         if (rf->channel <= 14) {
2336                 rfcsr = 0;
2337                 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2338                                   info->default_power3 & 0x1f);
2339         } else {
2340                 if (rt2x00_is_usb(rt2x00dev))
2341                         rfcsr = 0x40;
2342
2343                 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2344                                   ((info->default_power3 & 0x18) << 1) |
2345                                   (info->default_power3 & 7));
2346         }
2347         rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2348
2349         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2350         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2351         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2352         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2353         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2354         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2355         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2356         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2357         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2358
2359         switch (rt2x00dev->default_ant.tx_chain_num) {
2360         case 3:
2361                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2362                 /* fallthrough */
2363         case 2:
2364                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2365                 /* fallthrough */
2366         case 1:
2367                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2368                 break;
2369         }
2370
2371         switch (rt2x00dev->default_ant.rx_chain_num) {
2372         case 3:
2373                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2374                 /* fallthrough */
2375         case 2:
2376                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2377                 /* fallthrough */
2378         case 1:
2379                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2380                 break;
2381         }
2382         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2383
2384         rt2800_adjust_freq_offset(rt2x00dev);
2385
2386         if (conf_is_ht40(conf)) {
2387                 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2388                                                 RFCSR24_TX_AGC_FC);
2389                 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2390                                               RFCSR24_TX_H20M);
2391         } else {
2392                 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2393                                                 RFCSR24_TX_AGC_FC);
2394                 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2395                                               RFCSR24_TX_H20M);
2396         }
2397
2398         /* NOTE: the reference driver does not writes the new value
2399          * back to RFCSR 32
2400          */
2401         rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr);
2402         rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2403
2404         if (rf->channel <= 14)
2405                 rfcsr = 0xa0;
2406         else
2407                 rfcsr = 0x80;
2408         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2409
2410         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2411         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2412         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2413         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2414
2415         /* Band selection */
2416         rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr);
2417         if (rf->channel <= 14)
2418                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2419         else
2420                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2421         rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2422
2423         rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr);
2424         if (rf->channel <= 14)
2425                 rfcsr = 0x3c;
2426         else
2427                 rfcsr = 0x20;
2428         rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2429
2430         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2431         if (rf->channel <= 14)
2432                 rfcsr = 0x1a;
2433         else
2434                 rfcsr = 0x12;
2435         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2436
2437         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2438         if (rf->channel >= 1 && rf->channel <= 14)
2439                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2440         else if (rf->channel >= 36 && rf->channel <= 64)
2441                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2442         else if (rf->channel >= 100 && rf->channel <= 128)
2443                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2444         else
2445                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2446         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2447
2448         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2449         rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2450         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2451
2452         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2453
2454         if (rf->channel <= 14) {
2455                 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2456                 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2457         } else {
2458                 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2459                 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2460         }
2461
2462         rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2463         rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2464         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2465
2466         rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2467         if (rf->channel <= 14) {
2468                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2469                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2470         } else {
2471                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2472                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2473         }
2474         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2475
2476         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2477         if (rf->channel <= 14)
2478                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2479         else
2480                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2481
2482         if (txbf_enabled)
2483                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2484
2485         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2486
2487         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2488         rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2489         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2490
2491         rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr);
2492         if (rf->channel <= 14)
2493                 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2494         else
2495                 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2496         rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2497
2498         if (rf->channel <= 14) {
2499                 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2500                 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2501         } else {
2502                 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2503                 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2504         }
2505
2506         /* Initiate VCO calibration */
2507         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2508         if (rf->channel <= 14) {
2509                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2510         } else {
2511                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2512                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2513                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2514                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2515                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2516                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2517         }
2518         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2519
2520         if (rf->channel >= 1 && rf->channel <= 14) {
2521                 rfcsr = 0x23;
2522                 if (txbf_enabled)
2523                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2524                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2525
2526                 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2527         } else if (rf->channel >= 36 && rf->channel <= 64) {
2528                 rfcsr = 0x36;
2529                 if (txbf_enabled)
2530                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2531                 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2532
2533                 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2534         } else if (rf->channel >= 100 && rf->channel <= 128) {
2535                 rfcsr = 0x32;
2536                 if (txbf_enabled)
2537                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2538                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2539
2540                 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2541         } else {
2542                 rfcsr = 0x30;
2543                 if (txbf_enabled)
2544                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2545                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2546
2547                 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2548         }
2549 }
2550
2551 #define POWER_BOUND             0x27
2552 #define POWER_BOUND_5G          0x2b
2553
2554 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2555                                          struct ieee80211_conf *conf,
2556                                          struct rf_channel *rf,
2557                                          struct channel_info *info)
2558 {
2559         u8 rfcsr;
2560
2561         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2562         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2563         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2564         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2565         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2566
2567         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2568         if (info->default_power1 > POWER_BOUND)
2569                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2570         else
2571                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2572         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2573
2574         rt2800_adjust_freq_offset(rt2x00dev);
2575
2576         if (rf->channel <= 14) {
2577                 if (rf->channel == 6)
2578                         rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2579                 else
2580                         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2581
2582                 if (rf->channel >= 1 && rf->channel <= 6)
2583                         rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2584                 else if (rf->channel >= 7 && rf->channel <= 11)
2585                         rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2586                 else if (rf->channel >= 12 && rf->channel <= 14)
2587                         rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2588         }
2589 }
2590
2591 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2592                                          struct ieee80211_conf *conf,
2593                                          struct rf_channel *rf,
2594                                          struct channel_info *info)
2595 {
2596         u8 rfcsr;
2597
2598         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2599         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2600
2601         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2602         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2603         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2604
2605         if (info->default_power1 > POWER_BOUND)
2606                 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2607         else
2608                 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2609
2610         if (info->default_power2 > POWER_BOUND)
2611                 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2612         else
2613                 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2614
2615         rt2800_adjust_freq_offset(rt2x00dev);
2616
2617         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2618         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2619         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2620
2621         if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2622                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2623         else
2624                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2625
2626         if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2627                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2628         else
2629                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2630
2631         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2632         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2633
2634         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2635
2636         rt2800_rfcsr_write(rt2x00dev, 31, 80);
2637 }
2638
2639 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2640                                          struct ieee80211_conf *conf,
2641                                          struct rf_channel *rf,
2642                                          struct channel_info *info)
2643 {
2644         u8 rfcsr;
2645
2646         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2647         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2648         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2649         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2650         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2651
2652         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2653         if (info->default_power1 > POWER_BOUND)
2654                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2655         else
2656                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2657         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2658
2659         if (rt2x00_rt(rt2x00dev, RT5392)) {
2660                 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2661                 if (info->default_power2 > POWER_BOUND)
2662                         rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2663                 else
2664                         rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2665                                           info->default_power2);
2666                 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2667         }
2668
2669         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2670         if (rt2x00_rt(rt2x00dev, RT5392)) {
2671                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2672                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2673         }
2674         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2675         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2676         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2677         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2678         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2679
2680         rt2800_adjust_freq_offset(rt2x00dev);
2681
2682         if (rf->channel <= 14) {
2683                 int idx = rf->channel-1;
2684
2685                 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2686                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2687                                 /* r55/r59 value array of channel 1~14 */
2688                                 static const char r55_bt_rev[] = {0x83, 0x83,
2689                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2690                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2691                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
2692                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2693                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2694
2695                                 rt2800_rfcsr_write(rt2x00dev, 55,
2696                                                    r55_bt_rev[idx]);
2697                                 rt2800_rfcsr_write(rt2x00dev, 59,
2698                                                    r59_bt_rev[idx]);
2699                         } else {
2700                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2701                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2702                                         0x88, 0x88, 0x86, 0x85, 0x84};
2703
2704                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2705                         }
2706                 } else {
2707                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2708                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
2709                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2710                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2711                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
2712                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2713                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2714
2715                                 rt2800_rfcsr_write(rt2x00dev, 55,
2716                                                    r55_nonbt_rev[idx]);
2717                                 rt2800_rfcsr_write(rt2x00dev, 59,
2718                                                    r59_nonbt_rev[idx]);
2719                         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2720                                    rt2x00_rt(rt2x00dev, RT5392)) {
2721                                 static const char r59_non_bt[] = {0x8f, 0x8f,
2722                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2723                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2724
2725                                 rt2800_rfcsr_write(rt2x00dev, 59,
2726                                                    r59_non_bt[idx]);
2727                         }
2728                 }
2729         }
2730 }
2731
2732 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2733                                          struct ieee80211_conf *conf,
2734                                          struct rf_channel *rf,
2735                                          struct channel_info *info)
2736 {
2737         u8 rfcsr, ep_reg;
2738         u32 reg;
2739         int power_bound;
2740
2741         /* TODO */
2742         const bool is_11b = false;
2743         const bool is_type_ep = false;
2744
2745         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2746         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2747                            (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2748         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2749
2750         /* Order of values on rf_channel entry: N, K, mod, R */
2751         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2752
2753         rt2800_rfcsr_read(rt2x00dev,  9, &rfcsr);
2754         rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2755         rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2756         rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2757         rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2758
2759         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2760         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2761         rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2762         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2763
2764         if (rf->channel <= 14) {
2765                 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2766                 /* FIXME: RF11 owerwrite ? */
2767                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2768                 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2769                 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2770                 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2771                 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2772                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2773                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2774                 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2775                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2776                 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2777                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2778                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2779                 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2780                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2781                 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2782                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2783                 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2784                 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2785                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2786                 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2787                 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2788                 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2789                 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2790                 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2791                 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2792                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2793                 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2794                 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2795
2796                 /* TODO RF27 <- tssi */
2797
2798                 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2799                 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2800                 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2801
2802                 if (is_11b) {
2803                         /* CCK */
2804                         rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2805                         rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2806                         if (is_type_ep)
2807                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2808                         else
2809                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2810                 } else {
2811                         /* OFDM */
2812                         if (is_type_ep)
2813                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2814                         else
2815                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2816                 }
2817
2818                 power_bound = POWER_BOUND;
2819                 ep_reg = 0x2;
2820         } else {
2821                 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2822                 /* FIMXE: RF11 overwrite */
2823                 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2824                 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2825                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2826                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2827                 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2828                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2829                 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2830                 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2831                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2832                 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2833                 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2834                 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2835                 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2836                 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2837
2838                 /* TODO RF27 <- tssi */
2839
2840                 if (rf->channel >= 36 && rf->channel <= 64) {
2841
2842                         rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2843                         rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2844                         rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2845                         rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2846                         if (rf->channel <= 50)
2847                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2848                         else if (rf->channel >= 52)
2849                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2850                         rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2851                         rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2852                         rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2853                         rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2854                         rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2855                         rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2856                         rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2857                         if (rf->channel <= 50) {
2858                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2859                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2860                         } else if (rf->channel >= 52) {
2861                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2862                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2863                         }
2864
2865                         rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2866                         rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2867                         rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2868
2869                 } else if (rf->channel >= 100 && rf->channel <= 165) {
2870
2871                         rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2872                         rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2873                         rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2874                         if (rf->channel <= 153) {
2875                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2876                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2877                         } else if (rf->channel >= 155) {
2878                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2879                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2880                         }
2881                         if (rf->channel <= 138) {
2882                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2883                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2884                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2885                                 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2886                         } else if (rf->channel >= 140) {
2887                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2888                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2889                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2890                                 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2891                         }
2892                         if (rf->channel <= 124)
2893                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2894                         else if (rf->channel >= 126)
2895                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2896                         if (rf->channel <= 138)
2897                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2898                         else if (rf->channel >= 140)
2899                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2900                         rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2901                         if (rf->channel <= 138)
2902                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2903                         else if (rf->channel >= 140)
2904                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2905                         if (rf->channel <= 128)
2906                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2907                         else if (rf->channel >= 130)
2908                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2909                         if (rf->channel <= 116)
2910                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2911                         else if (rf->channel >= 118)
2912                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2913                         if (rf->channel <= 138)
2914                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2915                         else if (rf->channel >= 140)
2916                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2917                         if (rf->channel <= 116)
2918                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2919                         else if (rf->channel >= 118)
2920                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2921                 }
2922
2923                 power_bound = POWER_BOUND_5G;
2924                 ep_reg = 0x3;
2925         }
2926
2927         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2928         if (info->default_power1 > power_bound)
2929                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2930         else
2931                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2932         if (is_type_ep)
2933                 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2934         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2935
2936         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2937         if (info->default_power2 > power_bound)
2938                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2939         else
2940                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2941         if (is_type_ep)
2942                 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2943         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2944
2945         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2946         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2947         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2948
2949         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2950                           rt2x00dev->default_ant.tx_chain_num >= 1);
2951         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2952                           rt2x00dev->default_ant.tx_chain_num == 2);
2953         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2954
2955         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2956                           rt2x00dev->default_ant.rx_chain_num >= 1);
2957         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2958                           rt2x00dev->default_ant.rx_chain_num == 2);
2959         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2960
2961         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2962         rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2963
2964         if (conf_is_ht40(conf))
2965                 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2966         else
2967                 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2968
2969         if (!is_11b) {
2970                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2971                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2972         }
2973
2974         /* TODO proper frequency adjustment */
2975         rt2800_adjust_freq_offset(rt2x00dev);
2976
2977         /* TODO merge with others */
2978         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2979         rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2980         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2981
2982         /* BBP settings */
2983         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2984         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2985         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2986
2987         rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2988         rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2989         rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2990         rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2991
2992         /* GLRT band configuration */
2993         rt2800_bbp_write(rt2x00dev, 195, 128);
2994         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2995         rt2800_bbp_write(rt2x00dev, 195, 129);
2996         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2997         rt2800_bbp_write(rt2x00dev, 195, 130);
2998         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2999         rt2800_bbp_write(rt2x00dev, 195, 131);
3000         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3001         rt2800_bbp_write(rt2x00dev, 195, 133);
3002         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3003         rt2800_bbp_write(rt2x00dev, 195, 124);
3004         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
3005 }
3006
3007 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3008                                            const unsigned int word,
3009                                            const u8 value)
3010 {
3011         u8 chain, reg;
3012
3013         for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3014                 rt2800_bbp_read(rt2x00dev, 27, &reg);
3015                 rt2x00_set_field8(&reg,  BBP27_RX_CHAIN_SEL, chain);
3016                 rt2800_bbp_write(rt2x00dev, 27, reg);
3017
3018                 rt2800_bbp_write(rt2x00dev, word, value);
3019         }
3020 }
3021
3022 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3023 {
3024         u8 cal;
3025
3026         /* TX0 IQ Gain */
3027         rt2800_bbp_write(rt2x00dev, 158, 0x2c);
3028         if (channel <= 14)
3029                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3030         else if (channel >= 36 && channel <= 64)
3031                 cal = rt2x00_eeprom_byte(rt2x00dev,
3032                                          EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3033         else if (channel >= 100 && channel <= 138)
3034                 cal = rt2x00_eeprom_byte(rt2x00dev,
3035                                          EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3036         else if (channel >= 140 && channel <= 165)
3037                 cal = rt2x00_eeprom_byte(rt2x00dev,
3038                                          EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3039         else
3040                 cal = 0;
3041         rt2800_bbp_write(rt2x00dev, 159, cal);
3042
3043         /* TX0 IQ Phase */
3044         rt2800_bbp_write(rt2x00dev, 158, 0x2d);
3045         if (channel <= 14)
3046                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3047         else if (channel >= 36 && channel <= 64)
3048                 cal = rt2x00_eeprom_byte(rt2x00dev,
3049                                          EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3050         else if (channel >= 100 && channel <= 138)
3051                 cal = rt2x00_eeprom_byte(rt2x00dev,
3052                                          EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3053         else if (channel >= 140 && channel <= 165)
3054                 cal = rt2x00_eeprom_byte(rt2x00dev,
3055                                          EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3056         else
3057                 cal = 0;
3058         rt2800_bbp_write(rt2x00dev, 159, cal);
3059
3060         /* TX1 IQ Gain */
3061         rt2800_bbp_write(rt2x00dev, 158, 0x4a);
3062         if (channel <= 14)
3063                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3064         else if (channel >= 36 && channel <= 64)
3065                 cal = rt2x00_eeprom_byte(rt2x00dev,
3066                                          EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3067         else if (channel >= 100 && channel <= 138)
3068                 cal = rt2x00_eeprom_byte(rt2x00dev,
3069                                          EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3070         else if (channel >= 140 && channel <= 165)
3071                 cal = rt2x00_eeprom_byte(rt2x00dev,
3072                                          EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3073         else
3074                 cal = 0;
3075         rt2800_bbp_write(rt2x00dev, 159, cal);
3076
3077         /* TX1 IQ Phase */
3078         rt2800_bbp_write(rt2x00dev, 158, 0x4b);
3079         if (channel <= 14)
3080                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3081         else if (channel >= 36 && channel <= 64)
3082                 cal = rt2x00_eeprom_byte(rt2x00dev,
3083                                          EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3084         else if (channel >= 100 && channel <= 138)
3085                 cal = rt2x00_eeprom_byte(rt2x00dev,
3086                                          EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3087         else if (channel >= 140 && channel <= 165)
3088                 cal = rt2x00_eeprom_byte(rt2x00dev,
3089                                          EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3090         else
3091                 cal = 0;
3092         rt2800_bbp_write(rt2x00dev, 159, cal);
3093
3094         /* FIXME: possible RX0, RX1 callibration ? */
3095
3096         /* RF IQ compensation control */
3097         rt2800_bbp_write(rt2x00dev, 158, 0x04);
3098         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3099         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3100
3101         /* RF IQ imbalance compensation control */
3102         rt2800_bbp_write(rt2x00dev, 158, 0x03);
3103         cal = rt2x00_eeprom_byte(rt2x00dev,
3104                                  EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
3105         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3106 }
3107
3108 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3109                                   unsigned int channel,
3110                                   char txpower)
3111 {
3112         if (rt2x00_rt(rt2x00dev, RT3593))
3113                 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3114
3115         if (channel <= 14)
3116                 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
3117
3118         if (rt2x00_rt(rt2x00dev, RT3593))
3119                 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3120                                MAX_A_TXPOWER_3593);
3121         else
3122                 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3123 }
3124
3125 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3126                                   struct ieee80211_conf *conf,
3127                                   struct rf_channel *rf,
3128                                   struct channel_info *info)
3129 {
3130         u32 reg;
3131         unsigned int tx_pin;
3132         u8 bbp, rfcsr;
3133
3134         info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3135                                                      info->default_power1);
3136         info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3137                                                      info->default_power2);
3138         if (rt2x00dev->default_ant.tx_chain_num > 2)
3139                 info->default_power3 =
3140                         rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3141                                               info->default_power3);
3142
3143         switch (rt2x00dev->chip.rf) {
3144         case RF2020:
3145         case RF3020:
3146         case RF3021:
3147         case RF3022:
3148         case RF3320:
3149                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
3150                 break;
3151         case RF3052:
3152                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
3153                 break;
3154         case RF3053:
3155                 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3156                 break;
3157         case RF3290:
3158                 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3159                 break;
3160         case RF3322:
3161                 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3162                 break;
3163         case RF3070:
3164         case RF5360:
3165         case RF5362:
3166         case RF5370:
3167         case RF5372:
3168         case RF5390:
3169         case RF5392:
3170                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
3171                 break;
3172         case RF5592:
3173                 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3174                 break;
3175         default:
3176                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
3177         }
3178
3179         if (rt2x00_rf(rt2x00dev, RF3070) ||
3180             rt2x00_rf(rt2x00dev, RF3290) ||
3181             rt2x00_rf(rt2x00dev, RF3322) ||
3182             rt2x00_rf(rt2x00dev, RF5360) ||
3183             rt2x00_rf(rt2x00dev, RF5362) ||
3184             rt2x00_rf(rt2x00dev, RF5370) ||
3185             rt2x00_rf(rt2x00dev, RF5372) ||
3186             rt2x00_rf(rt2x00dev, RF5390) ||
3187             rt2x00_rf(rt2x00dev, RF5392)) {
3188                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3189                 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
3190                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
3191                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3192
3193                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3194                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3195                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3196         }
3197
3198         /*
3199          * Change BBP settings
3200          */
3201         if (rt2x00_rt(rt2x00dev, RT3352)) {
3202                 rt2800_bbp_write(rt2x00dev, 27, 0x0);
3203                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3204                 rt2800_bbp_write(rt2x00dev, 27, 0x20);
3205                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3206         } else if (rt2x00_rt(rt2x00dev, RT3593)) {
3207                 if (rf->channel > 14) {
3208                         /* Disable CCK Packet detection on 5GHz */
3209                         rt2800_bbp_write(rt2x00dev, 70, 0x00);
3210                 } else {
3211                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3212                 }
3213
3214                 if (conf_is_ht40(conf))
3215                         rt2800_bbp_write(rt2x00dev, 105, 0x04);
3216                 else
3217                         rt2800_bbp_write(rt2x00dev, 105, 0x34);
3218
3219                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3220                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3221                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3222                 rt2800_bbp_write(rt2x00dev, 77, 0x98);
3223         } else {
3224                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3225                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3226                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3227                 rt2800_bbp_write(rt2x00dev, 86, 0);
3228         }
3229
3230         if (rf->channel <= 14) {
3231                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
3232                     !rt2x00_rt(rt2x00dev, RT5392)) {
3233                         if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
3234                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3235                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3236                         } else {
3237                                 if (rt2x00_rt(rt2x00dev, RT3593))
3238                                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
3239                                 else
3240                                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
3241                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3242                         }
3243                         if (rt2x00_rt(rt2x00dev, RT3593))
3244                                 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
3245                 }
3246
3247         } else {
3248                 if (rt2x00_rt(rt2x00dev, RT3572))
3249                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
3250                 else if (rt2x00_rt(rt2x00dev, RT3593))
3251                         rt2800_bbp_write(rt2x00dev, 82, 0x82);
3252                 else
3253                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
3254
3255                 if (rt2x00_rt(rt2x00dev, RT3593))
3256                         rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3257
3258                 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
3259                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
3260                 else
3261                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
3262         }
3263
3264         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
3265         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
3266         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
3267         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
3268         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3269
3270         if (rt2x00_rt(rt2x00dev, RT3572))
3271                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
3272
3273         tx_pin = 0;
3274
3275         switch (rt2x00dev->default_ant.tx_chain_num) {
3276         case 3:
3277                 /* Turn on tertiary PAs */
3278                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3279                                    rf->channel > 14);
3280                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3281                                    rf->channel <= 14);
3282                 /* fall-through */
3283         case 2:
3284                 /* Turn on secondary PAs */
3285                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3286                                    rf->channel > 14);
3287                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3288                                    rf->channel <= 14);
3289                 /* fall-through */
3290         case 1:
3291                 /* Turn on primary PAs */
3292                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3293                                    rf->channel > 14);
3294                 if (rt2x00_has_cap_bt_coexist(rt2x00dev))
3295                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3296                 else
3297                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3298                                            rf->channel <= 14);
3299                 break;
3300         }
3301
3302         switch (rt2x00dev->default_ant.rx_chain_num) {
3303         case 3:
3304                 /* Turn on tertiary LNAs */
3305                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
3306                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
3307                 /* fall-through */
3308         case 2:
3309                 /* Turn on secondary LNAs */
3310                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
3311                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
3312                 /* fall-through */
3313         case 1:
3314                 /* Turn on primary LNAs */
3315                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
3316                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
3317                 break;
3318         }
3319
3320         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3321         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
3322
3323         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3324
3325         if (rt2x00_rt(rt2x00dev, RT3572)) {
3326                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3327
3328                 /* AGC init */
3329                 if (rf->channel <= 14)
3330                         reg = 0x1c + (2 * rt2x00dev->lna_gain);
3331                 else
3332                         reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3333
3334                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3335         }
3336
3337         if (rt2x00_rt(rt2x00dev, RT3593)) {
3338                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
3339
3340                 /* Band selection */
3341                 if (rt2x00_is_usb(rt2x00dev) ||
3342                     rt2x00_is_pcie(rt2x00dev)) {
3343                         /* GPIO #8 controls all paths */
3344                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
3345                         if (rf->channel <= 14)
3346                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
3347                         else
3348                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
3349                 }
3350
3351                 /* LNA PE control. */
3352                 if (rt2x00_is_usb(rt2x00dev)) {
3353                         /* GPIO #4 controls PE0 and PE1,
3354                          * GPIO #7 controls PE2
3355                          */
3356                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3357                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
3358
3359                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3360                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
3361                 } else if (rt2x00_is_pcie(rt2x00dev)) {
3362                         /* GPIO #4 controls PE0, PE1 and PE2 */
3363                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3364                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3365                 }
3366
3367                 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3368
3369                 /* AGC init */
3370                 if (rf->channel <= 14)
3371                         reg = 0x1c + 2 * rt2x00dev->lna_gain;
3372                 else
3373                         reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3374
3375                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3376
3377                 usleep_range(1000, 1500);
3378         }
3379
3380         if (rt2x00_rt(rt2x00dev, RT5592)) {
3381                 rt2800_bbp_write(rt2x00dev, 195, 141);
3382                 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
3383
3384                 /* AGC init */
3385                 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
3386                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3387
3388                 rt2800_iq_calibrate(rt2x00dev, rf->channel);
3389         }
3390
3391         rt2800_bbp_read(rt2x00dev, 4, &bbp);
3392         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
3393         rt2800_bbp_write(rt2x00dev, 4, bbp);
3394
3395         rt2800_bbp_read(rt2x00dev, 3, &bbp);
3396         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
3397         rt2800_bbp_write(rt2x00dev, 3, bbp);
3398
3399         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3400                 if (conf_is_ht40(conf)) {
3401                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
3402                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3403                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
3404                 } else {
3405                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
3406                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
3407                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
3408                 }
3409         }
3410
3411         msleep(1);
3412
3413         /*
3414          * Clear channel statistic counters
3415          */
3416         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
3417         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
3418         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
3419
3420         /*
3421          * Clear update flag
3422          */
3423         if (rt2x00_rt(rt2x00dev, RT3352)) {
3424                 rt2800_bbp_read(rt2x00dev, 49, &bbp);
3425                 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
3426                 rt2800_bbp_write(rt2x00dev, 49, bbp);
3427         }
3428 }
3429
3430 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
3431 {
3432         u8 tssi_bounds[9];
3433         u8 current_tssi;
3434         u16 eeprom;
3435         u8 step;
3436         int i;
3437
3438         /*
3439          * First check if temperature compensation is supported.
3440          */
3441         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3442         if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
3443                 return 0;
3444
3445         /*
3446          * Read TSSI boundaries for temperature compensation from
3447          * the EEPROM.
3448          *
3449          * Array idx               0    1    2    3    4    5    6    7    8
3450          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
3451          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3452          */
3453         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3454                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
3455                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3456                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
3457                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3458                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
3459
3460                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
3461                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3462                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
3463                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3464                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
3465
3466                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
3467                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3468                                         EEPROM_TSSI_BOUND_BG3_REF);
3469                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3470                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
3471
3472                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
3473                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3474                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
3475                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3476                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
3477
3478                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
3479                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3480                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
3481
3482                 step = rt2x00_get_field16(eeprom,
3483                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3484         } else {
3485                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
3486                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3487                                         EEPROM_TSSI_BOUND_A1_MINUS4);
3488                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3489                                         EEPROM_TSSI_BOUND_A1_MINUS3);
3490
3491                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
3492                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3493                                         EEPROM_TSSI_BOUND_A2_MINUS2);
3494                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3495                                         EEPROM_TSSI_BOUND_A2_MINUS1);
3496
3497                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
3498                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3499                                         EEPROM_TSSI_BOUND_A3_REF);
3500                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3501                                         EEPROM_TSSI_BOUND_A3_PLUS1);
3502
3503                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
3504                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3505                                         EEPROM_TSSI_BOUND_A4_PLUS2);
3506                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3507                                         EEPROM_TSSI_BOUND_A4_PLUS3);
3508
3509                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
3510                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3511                                         EEPROM_TSSI_BOUND_A5_PLUS4);
3512
3513                 step = rt2x00_get_field16(eeprom,
3514                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
3515         }
3516
3517         /*
3518          * Check if temperature compensation is supported.
3519          */
3520         if (tssi_bounds[4] == 0xff || step == 0xff)
3521                 return 0;
3522
3523         /*
3524          * Read current TSSI (BBP 49).
3525          */
3526         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
3527
3528         /*
3529          * Compare TSSI value (BBP49) with the compensation boundaries
3530          * from the EEPROM and increase or decrease tx power.
3531          */
3532         for (i = 0; i <= 3; i++) {
3533                 if (current_tssi > tssi_bounds[i])
3534                         break;
3535         }
3536
3537         if (i == 4) {
3538                 for (i = 8; i >= 5; i--) {
3539                         if (current_tssi < tssi_bounds[i])
3540                                 break;
3541                 }
3542         }
3543
3544         return (i - 4) * step;
3545 }
3546
3547 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
3548                                       enum ieee80211_band band)
3549 {
3550         u16 eeprom;
3551         u8 comp_en;
3552         u8 comp_type;
3553         int comp_value = 0;
3554
3555         rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
3556
3557         /*
3558          * HT40 compensation not required.
3559          */
3560         if (eeprom == 0xffff ||
3561             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3562                 return 0;
3563
3564         if (band == IEEE80211_BAND_2GHZ) {
3565                 comp_en = rt2x00_get_field16(eeprom,
3566                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
3567                 if (comp_en) {
3568                         comp_type = rt2x00_get_field16(eeprom,
3569                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
3570                         comp_value = rt2x00_get_field16(eeprom,
3571                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
3572                         if (!comp_type)
3573                                 comp_value = -comp_value;
3574                 }
3575         } else {
3576                 comp_en = rt2x00_get_field16(eeprom,
3577                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
3578                 if (comp_en) {
3579                         comp_type = rt2x00_get_field16(eeprom,
3580                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
3581                         comp_value = rt2x00_get_field16(eeprom,
3582                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
3583                         if (!comp_type)
3584                                 comp_value = -comp_value;
3585                 }
3586         }
3587
3588         return comp_value;
3589 }
3590
3591 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
3592                                         int power_level, int max_power)
3593 {
3594         int delta;
3595
3596         if (rt2x00_has_cap_power_limit(rt2x00dev))
3597                 return 0;
3598
3599         /*
3600          * XXX: We don't know the maximum transmit power of our hardware since
3601          * the EEPROM doesn't expose it. We only know that we are calibrated
3602          * to 100% tx power.
3603          *
3604          * Hence, we assume the regulatory limit that cfg80211 calulated for
3605          * the current channel is our maximum and if we are requested to lower
3606          * the value we just reduce our tx power accordingly.
3607          */
3608         delta = power_level - max_power;
3609         return min(delta, 0);
3610 }
3611
3612 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
3613                                    enum ieee80211_band band, int power_level,
3614                                    u8 txpower, int delta)
3615 {
3616         u16 eeprom;
3617         u8 criterion;
3618         u8 eirp_txpower;
3619         u8 eirp_txpower_criterion;
3620         u8 reg_limit;
3621
3622         if (rt2x00_rt(rt2x00dev, RT3593))
3623                 return min_t(u8, txpower, 0xc);
3624
3625         if (rt2x00_has_cap_power_limit(rt2x00dev)) {
3626                 /*
3627                  * Check if eirp txpower exceed txpower_limit.
3628                  * We use OFDM 6M as criterion and its eirp txpower
3629                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
3630                  * .11b data rate need add additional 4dbm
3631                  * when calculating eirp txpower.
3632                  */
3633                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3634                                               1, &eeprom);
3635                 criterion = rt2x00_get_field16(eeprom,
3636                                                EEPROM_TXPOWER_BYRATE_RATE0);
3637
3638                 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
3639                                    &eeprom);
3640
3641                 if (band == IEEE80211_BAND_2GHZ)
3642                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3643                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
3644                 else
3645                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3646                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
3647
3648                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
3649                                (is_rate_b ? 4 : 0) + delta;
3650
3651                 reg_limit = (eirp_txpower > power_level) ?
3652                                         (eirp_txpower - power_level) : 0;
3653         } else
3654                 reg_limit = 0;
3655
3656         txpower = max(0, txpower + delta - reg_limit);
3657         return min_t(u8, txpower, 0xc);
3658 }
3659
3660
3661 enum {
3662         TX_PWR_CFG_0_IDX,
3663         TX_PWR_CFG_1_IDX,
3664         TX_PWR_CFG_2_IDX,
3665         TX_PWR_CFG_3_IDX,
3666         TX_PWR_CFG_4_IDX,
3667         TX_PWR_CFG_5_IDX,
3668         TX_PWR_CFG_6_IDX,
3669         TX_PWR_CFG_7_IDX,
3670         TX_PWR_CFG_8_IDX,
3671         TX_PWR_CFG_9_IDX,
3672         TX_PWR_CFG_0_EXT_IDX,
3673         TX_PWR_CFG_1_EXT_IDX,
3674         TX_PWR_CFG_2_EXT_IDX,
3675         TX_PWR_CFG_3_EXT_IDX,
3676         TX_PWR_CFG_4_EXT_IDX,
3677         TX_PWR_CFG_IDX_COUNT,
3678 };
3679
3680 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
3681                                          struct ieee80211_channel *chan,
3682                                          int power_level)
3683 {
3684         u8 txpower;
3685         u16 eeprom;
3686         u32 regs[TX_PWR_CFG_IDX_COUNT];
3687         unsigned int offset;
3688         enum ieee80211_band band = chan->band;
3689         int delta;
3690         int i;
3691
3692         memset(regs, '\0', sizeof(regs));
3693
3694         /* TODO: adapt TX power reduction from the rt28xx code */
3695
3696         /* calculate temperature compensation delta */
3697         delta = rt2800_get_gain_calibration_delta(rt2x00dev);
3698
3699         if (band == IEEE80211_BAND_5GHZ)
3700                 offset = 16;
3701         else
3702                 offset = 0;
3703
3704         if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3705                 offset += 8;
3706
3707         /* read the next four txpower values */
3708         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3709                                       offset, &eeprom);
3710
3711         /* CCK 1MBS,2MBS */
3712         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3713         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3714                                             txpower, delta);
3715         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3716                            TX_PWR_CFG_0_CCK1_CH0, txpower);
3717         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3718                            TX_PWR_CFG_0_CCK1_CH1, txpower);
3719         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3720                            TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
3721
3722         /* CCK 5.5MBS,11MBS */
3723         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3724         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3725                                             txpower, delta);
3726         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3727                            TX_PWR_CFG_0_CCK5_CH0, txpower);
3728         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3729                            TX_PWR_CFG_0_CCK5_CH1, txpower);
3730         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3731                            TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
3732
3733         /* OFDM 6MBS,9MBS */
3734         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3735         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3736                                             txpower, delta);
3737         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3738                            TX_PWR_CFG_0_OFDM6_CH0, txpower);
3739         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3740                            TX_PWR_CFG_0_OFDM6_CH1, txpower);
3741         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3742                            TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
3743
3744         /* OFDM 12MBS,18MBS */
3745         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3746         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3747                                             txpower, delta);
3748         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3749                            TX_PWR_CFG_0_OFDM12_CH0, txpower);
3750         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3751                            TX_PWR_CFG_0_OFDM12_CH1, txpower);
3752         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3753                            TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
3754
3755         /* read the next four txpower values */
3756         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3757                                       offset + 1, &eeprom);
3758
3759         /* OFDM 24MBS,36MBS */
3760         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3761         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3762                                             txpower, delta);
3763         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3764                            TX_PWR_CFG_1_OFDM24_CH0, txpower);
3765         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3766                            TX_PWR_CFG_1_OFDM24_CH1, txpower);
3767         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3768                            TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
3769
3770         /* OFDM 48MBS */
3771         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3772         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3773                                             txpower, delta);
3774         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3775                            TX_PWR_CFG_1_OFDM48_CH0, txpower);
3776         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3777                            TX_PWR_CFG_1_OFDM48_CH1, txpower);
3778         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3779                            TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
3780
3781         /* OFDM 54MBS */
3782         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3783         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3784                                             txpower, delta);
3785         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3786                            TX_PWR_CFG_7_OFDM54_CH0, txpower);
3787         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3788                            TX_PWR_CFG_7_OFDM54_CH1, txpower);
3789         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3790                            TX_PWR_CFG_7_OFDM54_CH2, txpower);
3791
3792         /* read the next four txpower values */
3793         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3794                                       offset + 2, &eeprom);
3795
3796         /* MCS 0,1 */
3797         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3798         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3799                                             txpower, delta);
3800         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3801                            TX_PWR_CFG_1_MCS0_CH0, txpower);
3802         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3803                            TX_PWR_CFG_1_MCS0_CH1, txpower);
3804         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3805                            TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
3806
3807         /* MCS 2,3 */
3808         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3809         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3810                                             txpower, delta);
3811         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3812                            TX_PWR_CFG_1_MCS2_CH0, txpower);
3813         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3814                            TX_PWR_CFG_1_MCS2_CH1, txpower);
3815         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3816                            TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
3817
3818         /* MCS 4,5 */
3819         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3820         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3821                                             txpower, delta);
3822         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3823                            TX_PWR_CFG_2_MCS4_CH0, txpower);
3824         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3825                            TX_PWR_CFG_2_MCS4_CH1, txpower);
3826         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3827                            TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
3828
3829         /* MCS 6 */
3830         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3831         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3832                                             txpower, delta);
3833         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3834                            TX_PWR_CFG_2_MCS6_CH0, txpower);
3835         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3836                            TX_PWR_CFG_2_MCS6_CH1, txpower);
3837         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3838                            TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
3839
3840         /* read the next four txpower values */
3841         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3842                                       offset + 3, &eeprom);
3843
3844         /* MCS 7 */
3845         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3846         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3847                                             txpower, delta);
3848         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3849                            TX_PWR_CFG_7_MCS7_CH0, txpower);
3850         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3851                            TX_PWR_CFG_7_MCS7_CH1, txpower);
3852         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3853                            TX_PWR_CFG_7_MCS7_CH2, txpower);
3854
3855         /* MCS 8,9 */
3856         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3857         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3858                                             txpower, delta);
3859         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3860                            TX_PWR_CFG_2_MCS8_CH0, txpower);
3861         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3862                            TX_PWR_CFG_2_MCS8_CH1, txpower);
3863         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3864                            TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
3865
3866         /* MCS 10,11 */
3867         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3868         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3869                                             txpower, delta);
3870         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3871                            TX_PWR_CFG_2_MCS10_CH0, txpower);
3872         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3873                            TX_PWR_CFG_2_MCS10_CH1, txpower);
3874         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3875                            TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
3876
3877         /* MCS 12,13 */
3878         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3879         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3880                                             txpower, delta);
3881         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3882                            TX_PWR_CFG_3_MCS12_CH0, txpower);
3883         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3884                            TX_PWR_CFG_3_MCS12_CH1, txpower);
3885         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3886                            TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
3887
3888         /* read the next four txpower values */
3889         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3890                                       offset + 4, &eeprom);
3891
3892         /* MCS 14 */
3893         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3894         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3895                                             txpower, delta);
3896         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3897                            TX_PWR_CFG_3_MCS14_CH0, txpower);
3898         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3899                            TX_PWR_CFG_3_MCS14_CH1, txpower);
3900         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3901                            TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
3902
3903         /* MCS 15 */
3904         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3905         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3906                                             txpower, delta);
3907         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3908                            TX_PWR_CFG_8_MCS15_CH0, txpower);
3909         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3910                            TX_PWR_CFG_8_MCS15_CH1, txpower);
3911         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3912                            TX_PWR_CFG_8_MCS15_CH2, txpower);
3913
3914         /* MCS 16,17 */
3915         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3916         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3917                                             txpower, delta);
3918         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3919                            TX_PWR_CFG_5_MCS16_CH0, txpower);
3920         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3921                            TX_PWR_CFG_5_MCS16_CH1, txpower);
3922         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3923                            TX_PWR_CFG_5_MCS16_CH2, txpower);
3924
3925         /* MCS 18,19 */
3926         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3927         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3928                                             txpower, delta);
3929         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3930                            TX_PWR_CFG_5_MCS18_CH0, txpower);
3931         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3932                            TX_PWR_CFG_5_MCS18_CH1, txpower);
3933         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3934                            TX_PWR_CFG_5_MCS18_CH2, txpower);
3935
3936         /* read the next four txpower values */
3937         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3938                                       offset + 5, &eeprom);
3939
3940         /* MCS 20,21 */
3941         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3942         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3943                                             txpower, delta);
3944         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3945                            TX_PWR_CFG_6_MCS20_CH0, txpower);
3946         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3947                            TX_PWR_CFG_6_MCS20_CH1, txpower);
3948         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3949                            TX_PWR_CFG_6_MCS20_CH2, txpower);
3950
3951         /* MCS 22 */
3952         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3953         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3954                                             txpower, delta);
3955         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3956                            TX_PWR_CFG_6_MCS22_CH0, txpower);
3957         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3958                            TX_PWR_CFG_6_MCS22_CH1, txpower);
3959         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3960                            TX_PWR_CFG_6_MCS22_CH2, txpower);
3961
3962         /* MCS 23 */
3963         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3964         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3965                                             txpower, delta);
3966         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3967                            TX_PWR_CFG_8_MCS23_CH0, txpower);
3968         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3969                            TX_PWR_CFG_8_MCS23_CH1, txpower);
3970         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3971                            TX_PWR_CFG_8_MCS23_CH2, txpower);
3972
3973         /* read the next four txpower values */
3974         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3975                                       offset + 6, &eeprom);
3976
3977         /* STBC, MCS 0,1 */
3978         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3979         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3980                                             txpower, delta);
3981         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3982                            TX_PWR_CFG_3_STBC0_CH0, txpower);
3983         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3984                            TX_PWR_CFG_3_STBC0_CH1, txpower);
3985         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3986                            TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
3987
3988         /* STBC, MCS 2,3 */
3989         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3990         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3991                                             txpower, delta);
3992         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3993                            TX_PWR_CFG_3_STBC2_CH0, txpower);
3994         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3995                            TX_PWR_CFG_3_STBC2_CH1, txpower);
3996         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3997                            TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
3998
3999         /* STBC, MCS 4,5 */
4000         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4001         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4002                                             txpower, delta);
4003         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
4004         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
4005         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
4006                            txpower);
4007
4008         /* STBC, MCS 6 */
4009         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4010         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4011                                             txpower, delta);
4012         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
4013         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
4014         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
4015                            txpower);
4016
4017         /* read the next four txpower values */
4018         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4019                                       offset + 7, &eeprom);
4020
4021         /* STBC, MCS 7 */
4022         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4023         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4024                                             txpower, delta);
4025         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4026                            TX_PWR_CFG_9_STBC7_CH0, txpower);
4027         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4028                            TX_PWR_CFG_9_STBC7_CH1, txpower);
4029         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4030                            TX_PWR_CFG_9_STBC7_CH2, txpower);
4031
4032         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
4033         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
4034         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
4035         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
4036         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
4037         rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
4038         rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
4039         rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
4040         rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
4041         rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
4042
4043         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
4044                               regs[TX_PWR_CFG_0_EXT_IDX]);
4045         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
4046                               regs[TX_PWR_CFG_1_EXT_IDX]);
4047         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
4048                               regs[TX_PWR_CFG_2_EXT_IDX]);
4049         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
4050                               regs[TX_PWR_CFG_3_EXT_IDX]);
4051         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
4052                               regs[TX_PWR_CFG_4_EXT_IDX]);
4053
4054         for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
4055                 rt2x00_dbg(rt2x00dev,
4056                            "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
4057                            (band == IEEE80211_BAND_5GHZ) ? '5' : '2',
4058                            (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
4059                                                                 '4' : '2',
4060                            (i > TX_PWR_CFG_9_IDX) ?
4061                                         (i - TX_PWR_CFG_9_IDX - 1) : i,
4062                            (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
4063                            (unsigned long) regs[i]);
4064 }
4065
4066 /*
4067  * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4068  * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4069  * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4070  * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4071  * Reference per rate transmit power values are located in the EEPROM at
4072  * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4073  * current conditions (i.e. band, bandwidth, temperature, user settings).
4074  */
4075 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4076                                          struct ieee80211_channel *chan,
4077                                          int power_level)
4078 {
4079         u8 txpower, r1;
4080         u16 eeprom;
4081         u32 reg, offset;
4082         int i, is_rate_b, delta, power_ctrl;
4083         enum ieee80211_band band = chan->band;
4084
4085         /*
4086          * Calculate HT40 compensation. For 40MHz we need to add or subtract
4087          * value read from EEPROM (different for 2GHz and for 5GHz).
4088          */
4089         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
4090
4091         /*
4092          * Calculate temperature compensation. Depends on measurement of current
4093          * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4094          * to temperature or maybe other factors) is smaller or bigger than
4095          * expected. We adjust it, based on TSSI reference and boundaries values
4096          * provided in EEPROM.
4097          */
4098         switch (rt2x00dev->chip.rt) {
4099         case RT2860:
4100         case RT2872:
4101         case RT2883:
4102         case RT3070:
4103         case RT3071:
4104         case RT3090:
4105         case RT3572:
4106                 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
4107                 break;
4108         default:
4109                 /* TODO: temperature compensation code for other chips. */
4110                 break;
4111         }
4112
4113         /*
4114          * Decrease power according to user settings, on devices with unknown
4115          * maximum tx power. For other devices we take user power_level into
4116          * consideration on rt2800_compensate_txpower().
4117          */
4118         delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4119                                               chan->max_power);
4120
4121         /*
4122          * BBP_R1 controls TX power for all rates, it allow to set the following
4123          * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4124          *
4125          * TODO: we do not use +6 dBm option to do not increase power beyond
4126          * regulatory limit, however this could be utilized for devices with
4127          * CAPABILITY_POWER_LIMIT.
4128          */
4129         if (delta <= -12) {
4130                 power_ctrl = 2;
4131                 delta += 12;
4132         } else if (delta <= -6) {
4133                 power_ctrl = 1;
4134                 delta += 6;
4135         } else {
4136                 power_ctrl = 0;
4137         }
4138         rt2800_bbp_read(rt2x00dev, 1, &r1);
4139         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4140         rt2800_bbp_write(rt2x00dev, 1, r1);
4141
4142         offset = TX_PWR_CFG_0;
4143
4144         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4145                 /* just to be safe */
4146                 if (offset > TX_PWR_CFG_4)
4147                         break;
4148
4149                 rt2800_register_read(rt2x00dev, offset, &reg);
4150
4151                 /* read the next four txpower values */
4152                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4153                                               i, &eeprom);
4154
4155                 is_rate_b = i ? 0 : 1;
4156                 /*
4157                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
4158                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
4159                  * TX_PWR_CFG_4: unknown
4160                  */
4161                 txpower = rt2x00_get_field16(eeprom,
4162                                              EEPROM_TXPOWER_BYRATE_RATE0);
4163                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4164                                              power_level, txpower, delta);
4165                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
4166
4167                 /*
4168                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
4169                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
4170                  * TX_PWR_CFG_4: unknown
4171                  */
4172                 txpower = rt2x00_get_field16(eeprom,
4173                                              EEPROM_TXPOWER_BYRATE_RATE1);
4174                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4175                                              power_level, txpower, delta);
4176                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
4177
4178                 /*
4179                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
4180                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
4181                  * TX_PWR_CFG_4: unknown
4182                  */
4183                 txpower = rt2x00_get_field16(eeprom,
4184                                              EEPROM_TXPOWER_BYRATE_RATE2);
4185                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4186                                              power_level, txpower, delta);
4187                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
4188
4189                 /*
4190                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
4191                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
4192                  * TX_PWR_CFG_4: unknown
4193                  */
4194                 txpower = rt2x00_get_field16(eeprom,
4195                                              EEPROM_TXPOWER_BYRATE_RATE3);
4196                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4197                                              power_level, txpower, delta);
4198                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
4199
4200                 /* read the next four txpower values */
4201                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4202                                               i + 1, &eeprom);
4203
4204                 is_rate_b = 0;
4205                 /*
4206                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
4207                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
4208                  * TX_PWR_CFG_4: unknown
4209                  */
4210                 txpower = rt2x00_get_field16(eeprom,
4211                                              EEPROM_TXPOWER_BYRATE_RATE0);
4212                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4213                                              power_level, txpower, delta);
4214                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
4215
4216                 /*
4217                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
4218                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
4219                  * TX_PWR_CFG_4: unknown
4220                  */
4221                 txpower = rt2x00_get_field16(eeprom,
4222                                              EEPROM_TXPOWER_BYRATE_RATE1);
4223                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4224                                              power_level, txpower, delta);
4225                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
4226
4227                 /*
4228                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
4229                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
4230                  * TX_PWR_CFG_4: unknown
4231                  */
4232                 txpower = rt2x00_get_field16(eeprom,
4233                                              EEPROM_TXPOWER_BYRATE_RATE2);
4234                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4235                                              power_level, txpower, delta);
4236                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
4237
4238                 /*
4239                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
4240                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
4241                  * TX_PWR_CFG_4: unknown
4242                  */
4243                 txpower = rt2x00_get_field16(eeprom,
4244                                              EEPROM_TXPOWER_BYRATE_RATE3);
4245                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4246                                              power_level, txpower, delta);
4247                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
4248
4249                 rt2800_register_write(rt2x00dev, offset, reg);
4250
4251                 /* next TX_PWR_CFG register */
4252                 offset += 4;
4253         }
4254 }
4255
4256 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4257                                   struct ieee80211_channel *chan,
4258                                   int power_level)
4259 {
4260         if (rt2x00_rt(rt2x00dev, RT3593))
4261                 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
4262         else
4263                 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
4264 }
4265
4266 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
4267 {
4268         rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
4269                               rt2x00dev->tx_power);
4270 }
4271 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
4272
4273 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
4274 {
4275         u32     tx_pin;
4276         u8      rfcsr;
4277
4278         /*
4279          * A voltage-controlled oscillator(VCO) is an electronic oscillator
4280          * designed to be controlled in oscillation frequency by a voltage
4281          * input. Maybe the temperature will affect the frequency of
4282          * oscillation to be shifted. The VCO calibration will be called
4283          * periodically to adjust the frequency to be precision.
4284         */
4285
4286         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4287         tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
4288         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4289
4290         switch (rt2x00dev->chip.rf) {
4291         case RF2020:
4292         case RF3020:
4293         case RF3021:
4294         case RF3022:
4295         case RF3320:
4296         case RF3052:
4297                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
4298                 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
4299                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
4300                 break;
4301         case RF3053:
4302         case RF3070:
4303         case RF3290:
4304         case RF5360:
4305         case RF5362:
4306         case RF5370:
4307         case RF5372:
4308         case RF5390:
4309         case RF5392:
4310                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
4311                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
4312                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4313                 break;
4314         default:
4315                 return;
4316         }
4317
4318         mdelay(1);
4319
4320         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4321         if (rt2x00dev->rf_channel <= 14) {
4322                 switch (rt2x00dev->default_ant.tx_chain_num) {
4323                 case 3:
4324                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
4325                         /* fall through */
4326                 case 2:
4327                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
4328                         /* fall through */
4329                 case 1:
4330                 default:
4331                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4332                         break;
4333                 }
4334         } else {
4335                 switch (rt2x00dev->default_ant.tx_chain_num) {
4336                 case 3:
4337                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
4338                         /* fall through */
4339                 case 2:
4340                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
4341                         /* fall through */
4342                 case 1:
4343                 default:
4344                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
4345                         break;
4346                 }
4347         }
4348         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4349
4350 }
4351 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
4352
4353 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
4354                                       struct rt2x00lib_conf *libconf)
4355 {
4356         u32 reg;
4357
4358         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4359         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
4360                            libconf->conf->short_frame_max_tx_count);
4361         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
4362                            libconf->conf->long_frame_max_tx_count);
4363         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4364 }
4365
4366 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
4367                              struct rt2x00lib_conf *libconf)
4368 {
4369         enum dev_state state =
4370             (libconf->conf->flags & IEEE80211_CONF_PS) ?
4371                 STATE_SLEEP : STATE_AWAKE;
4372         u32 reg;
4373
4374         if (state == STATE_SLEEP) {
4375                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
4376
4377                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4378                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
4379                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
4380                                    libconf->conf->listen_interval - 1);
4381                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
4382                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4383
4384                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4385         } else {
4386                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4387                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
4388                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
4389                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
4390                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4391
4392                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4393         }
4394 }
4395
4396 void rt2800_config(struct rt2x00_dev *rt2x00dev,
4397                    struct rt2x00lib_conf *libconf,
4398                    const unsigned int flags)
4399 {
4400         /* Always recalculate LNA gain before changing configuration */
4401         rt2800_config_lna_gain(rt2x00dev, libconf);
4402
4403         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
4404                 rt2800_config_channel(rt2x00dev, libconf->conf,
4405                                       &libconf->rf, &libconf->channel);
4406                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
4407                                       libconf->conf->power_level);
4408         }
4409         if (flags & IEEE80211_CONF_CHANGE_POWER)
4410                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
4411                                       libconf->conf->power_level);
4412         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
4413                 rt2800_config_retry_limit(rt2x00dev, libconf);
4414         if (flags & IEEE80211_CONF_CHANGE_PS)
4415                 rt2800_config_ps(rt2x00dev, libconf);
4416 }
4417 EXPORT_SYMBOL_GPL(rt2800_config);
4418
4419 /*
4420  * Link tuning
4421  */
4422 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4423 {
4424         u32 reg;
4425
4426         /*
4427          * Update FCS error count from register.
4428          */
4429         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4430         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
4431 }
4432 EXPORT_SYMBOL_GPL(rt2800_link_stats);
4433
4434 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
4435 {
4436         u8 vgc;
4437
4438         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
4439                 if (rt2x00_rt(rt2x00dev, RT3070) ||
4440                     rt2x00_rt(rt2x00dev, RT3071) ||
4441                     rt2x00_rt(rt2x00dev, RT3090) ||
4442                     rt2x00_rt(rt2x00dev, RT3290) ||
4443                     rt2x00_rt(rt2x00dev, RT3390) ||
4444                     rt2x00_rt(rt2x00dev, RT3572) ||
4445                     rt2x00_rt(rt2x00dev, RT3593) ||
4446                     rt2x00_rt(rt2x00dev, RT5390) ||
4447                     rt2x00_rt(rt2x00dev, RT5392) ||
4448                     rt2x00_rt(rt2x00dev, RT5592))
4449                         vgc = 0x1c + (2 * rt2x00dev->lna_gain);
4450                 else
4451                         vgc = 0x2e + rt2x00dev->lna_gain;
4452         } else { /* 5GHZ band */
4453                 if (rt2x00_rt(rt2x00dev, RT3593))
4454                         vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
4455                 else if (rt2x00_rt(rt2x00dev, RT5592))
4456                         vgc = 0x24 + (2 * rt2x00dev->lna_gain);
4457                 else {
4458                         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4459                                 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
4460                         else
4461                                 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
4462                 }
4463         }
4464
4465         return vgc;
4466 }
4467
4468 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
4469                                   struct link_qual *qual, u8 vgc_level)
4470 {
4471         if (qual->vgc_level != vgc_level) {
4472                 if (rt2x00_rt(rt2x00dev, RT3572) ||
4473                     rt2x00_rt(rt2x00dev, RT3593)) {
4474                         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
4475                                                        vgc_level);
4476                 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
4477                         rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
4478                         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
4479                 } else {
4480                         rt2800_bbp_write(rt2x00dev, 66, vgc_level);
4481                 }
4482
4483                 qual->vgc_level = vgc_level;
4484                 qual->vgc_level_reg = vgc_level;
4485         }
4486 }
4487
4488 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4489 {
4490         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
4491 }
4492 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
4493
4494 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
4495                        const u32 count)
4496 {
4497         u8 vgc;
4498
4499         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
4500                 return;
4501
4502         /* When RSSI is better than a certain threshold, increase VGC
4503          * with a chip specific value in order to improve the balance
4504          * between sensibility and noise isolation.
4505          */
4506
4507         vgc = rt2800_get_default_vgc(rt2x00dev);
4508
4509         switch (rt2x00dev->chip.rt) {
4510         case RT3572:
4511         case RT3593:
4512                 if (qual->rssi > -65) {
4513                         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
4514                                 vgc += 0x20;
4515                         else
4516                                 vgc += 0x10;
4517                 }
4518                 break;
4519
4520         case RT5592:
4521                 if (qual->rssi > -65)
4522                         vgc += 0x20;
4523                 break;
4524
4525         default:
4526                 if (qual->rssi > -80)
4527                         vgc += 0x10;
4528                 break;
4529         }
4530
4531         rt2800_set_vgc(rt2x00dev, qual, vgc);
4532 }
4533 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
4534
4535 /*
4536  * Initialization functions.
4537  */
4538 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
4539 {
4540         u32 reg;
4541         u16 eeprom;
4542         unsigned int i;
4543         int ret;
4544
4545         rt2800_disable_wpdma(rt2x00dev);
4546
4547         ret = rt2800_drv_init_registers(rt2x00dev);
4548         if (ret)
4549                 return ret;
4550
4551         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
4552         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
4553
4554         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
4555
4556         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
4557         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
4558         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
4559         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
4560         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
4561         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
4562         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
4563         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
4564
4565         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
4566
4567         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
4568         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
4569         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
4570         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
4571
4572         if (rt2x00_rt(rt2x00dev, RT3290)) {
4573                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
4574                 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
4575                         rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
4576                         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
4577                 }
4578
4579                 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
4580                 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
4581                         rt2x00_set_field32(&reg, LDO0_EN, 1);
4582                         rt2x00_set_field32(&reg, LDO_BGSEL, 3);
4583                         rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
4584                 }
4585
4586                 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
4587                 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
4588                 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
4589                 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
4590                 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
4591
4592                 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
4593                 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
4594                 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
4595
4596                 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
4597                 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
4598                 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
4599                 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
4600                 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
4601                 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
4602
4603                 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
4604                 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
4605                 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
4606         }
4607
4608         if (rt2x00_rt(rt2x00dev, RT3071) ||
4609             rt2x00_rt(rt2x00dev, RT3090) ||
4610             rt2x00_rt(rt2x00dev, RT3290) ||
4611             rt2x00_rt(rt2x00dev, RT3390)) {
4612
4613                 if (rt2x00_rt(rt2x00dev, RT3290))
4614                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4615                                               0x00000404);
4616                 else
4617                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4618                                               0x00000400);
4619
4620                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4621                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4622                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4623                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4624                         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4625                                            &eeprom);
4626                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4627                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4628                                                       0x0000002c);
4629                         else
4630                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4631                                                       0x0000000f);
4632                 } else {
4633                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4634                 }
4635         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
4636                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4637
4638                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4639                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4640                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
4641                 } else {
4642                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4643                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4644                 }
4645         } else if (rt2800_is_305x_soc(rt2x00dev)) {
4646                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4647                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4648                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
4649         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4650                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4651                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4652                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4653         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4654                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4655                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4656         } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4657                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4658                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4659                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
4660                         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4661                                            &eeprom);
4662                         if (rt2x00_get_field16(eeprom,
4663                                                EEPROM_NIC_CONF1_DAC_TEST))
4664                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4665                                                       0x0000001f);
4666                         else
4667                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4668                                                       0x0000000f);
4669                 } else {
4670                         rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4671                                               0x00000000);
4672                 }
4673         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
4674                    rt2x00_rt(rt2x00dev, RT5392) ||
4675                    rt2x00_rt(rt2x00dev, RT5592)) {
4676                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
4677                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4678                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4679         } else {
4680                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
4681                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4682         }
4683
4684         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
4685         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
4686         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
4687         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
4688         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
4689         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
4690         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
4691         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
4692         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
4693         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
4694
4695         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
4696         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
4697         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
4698         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
4699         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
4700
4701         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
4702         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
4703         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
4704             rt2x00_rt(rt2x00dev, RT2883) ||
4705             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
4706                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
4707         else
4708                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
4709         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
4710         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
4711         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
4712
4713         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
4714         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
4715         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
4716         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
4717         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
4718         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
4719         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
4720         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
4721         rt2800_register_write(rt2x00dev, LED_CFG, reg);
4722
4723         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
4724
4725         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4726         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
4727         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
4728         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
4729         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
4730         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
4731         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
4732         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4733
4734         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
4735         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
4736         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
4737         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
4738         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
4739         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
4740         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
4741         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
4742         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
4743
4744         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4745         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
4746         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
4747         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
4748         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4749         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4750         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4751         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4752         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4753         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4754         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
4755         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4756
4757         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4758         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
4759         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
4760         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
4761         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4762         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4763         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4764         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4765         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4766         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4767         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
4768         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4769
4770         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4771         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
4772         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
4773         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4774         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4775         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4776         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4777         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4778         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4779         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4780         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
4781         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4782
4783         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4784         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
4785         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
4786         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4787         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4788         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4789         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4790         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4791         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4792         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4793         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
4794         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4795
4796         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4797         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
4798         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
4799         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4800         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4801         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4802         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4803         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4804         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4805         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4806         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
4807         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4808
4809         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4810         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
4811         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
4812         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4813         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4814         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4815         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4816         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4817         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4818         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4819         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
4820         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4821
4822         if (rt2x00_is_usb(rt2x00dev)) {
4823                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
4824
4825                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4826                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
4827                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
4828                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
4829                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
4830                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
4831                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
4832                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
4833                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
4834                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
4835                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4836         }
4837
4838         /*
4839          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
4840          * although it is reserved.
4841          */
4842         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
4843         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
4844         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
4845         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
4846         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
4847         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
4848         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
4849         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
4850         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
4851         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
4852         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
4853         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
4854
4855         reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
4856         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
4857
4858         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4859         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
4860         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
4861                            IEEE80211_MAX_RTS_THRESHOLD);
4862         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
4863         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4864
4865         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
4866
4867         /*
4868          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
4869          * time should be set to 16. However, the original Ralink driver uses
4870          * 16 for both and indeed using a value of 10 for CCK SIFS results in
4871          * connection problems with 11g + CTS protection. Hence, use the same
4872          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
4873          */
4874         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
4875         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
4876         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
4877         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
4878         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
4879         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
4880         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
4881
4882         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
4883
4884         /*
4885          * ASIC will keep garbage value after boot, clear encryption keys.
4886          */
4887         for (i = 0; i < 4; i++)
4888                 rt2800_register_write(rt2x00dev,
4889                                          SHARED_KEY_MODE_ENTRY(i), 0);
4890
4891         for (i = 0; i < 256; i++) {
4892                 rt2800_config_wcid(rt2x00dev, NULL, i);
4893                 rt2800_delete_wcid_attr(rt2x00dev, i);
4894                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
4895         }
4896
4897         /*
4898          * Clear all beacons
4899          */
4900         for (i = 0; i < 8; i++)
4901                 rt2800_clear_beacon_register(rt2x00dev, i);
4902
4903         if (rt2x00_is_usb(rt2x00dev)) {
4904                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4905                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
4906                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4907         } else if (rt2x00_is_pcie(rt2x00dev)) {
4908                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4909                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
4910                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4911         }
4912
4913         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
4914         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
4915         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
4916         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
4917         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
4918         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
4919         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
4920         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
4921         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
4922         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
4923
4924         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
4925         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
4926         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
4927         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
4928         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
4929         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
4930         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
4931         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
4932         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
4933         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
4934
4935         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
4936         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
4937         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
4938         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
4939         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
4940         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
4941         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
4942         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
4943         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
4944         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
4945
4946         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
4947         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
4948         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
4949         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
4950         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
4951         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
4952
4953         /*
4954          * Do not force the BA window size, we use the TXWI to set it
4955          */
4956         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
4957         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
4958         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
4959         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
4960
4961         /*
4962          * We must clear the error counters.
4963          * These registers are cleared on read,
4964          * so we may pass a useless variable to store the value.
4965          */
4966         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4967         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
4968         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
4969         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
4970         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
4971         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
4972
4973         /*
4974          * Setup leadtime for pre tbtt interrupt to 6ms
4975          */
4976         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
4977         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
4978         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
4979
4980         /*
4981          * Set up channel statistics timer
4982          */
4983         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
4984         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
4985         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
4986         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
4987         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
4988         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
4989         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
4990
4991         return 0;
4992 }
4993
4994 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
4995 {
4996         unsigned int i;
4997         u32 reg;
4998
4999         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5000                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
5001                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
5002                         return 0;
5003
5004                 udelay(REGISTER_BUSY_DELAY);
5005         }
5006
5007         rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
5008         return -EACCES;
5009 }
5010
5011 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
5012 {
5013         unsigned int i;
5014         u8 value;
5015
5016         /*
5017          * BBP was enabled after firmware was loaded,
5018          * but we need to reactivate it now.
5019          */
5020         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5021         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5022         msleep(1);
5023
5024         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5025                 rt2800_bbp_read(rt2x00dev, 0, &value);
5026                 if ((value != 0xff) && (value != 0x00))
5027                         return 0;
5028                 udelay(REGISTER_BUSY_DELAY);
5029         }
5030
5031         rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
5032         return -EACCES;
5033 }
5034
5035 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
5036 {
5037         u8 value;
5038
5039         rt2800_bbp_read(rt2x00dev, 4, &value);
5040         rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
5041         rt2800_bbp_write(rt2x00dev, 4, value);
5042 }
5043
5044 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
5045 {
5046         rt2800_bbp_write(rt2x00dev, 142, 1);
5047         rt2800_bbp_write(rt2x00dev, 143, 57);
5048 }
5049
5050 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
5051 {
5052         const u8 glrt_table[] = {
5053                 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
5054                 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
5055                 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
5056                 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
5057                 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
5058                 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
5059                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
5060                 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
5061                 0x2E, 0x36, 0x30, 0x6E,                                     /* 208 ~ 211 */
5062         };
5063         int i;
5064
5065         for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
5066                 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
5067                 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
5068         }
5069 };
5070
5071 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
5072 {
5073         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5074         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5075         rt2800_bbp_write(rt2x00dev, 68, 0x0B);
5076         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5077         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5078         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5079         rt2800_bbp_write(rt2x00dev, 81, 0x37);
5080         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5081         rt2800_bbp_write(rt2x00dev, 83, 0x6A);
5082         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5083         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5084         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5085         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5086         rt2800_bbp_write(rt2x00dev, 103, 0x00);
5087         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5088         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5089 }
5090
5091 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5092 {
5093         u16 eeprom;
5094         u8 value;
5095
5096         rt2800_bbp_read(rt2x00dev, 138, &value);
5097         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5098         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5099                 value |= 0x20;
5100         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5101                 value &= ~0x02;
5102         rt2800_bbp_write(rt2x00dev, 138, value);
5103 }
5104
5105 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5106 {
5107         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5108
5109         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5110         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5111
5112         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5113         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5114
5115         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5116
5117         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5118         rt2800_bbp_write(rt2x00dev, 80, 0x08);
5119
5120         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5121
5122         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5123
5124         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5125
5126         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5127
5128         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5129
5130         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5131
5132         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5133
5134         rt2800_bbp_write(rt2x00dev, 105, 0x01);
5135
5136         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5137 }
5138
5139 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5140 {
5141         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5142         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5143
5144         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5145                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
5146                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
5147         } else {
5148                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5149                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5150         }
5151
5152         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5153
5154         rt2800_bbp_write(rt2x00dev, 81, 0x37);
5155
5156         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5157
5158         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5159
5160         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5161                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5162         else
5163                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5164
5165         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5166
5167         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5168
5169         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5170
5171         rt2800_bbp_write(rt2x00dev, 103, 0x00);
5172
5173         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5174
5175         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5176 }
5177
5178 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5179 {
5180         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5181         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5182
5183         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5184         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5185
5186         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5187
5188         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5189         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5190         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5191
5192         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5193
5194         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5195
5196         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5197
5198         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5199
5200         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5201
5202         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5203
5204         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
5205             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
5206             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
5207                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5208         else
5209                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5210
5211         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5212
5213         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5214
5215         if (rt2x00_rt(rt2x00dev, RT3071) ||
5216             rt2x00_rt(rt2x00dev, RT3090))
5217                 rt2800_disable_unused_dac_adc(rt2x00dev);
5218 }
5219
5220 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
5221 {
5222         u8 value;
5223
5224         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5225
5226         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5227
5228         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5229         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5230
5231         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5232
5233         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5234         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5235         rt2800_bbp_write(rt2x00dev, 75, 0x46);
5236         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5237
5238         rt2800_bbp_write(rt2x00dev, 77, 0x58);
5239
5240         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5241
5242         rt2800_bbp_write(rt2x00dev, 74, 0x0b);
5243         rt2800_bbp_write(rt2x00dev, 79, 0x18);
5244         rt2800_bbp_write(rt2x00dev, 80, 0x09);
5245         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5246
5247         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5248
5249         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5250
5251         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5252
5253         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5254
5255         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5256
5257         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5258
5259         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5260
5261         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5262
5263         rt2800_bbp_write(rt2x00dev, 105, 0x1c);
5264
5265         rt2800_bbp_write(rt2x00dev, 106, 0x03);
5266
5267         rt2800_bbp_write(rt2x00dev, 128, 0x12);
5268
5269         rt2800_bbp_write(rt2x00dev, 67, 0x24);
5270         rt2800_bbp_write(rt2x00dev, 143, 0x04);
5271         rt2800_bbp_write(rt2x00dev, 142, 0x99);
5272         rt2800_bbp_write(rt2x00dev, 150, 0x30);
5273         rt2800_bbp_write(rt2x00dev, 151, 0x2e);
5274         rt2800_bbp_write(rt2x00dev, 152, 0x20);
5275         rt2800_bbp_write(rt2x00dev, 153, 0x34);
5276         rt2800_bbp_write(rt2x00dev, 154, 0x40);
5277         rt2800_bbp_write(rt2x00dev, 155, 0x3b);
5278         rt2800_bbp_write(rt2x00dev, 253, 0x04);
5279
5280         rt2800_bbp_read(rt2x00dev, 47, &value);
5281         rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
5282         rt2800_bbp_write(rt2x00dev, 47, value);
5283
5284         /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5285         rt2800_bbp_read(rt2x00dev, 3, &value);
5286         rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
5287         rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
5288         rt2800_bbp_write(rt2x00dev, 3, value);
5289 }
5290
5291 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
5292 {
5293         rt2800_bbp_write(rt2x00dev, 3, 0x00);
5294         rt2800_bbp_write(rt2x00dev, 4, 0x50);
5295
5296         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5297
5298         rt2800_bbp_write(rt2x00dev, 47, 0x48);
5299
5300         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5301         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5302
5303         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5304
5305         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5306         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5307         rt2800_bbp_write(rt2x00dev, 75, 0x46);
5308         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5309
5310         rt2800_bbp_write(rt2x00dev, 77, 0x59);
5311
5312         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5313
5314         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5315         rt2800_bbp_write(rt2x00dev, 80, 0x08);
5316         rt2800_bbp_write(rt2x00dev, 81, 0x37);
5317
5318         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5319
5320         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5321
5322         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5323
5324         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5325
5326         rt2800_bbp_write(rt2x00dev, 88, 0x90);
5327
5328         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5329
5330         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5331
5332         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5333
5334         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5335
5336         rt2800_bbp_write(rt2x00dev, 105, 0x34);
5337
5338         rt2800_bbp_write(rt2x00dev, 106, 0x05);
5339
5340         rt2800_bbp_write(rt2x00dev, 120, 0x50);
5341
5342         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5343
5344         rt2800_bbp_write(rt2x00dev, 163, 0xbd);
5345         /* Set ITxBF timeout to 0x9c40=1000msec */
5346         rt2800_bbp_write(rt2x00dev, 179, 0x02);
5347         rt2800_bbp_write(rt2x00dev, 180, 0x00);
5348         rt2800_bbp_write(rt2x00dev, 182, 0x40);
5349         rt2800_bbp_write(rt2x00dev, 180, 0x01);
5350         rt2800_bbp_write(rt2x00dev, 182, 0x9c);
5351         rt2800_bbp_write(rt2x00dev, 179, 0x00);
5352         /* Reprogram the inband interface to put right values in RXWI */
5353         rt2800_bbp_write(rt2x00dev, 142, 0x04);
5354         rt2800_bbp_write(rt2x00dev, 143, 0x3b);
5355         rt2800_bbp_write(rt2x00dev, 142, 0x06);
5356         rt2800_bbp_write(rt2x00dev, 143, 0xa0);
5357         rt2800_bbp_write(rt2x00dev, 142, 0x07);
5358         rt2800_bbp_write(rt2x00dev, 143, 0xa1);
5359         rt2800_bbp_write(rt2x00dev, 142, 0x08);
5360         rt2800_bbp_write(rt2x00dev, 143, 0xa2);
5361
5362         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
5363 }
5364
5365 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
5366 {
5367         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5368         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5369
5370         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5371         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5372
5373         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5374
5375         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5376         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5377         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5378
5379         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5380
5381         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5382
5383         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5384
5385         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5386
5387         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5388
5389         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5390
5391         if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
5392                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5393         else
5394                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5395
5396         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5397
5398         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5399
5400         rt2800_disable_unused_dac_adc(rt2x00dev);
5401 }
5402
5403 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
5404 {
5405         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5406
5407         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5408         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5409
5410         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5411         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5412
5413         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5414
5415         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5416         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5417         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5418
5419         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5420
5421         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5422
5423         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5424
5425         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5426
5427         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5428
5429         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5430
5431         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5432
5433         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5434
5435         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5436
5437         rt2800_disable_unused_dac_adc(rt2x00dev);
5438 }
5439
5440 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
5441 {
5442         rt2800_init_bbp_early(rt2x00dev);
5443
5444         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5445         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5446         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5447         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5448
5449         rt2800_bbp_write(rt2x00dev, 84, 0x19);
5450
5451         /* Enable DC filter */
5452         if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
5453                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5454 }
5455
5456 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
5457 {
5458         int ant, div_mode;
5459         u16 eeprom;
5460         u8 value;
5461
5462         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5463
5464         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5465
5466         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5467         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5468
5469         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5470
5471         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5472         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5473         rt2800_bbp_write(rt2x00dev, 75, 0x46);
5474         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5475
5476         rt2800_bbp_write(rt2x00dev, 77, 0x59);
5477
5478         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5479
5480         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5481         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5482         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5483
5484         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5485
5486         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5487
5488         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5489
5490         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5491
5492         if (rt2x00_rt(rt2x00dev, RT5392))
5493                 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5494
5495         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5496
5497         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5498
5499         if (rt2x00_rt(rt2x00dev, RT5392)) {
5500                 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5501                 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5502         }
5503
5504         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5505
5506         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5507
5508         rt2800_bbp_write(rt2x00dev, 105, 0x3c);
5509
5510         if (rt2x00_rt(rt2x00dev, RT5390))
5511                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5512         else if (rt2x00_rt(rt2x00dev, RT5392))
5513                 rt2800_bbp_write(rt2x00dev, 106, 0x12);
5514         else
5515                 WARN_ON(1);
5516
5517         rt2800_bbp_write(rt2x00dev, 128, 0x12);
5518
5519         if (rt2x00_rt(rt2x00dev, RT5392)) {
5520                 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
5521                 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
5522         }
5523
5524         rt2800_disable_unused_dac_adc(rt2x00dev);
5525
5526         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5527         div_mode = rt2x00_get_field16(eeprom,
5528                                       EEPROM_NIC_CONF1_ANT_DIVERSITY);
5529         ant = (div_mode == 3) ? 1 : 0;
5530
5531         /* check if this is a Bluetooth combo card */
5532         if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
5533                 u32 reg;
5534
5535                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5536                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
5537                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
5538                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
5539                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
5540                 if (ant == 0)
5541                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
5542                 else if (ant == 1)
5543                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
5544                 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5545         }
5546
5547         /* This chip has hardware antenna diversity*/
5548         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5549                 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
5550                 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
5551                 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
5552         }
5553
5554         rt2800_bbp_read(rt2x00dev, 152, &value);
5555         if (ant == 0)
5556                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5557         else
5558                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5559         rt2800_bbp_write(rt2x00dev, 152, value);
5560
5561         rt2800_init_freq_calibration(rt2x00dev);
5562 }
5563
5564 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
5565 {
5566         int ant, div_mode;
5567         u16 eeprom;
5568         u8 value;
5569
5570         rt2800_init_bbp_early(rt2x00dev);
5571
5572         rt2800_bbp_read(rt2x00dev, 105, &value);
5573         rt2x00_set_field8(&value, BBP105_MLD,
5574                           rt2x00dev->default_ant.rx_chain_num == 2);
5575         rt2800_bbp_write(rt2x00dev, 105, value);
5576
5577         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5578
5579         rt2800_bbp_write(rt2x00dev, 20, 0x06);
5580         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5581         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5582         rt2800_bbp_write(rt2x00dev, 68, 0xDD);
5583         rt2800_bbp_write(rt2x00dev, 69, 0x1A);
5584         rt2800_bbp_write(rt2x00dev, 70, 0x05);
5585         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5586         rt2800_bbp_write(rt2x00dev, 74, 0x0F);
5587         rt2800_bbp_write(rt2x00dev, 75, 0x4F);
5588         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5589         rt2800_bbp_write(rt2x00dev, 77, 0x59);
5590         rt2800_bbp_write(rt2x00dev, 84, 0x9A);
5591         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5592         rt2800_bbp_write(rt2x00dev, 88, 0x90);
5593         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5594         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5595         rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5596         rt2800_bbp_write(rt2x00dev, 98, 0x12);
5597         rt2800_bbp_write(rt2x00dev, 103, 0xC0);
5598         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5599         /* FIXME BBP105 owerwrite */
5600         rt2800_bbp_write(rt2x00dev, 105, 0x3C);
5601         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5602         rt2800_bbp_write(rt2x00dev, 128, 0x12);
5603         rt2800_bbp_write(rt2x00dev, 134, 0xD0);
5604         rt2800_bbp_write(rt2x00dev, 135, 0xF6);
5605         rt2800_bbp_write(rt2x00dev, 137, 0x0F);
5606
5607         /* Initialize GLRT (Generalized Likehood Radio Test) */
5608         rt2800_init_bbp_5592_glrt(rt2x00dev);
5609
5610         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5611
5612         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5613         div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
5614         ant = (div_mode == 3) ? 1 : 0;
5615         rt2800_bbp_read(rt2x00dev, 152, &value);
5616         if (ant == 0) {
5617                 /* Main antenna */
5618                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5619         } else {
5620                 /* Auxiliary antenna */
5621                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5622         }
5623         rt2800_bbp_write(rt2x00dev, 152, value);
5624
5625         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
5626                 rt2800_bbp_read(rt2x00dev, 254, &value);
5627                 rt2x00_set_field8(&value, BBP254_BIT7, 1);
5628                 rt2800_bbp_write(rt2x00dev, 254, value);
5629         }
5630
5631         rt2800_init_freq_calibration(rt2x00dev);
5632
5633         rt2800_bbp_write(rt2x00dev, 84, 0x19);
5634         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5635                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5636 }
5637
5638 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
5639 {
5640         unsigned int i;
5641         u16 eeprom;
5642         u8 reg_id;
5643         u8 value;
5644
5645         if (rt2800_is_305x_soc(rt2x00dev))
5646                 rt2800_init_bbp_305x_soc(rt2x00dev);
5647
5648         switch (rt2x00dev->chip.rt) {
5649         case RT2860:
5650         case RT2872:
5651         case RT2883:
5652                 rt2800_init_bbp_28xx(rt2x00dev);
5653                 break;
5654         case RT3070:
5655         case RT3071:
5656         case RT3090:
5657                 rt2800_init_bbp_30xx(rt2x00dev);
5658                 break;
5659         case RT3290:
5660                 rt2800_init_bbp_3290(rt2x00dev);
5661                 break;
5662         case RT3352:
5663                 rt2800_init_bbp_3352(rt2x00dev);
5664                 break;
5665         case RT3390:
5666                 rt2800_init_bbp_3390(rt2x00dev);
5667                 break;
5668         case RT3572:
5669                 rt2800_init_bbp_3572(rt2x00dev);
5670                 break;
5671         case RT3593:
5672                 rt2800_init_bbp_3593(rt2x00dev);
5673                 return;
5674         case RT5390:
5675         case RT5392:
5676                 rt2800_init_bbp_53xx(rt2x00dev);
5677                 break;
5678         case RT5592:
5679                 rt2800_init_bbp_5592(rt2x00dev);
5680                 return;
5681         }
5682
5683         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
5684                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
5685                                               &eeprom);
5686
5687                 if (eeprom != 0xffff && eeprom != 0x0000) {
5688                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
5689                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
5690                         rt2800_bbp_write(rt2x00dev, reg_id, value);
5691                 }
5692         }
5693 }
5694
5695 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
5696 {
5697         u32 reg;
5698
5699         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
5700         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
5701         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
5702 }
5703
5704 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
5705                                 u8 filter_target)
5706 {
5707         unsigned int i;
5708         u8 bbp;
5709         u8 rfcsr;
5710         u8 passband;
5711         u8 stopband;
5712         u8 overtuned = 0;
5713         u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
5714
5715         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5716
5717         rt2800_bbp_read(rt2x00dev, 4, &bbp);
5718         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
5719         rt2800_bbp_write(rt2x00dev, 4, bbp);
5720
5721         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
5722         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
5723         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
5724
5725         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5726         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
5727         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5728
5729         /*
5730          * Set power & frequency of passband test tone
5731          */
5732         rt2800_bbp_write(rt2x00dev, 24, 0);
5733
5734         for (i = 0; i < 100; i++) {
5735                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5736                 msleep(1);
5737
5738                 rt2800_bbp_read(rt2x00dev, 55, &passband);
5739                 if (passband)
5740                         break;
5741         }
5742
5743         /*
5744          * Set power & frequency of stopband test tone
5745          */
5746         rt2800_bbp_write(rt2x00dev, 24, 0x06);
5747
5748         for (i = 0; i < 100; i++) {
5749                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5750                 msleep(1);
5751
5752                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
5753
5754                 if ((passband - stopband) <= filter_target) {
5755                         rfcsr24++;
5756                         overtuned += ((passband - stopband) == filter_target);
5757                 } else
5758                         break;
5759
5760                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5761         }
5762
5763         rfcsr24 -= !!overtuned;
5764
5765         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5766         return rfcsr24;
5767 }
5768
5769 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
5770                                        const unsigned int rf_reg)
5771 {
5772         u8 rfcsr;
5773
5774         rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
5775         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
5776         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5777         msleep(1);
5778         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
5779         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5780 }
5781
5782 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
5783 {
5784         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5785         u8 filter_tgt_bw20;
5786         u8 filter_tgt_bw40;
5787         u8 rfcsr, bbp;
5788
5789         /*
5790          * TODO: sync filter_tgt values with vendor driver
5791          */
5792         if (rt2x00_rt(rt2x00dev, RT3070)) {
5793                 filter_tgt_bw20 = 0x16;
5794                 filter_tgt_bw40 = 0x19;
5795         } else {
5796                 filter_tgt_bw20 = 0x13;
5797                 filter_tgt_bw40 = 0x15;
5798         }
5799
5800         drv_data->calibration_bw20 =
5801                 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
5802         drv_data->calibration_bw40 =
5803                 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
5804
5805         /*
5806          * Save BBP 25 & 26 values for later use in channel switching (for 3052)
5807          */
5808         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5809         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5810
5811         /*
5812          * Set back to initial state
5813          */
5814         rt2800_bbp_write(rt2x00dev, 24, 0);
5815
5816         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5817         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
5818         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5819
5820         /*
5821          * Set BBP back to BW20
5822          */
5823         rt2800_bbp_read(rt2x00dev, 4, &bbp);
5824         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
5825         rt2800_bbp_write(rt2x00dev, 4, bbp);
5826 }
5827
5828 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
5829 {
5830         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5831         u8 min_gain, rfcsr, bbp;
5832         u16 eeprom;
5833
5834         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
5835
5836         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
5837         if (rt2x00_rt(rt2x00dev, RT3070) ||
5838             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5839             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5840             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5841                 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
5842                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
5843         }
5844
5845         min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
5846         if (drv_data->txmixer_gain_24g >= min_gain) {
5847                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
5848                                   drv_data->txmixer_gain_24g);
5849         }
5850
5851         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
5852
5853         if (rt2x00_rt(rt2x00dev, RT3090)) {
5854                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
5855                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
5856                 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5857                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5858                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
5859                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5860                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5861                 rt2800_bbp_write(rt2x00dev, 138, bbp);
5862         }
5863
5864         if (rt2x00_rt(rt2x00dev, RT3070)) {
5865                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5866                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5867                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5868                 else
5869                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5870                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5871                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5872                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5873                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5874         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5875                    rt2x00_rt(rt2x00dev, RT3090) ||
5876                    rt2x00_rt(rt2x00dev, RT3390)) {
5877                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5878                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5879                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5880                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5881                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5882                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5883                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5884
5885                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5886                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5887                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5888
5889                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5890                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5891                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5892
5893                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5894                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5895                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5896         }
5897 }
5898
5899 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
5900 {
5901         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5902         u8 rfcsr;
5903         u8 tx_gain;
5904
5905         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
5906         rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
5907         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
5908
5909         rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
5910         tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
5911                                     RFCSR17_TXMIXER_GAIN);
5912         rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
5913         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
5914
5915         rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5916         rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5917         rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5918
5919         rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5920         rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5921         rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5922
5923         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5924         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5925         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
5926         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5927
5928         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5929         rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5930         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5931
5932         /* TODO: enable stream mode */
5933 }
5934
5935 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
5936 {
5937         u8 reg;
5938         u16 eeprom;
5939
5940         /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
5941         rt2800_bbp_read(rt2x00dev, 138, &reg);
5942         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5943         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5944                 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
5945         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5946                 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
5947         rt2800_bbp_write(rt2x00dev, 138, reg);
5948
5949         rt2800_rfcsr_read(rt2x00dev, 38, &reg);
5950         rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
5951         rt2800_rfcsr_write(rt2x00dev, 38, reg);
5952
5953         rt2800_rfcsr_read(rt2x00dev, 39, &reg);
5954         rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
5955         rt2800_rfcsr_write(rt2x00dev, 39, reg);
5956
5957         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5958
5959         rt2800_rfcsr_read(rt2x00dev, 30, &reg);
5960         rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
5961         rt2800_rfcsr_write(rt2x00dev, 30, reg);
5962 }
5963
5964 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
5965 {
5966         rt2800_rf_init_calibration(rt2x00dev, 30);
5967
5968         rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
5969         rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
5970         rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
5971         rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
5972         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5973         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5974         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5975         rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
5976         rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
5977         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5978         rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
5979         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5980         rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
5981         rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
5982         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5983         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5984         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5985         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5986         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5987         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5988         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5989         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5990         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5991         rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
5992         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
5993         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5994         rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
5995         rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
5996         rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
5997         rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
5998         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
5999         rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
6000 }
6001
6002 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
6003 {
6004         u8 rfcsr;
6005         u16 eeprom;
6006         u32 reg;
6007
6008         /* XXX vendor driver do this only for 3070 */
6009         rt2800_rf_init_calibration(rt2x00dev, 30);
6010
6011         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6012         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
6013         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
6014         rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
6015         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
6016         rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
6017         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6018         rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
6019         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6020         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6021         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6022         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6023         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6024         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6025         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6026         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6027         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6028         rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
6029         rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
6030
6031         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
6032                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6033                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6034                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6035                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6036         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
6037                    rt2x00_rt(rt2x00dev, RT3090)) {
6038                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
6039
6040                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6041                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6042                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6043
6044                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6045                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6046                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6047                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
6048                         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
6049                                            &eeprom);
6050                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
6051                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6052                         else
6053                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6054                 }
6055                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6056
6057                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6058                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6059                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6060         }
6061
6062         rt2800_rx_filter_calibration(rt2x00dev);
6063
6064         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
6065             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6066             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
6067                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6068
6069         rt2800_led_open_drain_enable(rt2x00dev);
6070         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6071 }
6072
6073 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
6074 {
6075         u8 rfcsr;
6076
6077         rt2800_rf_init_calibration(rt2x00dev, 2);
6078
6079         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6080         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6081         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6082         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6083         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6084         rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
6085         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6086         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6087         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6088         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6089         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6090         rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
6091         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6092         rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
6093         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6094         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6095         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6096         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6097         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6098         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6099         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6100         rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
6101         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6102         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6103         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6104         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6105         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6106         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6107         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6108         rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
6109         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6110         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6111         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6112         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6113         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6114         rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
6115         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6116         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6117         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6118         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6119         rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
6120         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6121         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6122         rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
6123         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6124         rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
6125
6126         rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
6127         rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
6128         rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
6129
6130         rt2800_led_open_drain_enable(rt2x00dev);
6131         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6132 }
6133
6134 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
6135 {
6136         rt2800_rf_init_calibration(rt2x00dev, 30);
6137
6138         rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
6139         rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
6140         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
6141         rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
6142         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6143         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6144         rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
6145         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6146         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6147         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6148         rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
6149         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
6150         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
6151         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
6152         rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
6153         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6154         rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
6155         rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
6156         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6157         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6158         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6159         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6160         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6161         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6162         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6163         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6164         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6165         rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
6166         rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
6167         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6168         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6169         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6170         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6171         rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
6172         rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
6173         rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
6174         rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
6175         rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
6176         rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
6177         rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
6178         rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
6179         rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
6180         rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
6181         rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
6182         rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
6183         rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
6184         rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
6185         rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
6186         rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
6187         rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
6188         rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
6189         rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
6190         rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
6191         rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
6192         rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
6193         rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
6194         rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
6195         rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
6196         rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
6197         rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
6198         rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
6199         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6200         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
6201
6202         rt2800_rx_filter_calibration(rt2x00dev);
6203         rt2800_led_open_drain_enable(rt2x00dev);
6204         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6205 }
6206
6207 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
6208 {
6209         u32 reg;
6210
6211         rt2800_rf_init_calibration(rt2x00dev, 30);
6212
6213         rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
6214         rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
6215         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6216         rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
6217         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6218         rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
6219         rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
6220         rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
6221         rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
6222         rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
6223         rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
6224         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6225         rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
6226         rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
6227         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6228         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6229         rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
6230         rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
6231         rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
6232         rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
6233         rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
6234         rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
6235         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6236         rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
6237         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6238         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
6239         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6240         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6241         rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
6242         rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
6243         rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
6244         rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
6245
6246         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6247         rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6248         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6249
6250         rt2800_rx_filter_calibration(rt2x00dev);
6251
6252         if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
6253                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6254
6255         rt2800_led_open_drain_enable(rt2x00dev);
6256         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6257 }
6258
6259 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
6260 {
6261         u8 rfcsr;
6262         u32 reg;
6263
6264         rt2800_rf_init_calibration(rt2x00dev, 30);
6265
6266         rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
6267         rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
6268         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6269         rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
6270         rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
6271         rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
6272         rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
6273         rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
6274         rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
6275         rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
6276         rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
6277         rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
6278         rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
6279         rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
6280         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6281         rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
6282         rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
6283         rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
6284         rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
6285         rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
6286         rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
6287         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6288         rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
6289         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6290         rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
6291         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6292         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6293         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6294         rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
6295         rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
6296         rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
6297
6298         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6299         rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6300         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6301
6302         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6303         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6304         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6305         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6306         msleep(1);
6307         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6308         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6309         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6310         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6311
6312         rt2800_rx_filter_calibration(rt2x00dev);
6313         rt2800_led_open_drain_enable(rt2x00dev);
6314         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6315 }
6316
6317 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
6318 {
6319         u8 bbp;
6320         bool txbf_enabled = false; /* FIXME */
6321
6322         rt2800_bbp_read(rt2x00dev, 105, &bbp);
6323         if (rt2x00dev->default_ant.rx_chain_num == 1)
6324                 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
6325         else
6326                 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
6327         rt2800_bbp_write(rt2x00dev, 105, bbp);
6328
6329         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6330
6331         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6332         rt2800_bbp_write(rt2x00dev, 82, 0x82);
6333         rt2800_bbp_write(rt2x00dev, 106, 0x05);
6334         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6335         rt2800_bbp_write(rt2x00dev, 88, 0x90);
6336         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6337         rt2800_bbp_write(rt2x00dev, 47, 0x48);
6338         rt2800_bbp_write(rt2x00dev, 120, 0x50);
6339
6340         if (txbf_enabled)
6341                 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6342         else
6343                 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6344
6345         /* SNR mapping */
6346         rt2800_bbp_write(rt2x00dev, 142, 6);
6347         rt2800_bbp_write(rt2x00dev, 143, 160);
6348         rt2800_bbp_write(rt2x00dev, 142, 7);
6349         rt2800_bbp_write(rt2x00dev, 143, 161);
6350         rt2800_bbp_write(rt2x00dev, 142, 8);
6351         rt2800_bbp_write(rt2x00dev, 143, 162);
6352
6353         /* ADC/DAC control */
6354         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6355
6356         /* RX AGC energy lower bound in log2 */
6357         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6358
6359         /* FIXME: BBP 105 owerwrite? */
6360         rt2800_bbp_write(rt2x00dev, 105, 0x04);
6361
6362 }
6363
6364 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
6365 {
6366         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6367         u32 reg;
6368         u8 rfcsr;
6369
6370         /* Disable GPIO #4 and #7 function for LAN PE control */
6371         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6372         rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
6373         rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
6374         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6375
6376         /* Initialize default register values */
6377         rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
6378         rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
6379         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6380         rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
6381         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6382         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6383         rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
6384         rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
6385         rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
6386         rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
6387         rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
6388         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6389         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6390         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6391         rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
6392         rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
6393         rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
6394         rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
6395         rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
6396         rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
6397         rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
6398         rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
6399         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
6400         rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
6401         rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
6402         rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
6403         rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
6404         rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
6405         rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
6406         rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
6407         rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
6408         rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
6409
6410         /* Initiate calibration */
6411         /* TODO: use rt2800_rf_init_calibration ? */
6412         rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
6413         rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
6414         rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
6415
6416         rt2800_adjust_freq_offset(rt2x00dev);
6417
6418         rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
6419         rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
6420         rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
6421
6422         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6423         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6424         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6425         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6426         usleep_range(1000, 1500);
6427         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6428         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6429         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6430
6431         /* Set initial values for RX filter calibration */
6432         drv_data->calibration_bw20 = 0x1f;
6433         drv_data->calibration_bw40 = 0x2f;
6434
6435         /* Save BBP 25 & 26 values for later use in channel switching */
6436         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
6437         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
6438
6439         rt2800_led_open_drain_enable(rt2x00dev);
6440         rt2800_normal_mode_setup_3593(rt2x00dev);
6441
6442         rt3593_post_bbp_init(rt2x00dev);
6443
6444         /* TODO: enable stream mode support */
6445 }
6446
6447 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
6448 {
6449         rt2800_rf_init_calibration(rt2x00dev, 2);
6450
6451         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6452         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6453         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6454         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6455         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6456                 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6457         else
6458                 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6459         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6460         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6461         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6462         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6463         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6464         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6465         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6466         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6467         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6468         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
6469
6470         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6471         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6472         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6473         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6474         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6475         if (rt2x00_is_usb(rt2x00dev) &&
6476             rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6477                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6478         else
6479                 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
6480         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6481         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6482         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6483         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6484
6485         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6486         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6487         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6488         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6489         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6490         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6491         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6492         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6493         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6494         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6495
6496         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6497         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6498         rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
6499         rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
6500         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6501         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6502         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6503                 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6504         else
6505                 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
6506         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6507         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6508         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6509
6510         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6511         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6512                 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6513         else
6514                 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
6515         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6516         rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
6517         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6518                 rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
6519         else
6520                 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
6521         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6522         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6523         rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
6524
6525         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6526         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
6527                 if (rt2x00_is_usb(rt2x00dev))
6528                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
6529                 else
6530                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
6531         } else {
6532                 if (rt2x00_is_usb(rt2x00dev))
6533                         rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
6534                 else
6535                         rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
6536         }
6537         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6538         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
6539
6540         rt2800_normal_mode_setup_5xxx(rt2x00dev);
6541
6542         rt2800_led_open_drain_enable(rt2x00dev);
6543 }
6544
6545 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
6546 {
6547         rt2800_rf_init_calibration(rt2x00dev, 2);
6548
6549         rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
6550         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6551         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6552         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6553         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6554         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6555         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6556         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6557         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6558         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6559         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6560         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6561         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6562         rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
6563         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6564         rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
6565         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6566         rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
6567         rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
6568         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6569         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6570         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6571         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6572         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6573         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6574         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6575         rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
6576         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6577         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6578         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6579         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6580         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6581         rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
6582         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6583         rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
6584         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6585         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6586         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
6587         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6588         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6589         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6590         rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
6591         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6592         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6593         rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
6594         rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
6595         rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
6596         rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
6597         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
6598         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6599         rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
6600         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
6601         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
6602         rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
6603         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6604         rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
6605         rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
6606         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6607
6608         rt2800_normal_mode_setup_5xxx(rt2x00dev);
6609
6610         rt2800_led_open_drain_enable(rt2x00dev);
6611 }
6612
6613 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
6614 {
6615         rt2800_rf_init_calibration(rt2x00dev, 30);
6616
6617         rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
6618         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6619         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6620         rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
6621         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6622         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6623         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6624         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6625         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6626         rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
6627         rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
6628         rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
6629         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6630         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6631         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6632         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6633         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6634         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6635         rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
6636         rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
6637         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6638
6639         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6640         msleep(1);
6641
6642         rt2800_adjust_freq_offset(rt2x00dev);
6643
6644         /* Enable DC filter */
6645         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6646                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6647
6648         rt2800_normal_mode_setup_5xxx(rt2x00dev);
6649
6650         if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
6651                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6652
6653         rt2800_led_open_drain_enable(rt2x00dev);
6654 }
6655
6656 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
6657 {
6658         if (rt2800_is_305x_soc(rt2x00dev)) {
6659                 rt2800_init_rfcsr_305x_soc(rt2x00dev);
6660                 return;
6661         }
6662
6663         switch (rt2x00dev->chip.rt) {
6664         case RT3070:
6665         case RT3071:
6666         case RT3090:
6667                 rt2800_init_rfcsr_30xx(rt2x00dev);
6668                 break;
6669         case RT3290:
6670                 rt2800_init_rfcsr_3290(rt2x00dev);
6671                 break;
6672         case RT3352:
6673                 rt2800_init_rfcsr_3352(rt2x00dev);
6674                 break;
6675         case RT3390:
6676                 rt2800_init_rfcsr_3390(rt2x00dev);
6677                 break;
6678         case RT3572:
6679                 rt2800_init_rfcsr_3572(rt2x00dev);
6680                 break;
6681         case RT3593:
6682                 rt2800_init_rfcsr_3593(rt2x00dev);
6683                 break;
6684         case RT5390:
6685                 rt2800_init_rfcsr_5390(rt2x00dev);
6686                 break;
6687         case RT5392:
6688                 rt2800_init_rfcsr_5392(rt2x00dev);
6689                 break;
6690         case RT5592:
6691                 rt2800_init_rfcsr_5592(rt2x00dev);
6692                 break;
6693         }
6694 }
6695
6696 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
6697 {
6698         u32 reg;
6699         u16 word;
6700
6701         /*
6702          * Initialize MAC registers.
6703          */
6704         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
6705                      rt2800_init_registers(rt2x00dev)))
6706                 return -EIO;
6707
6708         /*
6709          * Wait BBP/RF to wake up.
6710          */
6711         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
6712                 return -EIO;
6713
6714         /*
6715          * Send signal during boot time to initialize firmware.
6716          */
6717         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6718         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
6719         if (rt2x00_is_usb(rt2x00dev))
6720                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
6721         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
6722         msleep(1);
6723
6724         /*
6725          * Make sure BBP is up and running.
6726          */
6727         if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
6728                 return -EIO;
6729
6730         /*
6731          * Initialize BBP/RF registers.
6732          */
6733         rt2800_init_bbp(rt2x00dev);
6734         rt2800_init_rfcsr(rt2x00dev);
6735
6736         if (rt2x00_is_usb(rt2x00dev) &&
6737             (rt2x00_rt(rt2x00dev, RT3070) ||
6738              rt2x00_rt(rt2x00dev, RT3071) ||
6739              rt2x00_rt(rt2x00dev, RT3572))) {
6740                 udelay(200);
6741                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
6742                 udelay(10);
6743         }
6744
6745         /*
6746          * Enable RX.
6747          */
6748         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6749         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6750         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6751         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6752
6753         udelay(50);
6754
6755         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6756         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
6757         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
6758         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
6759         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
6760         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6761
6762         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6763         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6764         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
6765         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6766
6767         /*
6768          * Initialize LED control
6769          */
6770         rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
6771         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
6772                            word & 0xff, (word >> 8) & 0xff);
6773
6774         rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
6775         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
6776                            word & 0xff, (word >> 8) & 0xff);
6777
6778         rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
6779         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
6780                            word & 0xff, (word >> 8) & 0xff);
6781
6782         return 0;
6783 }
6784 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
6785
6786 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
6787 {
6788         u32 reg;
6789
6790         rt2800_disable_wpdma(rt2x00dev);
6791
6792         /* Wait for DMA, ignore error */
6793         rt2800_wait_wpdma_ready(rt2x00dev);
6794
6795         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6796         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
6797         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6798         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6799 }
6800 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
6801
6802 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
6803 {
6804         u32 reg;
6805         u16 efuse_ctrl_reg;
6806
6807         if (rt2x00_rt(rt2x00dev, RT3290))
6808                 efuse_ctrl_reg = EFUSE_CTRL_3290;
6809         else
6810                 efuse_ctrl_reg = EFUSE_CTRL;
6811
6812         rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
6813         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
6814 }
6815 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
6816
6817 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
6818 {
6819         u32 reg;
6820         u16 efuse_ctrl_reg;
6821         u16 efuse_data0_reg;
6822         u16 efuse_data1_reg;
6823         u16 efuse_data2_reg;
6824         u16 efuse_data3_reg;
6825
6826         if (rt2x00_rt(rt2x00dev, RT3290)) {
6827                 efuse_ctrl_reg = EFUSE_CTRL_3290;
6828                 efuse_data0_reg = EFUSE_DATA0_3290;
6829                 efuse_data1_reg = EFUSE_DATA1_3290;
6830                 efuse_data2_reg = EFUSE_DATA2_3290;
6831                 efuse_data3_reg = EFUSE_DATA3_3290;
6832         } else {
6833                 efuse_ctrl_reg = EFUSE_CTRL;
6834                 efuse_data0_reg = EFUSE_DATA0;
6835                 efuse_data1_reg = EFUSE_DATA1;
6836                 efuse_data2_reg = EFUSE_DATA2;
6837                 efuse_data3_reg = EFUSE_DATA3;
6838         }
6839         mutex_lock(&rt2x00dev->csr_mutex);
6840
6841         rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
6842         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
6843         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
6844         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
6845         rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
6846
6847         /* Wait until the EEPROM has been loaded */
6848         rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
6849         /* Apparently the data is read from end to start */
6850         rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
6851         /* The returned value is in CPU order, but eeprom is le */
6852         *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
6853         rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
6854         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
6855         rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
6856         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
6857         rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
6858         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
6859
6860         mutex_unlock(&rt2x00dev->csr_mutex);
6861 }
6862
6863 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
6864 {
6865         unsigned int i;
6866
6867         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
6868                 rt2800_efuse_read(rt2x00dev, i);
6869
6870         return 0;
6871 }
6872 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
6873
6874 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
6875 {
6876         u16 word;
6877
6878         if (rt2x00_rt(rt2x00dev, RT3593))
6879                 return 0;
6880
6881         rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
6882         if ((word & 0x00ff) != 0x00ff)
6883                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
6884
6885         return 0;
6886 }
6887
6888 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
6889 {
6890         u16 word;
6891
6892         if (rt2x00_rt(rt2x00dev, RT3593))
6893                 return 0;
6894
6895         rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
6896         if ((word & 0x00ff) != 0x00ff)
6897                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
6898
6899         return 0;
6900 }
6901
6902 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
6903 {
6904         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6905         u16 word;
6906         u8 *mac;
6907         u8 default_lna_gain;
6908         int retval;
6909
6910         /*
6911          * Read the EEPROM.
6912          */
6913         retval = rt2800_read_eeprom(rt2x00dev);
6914         if (retval)
6915                 return retval;
6916
6917         /*
6918          * Start validation of the data that has been read.
6919          */
6920         mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
6921         if (!is_valid_ether_addr(mac)) {
6922                 eth_random_addr(mac);
6923                 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
6924         }
6925
6926         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
6927         if (word == 0xffff) {
6928                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6929                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
6930                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
6931                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6932                 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
6933         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
6934                    rt2x00_rt(rt2x00dev, RT2872)) {
6935                 /*
6936                  * There is a max of 2 RX streams for RT28x0 series
6937                  */
6938                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
6939                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6940                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6941         }
6942
6943         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
6944         if (word == 0xffff) {
6945                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
6946                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
6947                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
6948                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
6949                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
6950                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
6951                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
6952                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
6953                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
6954                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
6955                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
6956                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
6957                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
6958                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
6959                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
6960                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
6961                 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
6962         }
6963
6964         rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
6965         if ((word & 0x00ff) == 0x00ff) {
6966                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
6967                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6968                 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
6969         }
6970         if ((word & 0xff00) == 0xff00) {
6971                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
6972                                    LED_MODE_TXRX_ACTIVITY);
6973                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
6974                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6975                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
6976                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
6977                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
6978                 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
6979         }
6980
6981         /*
6982          * During the LNA validation we are going to use
6983          * lna0 as correct value. Note that EEPROM_LNA
6984          * is never validated.
6985          */
6986         rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
6987         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
6988
6989         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
6990         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
6991                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
6992         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
6993                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
6994         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
6995
6996         drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
6997
6998         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
6999         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
7000                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
7001         if (!rt2x00_rt(rt2x00dev, RT3593)) {
7002                 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
7003                     rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
7004                         rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
7005                                            default_lna_gain);
7006         }
7007         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
7008
7009         drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
7010
7011         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
7012         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
7013                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
7014         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
7015                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
7016         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
7017
7018         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
7019         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
7020                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
7021         if (!rt2x00_rt(rt2x00dev, RT3593)) {
7022                 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
7023                     rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
7024                         rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
7025                                            default_lna_gain);
7026         }
7027         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
7028
7029         if (rt2x00_rt(rt2x00dev, RT3593)) {
7030                 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
7031                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
7032                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
7033                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
7034                                            default_lna_gain);
7035                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
7036                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
7037                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
7038                                            default_lna_gain);
7039                 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
7040         }
7041
7042         return 0;
7043 }
7044
7045 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
7046 {
7047         u16 value;
7048         u16 eeprom;
7049         u16 rf;
7050
7051         /*
7052          * Read EEPROM word for configuration.
7053          */
7054         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
7055
7056         /*
7057          * Identify RF chipset by EEPROM value
7058          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
7059          * RT53xx: defined in "EEPROM_CHIP_ID" field
7060          */
7061         if (rt2x00_rt(rt2x00dev, RT3290) ||
7062             rt2x00_rt(rt2x00dev, RT5390) ||
7063             rt2x00_rt(rt2x00dev, RT5392))
7064                 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
7065         else
7066                 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
7067
7068         switch (rf) {
7069         case RF2820:
7070         case RF2850:
7071         case RF2720:
7072         case RF2750:
7073         case RF3020:
7074         case RF2020:
7075         case RF3021:
7076         case RF3022:
7077         case RF3052:
7078         case RF3053:
7079         case RF3070:
7080         case RF3290:
7081         case RF3320:
7082         case RF3322:
7083         case RF5360:
7084         case RF5362:
7085         case RF5370:
7086         case RF5372:
7087         case RF5390:
7088         case RF5392:
7089         case RF5592:
7090                 break;
7091         default:
7092                 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
7093                            rf);
7094                 return -ENODEV;
7095         }
7096
7097         rt2x00_set_rf(rt2x00dev, rf);
7098
7099         /*
7100          * Identify default antenna configuration.
7101          */
7102         rt2x00dev->default_ant.tx_chain_num =
7103             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
7104         rt2x00dev->default_ant.rx_chain_num =
7105             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
7106
7107         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
7108
7109         if (rt2x00_rt(rt2x00dev, RT3070) ||
7110             rt2x00_rt(rt2x00dev, RT3090) ||
7111             rt2x00_rt(rt2x00dev, RT3352) ||
7112             rt2x00_rt(rt2x00dev, RT3390)) {
7113                 value = rt2x00_get_field16(eeprom,
7114                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
7115                 switch (value) {
7116                 case 0:
7117                 case 1:
7118                 case 2:
7119                         rt2x00dev->default_ant.tx = ANTENNA_A;
7120                         rt2x00dev->default_ant.rx = ANTENNA_A;
7121                         break;
7122                 case 3:
7123                         rt2x00dev->default_ant.tx = ANTENNA_A;
7124                         rt2x00dev->default_ant.rx = ANTENNA_B;
7125                         break;
7126                 }
7127         } else {
7128                 rt2x00dev->default_ant.tx = ANTENNA_A;
7129                 rt2x00dev->default_ant.rx = ANTENNA_A;
7130         }
7131
7132         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
7133                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
7134                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
7135         }
7136
7137         /*
7138          * Determine external LNA informations.
7139          */
7140         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7141                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
7142         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7143                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
7144
7145         /*
7146          * Detect if this device has an hardware controlled radio.
7147          */
7148         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7149                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
7150
7151         /*
7152          * Detect if this device has Bluetooth co-existence.
7153          */
7154         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
7155                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
7156
7157         /*
7158          * Read frequency offset and RF programming sequence.
7159          */
7160         rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
7161         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
7162
7163         /*
7164          * Store led settings, for correct led behaviour.
7165          */
7166 #ifdef CONFIG_RT2X00_LIB_LEDS
7167         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
7168         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
7169         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
7170
7171         rt2x00dev->led_mcu_reg = eeprom;
7172 #endif /* CONFIG_RT2X00_LIB_LEDS */
7173
7174         /*
7175          * Check if support EIRP tx power limit feature.
7176          */
7177         rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
7178
7179         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
7180                                         EIRP_MAX_TX_POWER_LIMIT)
7181                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
7182
7183         return 0;
7184 }
7185
7186 /*
7187  * RF value list for rt28xx
7188  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
7189  */
7190 static const struct rf_channel rf_vals[] = {
7191         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
7192         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
7193         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
7194         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
7195         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
7196         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
7197         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
7198         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
7199         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
7200         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
7201         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
7202         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
7203         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
7204         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
7205
7206         /* 802.11 UNI / HyperLan 2 */
7207         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
7208         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
7209         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
7210         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
7211         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
7212         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
7213         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
7214         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
7215         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
7216         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
7217         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
7218         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
7219
7220         /* 802.11 HyperLan 2 */
7221         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
7222         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
7223         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
7224         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
7225         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
7226         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
7227         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
7228         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
7229         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
7230         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
7231         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
7232         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
7233         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
7234         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
7235         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
7236         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
7237
7238         /* 802.11 UNII */
7239         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
7240         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
7241         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
7242         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
7243         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
7244         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
7245         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
7246         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
7247         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
7248         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
7249         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
7250
7251         /* 802.11 Japan */
7252         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
7253         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
7254         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
7255         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
7256         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
7257         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
7258         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
7259 };
7260
7261 /*
7262  * RF value list for rt3xxx
7263  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
7264  */
7265 static const struct rf_channel rf_vals_3x[] = {
7266         {1,  241, 2, 2 },
7267         {2,  241, 2, 7 },
7268         {3,  242, 2, 2 },
7269         {4,  242, 2, 7 },
7270         {5,  243, 2, 2 },
7271         {6,  243, 2, 7 },
7272         {7,  244, 2, 2 },
7273         {8,  244, 2, 7 },
7274         {9,  245, 2, 2 },
7275         {10, 245, 2, 7 },
7276         {11, 246, 2, 2 },
7277         {12, 246, 2, 7 },
7278         {13, 247, 2, 2 },
7279         {14, 248, 2, 4 },
7280
7281         /* 802.11 UNI / HyperLan 2 */
7282         {36, 0x56, 0, 4},
7283         {38, 0x56, 0, 6},
7284         {40, 0x56, 0, 8},
7285         {44, 0x57, 0, 0},
7286         {46, 0x57, 0, 2},
7287         {48, 0x57, 0, 4},
7288         {52, 0x57, 0, 8},
7289         {54, 0x57, 0, 10},
7290         {56, 0x58, 0, 0},
7291         {60, 0x58, 0, 4},
7292         {62, 0x58, 0, 6},
7293         {64, 0x58, 0, 8},
7294
7295         /* 802.11 HyperLan 2 */
7296         {100, 0x5b, 0, 8},
7297         {102, 0x5b, 0, 10},
7298         {104, 0x5c, 0, 0},
7299         {108, 0x5c, 0, 4},
7300         {110, 0x5c, 0, 6},
7301         {112, 0x5c, 0, 8},
7302         {116, 0x5d, 0, 0},
7303         {118, 0x5d, 0, 2},
7304         {120, 0x5d, 0, 4},
7305         {124, 0x5d, 0, 8},
7306         {126, 0x5d, 0, 10},
7307         {128, 0x5e, 0, 0},
7308         {132, 0x5e, 0, 4},
7309         {134, 0x5e, 0, 6},
7310         {136, 0x5e, 0, 8},
7311         {140, 0x5f, 0, 0},
7312
7313         /* 802.11 UNII */
7314         {149, 0x5f, 0, 9},
7315         {151, 0x5f, 0, 11},
7316         {153, 0x60, 0, 1},
7317         {157, 0x60, 0, 5},
7318         {159, 0x60, 0, 7},
7319         {161, 0x60, 0, 9},
7320         {165, 0x61, 0, 1},
7321         {167, 0x61, 0, 3},
7322         {169, 0x61, 0, 5},
7323         {171, 0x61, 0, 7},
7324         {173, 0x61, 0, 9},
7325 };
7326
7327 static const struct rf_channel rf_vals_5592_xtal20[] = {
7328         /* Channel, N, K, mod, R */
7329         {1, 482, 4, 10, 3},
7330         {2, 483, 4, 10, 3},
7331         {3, 484, 4, 10, 3},
7332         {4, 485, 4, 10, 3},
7333         {5, 486, 4, 10, 3},
7334         {6, 487, 4, 10, 3},
7335         {7, 488, 4, 10, 3},
7336         {8, 489, 4, 10, 3},
7337         {9, 490, 4, 10, 3},
7338         {10, 491, 4, 10, 3},
7339         {11, 492, 4, 10, 3},
7340         {12, 493, 4, 10, 3},
7341         {13, 494, 4, 10, 3},
7342         {14, 496, 8, 10, 3},
7343         {36, 172, 8, 12, 1},
7344         {38, 173, 0, 12, 1},
7345         {40, 173, 4, 12, 1},
7346         {42, 173, 8, 12, 1},
7347         {44, 174, 0, 12, 1},
7348         {46, 174, 4, 12, 1},
7349         {48, 174, 8, 12, 1},
7350         {50, 175, 0, 12, 1},
7351         {52, 175, 4, 12, 1},
7352         {54, 175, 8, 12, 1},
7353         {56, 176, 0, 12, 1},
7354         {58, 176, 4, 12, 1},
7355         {60, 176, 8, 12, 1},
7356         {62, 177, 0, 12, 1},
7357         {64, 177, 4, 12, 1},
7358         {100, 183, 4, 12, 1},
7359         {102, 183, 8, 12, 1},
7360         {104, 184, 0, 12, 1},
7361         {106, 184, 4, 12, 1},
7362         {108, 184, 8, 12, 1},
7363         {110, 185, 0, 12, 1},
7364         {112, 185, 4, 12, 1},
7365         {114, 185, 8, 12, 1},
7366         {116, 186, 0, 12, 1},
7367         {118, 186, 4, 12, 1},
7368         {120, 186, 8, 12, 1},
7369         {122, 187, 0, 12, 1},
7370         {124, 187, 4, 12, 1},
7371         {126, 187, 8, 12, 1},
7372         {128, 188, 0, 12, 1},
7373         {130, 188, 4, 12, 1},
7374         {132, 188, 8, 12, 1},
7375         {134, 189, 0, 12, 1},
7376         {136, 189, 4, 12, 1},
7377         {138, 189, 8, 12, 1},
7378         {140, 190, 0, 12, 1},
7379         {149, 191, 6, 12, 1},
7380         {151, 191, 10, 12, 1},
7381         {153, 192, 2, 12, 1},
7382         {155, 192, 6, 12, 1},
7383         {157, 192, 10, 12, 1},
7384         {159, 193, 2, 12, 1},
7385         {161, 193, 6, 12, 1},
7386         {165, 194, 2, 12, 1},
7387         {184, 164, 0, 12, 1},
7388         {188, 164, 4, 12, 1},
7389         {192, 165, 8, 12, 1},
7390         {196, 166, 0, 12, 1},
7391 };
7392
7393 static const struct rf_channel rf_vals_5592_xtal40[] = {
7394         /* Channel, N, K, mod, R */
7395         {1, 241, 2, 10, 3},
7396         {2, 241, 7, 10, 3},
7397         {3, 242, 2, 10, 3},
7398         {4, 242, 7, 10, 3},
7399         {5, 243, 2, 10, 3},
7400         {6, 243, 7, 10, 3},
7401         {7, 244, 2, 10, 3},
7402         {8, 244, 7, 10, 3},
7403         {9, 245, 2, 10, 3},
7404         {10, 245, 7, 10, 3},
7405         {11, 246, 2, 10, 3},
7406         {12, 246, 7, 10, 3},
7407         {13, 247, 2, 10, 3},
7408         {14, 248, 4, 10, 3},
7409         {36, 86, 4, 12, 1},
7410         {38, 86, 6, 12, 1},
7411         {40, 86, 8, 12, 1},
7412         {42, 86, 10, 12, 1},
7413         {44, 87, 0, 12, 1},
7414         {46, 87, 2, 12, 1},
7415         {48, 87, 4, 12, 1},
7416         {50, 87, 6, 12, 1},
7417         {52, 87, 8, 12, 1},
7418         {54, 87, 10, 12, 1},
7419         {56, 88, 0, 12, 1},
7420         {58, 88, 2, 12, 1},
7421         {60, 88, 4, 12, 1},
7422         {62, 88, 6, 12, 1},
7423         {64, 88, 8, 12, 1},
7424         {100, 91, 8, 12, 1},
7425         {102, 91, 10, 12, 1},
7426         {104, 92, 0, 12, 1},
7427         {106, 92, 2, 12, 1},
7428         {108, 92, 4, 12, 1},
7429         {110, 92, 6, 12, 1},
7430         {112, 92, 8, 12, 1},
7431         {114, 92, 10, 12, 1},
7432         {116, 93, 0, 12, 1},
7433         {118, 93, 2, 12, 1},
7434         {120, 93, 4, 12, 1},
7435         {122, 93, 6, 12, 1},
7436         {124, 93, 8, 12, 1},
7437         {126, 93, 10, 12, 1},
7438         {128, 94, 0, 12, 1},
7439         {130, 94, 2, 12, 1},
7440         {132, 94, 4, 12, 1},
7441         {134, 94, 6, 12, 1},
7442         {136, 94, 8, 12, 1},
7443         {138, 94, 10, 12, 1},
7444         {140, 95, 0, 12, 1},
7445         {149, 95, 9, 12, 1},
7446         {151, 95, 11, 12, 1},
7447         {153, 96, 1, 12, 1},
7448         {155, 96, 3, 12, 1},
7449         {157, 96, 5, 12, 1},
7450         {159, 96, 7, 12, 1},
7451         {161, 96, 9, 12, 1},
7452         {165, 97, 1, 12, 1},
7453         {184, 82, 0, 12, 1},
7454         {188, 82, 4, 12, 1},
7455         {192, 82, 8, 12, 1},
7456         {196, 83, 0, 12, 1},
7457 };
7458
7459 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
7460 {
7461         struct hw_mode_spec *spec = &rt2x00dev->spec;
7462         struct channel_info *info;
7463         char *default_power1;
7464         char *default_power2;
7465         char *default_power3;
7466         unsigned int i;
7467         u32 reg;
7468
7469         /*
7470          * Disable powersaving as default.
7471          */
7472         rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
7473
7474         /*
7475          * Initialize all hw fields.
7476          */
7477         ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_HT_CCK_RATES);
7478         ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
7479         ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
7480         ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
7481         ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
7482         ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
7483
7484         /*
7485          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
7486          * unless we are capable of sending the buffered frames out after the
7487          * DTIM transmission using rt2x00lib_beacondone. This will send out
7488          * multicast and broadcast traffic immediately instead of buffering it
7489          * infinitly and thus dropping it after some time.
7490          */
7491         if (!rt2x00_is_usb(rt2x00dev))
7492                 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
7493
7494         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
7495         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
7496                                 rt2800_eeprom_addr(rt2x00dev,
7497                                                    EEPROM_MAC_ADDR_0));
7498
7499         /*
7500          * As rt2800 has a global fallback table we cannot specify
7501          * more then one tx rate per frame but since the hw will
7502          * try several rates (based on the fallback table) we should
7503          * initialize max_report_rates to the maximum number of rates
7504          * we are going to try. Otherwise mac80211 will truncate our
7505          * reported tx rates and the rc algortihm will end up with
7506          * incorrect data.
7507          */
7508         rt2x00dev->hw->max_rates = 1;
7509         rt2x00dev->hw->max_report_rates = 7;
7510         rt2x00dev->hw->max_rate_tries = 1;
7511
7512         /*
7513          * Initialize hw_mode information.
7514          */
7515         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
7516
7517         switch (rt2x00dev->chip.rf) {
7518         case RF2720:
7519         case RF2820:
7520                 spec->num_channels = 14;
7521                 spec->channels = rf_vals;
7522                 break;
7523
7524         case RF2750:
7525         case RF2850:
7526                 spec->num_channels = ARRAY_SIZE(rf_vals);
7527                 spec->channels = rf_vals;
7528                 break;
7529
7530         case RF2020:
7531         case RF3020:
7532         case RF3021:
7533         case RF3022:
7534         case RF3070:
7535         case RF3290:
7536         case RF3320:
7537         case RF3322:
7538         case RF5360:
7539         case RF5362:
7540         case RF5370:
7541         case RF5372:
7542         case RF5390:
7543         case RF5392:
7544                 spec->num_channels = 14;
7545                 spec->channels = rf_vals_3x;
7546                 break;
7547
7548         case RF3052:
7549         case RF3053:
7550                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
7551                 spec->channels = rf_vals_3x;
7552                 break;
7553
7554         case RF5592:
7555                 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
7556                 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
7557                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
7558                         spec->channels = rf_vals_5592_xtal40;
7559                 } else {
7560                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
7561                         spec->channels = rf_vals_5592_xtal20;
7562                 }
7563                 break;
7564         }
7565
7566         if (WARN_ON_ONCE(!spec->channels))
7567                 return -ENODEV;
7568
7569         spec->supported_bands = SUPPORT_BAND_2GHZ;
7570         if (spec->num_channels > 14)
7571                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7572
7573         /*
7574          * Initialize HT information.
7575          */
7576         if (!rt2x00_rf(rt2x00dev, RF2020))
7577                 spec->ht.ht_supported = true;
7578         else
7579                 spec->ht.ht_supported = false;
7580
7581         spec->ht.cap =
7582             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
7583             IEEE80211_HT_CAP_GRN_FLD |
7584             IEEE80211_HT_CAP_SGI_20 |
7585             IEEE80211_HT_CAP_SGI_40;
7586
7587         if (rt2x00dev->default_ant.tx_chain_num >= 2)
7588                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
7589
7590         spec->ht.cap |= rt2x00dev->default_ant.rx_chain_num <<
7591                         IEEE80211_HT_CAP_RX_STBC_SHIFT;
7592
7593         spec->ht.ampdu_factor = 3;
7594         spec->ht.ampdu_density = 4;
7595         spec->ht.mcs.tx_params =
7596             IEEE80211_HT_MCS_TX_DEFINED |
7597             IEEE80211_HT_MCS_TX_RX_DIFF |
7598             ((rt2x00dev->default_ant.tx_chain_num - 1) <<
7599              IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
7600
7601         switch (rt2x00dev->default_ant.rx_chain_num) {
7602         case 3:
7603                 spec->ht.mcs.rx_mask[2] = 0xff;
7604         case 2:
7605                 spec->ht.mcs.rx_mask[1] = 0xff;
7606         case 1:
7607                 spec->ht.mcs.rx_mask[0] = 0xff;
7608                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
7609                 break;
7610         }
7611
7612         /*
7613          * Create channel information array
7614          */
7615         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
7616         if (!info)
7617                 return -ENOMEM;
7618
7619         spec->channels_info = info;
7620
7621         default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
7622         default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
7623
7624         if (rt2x00dev->default_ant.tx_chain_num > 2)
7625                 default_power3 = rt2800_eeprom_addr(rt2x00dev,
7626                                                     EEPROM_EXT_TXPOWER_BG3);
7627         else
7628                 default_power3 = NULL;
7629
7630         for (i = 0; i < 14; i++) {
7631                 info[i].default_power1 = default_power1[i];
7632                 info[i].default_power2 = default_power2[i];
7633                 if (default_power3)
7634                         info[i].default_power3 = default_power3[i];
7635         }
7636
7637         if (spec->num_channels > 14) {
7638                 default_power1 = rt2800_eeprom_addr(rt2x00dev,
7639                                                     EEPROM_TXPOWER_A1);
7640                 default_power2 = rt2800_eeprom_addr(rt2x00dev,
7641                                                     EEPROM_TXPOWER_A2);
7642
7643                 if (rt2x00dev->default_ant.tx_chain_num > 2)
7644                         default_power3 =
7645                                 rt2800_eeprom_addr(rt2x00dev,
7646                                                    EEPROM_EXT_TXPOWER_A3);
7647                 else
7648                         default_power3 = NULL;
7649
7650                 for (i = 14; i < spec->num_channels; i++) {
7651                         info[i].default_power1 = default_power1[i - 14];
7652                         info[i].default_power2 = default_power2[i - 14];
7653                         if (default_power3)
7654                                 info[i].default_power3 = default_power3[i - 14];
7655                 }
7656         }
7657
7658         switch (rt2x00dev->chip.rf) {
7659         case RF2020:
7660         case RF3020:
7661         case RF3021:
7662         case RF3022:
7663         case RF3320:
7664         case RF3052:
7665         case RF3053:
7666         case RF3070:
7667         case RF3290:
7668         case RF5360:
7669         case RF5362:
7670         case RF5370:
7671         case RF5372:
7672         case RF5390:
7673         case RF5392:
7674                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
7675                 break;
7676         }
7677
7678         return 0;
7679 }
7680
7681 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
7682 {
7683         u32 reg;
7684         u32 rt;
7685         u32 rev;
7686
7687         if (rt2x00_rt(rt2x00dev, RT3290))
7688                 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
7689         else
7690                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
7691
7692         rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
7693         rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
7694
7695         switch (rt) {
7696         case RT2860:
7697         case RT2872:
7698         case RT2883:
7699         case RT3070:
7700         case RT3071:
7701         case RT3090:
7702         case RT3290:
7703         case RT3352:
7704         case RT3390:
7705         case RT3572:
7706         case RT3593:
7707         case RT5390:
7708         case RT5392:
7709         case RT5592:
7710                 break;
7711         default:
7712                 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
7713                            rt, rev);
7714                 return -ENODEV;
7715         }
7716
7717         rt2x00_set_rt(rt2x00dev, rt, rev);
7718
7719         return 0;
7720 }
7721
7722 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
7723 {
7724         int retval;
7725         u32 reg;
7726
7727         retval = rt2800_probe_rt(rt2x00dev);
7728         if (retval)
7729                 return retval;
7730
7731         /*
7732          * Allocate eeprom data.
7733          */
7734         retval = rt2800_validate_eeprom(rt2x00dev);
7735         if (retval)
7736                 return retval;
7737
7738         retval = rt2800_init_eeprom(rt2x00dev);
7739         if (retval)
7740                 return retval;
7741
7742         /*
7743          * Enable rfkill polling by setting GPIO direction of the
7744          * rfkill switch GPIO pin correctly.
7745          */
7746         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
7747         rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
7748         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
7749
7750         /*
7751          * Initialize hw specifications.
7752          */
7753         retval = rt2800_probe_hw_mode(rt2x00dev);
7754         if (retval)
7755                 return retval;
7756
7757         /*
7758          * Set device capabilities.
7759          */
7760         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
7761         __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
7762         if (!rt2x00_is_usb(rt2x00dev))
7763                 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
7764
7765         /*
7766          * Set device requirements.
7767          */
7768         if (!rt2x00_is_soc(rt2x00dev))
7769                 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
7770         __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
7771         __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
7772         if (!rt2800_hwcrypt_disabled(rt2x00dev))
7773                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
7774         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
7775         __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
7776         if (rt2x00_is_usb(rt2x00dev))
7777                 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
7778         else {
7779                 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
7780                 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
7781         }
7782
7783         /*
7784          * Set the rssi offset.
7785          */
7786         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
7787
7788         return 0;
7789 }
7790 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
7791
7792 /*
7793  * IEEE80211 stack callback functions.
7794  */
7795 void rt2800_get_key_seq(struct ieee80211_hw *hw,
7796                         struct ieee80211_key_conf *key,
7797                         struct ieee80211_key_seq *seq)
7798 {
7799         struct rt2x00_dev *rt2x00dev = hw->priv;
7800         struct mac_iveiv_entry iveiv_entry;
7801         u32 offset;
7802
7803         if (key->cipher != WLAN_CIPHER_SUITE_TKIP)
7804                 return;
7805
7806         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
7807         rt2800_register_multiread(rt2x00dev, offset,
7808                                       &iveiv_entry, sizeof(iveiv_entry));
7809
7810         memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2);
7811         memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4);
7812 }
7813 EXPORT_SYMBOL_GPL(rt2800_get_key_seq);
7814
7815 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
7816 {
7817         struct rt2x00_dev *rt2x00dev = hw->priv;
7818         u32 reg;
7819         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
7820
7821         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
7822         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
7823         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
7824
7825         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
7826         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
7827         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
7828
7829         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
7830         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
7831         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
7832
7833         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
7834         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
7835         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
7836
7837         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
7838         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
7839         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
7840
7841         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
7842         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
7843         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
7844
7845         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
7846         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
7847         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
7848
7849         return 0;
7850 }
7851 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
7852
7853 int rt2800_conf_tx(struct ieee80211_hw *hw,
7854                    struct ieee80211_vif *vif, u16 queue_idx,
7855                    const struct ieee80211_tx_queue_params *params)
7856 {
7857         struct rt2x00_dev *rt2x00dev = hw->priv;
7858         struct data_queue *queue;
7859         struct rt2x00_field32 field;
7860         int retval;
7861         u32 reg;
7862         u32 offset;
7863
7864         /*
7865          * First pass the configuration through rt2x00lib, that will
7866          * update the queue settings and validate the input. After that
7867          * we are free to update the registers based on the value
7868          * in the queue parameter.
7869          */
7870         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
7871         if (retval)
7872                 return retval;
7873
7874         /*
7875          * We only need to perform additional register initialization
7876          * for WMM queues/
7877          */
7878         if (queue_idx >= 4)
7879                 return 0;
7880
7881         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
7882
7883         /* Update WMM TXOP register */
7884         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
7885         field.bit_offset = (queue_idx & 1) * 16;
7886         field.bit_mask = 0xffff << field.bit_offset;
7887
7888         rt2800_register_read(rt2x00dev, offset, &reg);
7889         rt2x00_set_field32(&reg, field, queue->txop);
7890         rt2800_register_write(rt2x00dev, offset, reg);
7891
7892         /* Update WMM registers */
7893         field.bit_offset = queue_idx * 4;
7894         field.bit_mask = 0xf << field.bit_offset;
7895
7896         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
7897         rt2x00_set_field32(&reg, field, queue->aifs);
7898         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
7899
7900         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
7901         rt2x00_set_field32(&reg, field, queue->cw_min);
7902         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
7903
7904         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
7905         rt2x00_set_field32(&reg, field, queue->cw_max);
7906         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
7907
7908         /* Update EDCA registers */
7909         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
7910
7911         rt2800_register_read(rt2x00dev, offset, &reg);
7912         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
7913         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
7914         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
7915         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
7916         rt2800_register_write(rt2x00dev, offset, reg);
7917
7918         return 0;
7919 }
7920 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
7921
7922 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
7923 {
7924         struct rt2x00_dev *rt2x00dev = hw->priv;
7925         u64 tsf;
7926         u32 reg;
7927
7928         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
7929         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
7930         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
7931         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
7932
7933         return tsf;
7934 }
7935 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
7936
7937 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7938                         enum ieee80211_ampdu_mlme_action action,
7939                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
7940                         u8 buf_size, bool amsdu)
7941 {
7942         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
7943         int ret = 0;
7944
7945         /*
7946          * Don't allow aggregation for stations the hardware isn't aware
7947          * of because tx status reports for frames to an unknown station
7948          * always contain wcid=WCID_END+1 and thus we can't distinguish
7949          * between multiple stations which leads to unwanted situations
7950          * when the hw reorders frames due to aggregation.
7951          */
7952         if (sta_priv->wcid > WCID_END)
7953                 return 1;
7954
7955         switch (action) {
7956         case IEEE80211_AMPDU_RX_START:
7957         case IEEE80211_AMPDU_RX_STOP:
7958                 /*
7959                  * The hw itself takes care of setting up BlockAck mechanisms.
7960                  * So, we only have to allow mac80211 to nagotiate a BlockAck
7961                  * agreement. Once that is done, the hw will BlockAck incoming
7962                  * AMPDUs without further setup.
7963                  */
7964                 break;
7965         case IEEE80211_AMPDU_TX_START:
7966                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7967                 break;
7968         case IEEE80211_AMPDU_TX_STOP_CONT:
7969         case IEEE80211_AMPDU_TX_STOP_FLUSH:
7970         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
7971                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7972                 break;
7973         case IEEE80211_AMPDU_TX_OPERATIONAL:
7974                 break;
7975         default:
7976                 rt2x00_warn((struct rt2x00_dev *)hw->priv,
7977                             "Unknown AMPDU action\n");
7978         }
7979
7980         return ret;
7981 }
7982 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
7983
7984 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
7985                       struct survey_info *survey)
7986 {
7987         struct rt2x00_dev *rt2x00dev = hw->priv;
7988         struct ieee80211_conf *conf = &hw->conf;
7989         u32 idle, busy, busy_ext;
7990
7991         if (idx != 0)
7992                 return -ENOENT;
7993
7994         survey->channel = conf->chandef.chan;
7995
7996         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
7997         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
7998         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
7999
8000         if (idle || busy) {
8001                 survey->filled = SURVEY_INFO_TIME |
8002                                  SURVEY_INFO_TIME_BUSY |
8003                                  SURVEY_INFO_TIME_EXT_BUSY;
8004
8005                 survey->time = (idle + busy) / 1000;
8006                 survey->time_busy = busy / 1000;
8007                 survey->time_ext_busy = busy_ext / 1000;
8008         }
8009
8010         if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
8011                 survey->filled |= SURVEY_INFO_IN_USE;
8012
8013         return 0;
8014
8015 }
8016 EXPORT_SYMBOL_GPL(rt2800_get_survey);
8017
8018 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
8019 MODULE_VERSION(DRV_VERSION);
8020 MODULE_DESCRIPTION("Ralink RT2800 library");
8021 MODULE_LICENSE("GPL");