drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c

   1 /*
   2  * RTL8XXXU mac80211 USB driver
   3  *
   4  * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
   5  *
   6  * Portions, notably calibration code:
   7  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   8  *
   9  * This driver was written as a replacement for the vendor provided
  10  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
  11  * their programming interface, I have started adding support for
  12  * additional 8xxx chips like the 8192cu, 8188cus, etc.
  13  *
  14  * This program is free software; you can redistribute it and/or modify it
  15  * under the terms of version 2 of the GNU General Public License as
  16  * published by the Free Software Foundation.
  17  *
  18  * This program is distributed in the hope that it will be useful, but WITHOUT
  19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  21  * more details.
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/kernel.h>
  26 #include <linux/sched.h>
  27 #include <linux/errno.h>
  28 #include <linux/slab.h>
  29 #include <linux/module.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/list.h>
  32 #include <linux/usb.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/wireless.h>
  37 #include <linux/firmware.h>
  38 #include <linux/moduleparam.h>
  39 #include <net/mac80211.h>
  40 #include "rtl8xxxu.h"
  41 #include "rtl8xxxu_regs.h"
  42
  43 #define DRIVER_NAME "rtl8xxxu"
  44
  45 static int rtl8xxxu_debug;
  46 static bool rtl8xxxu_ht40_2g;
  47
  48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
  49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
  50 MODULE_LICENSE("GPL");
  51 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
  52 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
  53 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
  54 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
  55 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
  56 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
  57
  58 module_param_named(debug, rtl8xxxu_debug, int, 0600);
  59 MODULE_PARM_DESC(debug, "Set debug mask");
  60 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
  61 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
  62
  63 #define USB_VENDOR_ID_REALTEK           0x0bda
  64 /* Minimum IEEE80211_MAX_FRAME_LEN */
  65 #define RTL_RX_BUFFER_SIZE              IEEE80211_MAX_FRAME_LEN
  66 #define RTL8XXXU_RX_URBS                32
  67 #define RTL8XXXU_RX_URB_PENDING_WATER   8
  68 #define RTL8XXXU_TX_URBS                64
  69 #define RTL8XXXU_TX_URB_LOW_WATER       25
  70 #define RTL8XXXU_TX_URB_HIGH_WATER      32
  71
  72 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
  73                                   struct rtl8xxxu_rx_urb *rx_urb);
  74
  75 static struct ieee80211_rate rtl8xxxu_rates[] = {
  76         { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
  77         { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
  78         { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
  79         { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
  80         { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
  81         { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
  82         { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
  83         { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
  84         { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
  85         { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
  86         { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
  87         { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
  88 };
  89
  90 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
  91         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
  92           .hw_value = 1, .max_power = 30 },
  93         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
  94           .hw_value = 2, .max_power = 30 },
  95         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
  96           .hw_value = 3, .max_power = 30 },
  97         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
  98           .hw_value = 4, .max_power = 30 },
  99         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
 100           .hw_value = 5, .max_power = 30 },
 101         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
 102           .hw_value = 6, .max_power = 30 },
 103         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
 104           .hw_value = 7, .max_power = 30 },
 105         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
 106           .hw_value = 8, .max_power = 30 },
 107         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
 108           .hw_value = 9, .max_power = 30 },
 109         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
 110           .hw_value = 10, .max_power = 30 },
 111         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
 112           .hw_value = 11, .max_power = 30 },
 113         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
 114           .hw_value = 12, .max_power = 30 },
 115         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
 116           .hw_value = 13, .max_power = 30 },
 117         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
 118           .hw_value = 14, .max_power = 30 }
 119 };
 120
 121 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
 122         .channels = rtl8xxxu_channels_2g,
 123         .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
 124         .bitrates = rtl8xxxu_rates,
 125         .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
 126 };
 127
 128 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
 129         {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
 130         {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
 131         {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
 132         {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
 133         {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
 134         {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
 135         {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
 136         {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
 137         {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
 138         {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
 139         {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
 140         {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
 141         {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
 142         {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
 143         {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
 144         {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
 145         {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
 146         {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
 147         {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
 148         {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
 149         {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
 150         {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
 151 };
 152
 153 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
 154         {0x800, 0x80040000}, {0x804, 0x00000003},
 155         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 156         {0x810, 0x10001331}, {0x814, 0x020c3d10},
 157         {0x818, 0x02200385}, {0x81c, 0x00000000},
 158         {0x820, 0x01000100}, {0x824, 0x00390004},
 159         {0x828, 0x00000000}, {0x82c, 0x00000000},
 160         {0x830, 0x00000000}, {0x834, 0x00000000},
 161         {0x838, 0x00000000}, {0x83c, 0x00000000},
 162         {0x840, 0x00010000}, {0x844, 0x00000000},
 163         {0x848, 0x00000000}, {0x84c, 0x00000000},
 164         {0x850, 0x00000000}, {0x854, 0x00000000},
 165         {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
 166         {0x860, 0x66f60110}, {0x864, 0x061f0130},
 167         {0x868, 0x00000000}, {0x86c, 0x32323200},
 168         {0x870, 0x07000760}, {0x874, 0x22004000},
 169         {0x878, 0x00000808}, {0x87c, 0x00000000},
 170         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 171         {0x888, 0x00000000}, {0x88c, 0xccc000c0},
 172         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 173         {0x898, 0x40302010}, {0x89c, 0x00706050},
 174         {0x900, 0x00000000}, {0x904, 0x00000023},
 175         {0x908, 0x00000000}, {0x90c, 0x81121111},
 176         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 177         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 178         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 179         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 180         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 181         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 182         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 183         {0xa78, 0x00000900},
 184         {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
 185         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 186         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 187         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 188         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 189         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 190         {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
 191         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 192         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 193         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 194         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 195         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 196         {0xc60, 0x00000000}, {0xc64, 0x7112848b},
 197         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 198         {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
 199         {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
 200         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 201         {0xc88, 0x40000100}, {0xc8c, 0x20200000},
 202         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 203         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 204         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 205         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 206         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 207         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 208         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 209         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 210         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 211         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 212         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 213         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 214         {0xd00, 0x00080740}, {0xd04, 0x00020401},
 215         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 216         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 217         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 218         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 219         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 220         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 221         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 222         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 223         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 224         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 225         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 226         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 227         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 228         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 229         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 230         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 231         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 232         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 233         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 234         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 235         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 236         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 237         {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
 238         {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
 239         {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
 240         {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
 241         {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
 242         {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
 243         {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
 244         {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
 245         {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
 246         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 247         {0xf00, 0x00000300},
 248         {0xffff, 0xffffffff},
 249 };
 250
 251 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
 252         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 253         {0x800, 0x80040002}, {0x804, 0x00000003},
 254         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 255         {0x810, 0x10000330}, {0x814, 0x020c3d10},
 256         {0x818, 0x02200385}, {0x81c, 0x00000000},
 257         {0x820, 0x01000100}, {0x824, 0x00390004},
 258         {0x828, 0x01000100}, {0x82c, 0x00390004},
 259         {0x830, 0x27272727}, {0x834, 0x27272727},
 260         {0x838, 0x27272727}, {0x83c, 0x27272727},
 261         {0x840, 0x00010000}, {0x844, 0x00010000},
 262         {0x848, 0x27272727}, {0x84c, 0x27272727},
 263         {0x850, 0x00000000}, {0x854, 0x00000000},
 264         {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
 265         {0x860, 0x66e60230}, {0x864, 0x061f0130},
 266         {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
 267         {0x870, 0x07000700}, {0x874, 0x22184000},
 268         {0x878, 0x08080808}, {0x87c, 0x00000000},
 269         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 270         {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
 271         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 272         {0x898, 0x40302010}, {0x89c, 0x00706050},
 273         {0x900, 0x00000000}, {0x904, 0x00000023},
 274         {0x908, 0x00000000}, {0x90c, 0x81121313},
 275         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 276         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 277         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 278         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 279         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 280         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 281         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 282         {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
 283         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 284         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 285         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 286         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 287         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 288         {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
 289         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 290         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 291         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 292         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 293         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 294         {0xc60, 0x00000000}, {0xc64, 0x5116848b},
 295         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 296         {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
 297         {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
 298         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 299         {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
 300         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 301         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 302         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 303         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 304         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 305         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 306         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 307         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 308         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 309         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 310         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 311         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 312         {0xd00, 0x00080740}, {0xd04, 0x00020403},
 313         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 314         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 315         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 316         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 317         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 318         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 319         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 320         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 321         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 322         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 323         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 324         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 325         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 326         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 327         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 328         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 329         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 330         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 331         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 332         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 333         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 334         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 335         {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
 336         {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
 337         {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
 338         {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
 339         {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
 340         {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
 341         {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
 342         {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
 343         {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
 344         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 345         {0xf00, 0x00000300},
 346         {0xffff, 0xffffffff},
 347 };
 348
 349 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
 350         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 351         {0x040, 0x000c0004}, {0x800, 0x80040000},
 352         {0x804, 0x00000001}, {0x808, 0x0000fc00},
 353         {0x80c, 0x0000000a}, {0x810, 0x10005388},
 354         {0x814, 0x020c3d10}, {0x818, 0x02200385},
 355         {0x81c, 0x00000000}, {0x820, 0x01000100},
 356         {0x824, 0x00390204}, {0x828, 0x00000000},
 357         {0x82c, 0x00000000}, {0x830, 0x00000000},
 358         {0x834, 0x00000000}, {0x838, 0x00000000},
 359         {0x83c, 0x00000000}, {0x840, 0x00010000},
 360         {0x844, 0x00000000}, {0x848, 0x00000000},
 361         {0x84c, 0x00000000}, {0x850, 0x00000000},
 362         {0x854, 0x00000000}, {0x858, 0x569a569a},
 363         {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
 364         {0x864, 0x061f0130}, {0x868, 0x00000000},
 365         {0x86c, 0x20202000}, {0x870, 0x03000300},
 366         {0x874, 0x22004000}, {0x878, 0x00000808},
 367         {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
 368         {0x884, 0x000004d5}, {0x888, 0x00000000},
 369         {0x88c, 0xccc000c0}, {0x890, 0x00000800},
 370         {0x894, 0xfffffffe}, {0x898, 0x40302010},
 371         {0x89c, 0x00706050}, {0x900, 0x00000000},
 372         {0x904, 0x00000023}, {0x908, 0x00000000},
 373         {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
 374         {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
 375         {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
 376         {0xa14, 0x11144028}, {0xa18, 0x00881117},
 377         {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
 378         {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
 379         {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
 380         {0xa74, 0x00000007}, {0xc00, 0x48071d40},
 381         {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
 382         {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
 383         {0xc14, 0x40000100}, {0xc18, 0x08800000},
 384         {0xc1c, 0x40000100}, {0xc20, 0x00000000},
 385         {0xc24, 0x00000000}, {0xc28, 0x00000000},
 386         {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
 387         {0xc34, 0x469652cf}, {0xc38, 0x49795994},
 388         {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
 389         {0xc44, 0x000100b7}, {0xc48, 0xec020107},
 390         {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
 391         {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
 392         {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
 393         {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
 394         {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
 395         {0xc74, 0x018610db}, {0xc78, 0x0000001f},
 396         {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
 397         {0xc84, 0x20f60000}, {0xc88, 0x24000090},
 398         {0xc8c, 0x20200000}, {0xc90, 0x00121820},
 399         {0xc94, 0x00000000}, {0xc98, 0x00121820},
 400         {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
 401         {0xca4, 0x00000080}, {0xca8, 0x00000000},
 402         {0xcac, 0x00000000}, {0xcb0, 0x00000000},
 403         {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
 404         {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
 405         {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
 406         {0xccc, 0x00000000}, {0xcd0, 0x00000000},
 407         {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
 408         {0xcdc, 0x00766932}, {0xce0, 0x00222222},
 409         {0xce4, 0x00000000}, {0xce8, 0x37644302},
 410         {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
 411         {0xd04, 0x00020401}, {0xd08, 0x0000907f},
 412         {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
 413         {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
 414         {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
 415         {0xd34, 0x80608000}, {0xd38, 0x00000000},
 416         {0xd3c, 0x00027293}, {0xd40, 0x00000000},
 417         {0xd44, 0x00000000}, {0xd48, 0x00000000},
 418         {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
 419         {0xd54, 0x00000000}, {0xd58, 0x00000000},
 420         {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
 421         {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
 422         {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
 423         {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
 424         {0xe00, 0x24242424}, {0xe04, 0x24242424},
 425         {0xe08, 0x03902024}, {0xe10, 0x24242424},
 426         {0xe14, 0x24242424}, {0xe18, 0x24242424},
 427         {0xe1c, 0x24242424}, {0xe28, 0x00000000},
 428         {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
 429         {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
 430         {0xe40, 0x01007c00}, {0xe44, 0x01004800},
 431         {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
 432         {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
 433         {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
 434         {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
 435         {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
 436         {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
 437         {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
 438         {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
 439         {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
 440         {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
 441         {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
 442         {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
 443         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 444         {0xf00, 0x00000300},
 445         {0xffff, 0xffffffff},
 446 };
 447
 448 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
 449         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 450         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 451         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 452         {0xc78, 0x7a060001}, {0xc78, 0x79070001},
 453         {0xc78, 0x78080001}, {0xc78, 0x77090001},
 454         {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
 455         {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
 456         {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
 457         {0xc78, 0x70100001}, {0xc78, 0x6f110001},
 458         {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
 459         {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
 460         {0xc78, 0x6a160001}, {0xc78, 0x69170001},
 461         {0xc78, 0x68180001}, {0xc78, 0x67190001},
 462         {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
 463         {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
 464         {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
 465         {0xc78, 0x60200001}, {0xc78, 0x49210001},
 466         {0xc78, 0x48220001}, {0xc78, 0x47230001},
 467         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 468         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 469         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 470         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 471         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 472         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 473         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 474         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 475         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 476         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 477         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 478         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 479         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 480         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 481         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 482         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 483         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 484         {0xc78, 0x7a460001}, {0xc78, 0x79470001},
 485         {0xc78, 0x78480001}, {0xc78, 0x77490001},
 486         {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
 487         {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
 488         {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
 489         {0xc78, 0x70500001}, {0xc78, 0x6f510001},
 490         {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
 491         {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
 492         {0xc78, 0x6a560001}, {0xc78, 0x69570001},
 493         {0xc78, 0x68580001}, {0xc78, 0x67590001},
 494         {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
 495         {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
 496         {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
 497         {0xc78, 0x60600001}, {0xc78, 0x49610001},
 498         {0xc78, 0x48620001}, {0xc78, 0x47630001},
 499         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 500         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 501         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 502         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 503         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 504         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 505         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 506         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 507         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 508         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 509         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 510         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 511         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 512         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 513         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 514         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 515         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 516         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 517         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 518         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 519         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 520         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 521         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 522         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 523         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 524         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 525         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 526         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 527         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 528         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 529         {0xffff, 0xffffffff}
 530 };
 531
 532 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
 533         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 534         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 535         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 536         {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
 537         {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
 538         {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
 539         {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
 540         {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
 541         {0xc78, 0x73100001}, {0xc78, 0x72110001},
 542         {0xc78, 0x71120001}, {0xc78, 0x70130001},
 543         {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
 544         {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
 545         {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
 546         {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
 547         {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
 548         {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
 549         {0xc78, 0x63200001}, {0xc78, 0x62210001},
 550         {0xc78, 0x61220001}, {0xc78, 0x60230001},
 551         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 552         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 553         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 554         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 555         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 556         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 557         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 558         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 559         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 560         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 561         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 562         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 563         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 564         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 565         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 566         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 567         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 568         {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
 569         {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
 570         {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
 571         {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
 572         {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
 573         {0xc78, 0x73500001}, {0xc78, 0x72510001},
 574         {0xc78, 0x71520001}, {0xc78, 0x70530001},
 575         {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
 576         {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
 577         {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
 578         {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
 579         {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
 580         {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
 581         {0xc78, 0x63600001}, {0xc78, 0x62610001},
 582         {0xc78, 0x61620001}, {0xc78, 0x60630001},
 583         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 584         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 585         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 586         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 587         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 588         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 589         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 590         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 591         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 592         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 593         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 594         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 595         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 596         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 597         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 598         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 599         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 600         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 601         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 602         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 603         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 604         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 605         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 606         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 607         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 608         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 609         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 610         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 611         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 612         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 613         {0xffff, 0xffffffff}
 614 };
 615
 616 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
 617         {0x00, 0x00030159}, {0x01, 0x00031284},
 618         {0x02, 0x00098000}, {0x03, 0x00039c63},
 619         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 620         {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
 621         {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
 622         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 623         {0x19, 0x00000000}, {0x1a, 0x00030355},
 624         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 625         {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
 626         {0x1f, 0x00000000}, {0x20, 0x0000b614},
 627         {0x21, 0x0006c000}, {0x22, 0x00000000},
 628         {0x23, 0x00001558}, {0x24, 0x00000060},
 629         {0x25, 0x00000483}, {0x26, 0x0004f000},
 630         {0x27, 0x000ec7d9}, {0x28, 0x00057730},
 631         {0x29, 0x00004783}, {0x2a, 0x00000001},
 632         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 633         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 634         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 635         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 636         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 637         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 638         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 639         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 640         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 641         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 642         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 643         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 644         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 645         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 646         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 647         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 648         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 649         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 650         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 651         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 652         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 653         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 654         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 655         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 656         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 657         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 658         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 659         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 660         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 661         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 662         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 663         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 664         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 665         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 666         {0x10, 0x00000000}, {0x11, 0x00000000},
 667         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 668         {0x10, 0x0009000f}, {0x11, 0x00023100},
 669         {0x12, 0x00032000}, {0x12, 0x00071000},
 670         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 671         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 672         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 673         {0x13, 0x00018493}, {0x13, 0x0001429b},
 674         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 675         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 676         {0x13, 0x00000020}, {0x14, 0x0001944c},
 677         {0x14, 0x00059444}, {0x14, 0x0009944c},
 678         {0x14, 0x000d9444}, {0x15, 0x0000f474},
 679         {0x15, 0x0004f477}, {0x15, 0x0008f455},
 680         {0x15, 0x000cf455}, {0x16, 0x00000339},
 681         {0x16, 0x00040339}, {0x16, 0x00080339},
 682         {0x16, 0x000c0366}, {0x00, 0x00010159},
 683         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 684         {0xfe, 0x00000000}, {0x1f, 0x00000003},
 685         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 686         {0x1e, 0x00000247}, {0x1f, 0x00000000},
 687         {0x00, 0x00030159},
 688         {0xff, 0xffffffff}
 689 };
 690
 691 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
 692         {0x00, 0x00030159}, {0x01, 0x00031284},
 693         {0x02, 0x00098000}, {0x03, 0x00018c63},
 694         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 695         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 696         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 697         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 698         {0x19, 0x00000000}, {0x1a, 0x00010255},
 699         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 700         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
 701         {0x1f, 0x00080001}, {0x20, 0x0000b614},
 702         {0x21, 0x0006c000}, {0x22, 0x00000000},
 703         {0x23, 0x00001558}, {0x24, 0x00000060},
 704         {0x25, 0x00000483}, {0x26, 0x0004f000},
 705         {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
 706         {0x29, 0x00004783}, {0x2a, 0x00000001},
 707         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 708         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 709         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 710         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 711         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 712         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 713         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 714         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 715         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 716         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 717         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 718         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 719         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 720         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 721         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 722         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 723         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 724         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 725         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 726         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 727         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 728         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 729         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 730         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 731         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 732         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 733         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 734         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 735         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 736         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 737         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 738         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 739         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 740         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 741         {0x10, 0x00000000}, {0x11, 0x00000000},
 742         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 743         {0x10, 0x0009000f}, {0x11, 0x00023100},
 744         {0x12, 0x00032000}, {0x12, 0x00071000},
 745         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 746         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 747         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 748         {0x13, 0x00018493}, {0x13, 0x0001429b},
 749         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 750         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 751         {0x13, 0x00000020}, {0x14, 0x0001944c},
 752         {0x14, 0x00059444}, {0x14, 0x0009944c},
 753         {0x14, 0x000d9444}, {0x15, 0x0000f424},
 754         {0x15, 0x0004f424}, {0x15, 0x0008f424},
 755         {0x15, 0x000cf424}, {0x16, 0x000e0330},
 756         {0x16, 0x000a0330}, {0x16, 0x00060330},
 757         {0x16, 0x00020330}, {0x00, 0x00010159},
 758         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 759         {0xfe, 0x00000000}, {0x1f, 0x00080003},
 760         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 761         {0x1e, 0x00044457}, {0x1f, 0x00080000},
 762         {0x00, 0x00030159},
 763         {0xff, 0xffffffff}
 764 };
 765
 766 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
 767         {0x00, 0x00030159}, {0x01, 0x00031284},
 768         {0x02, 0x00098000}, {0x03, 0x00018c63},
 769         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 770         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 771         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 772         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 773         {0x12, 0x00032000}, {0x12, 0x00071000},
 774         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 775         {0x13, 0x000287af}, {0x13, 0x000244b7},
 776         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 777         {0x13, 0x00018493}, {0x13, 0x00014297},
 778         {0x13, 0x00010295}, {0x13, 0x0000c298},
 779         {0x13, 0x0000819c}, {0x13, 0x000040a8},
 780         {0x13, 0x0000001c}, {0x14, 0x0001944c},
 781         {0x14, 0x00059444}, {0x14, 0x0009944c},
 782         {0x14, 0x000d9444}, {0x15, 0x0000f424},
 783         {0x15, 0x0004f424}, {0x15, 0x0008f424},
 784         {0x15, 0x000cf424}, {0x16, 0x000e0330},
 785         {0x16, 0x000a0330}, {0x16, 0x00060330},
 786         {0x16, 0x00020330},
 787         {0xff, 0xffffffff}
 788 };
 789
 790 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
 791         {0x00, 0x00030159}, {0x01, 0x00031284},
 792         {0x02, 0x00098000}, {0x03, 0x00018c63},
 793         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 794         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 795         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 796         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 797         {0x19, 0x00000000}, {0x1a, 0x00010255},
 798         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 799         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
 800         {0x1f, 0x00080001}, {0x20, 0x0000b614},
 801         {0x21, 0x0006c000}, {0x22, 0x00000000},
 802         {0x23, 0x00001558}, {0x24, 0x00000060},
 803         {0x25, 0x00000483}, {0x26, 0x0004f000},
 804         {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
 805         {0x29, 0x00004783}, {0x2a, 0x00000001},
 806         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 807         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 808         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 809         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 810         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 811         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 812         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 813         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 814         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 815         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 816         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 817         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 818         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 819         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 820         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 821         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 822         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 823         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 824         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 825         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 826         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 827         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 828         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 829         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 830         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 831         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 832         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 833         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 834         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 835         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 836         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 837         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 838         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 839         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 840         {0x10, 0x00000000}, {0x11, 0x00000000},
 841         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 842         {0x10, 0x0009000f}, {0x11, 0x00023100},
 843         {0x12, 0x00032000}, {0x12, 0x00071000},
 844         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 845         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 846         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 847         {0x13, 0x00018493}, {0x13, 0x0001429b},
 848         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 849         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 850         {0x13, 0x00000020}, {0x14, 0x0001944c},
 851         {0x14, 0x00059444}, {0x14, 0x0009944c},
 852         {0x14, 0x000d9444}, {0x15, 0x0000f405},
 853         {0x15, 0x0004f405}, {0x15, 0x0008f405},
 854         {0x15, 0x000cf405}, {0x16, 0x000e0330},
 855         {0x16, 0x000a0330}, {0x16, 0x00060330},
 856         {0x16, 0x00020330}, {0x00, 0x00010159},
 857         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 858         {0xfe, 0x00000000}, {0x1f, 0x00080003},
 859         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 860         {0x1e, 0x00044457}, {0x1f, 0x00080000},
 861         {0x00, 0x00030159},
 862         {0xff, 0xffffffff}
 863 };
 864
 865 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
 866         {0x00, 0x00030159}, {0x01, 0x00031284},
 867         {0x02, 0x00098000}, {0x03, 0x00018c63},
 868         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 869         {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
 870         {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
 871         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 872         {0x19, 0x00000000}, {0x1a, 0x00000255},
 873         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 874         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
 875         {0x1f, 0x00080001}, {0x20, 0x0000b614},
 876         {0x21, 0x0006c000}, {0x22, 0x0000083c},
 877         {0x23, 0x00001558}, {0x24, 0x00000060},
 878         {0x25, 0x00000483}, {0x26, 0x0004f000},
 879         {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
 880         {0x29, 0x00004783}, {0x2a, 0x00000001},
 881         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 882         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 883         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 884         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 885         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 886         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 887         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 888         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 889         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 890         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 891         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 892         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 893         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 894         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 895         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 896         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 897         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 898         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 899         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 900         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 901         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 902         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 903         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 904         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 905         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 906         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 907         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 908         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 909         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 910         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 911         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 912         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 913         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 914         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 915         {0x10, 0x00000000}, {0x11, 0x00000000},
 916         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 917         {0x10, 0x0009000f}, {0x11, 0x00023100},
 918         {0x12, 0x000d8000}, {0x12, 0x00090000},
 919         {0x12, 0x00051000}, {0x12, 0x00012000},
 920         {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
 921         {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
 922         {0x13, 0x000183a4}, {0x13, 0x00014398},
 923         {0x13, 0x000101a4}, {0x13, 0x0000c198},
 924         {0x13, 0x000080a4}, {0x13, 0x00004098},
 925         {0x13, 0x00000000}, {0x14, 0x0001944c},
 926         {0x14, 0x00059444}, {0x14, 0x0009944c},
 927         {0x14, 0x000d9444}, {0x15, 0x0000f405},
 928         {0x15, 0x0004f405}, {0x15, 0x0008f405},
 929         {0x15, 0x000cf405}, {0x16, 0x000e0330},
 930         {0x16, 0x000a0330}, {0x16, 0x00060330},
 931         {0x16, 0x00020330}, {0x00, 0x00010159},
 932         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 933         {0xfe, 0x00000000}, {0x1f, 0x00080003},
 934         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 935         {0x1e, 0x00044457}, {0x1f, 0x00080000},
 936         {0x00, 0x00030159},
 937         {0xff, 0xffffffff}
 938 };
 939
 940 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
 941         {       /* RF_A */
 942                 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
 943                 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
 944                 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
 945                 .hspiread = REG_HSPI_XA_READBACK,
 946                 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
 947                 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
 948         },
 949         {       /* RF_B */
 950                 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
 951                 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
 952                 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
 953                 .hspiread = REG_HSPI_XB_READBACK,
 954                 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
 955                 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
 956         },
 957 };
 958
 959 static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
 960         REG_OFDM0_XA_RX_IQ_IMBALANCE,
 961         REG_OFDM0_XB_RX_IQ_IMBALANCE,
 962         REG_OFDM0_ENERGY_CCA_THRES,
 963         REG_OFDM0_AGCR_SSI_TABLE,
 964         REG_OFDM0_XA_TX_IQ_IMBALANCE,
 965         REG_OFDM0_XB_TX_IQ_IMBALANCE,
 966         REG_OFDM0_XC_TX_AFE,
 967         REG_OFDM0_XD_TX_AFE,
 968         REG_OFDM0_RX_IQ_EXT_ANTA
 969 };
 970
 971 static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
 972 {
 973         struct usb_device *udev = priv->udev;
 974         int len;
 975         u8 data;
 976
 977         mutex_lock(&priv->usb_buf_mutex);
 978         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
 979                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
 980                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
 981                               RTW_USB_CONTROL_MSG_TIMEOUT);
 982         data = priv->usb_buf.val8;
 983         mutex_unlock(&priv->usb_buf_mutex);
 984
 985         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
 986                 dev_info(&udev->dev, "%s(%04x)   = 0x%02x, len %i\n",
 987                          __func__, addr, data, len);
 988         return data;
 989 }
 990
 991 static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
 992 {
 993         struct usb_device *udev = priv->udev;
 994         int len;
 995         u16 data;
 996
 997         mutex_lock(&priv->usb_buf_mutex);
 998         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
 999                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1000                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
1001                               RTW_USB_CONTROL_MSG_TIMEOUT);
1002         data = le16_to_cpu(priv->usb_buf.val16);
1003         mutex_unlock(&priv->usb_buf_mutex);
1004
1005         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1006                 dev_info(&udev->dev, "%s(%04x)  = 0x%04x, len %i\n",
1007                          __func__, addr, data, len);
1008         return data;
1009 }
1010
1011 static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1012 {
1013         struct usb_device *udev = priv->udev;
1014         int len;
1015         u32 data;
1016
1017         mutex_lock(&priv->usb_buf_mutex);
1018         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1019                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1020                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
1021                               RTW_USB_CONTROL_MSG_TIMEOUT);
1022         data = le32_to_cpu(priv->usb_buf.val32);
1023         mutex_unlock(&priv->usb_buf_mutex);
1024
1025         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1026                 dev_info(&udev->dev, "%s(%04x)  = 0x%08x, len %i\n",
1027                          __func__, addr, data, len);
1028         return data;
1029 }
1030
1031 static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1032 {
1033         struct usb_device *udev = priv->udev;
1034         int ret;
1035
1036         mutex_lock(&priv->usb_buf_mutex);
1037         priv->usb_buf.val8 = val;
1038         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1039                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1040                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
1041                               RTW_USB_CONTROL_MSG_TIMEOUT);
1042
1043         mutex_unlock(&priv->usb_buf_mutex);
1044
1045         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1046                 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1047                          __func__, addr, val);
1048         return ret;
1049 }
1050
1051 static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1052 {
1053         struct usb_device *udev = priv->udev;
1054         int ret;
1055
1056         mutex_lock(&priv->usb_buf_mutex);
1057         priv->usb_buf.val16 = cpu_to_le16(val);
1058         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1059                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1060                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
1061                               RTW_USB_CONTROL_MSG_TIMEOUT);
1062         mutex_unlock(&priv->usb_buf_mutex);
1063
1064         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1065                 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1066                          __func__, addr, val);
1067         return ret;
1068 }
1069
1070 static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1071 {
1072         struct usb_device *udev = priv->udev;
1073         int ret;
1074
1075         mutex_lock(&priv->usb_buf_mutex);
1076         priv->usb_buf.val32 = cpu_to_le32(val);
1077         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1078                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1079                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
1080                               RTW_USB_CONTROL_MSG_TIMEOUT);
1081         mutex_unlock(&priv->usb_buf_mutex);
1082
1083         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1084                 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1085                          __func__, addr, val);
1086         return ret;
1087 }
1088
1089 static int
1090 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1091 {
1092         struct usb_device *udev = priv->udev;
1093         int blocksize = priv->fops->writeN_block_size;
1094         int ret, i, count, remainder;
1095
1096         count = len / blocksize;
1097         remainder = len % blocksize;
1098
1099         for (i = 0; i < count; i++) {
1100                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1101                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1102                                       addr, 0, buf, blocksize,
1103                                       RTW_USB_CONTROL_MSG_TIMEOUT);
1104                 if (ret != blocksize)
1105                         goto write_error;
1106
1107                 addr += blocksize;
1108                 buf += blocksize;
1109         }
1110
1111         if (remainder) {
1112                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1113                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1114                                       addr, 0, buf, remainder,
1115                                       RTW_USB_CONTROL_MSG_TIMEOUT);
1116                 if (ret != remainder)
1117                         goto write_error;
1118         }
1119
1120         return len;
1121
1122 write_error:
1123         dev_info(&udev->dev,
1124                  "%s: Failed to write block at addr: %04x size: %04x\n",
1125                  __func__, addr, blocksize);
1126         return -EAGAIN;
1127 }
1128
1129 static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1130                                enum rtl8xxxu_rfpath path, u8 reg)
1131 {
1132         u32 hssia, val32, retval;
1133
1134         hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1135         if (path != RF_A)
1136                 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1137         else
1138                 val32 = hssia;
1139
1140         val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1141         val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1142         val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1143         hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1144         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1145
1146         udelay(10);
1147
1148         rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1149         udelay(100);
1150
1151         hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1152         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1153         udelay(10);
1154
1155         val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1156         if (val32 & FPGA0_HSSI_PARM1_PI)
1157                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1158         else
1159                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1160
1161         retval &= 0xfffff;
1162
1163         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1164                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1165                          __func__, reg, retval);
1166         return retval;
1167 }
1168
1169 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1170                                 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1171 {
1172         int ret, retval;
1173         u32 dataaddr;
1174
1175         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1176                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1177                          __func__, reg, data);
1178
1179         data &= FPGA0_LSSI_PARM_DATA_MASK;
1180         dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1181
1182         /* Use XB for path B */
1183         ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1184         if (ret != sizeof(dataaddr))
1185                 retval = -EIO;
1186         else
1187                 retval = 0;
1188
1189         udelay(1);
1190
1191         return retval;
1192 }
1193
1194 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c)
1195 {
1196         struct device *dev = &priv->udev->dev;
1197         int mbox_nr, retry, retval = 0;
1198         int mbox_reg, mbox_ext_reg;
1199         u8 val8;
1200
1201         mutex_lock(&priv->h2c_mutex);
1202
1203         mbox_nr = priv->next_mbox;
1204         mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1205         mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);
1206
1207         /*
1208          * MBOX ready?
1209          */
1210         retry = 100;
1211         do {
1212                 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1213                 if (!(val8 & BIT(mbox_nr)))
1214                         break;
1215         } while (retry--);
1216
1217         if (!retry) {
1218                 dev_dbg(dev, "%s: Mailbox busy\n", __func__);
1219                 retval = -EBUSY;
1220                 goto error;
1221         }
1222
1223         /*
1224          * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1225          */
1226         if (h2c->cmd.cmd & H2C_EXT) {
1227                 rtl8xxxu_write16(priv, mbox_ext_reg,
1228                                  le16_to_cpu(h2c->raw.ext));
1229                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1230                         dev_info(dev, "H2C_EXT %04x\n",
1231                                  le16_to_cpu(h2c->raw.ext));
1232         }
1233         rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1234         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1235                 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1236
1237         priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1238
1239 error:
1240         mutex_unlock(&priv->h2c_mutex);
1241         return retval;
1242 }
1243
1244 static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1245 {
1246         u8 val8;
1247         u32 val32;
1248
1249         val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1250         val8 |= BIT(0) | BIT(3);
1251         rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1252
1253         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1254         val32 &= ~(BIT(4) | BIT(5));
1255         val32 |= BIT(3);
1256         if (priv->rf_paths == 2) {
1257                 val32 &= ~(BIT(20) | BIT(21));
1258                 val32 |= BIT(19);
1259         }
1260         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1261
1262         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1263         val32 &= ~OFDM_RF_PATH_TX_MASK;
1264         if (priv->tx_paths == 2)
1265                 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1266         else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1267                 val32 |= OFDM_RF_PATH_TX_B;
1268         else
1269                 val32 |= OFDM_RF_PATH_TX_A;
1270         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1271
1272         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1273         val32 &= ~FPGA_RF_MODE_JAPAN;
1274         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1275
1276         if (priv->rf_paths == 2)
1277                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1278         else
1279                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1280
1281         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1282         if (priv->rf_paths == 2)
1283                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1284
1285         rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1286 }
1287
1288 static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1289 {
1290         u8 sps0;
1291         u32 val32;
1292
1293         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1294
1295         sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1296
1297         /* RF RX code for preamble power saving */
1298         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1299         val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1300         if (priv->rf_paths == 2)
1301                 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1302         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1303
1304         /* Disable TX for four paths */
1305         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1306         val32 &= ~OFDM_RF_PATH_TX_MASK;
1307         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1308
1309         /* Enable power saving */
1310         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1311         val32 |= FPGA_RF_MODE_JAPAN;
1312         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1313
1314         /* AFE control register to power down bits [30:22] */
1315         if (priv->rf_paths == 2)
1316                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1317         else
1318                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1319
1320         /* Power down RF module */
1321         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1322         if (priv->rf_paths == 2)
1323                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1324
1325         sps0 &= ~(BIT(0) | BIT(3));
1326         rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1327 }
1328
1329
1330 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1331 {
1332         u8 val8;
1333
1334         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1335         val8 &= ~BIT(6);
1336         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1337
1338         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1339         val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1340         val8 &= ~BIT(0);
1341         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1342 }
1343
1344
1345 /*
1346  * The rtl8723a has 3 channel groups for it's efuse settings. It only
1347  * supports the 2.4GHz band, so channels 1 - 14:
1348  *  group 0: channels 1 - 3
1349  *  group 1: channels 4 - 9
1350  *  group 2: channels 10 - 14
1351  *
1352  * Note: We index from 0 in the code
1353  */
1354 static int rtl8723a_channel_to_group(int channel)
1355 {
1356         int group;
1357
1358         if (channel < 4)
1359                 group = 0;
1360         else if (channel < 10)
1361                 group = 1;
1362         else
1363                 group = 2;
1364
1365         return group;
1366 }
1367
1368 static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1369 {
1370         struct rtl8xxxu_priv *priv = hw->priv;
1371         u32 val32, rsr;
1372         u8 val8, opmode;
1373         bool ht = true;
1374         int sec_ch_above, channel;
1375         int i;
1376
1377         opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1378         rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1379         channel = hw->conf.chandef.chan->hw_value;
1380
1381         switch (hw->conf.chandef.width) {
1382         case NL80211_CHAN_WIDTH_20_NOHT:
1383                 ht = false;
1384         case NL80211_CHAN_WIDTH_20:
1385                 opmode |= BW_OPMODE_20MHZ;
1386                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1387
1388                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1389                 val32 &= ~FPGA_RF_MODE;
1390                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1391
1392                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1393                 val32 &= ~FPGA_RF_MODE;
1394                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1395
1396                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1397                 val32 |= FPGA0_ANALOG2_20MHZ;
1398                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1399                 break;
1400         case NL80211_CHAN_WIDTH_40:
1401                 if (hw->conf.chandef.center_freq1 >
1402                     hw->conf.chandef.chan->center_freq) {
1403                         sec_ch_above = 1;
1404                         channel += 2;
1405                 } else {
1406                         sec_ch_above = 0;
1407                         channel -= 2;
1408                 }
1409
1410                 opmode &= ~BW_OPMODE_20MHZ;
1411                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1412                 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1413                 if (sec_ch_above)
1414                         rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1415                 else
1416                         rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1417                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1418
1419                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1420                 val32 |= FPGA_RF_MODE;
1421                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1422
1423                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1424                 val32 |= FPGA_RF_MODE;
1425                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1426
1427                 /*
1428                  * Set Control channel to upper or lower. These settings
1429                  * are required only for 40MHz
1430                  */
1431                 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1432                 val32 &= ~CCK0_SIDEBAND;
1433                 if (!sec_ch_above)
1434                         val32 |= CCK0_SIDEBAND;
1435                 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1436
1437                 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1438                 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1439                 if (sec_ch_above)
1440                         val32 |= OFDM_LSTF_PRIME_CH_LOW;
1441                 else
1442                         val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1443                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1444
1445                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1446                 val32 &= ~FPGA0_ANALOG2_20MHZ;
1447                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1448
1449                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1450                 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1451                 if (sec_ch_above)
1452                         val32 |= FPGA0_PS_UPPER_CHANNEL;
1453                 else
1454                         val32 |= FPGA0_PS_LOWER_CHANNEL;
1455                 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1456                 break;
1457
1458         default:
1459                 break;
1460         }
1461
1462         for (i = RF_A; i < priv->rf_paths; i++) {
1463                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1464                 val32 &= ~MODE_AG_CHANNEL_MASK;
1465                 val32 |= channel;
1466                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1467         }
1468
1469         if (ht)
1470                 val8 = 0x0e;
1471         else
1472                 val8 = 0x0a;
1473
1474         rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1475         rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1476
1477         rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1478         rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1479
1480         for (i = RF_A; i < priv->rf_paths; i++) {
1481                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1482                 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1483                         val32 &= ~MODE_AG_CHANNEL_20MHZ;
1484                 else
1485                         val32 |= MODE_AG_CHANNEL_20MHZ;
1486                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1487         }
1488 }
1489
1490 static void
1491 rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1492 {
1493         u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1494         u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1495         u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1496         u8 val8;
1497         int group, i;
1498
1499         group = rtl8723a_channel_to_group(channel);
1500
1501         cck[0] = priv->cck_tx_power_index_A[group];
1502         cck[1] = priv->cck_tx_power_index_B[group];
1503
1504         ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1505         ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1506
1507         ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1508         ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1509
1510         mcsbase[0] = ofdm[0];
1511         mcsbase[1] = ofdm[1];
1512         if (!ht40) {
1513                 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1514                 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1515         }
1516
1517         if (priv->tx_paths > 1) {
1518                 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1519                         ofdm[0] -=  priv->ht40_2s_tx_power_index_diff[group].a;
1520                 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1521                         ofdm[1] -=  priv->ht40_2s_tx_power_index_diff[group].b;
1522         }
1523
1524         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1525                 dev_info(&priv->udev->dev,
1526                          "%s: Setting TX power CCK A: %02x, "
1527                          "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1528                          __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1529
1530         for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1531                 if (cck[i] > RF6052_MAX_TX_PWR)
1532                         cck[i] = RF6052_MAX_TX_PWR;
1533                 if (ofdm[i] > RF6052_MAX_TX_PWR)
1534                         ofdm[i] = RF6052_MAX_TX_PWR;
1535         }
1536
1537         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1538         val32 &= 0xffff00ff;
1539         val32 |= (cck[0] << 8);
1540         rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1541
1542         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1543         val32 &= 0xff;
1544         val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1545         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1546
1547         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1548         val32 &= 0xffffff00;
1549         val32 |= cck[1];
1550         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1551
1552         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1553         val32 &= 0xff;
1554         val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1555         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1556
1557         ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1558                 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1559         ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1560                 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1561         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
1562         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
1563
1564         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
1565         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
1566
1567         mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1568                 mcsbase[0] << 16 | mcsbase[0] << 24;
1569         mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1570                 mcsbase[1] << 16 | mcsbase[1] << 24;
1571
1572         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
1573         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
1574
1575         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
1576         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
1577
1578         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
1579         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
1580
1581         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
1582         for (i = 0; i < 3; i++) {
1583                 if (i != 2)
1584                         val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1585                 else
1586                         val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1587                 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1588         }
1589         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
1590         for (i = 0; i < 3; i++) {
1591                 if (i != 2)
1592                         val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1593                 else
1594                         val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1595                 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1596         }
1597 }
1598
1599 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1600                                   enum nl80211_iftype linktype)
1601 {
1602         u16 val8;
1603
1604         val8 = rtl8xxxu_read16(priv, REG_MSR);
1605         val8 &= ~MSR_LINKTYPE_MASK;
1606
1607         switch (linktype) {
1608         case NL80211_IFTYPE_UNSPECIFIED:
1609                 val8 |= MSR_LINKTYPE_NONE;
1610                 break;
1611         case NL80211_IFTYPE_ADHOC:
1612                 val8 |= MSR_LINKTYPE_ADHOC;
1613                 break;
1614         case NL80211_IFTYPE_STATION:
1615                 val8 |= MSR_LINKTYPE_STATION;
1616                 break;
1617         case NL80211_IFTYPE_AP:
1618                 val8 |= MSR_LINKTYPE_AP;
1619                 break;
1620         default:
1621                 goto out;
1622         }
1623
1624         rtl8xxxu_write8(priv, REG_MSR, val8);
1625 out:
1626         return;
1627 }
1628
1629 static void
1630 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1631 {
1632         u16 val16;
1633
1634         val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1635                  RETRY_LIMIT_SHORT_MASK) |
1636                 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1637                  RETRY_LIMIT_LONG_MASK);
1638
1639         rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1640 }
1641
1642 static void
1643 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1644 {
1645         u16 val16;
1646
1647         val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1648                 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1649
1650         rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1651 }
1652
1653 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1654 {
1655         struct device *dev = &priv->udev->dev;
1656         char *cut;
1657
1658         switch (priv->chip_cut) {
1659         case 0:
1660                 cut = "A";
1661                 break;
1662         case 1:
1663                 cut = "B";
1664                 break;
1665         default:
1666                 cut = "unknown";
1667         }
1668
1669         dev_info(dev,
1670                  "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
1671                  priv->chip_name, cut, priv->vendor_umc ? "UMC" : "TSMC",
1672                  priv->tx_paths, priv->rx_paths, priv->ep_tx_count,
1673                  priv->has_wifi, priv->has_bluetooth, priv->has_gps,
1674                  priv->hi_pa);
1675
1676         dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1677 }
1678
1679 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
1680 {
1681         struct device *dev = &priv->udev->dev;
1682         u32 val32, bonding;
1683         u16 val16;
1684
1685         val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1686         priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
1687                 SYS_CFG_CHIP_VERSION_SHIFT;
1688         if (val32 & SYS_CFG_TRP_VAUX_EN) {
1689                 dev_info(dev, "Unsupported test chip\n");
1690                 return -ENOTSUPP;
1691         }
1692
1693         if (val32 & SYS_CFG_BT_FUNC) {
1694                 sprintf(priv->chip_name, "8723AU");
1695                 priv->rf_paths = 1;
1696                 priv->rx_paths = 1;
1697                 priv->tx_paths = 1;
1698                 priv->rtlchip = 0x8723a;
1699
1700                 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
1701                 if (val32 & MULTI_WIFI_FUNC_EN)
1702                         priv->has_wifi = 1;
1703                 if (val32 & MULTI_BT_FUNC_EN)
1704                         priv->has_bluetooth = 1;
1705                 if (val32 & MULTI_GPS_FUNC_EN)
1706                         priv->has_gps = 1;
1707         } else if (val32 & SYS_CFG_TYPE_ID) {
1708                 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
1709                 bonding &= HPON_FSM_BONDING_MASK;
1710                 if (bonding == HPON_FSM_BONDING_1T2R) {
1711                         sprintf(priv->chip_name, "8191CU");
1712                         priv->rf_paths = 2;
1713                         priv->rx_paths = 2;
1714                         priv->tx_paths = 1;
1715                         priv->rtlchip = 0x8191c;
1716                 } else {
1717                         sprintf(priv->chip_name, "8192CU");
1718                         priv->rf_paths = 2;
1719                         priv->rx_paths = 2;
1720                         priv->tx_paths = 2;
1721                         priv->rtlchip = 0x8192c;
1722                 }
1723                 priv->has_wifi = 1;
1724         } else {
1725                 sprintf(priv->chip_name, "8188CU");
1726                 priv->rf_paths = 1;
1727                 priv->rx_paths = 1;
1728                 priv->tx_paths = 1;
1729                 priv->rtlchip = 0x8188c;
1730                 priv->has_wifi = 1;
1731         }
1732
1733         if (val32 & SYS_CFG_VENDOR_ID)
1734                 priv->vendor_umc = 1;
1735
1736         val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
1737         priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
1738
1739         val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
1740         if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
1741                 priv->ep_tx_high_queue = 1;
1742                 priv->ep_tx_count++;
1743         }
1744
1745         if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
1746                 priv->ep_tx_normal_queue = 1;
1747                 priv->ep_tx_count++;
1748         }
1749
1750         if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
1751                 priv->ep_tx_low_queue = 1;
1752                 priv->ep_tx_count++;
1753         }
1754
1755         /*
1756          * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
1757          */
1758         if (!priv->ep_tx_count) {
1759                 switch (priv->nr_out_eps) {
1760                 case 3:
1761                         priv->ep_tx_low_queue = 1;
1762                         priv->ep_tx_count++;
1763                 case 2:
1764                         priv->ep_tx_normal_queue = 1;
1765                         priv->ep_tx_count++;
1766                 case 1:
1767                         priv->ep_tx_high_queue = 1;
1768                         priv->ep_tx_count++;
1769                         break;
1770                 default:
1771                         dev_info(dev, "Unsupported USB TX end-points\n");
1772                         return -ENOTSUPP;
1773                 }
1774         }
1775
1776         return 0;
1777 }
1778
1779 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
1780 {
1781         if (priv->efuse_wifi.efuse8723.rtl_id != cpu_to_le16(0x8129))
1782                 return -EINVAL;
1783
1784         ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8723.mac_addr);
1785
1786         memcpy(priv->cck_tx_power_index_A,
1787                priv->efuse_wifi.efuse8723.cck_tx_power_index_A,
1788                sizeof(priv->cck_tx_power_index_A));
1789         memcpy(priv->cck_tx_power_index_B,
1790                priv->efuse_wifi.efuse8723.cck_tx_power_index_B,
1791                sizeof(priv->cck_tx_power_index_B));
1792
1793         memcpy(priv->ht40_1s_tx_power_index_A,
1794                priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_A,
1795                sizeof(priv->ht40_1s_tx_power_index_A));
1796         memcpy(priv->ht40_1s_tx_power_index_B,
1797                priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_B,
1798                sizeof(priv->ht40_1s_tx_power_index_B));
1799
1800         memcpy(priv->ht20_tx_power_index_diff,
1801                priv->efuse_wifi.efuse8723.ht20_tx_power_index_diff,
1802                sizeof(priv->ht20_tx_power_index_diff));
1803         memcpy(priv->ofdm_tx_power_index_diff,
1804                priv->efuse_wifi.efuse8723.ofdm_tx_power_index_diff,
1805                sizeof(priv->ofdm_tx_power_index_diff));
1806
1807         memcpy(priv->ht40_max_power_offset,
1808                priv->efuse_wifi.efuse8723.ht40_max_power_offset,
1809                sizeof(priv->ht40_max_power_offset));
1810         memcpy(priv->ht20_max_power_offset,
1811                priv->efuse_wifi.efuse8723.ht20_max_power_offset,
1812                sizeof(priv->ht20_max_power_offset));
1813
1814         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
1815                  priv->efuse_wifi.efuse8723.vendor_name);
1816         dev_info(&priv->udev->dev, "Product: %.41s\n",
1817                  priv->efuse_wifi.efuse8723.device_name);
1818         return 0;
1819 }
1820
1821 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
1822 {
1823         int i;
1824
1825         if (priv->efuse_wifi.efuse8192.rtl_id != cpu_to_le16(0x8129))
1826                 return -EINVAL;
1827
1828         ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8192.mac_addr);
1829
1830         memcpy(priv->cck_tx_power_index_A,
1831                priv->efuse_wifi.efuse8192.cck_tx_power_index_A,
1832                sizeof(priv->cck_tx_power_index_A));
1833         memcpy(priv->cck_tx_power_index_B,
1834                priv->efuse_wifi.efuse8192.cck_tx_power_index_B,
1835                sizeof(priv->cck_tx_power_index_B));
1836
1837         memcpy(priv->ht40_1s_tx_power_index_A,
1838                priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_A,
1839                sizeof(priv->ht40_1s_tx_power_index_A));
1840         memcpy(priv->ht40_1s_tx_power_index_B,
1841                priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_B,
1842                sizeof(priv->ht40_1s_tx_power_index_B));
1843         memcpy(priv->ht40_2s_tx_power_index_diff,
1844                priv->efuse_wifi.efuse8192.ht40_2s_tx_power_index_diff,
1845                sizeof(priv->ht40_2s_tx_power_index_diff));
1846
1847         memcpy(priv->ht20_tx_power_index_diff,
1848                priv->efuse_wifi.efuse8192.ht20_tx_power_index_diff,
1849                sizeof(priv->ht20_tx_power_index_diff));
1850         memcpy(priv->ofdm_tx_power_index_diff,
1851                priv->efuse_wifi.efuse8192.ofdm_tx_power_index_diff,
1852                sizeof(priv->ofdm_tx_power_index_diff));
1853
1854         memcpy(priv->ht40_max_power_offset,
1855                priv->efuse_wifi.efuse8192.ht40_max_power_offset,
1856                sizeof(priv->ht40_max_power_offset));
1857         memcpy(priv->ht20_max_power_offset,
1858                priv->efuse_wifi.efuse8192.ht20_max_power_offset,
1859                sizeof(priv->ht20_max_power_offset));
1860
1861         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
1862                  priv->efuse_wifi.efuse8192.vendor_name);
1863         dev_info(&priv->udev->dev, "Product: %.20s\n",
1864                  priv->efuse_wifi.efuse8192.device_name);
1865
1866         if (priv->efuse_wifi.efuse8192.rf_regulatory & 0x20) {
1867                 sprintf(priv->chip_name, "8188RU");
1868                 priv->hi_pa = 1;
1869         }
1870
1871         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
1872                 unsigned char *raw = priv->efuse_wifi.raw;
1873
1874                 dev_info(&priv->udev->dev,
1875                          "%s: dumping efuse (0x%02zx bytes):\n",
1876                          __func__, sizeof(struct rtl8192cu_efuse));
1877                 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
1878                         dev_info(&priv->udev->dev, "%02x: "
1879                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
1880                                  raw[i], raw[i + 1], raw[i + 2],
1881                                  raw[i + 3], raw[i + 4], raw[i + 5],
1882                                  raw[i + 6], raw[i + 7]);
1883                 }
1884         }
1885         return 0;
1886 }
1887
1888 static int
1889 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
1890 {
1891         int i;
1892         u8 val8;
1893         u32 val32;
1894
1895         /* Write Address */
1896         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
1897         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
1898         val8 &= 0xfc;
1899         val8 |= (offset >> 8) & 0x03;
1900         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
1901
1902         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
1903         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
1904
1905         /* Poll for data read */
1906         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1907         for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
1908                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1909                 if (val32 & BIT(31))
1910                         break;
1911         }
1912
1913         if (i == RTL8XXXU_MAX_REG_POLL)
1914                 return -EIO;
1915
1916         udelay(50);
1917         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1918
1919         *data = val32 & 0xff;
1920         return 0;
1921 }
1922
1923 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
1924 {
1925         struct device *dev = &priv->udev->dev;
1926         int i, ret = 0;
1927         u8 val8, word_mask, header, extheader;
1928         u16 val16, efuse_addr, offset;
1929         u32 val32;
1930
1931         val16 = rtl8xxxu_read16(priv, REG_9346CR);
1932         if (val16 & EEPROM_ENABLE)
1933                 priv->has_eeprom = 1;
1934         if (val16 & EEPROM_BOOT)
1935                 priv->boot_eeprom = 1;
1936
1937         val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
1938         val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
1939         rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
1940
1941         dev_dbg(dev, "Booting from %s\n",
1942                 priv->boot_eeprom ? "EEPROM" : "EFUSE");
1943
1944         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
1945
1946         /*  1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
1947         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
1948         if (!(val16 & SYS_ISO_PWC_EV12V)) {
1949                 val16 |= SYS_ISO_PWC_EV12V;
1950                 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
1951         }
1952         /*  Reset: 0x0000[28], default valid */
1953         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1954         if (!(val16 & SYS_FUNC_ELDR)) {
1955                 val16 |= SYS_FUNC_ELDR;
1956                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1957         }
1958
1959         /*
1960          * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
1961          */
1962         val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
1963         if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
1964                 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
1965                 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
1966         }
1967
1968         /* Default value is 0xff */
1969         memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN_8723A);
1970
1971         efuse_addr = 0;
1972         while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
1973                 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
1974                 if (ret || header == 0xff)
1975                         goto exit;
1976
1977                 if ((header & 0x1f) == 0x0f) {  /* extended header */
1978                         offset = (header & 0xe0) >> 5;
1979
1980                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
1981                                                    &extheader);
1982                         if (ret)
1983                                 goto exit;
1984                         /* All words disabled */
1985                         if ((extheader & 0x0f) == 0x0f)
1986                                 continue;
1987
1988                         offset |= ((extheader & 0xf0) >> 1);
1989                         word_mask = extheader & 0x0f;
1990                 } else {
1991                         offset = (header >> 4) & 0x0f;
1992                         word_mask = header & 0x0f;
1993                 }
1994
1995                 if (offset < EFUSE_MAX_SECTION_8723A) {
1996                         u16 map_addr;
1997                         /* Get word enable value from PG header */
1998
1999                         /* We have 8 bits to indicate validity */
2000                         map_addr = offset * 8;
2001                         if (map_addr >= EFUSE_MAP_LEN_8723A) {
2002                                 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2003                                          "efuse corrupt!\n",
2004                                          __func__, map_addr);
2005                                 ret = -EINVAL;
2006                                 goto exit;
2007                         }
2008                         for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2009                                 /* Check word enable condition in the section */
2010                                 if (!(word_mask & BIT(i))) {
2011                                         ret = rtl8xxxu_read_efuse8(priv,
2012                                                                    efuse_addr++,
2013                                                                    &val8);
2014                                         if (ret)
2015                                                 goto exit;
2016                                         priv->efuse_wifi.raw[map_addr++] = val8;
2017
2018                                         ret = rtl8xxxu_read_efuse8(priv,
2019                                                                    efuse_addr++,
2020                                                                    &val8);
2021                                         if (ret)
2022                                                 goto exit;
2023                                         priv->efuse_wifi.raw[map_addr++] = val8;
2024                                 } else
2025                                         map_addr += 2;
2026                         }
2027                 } else {
2028                         dev_warn(dev,
2029                                  "%s: Illegal offset (%04x), efuse corrupt!\n",
2030                                  __func__, offset);
2031                         ret = -EINVAL;
2032                         goto exit;
2033                 }
2034         }
2035
2036 exit:
2037         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2038
2039         return ret;
2040 }
2041
2042 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2043 {
2044         struct device *dev = &priv->udev->dev;
2045         int ret = 0, i;
2046         u32 val32;
2047
2048         /* Poll checksum report */
2049         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2050                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2051                 if (val32 & MCU_FW_DL_CSUM_REPORT)
2052                         break;
2053         }
2054
2055         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2056                 dev_warn(dev, "Firmware checksum poll timed out\n");
2057                 ret = -EAGAIN;
2058                 goto exit;
2059         }
2060
2061         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2062         val32 |= MCU_FW_DL_READY;
2063         val32 &= ~MCU_WINT_INIT_READY;
2064         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2065
2066         /* Wait for firmware to become ready */
2067         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2068                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2069                 if (val32 & MCU_WINT_INIT_READY)
2070                         break;
2071
2072                 udelay(100);
2073         }
2074
2075         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2076                 dev_warn(dev, "Firmware failed to start\n");
2077                 ret = -EAGAIN;
2078                 goto exit;
2079         }
2080
2081 exit:
2082         return ret;
2083 }
2084
2085 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2086 {
2087         int pages, remainder, i, ret;
2088         u8 val8;
2089         u16 val16;
2090         u32 val32;
2091         u8 *fwptr;
2092
2093         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2094         val8 |= 4;
2095         rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2096
2097         /* 8051 enable */
2098         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2099         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16 | SYS_FUNC_CPU_ENABLE);
2100
2101         /* MCU firmware download enable */
2102         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2103         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8 | MCU_FW_DL_ENABLE);
2104
2105         /* 8051 reset */
2106         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2107         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32 & ~BIT(19));
2108
2109         /* Reset firmware download checksum */
2110         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2111         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8 | MCU_FW_DL_CSUM_REPORT);
2112
2113         pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2114         remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2115
2116         fwptr = priv->fw_data->data;
2117
2118         for (i = 0; i < pages; i++) {
2119                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2120                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8 | i);
2121
2122                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2123                                       fwptr, RTL_FW_PAGE_SIZE);
2124                 if (ret != RTL_FW_PAGE_SIZE) {
2125                         ret = -EAGAIN;
2126                         goto fw_abort;
2127                 }
2128
2129                 fwptr += RTL_FW_PAGE_SIZE;
2130         }
2131
2132         if (remainder) {
2133                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2134                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8 | i);
2135                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2136                                       fwptr, remainder);
2137                 if (ret != remainder) {
2138                         ret = -EAGAIN;
2139                         goto fw_abort;
2140                 }
2141         }
2142
2143         ret = 0;
2144 fw_abort:
2145         /* MCU firmware download disable */
2146         val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2147         rtl8xxxu_write16(priv, REG_MCU_FW_DL,
2148                          val16 & (~MCU_FW_DL_ENABLE & 0xff));
2149
2150         return ret;
2151 }
2152
2153 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2154 {
2155         struct device *dev = &priv->udev->dev;
2156         const struct firmware *fw;
2157         int ret = 0;
2158         u16 signature;
2159
2160         dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2161         if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2162                 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2163                 ret = -EAGAIN;
2164                 goto exit;
2165         }
2166         if (!fw) {
2167                 dev_warn(dev, "Firmware data not available\n");
2168                 ret = -EINVAL;
2169                 goto exit;
2170         }
2171
2172         priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2173         priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2174
2175         signature = le16_to_cpu(priv->fw_data->signature);
2176         switch (signature & 0xfff0) {
2177         case 0x92c0:
2178         case 0x88c0:
2179         case 0x2300:
2180                 break;
2181         default:
2182                 ret = -EINVAL;
2183                 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2184                          __func__, signature);
2185         }
2186
2187         dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2188                  le16_to_cpu(priv->fw_data->major_version),
2189                  priv->fw_data->minor_version, signature);
2190
2191 exit:
2192         release_firmware(fw);
2193         return ret;
2194 }
2195
2196 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2197 {
2198         char *fw_name;
2199         int ret;
2200
2201         switch (priv->chip_cut) {
2202         case 0:
2203                 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2204                 break;
2205         case 1:
2206                 if (priv->enable_bluetooth)
2207                         fw_name = "rtlwifi/rtl8723aufw_B.bin";
2208                 else
2209                         fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2210
2211                 break;
2212         default:
2213                 return -EINVAL;
2214         }
2215
2216         ret = rtl8xxxu_load_firmware(priv, fw_name);
2217         return ret;
2218 }
2219
2220 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2221 {
2222         char *fw_name;
2223         int ret;
2224
2225         if (!priv->vendor_umc)
2226                 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2227         else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2228                 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2229         else
2230                 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2231
2232         ret = rtl8xxxu_load_firmware(priv, fw_name);
2233
2234         return ret;
2235 }
2236
2237 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2238 {
2239         u16 val16;
2240         int i = 100;
2241
2242         /* Inform 8051 to perform reset */
2243         rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2244
2245         for (i = 100; i > 0; i--) {
2246                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2247
2248                 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2249                         dev_dbg(&priv->udev->dev,
2250                                 "%s: Firmware self reset success!\n", __func__);
2251                         break;
2252                 }
2253                 udelay(50);
2254         }
2255
2256         if (!i) {
2257                 /* Force firmware reset */
2258                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2259                 val16 &= ~SYS_FUNC_CPU_ENABLE;
2260                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2261         }
2262 }
2263
2264 static int
2265 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
2266 {
2267         int i, ret;
2268         u16 reg;
2269         u8 val;
2270
2271         for (i = 0; ; i++) {
2272                 reg = array[i].reg;
2273                 val = array[i].val;
2274
2275                 if (reg == 0xffff && val == 0xff)
2276                         break;
2277
2278                 ret = rtl8xxxu_write8(priv, reg, val);
2279                 if (ret != 1) {
2280                         dev_warn(&priv->udev->dev,
2281                                  "Failed to initialize MAC\n");
2282                         return -EAGAIN;
2283                 }
2284         }
2285
2286         rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2287
2288         return 0;
2289 }
2290
2291 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2292                                   struct rtl8xxxu_reg32val *array)
2293 {
2294         int i, ret;
2295         u16 reg;
2296         u32 val;
2297
2298         for (i = 0; ; i++) {
2299                 reg = array[i].reg;
2300                 val = array[i].val;
2301
2302                 if (reg == 0xffff && val == 0xffffffff)
2303                         break;
2304
2305                 ret = rtl8xxxu_write32(priv, reg, val);
2306                 if (ret != sizeof(val)) {
2307                         dev_warn(&priv->udev->dev,
2308                                  "Failed to initialize PHY\n");
2309                         return -EAGAIN;
2310                 }
2311                 udelay(1);
2312         }
2313
2314         return 0;
2315 }
2316
2317 /*
2318  * Most of this is black magic retrieved from the old rtl8723au driver
2319  */
2320 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2321 {
2322         u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2323         u32 val32;
2324
2325         /*
2326          * Todo: The vendor driver maintains a table of PHY register
2327          *       addresses, which is initialized here. Do we need this?
2328          */
2329
2330         val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2331         udelay(2);
2332         val8 |= AFE_PLL_320_ENABLE;
2333         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2334         udelay(2);
2335
2336         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2337         udelay(2);
2338
2339         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
2340         val8 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2341         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
2342
2343         /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
2344         val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2345         val32 &= ~AFE_XTAL_RF_GATE;
2346         if (priv->has_bluetooth)
2347                 val32 &= ~AFE_XTAL_BT_GATE;
2348         rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2349
2350         /* 6. 0x1f[7:0] = 0x07 */
2351         val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2352         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2353
2354         if (priv->hi_pa)
2355                 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2356         else if (priv->tx_paths == 2)
2357                 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2358         else
2359                 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2360
2361
2362         if (priv->rtlchip == 0x8188c && priv->hi_pa &&
2363             priv->vendor_umc && priv->chip_cut == 1)
2364                 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2365
2366         if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2367                 /*
2368                  * For 1T2R boards, patch the registers.
2369                  *
2370                  * It looks like 8191/2 1T2R boards use path B for TX
2371                  */
2372                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2373                 val32 &= ~(BIT(0) | BIT(1));
2374                 val32 |= BIT(1);
2375                 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2376
2377                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2378                 val32 &= ~0x300033;
2379                 val32 |= 0x200022;
2380                 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2381
2382                 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2383                 val32 &= 0xff000000;
2384                 val32 |= 0x45000000;
2385                 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2386
2387                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2388                 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2389                 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2390                           OFDM_RF_PATH_TX_B);
2391                 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2392
2393                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2394                 val32 &= ~(BIT(4) | BIT(5));
2395                 val32 |= BIT(4);
2396                 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2397
2398                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2399                 val32 &= ~(BIT(27) | BIT(26));
2400                 val32 |= BIT(27);
2401                 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2402
2403                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2404                 val32 &= ~(BIT(27) | BIT(26));
2405                 val32 |= BIT(27);
2406                 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2407
2408                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2409                 val32 &= ~(BIT(27) | BIT(26));
2410                 val32 |= BIT(27);
2411                 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2412
2413                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2414                 val32 &= ~(BIT(27) | BIT(26));
2415                 val32 |= BIT(27);
2416                 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2417
2418                 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2419                 val32 &= ~(BIT(27) | BIT(26));
2420                 val32 |= BIT(27);
2421                 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2422         }
2423
2424         if (priv->hi_pa)
2425                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2426         else
2427                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2428
2429         if (priv->rtlchip == 0x8723a &&
2430             priv->efuse_wifi.efuse8723.version >= 0x01) {
2431                 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
2432
2433                 val8 = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2434                 val32 &= 0xff000fff;
2435                 val32 |= ((val8 | (val8 << 6)) << 12);
2436
2437                 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
2438         }
2439
2440         ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2441         ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2442         ldohci12 = 0x57;
2443         lpldo = 1;
2444         val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2445
2446         rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2447
2448         return 0;
2449 }
2450
2451 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2452                                  struct rtl8xxxu_rfregval *array,
2453                                  enum rtl8xxxu_rfpath path)
2454 {
2455         int i, ret;
2456         u8 reg;
2457         u32 val;
2458
2459         for (i = 0; ; i++) {
2460                 reg = array[i].reg;
2461                 val = array[i].val;
2462
2463                 if (reg == 0xff && val == 0xffffffff)
2464                         break;
2465
2466                 switch (reg) {
2467                 case 0xfe:
2468                         msleep(50);
2469                         continue;
2470                 case 0xfd:
2471                         mdelay(5);
2472                         continue;
2473                 case 0xfc:
2474                         mdelay(1);
2475                         continue;
2476                 case 0xfb:
2477                         udelay(50);
2478                         continue;
2479                 case 0xfa:
2480                         udelay(5);
2481                         continue;
2482                 case 0xf9:
2483                         udelay(1);
2484                         continue;
2485                 }
2486
2487                 reg &= 0x3f;
2488
2489                 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
2490                 if (ret) {
2491                         dev_warn(&priv->udev->dev,
2492                                  "Failed to initialize RF\n");
2493                         return -EAGAIN;
2494                 }
2495                 udelay(1);
2496         }
2497
2498         return 0;
2499 }
2500
2501 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2502                                 struct rtl8xxxu_rfregval *table,
2503                                 enum rtl8xxxu_rfpath path)
2504 {
2505         u32 val32;
2506         u16 val16, rfsi_rfenv;
2507         u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
2508
2509         switch (path) {
2510         case RF_A:
2511                 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
2512                 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
2513                 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
2514                 break;
2515         case RF_B:
2516                 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
2517                 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
2518                 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
2519                 break;
2520         default:
2521                 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
2522                         __func__, path + 'A');
2523                 return -EINVAL;
2524         }
2525         /* For path B, use XB */
2526         rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
2527         rfsi_rfenv &= FPGA0_RF_RFENV;
2528
2529         /*
2530          * These two we might be able to optimize into one
2531          */
2532         val32 = rtl8xxxu_read32(priv, reg_int_oe);
2533         val32 |= BIT(20);       /* 0x10 << 16 */
2534         rtl8xxxu_write32(priv, reg_int_oe, val32);
2535         udelay(1);
2536
2537         val32 = rtl8xxxu_read32(priv, reg_int_oe);
2538         val32 |= BIT(4);
2539         rtl8xxxu_write32(priv, reg_int_oe, val32);
2540         udelay(1);
2541
2542         /*
2543          * These two we might be able to optimize into one
2544          */
2545         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2546         val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
2547         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2548         udelay(1);
2549
2550         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2551         val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
2552         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2553         udelay(1);
2554
2555         rtl8xxxu_init_rf_regs(priv, table, path);
2556
2557         /* For path B, use XB */
2558         val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
2559         val16 &= ~FPGA0_RF_RFENV;
2560         val16 |= rfsi_rfenv;
2561         rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
2562
2563         return 0;
2564 }
2565
2566 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
2567 {
2568         int ret = -EBUSY;
2569         int count = 0;
2570         u32 value;
2571
2572         value = LLT_OP_WRITE | address << 8 | data;
2573
2574         rtl8xxxu_write32(priv, REG_LLT_INIT, value);
2575
2576         do {
2577                 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
2578                 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
2579                         ret = 0;
2580                         break;
2581                 }
2582         } while (count++ < 20);
2583
2584         return ret;
2585 }
2586
2587 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
2588 {
2589         int ret;
2590         int i;
2591
2592         for (i = 0; i < last_tx_page; i++) {
2593                 ret = rtl8xxxu_llt_write(priv, i, i + 1);
2594                 if (ret)
2595                         goto exit;
2596         }
2597
2598         ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
2599         if (ret)
2600                 goto exit;
2601
2602         /* Mark remaining pages as a ring buffer */
2603         for (i = last_tx_page + 1; i < 0xff; i++) {
2604                 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
2605                 if (ret)
2606                         goto exit;
2607         }
2608
2609         /*  Let last entry point to the start entry of ring buffer */
2610         ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
2611         if (ret)
2612                 goto exit;
2613
2614 exit:
2615         return ret;
2616 }
2617
2618 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
2619 {
2620         u16 val16, hi, lo;
2621         u16 hiq, mgq, bkq, beq, viq, voq;
2622         int hip, mgp, bkp, bep, vip, vop;
2623         int ret = 0;
2624
2625         switch (priv->ep_tx_count) {
2626         case 1:
2627                 if (priv->ep_tx_high_queue) {
2628                         hi = TRXDMA_QUEUE_HIGH;
2629                 } else if (priv->ep_tx_low_queue) {
2630                         hi = TRXDMA_QUEUE_LOW;
2631                 } else if (priv->ep_tx_normal_queue) {
2632                         hi = TRXDMA_QUEUE_NORMAL;
2633                 } else {
2634                         hi = 0;
2635                         ret = -EINVAL;
2636                 }
2637
2638                 hiq = hi;
2639                 mgq = hi;
2640                 bkq = hi;
2641                 beq = hi;
2642                 viq = hi;
2643                 voq = hi;
2644
2645                 hip = 0;
2646                 mgp = 0;
2647                 bkp = 0;
2648                 bep = 0;
2649                 vip = 0;
2650                 vop = 0;
2651                 break;
2652         case 2:
2653                 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
2654                         hi = TRXDMA_QUEUE_HIGH;
2655                         lo = TRXDMA_QUEUE_LOW;
2656                 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
2657                         hi = TRXDMA_QUEUE_NORMAL;
2658                         lo = TRXDMA_QUEUE_LOW;
2659                 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
2660                         hi = TRXDMA_QUEUE_HIGH;
2661                         lo = TRXDMA_QUEUE_NORMAL;
2662                 } else {
2663                         ret = -EINVAL;
2664                         hi = 0;
2665                         lo = 0;
2666                 }
2667
2668                 hiq = hi;
2669                 mgq = hi;
2670                 bkq = lo;
2671                 beq = lo;
2672                 viq = hi;
2673                 voq = hi;
2674
2675                 hip = 0;
2676                 mgp = 0;
2677                 bkp = 1;
2678                 bep = 1;
2679                 vip = 0;
2680                 vop = 0;
2681                 break;
2682         case 3:
2683                 beq = TRXDMA_QUEUE_LOW;
2684                 bkq = TRXDMA_QUEUE_LOW;
2685                 viq = TRXDMA_QUEUE_NORMAL;
2686                 voq = TRXDMA_QUEUE_HIGH;
2687                 mgq = TRXDMA_QUEUE_HIGH;
2688                 hiq = TRXDMA_QUEUE_HIGH;
2689
2690                 hip = hiq ^ 3;
2691                 mgp = mgq ^ 3;
2692                 bkp = bkq ^ 3;
2693                 bep = beq ^ 3;
2694                 vip = viq ^ 3;
2695                 vop = viq ^ 3;
2696                 break;
2697         default:
2698                 ret = -EINVAL;
2699         }
2700
2701         /*
2702          * None of the vendor drivers are configuring the beacon
2703          * queue here .... why?
2704          */
2705         if (!ret) {
2706                 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
2707                 val16 &= 0x7;
2708                 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
2709                         (viq << TRXDMA_CTRL_VIQ_SHIFT) |
2710                         (beq << TRXDMA_CTRL_BEQ_SHIFT) |
2711                         (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
2712                         (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
2713                         (hiq << TRXDMA_CTRL_HIQ_SHIFT);
2714                 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
2715
2716                 priv->pipe_out[TXDESC_QUEUE_VO] =
2717                         usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
2718                 priv->pipe_out[TXDESC_QUEUE_VI] =
2719                         usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
2720                 priv->pipe_out[TXDESC_QUEUE_BE] =
2721                         usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
2722                 priv->pipe_out[TXDESC_QUEUE_BK] =
2723                         usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
2724                 priv->pipe_out[TXDESC_QUEUE_BEACON] =
2725                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2726                 priv->pipe_out[TXDESC_QUEUE_MGNT] =
2727                         usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
2728                 priv->pipe_out[TXDESC_QUEUE_HIGH] =
2729                         usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
2730                 priv->pipe_out[TXDESC_QUEUE_CMD] =
2731                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2732         }
2733
2734         return ret;
2735 }
2736
2737 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
2738                                        bool iqk_ok, int result[][8],
2739                                        int candidate, bool tx_only)
2740 {
2741         u32 oldval, x, tx0_a, reg;
2742         int y, tx0_c;
2743         u32 val32;
2744
2745         if (!iqk_ok)
2746                 return;
2747
2748         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2749         oldval = val32 >> 22;
2750
2751         x = result[candidate][0];
2752         if ((x & 0x00000200) != 0)
2753                 x = x | 0xfffffc00;
2754         tx0_a = (x * oldval) >> 8;
2755
2756         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2757         val32 &= ~0x3ff;
2758         val32 |= tx0_a;
2759         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2760
2761         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2762         val32 &= ~BIT(31);
2763         if ((x * oldval >> 7) & 0x1)
2764                 val32 |= BIT(31);
2765         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2766
2767         y = result[candidate][1];
2768         if ((y & 0x00000200) != 0)
2769                 y = y | 0xfffffc00;
2770         tx0_c = (y * oldval) >> 8;
2771
2772         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
2773         val32 &= ~0xf0000000;
2774         val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
2775         rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
2776
2777         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2778         val32 &= ~0x003f0000;
2779         val32 |= ((tx0_c & 0x3f) << 16);
2780         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2781
2782         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2783         val32 &= ~BIT(29);
2784         if ((y * oldval >> 7) & 0x1)
2785                 val32 |= BIT(29);
2786         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2787
2788         if (tx_only) {
2789                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2790                 return;
2791         }
2792
2793         reg = result[candidate][2];
2794
2795         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2796         val32 &= ~0x3ff;
2797         val32 |= (reg & 0x3ff);
2798         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2799
2800         reg = result[candidate][3] & 0x3F;
2801
2802         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2803         val32 &= ~0xfc00;
2804         val32 |= ((reg << 10) & 0xfc00);
2805         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2806
2807         reg = (result[candidate][3] >> 6) & 0xF;
2808
2809         val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
2810         val32 &= ~0xf0000000;
2811         val32 |= (reg << 28);
2812         rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
2813 }
2814
2815 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
2816                                        bool iqk_ok, int result[][8],
2817                                        int candidate, bool tx_only)
2818 {
2819         u32 oldval, x, tx1_a, reg;
2820         int y, tx1_c;
2821         u32 val32;
2822
2823         if (!iqk_ok)
2824                 return;
2825
2826         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2827         oldval = val32 >> 22;
2828
2829         x = result[candidate][4];
2830         if ((x & 0x00000200) != 0)
2831                 x = x | 0xfffffc00;
2832         tx1_a = (x * oldval) >> 8;
2833
2834         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2835         val32 &= ~0x3ff;
2836         val32 |= tx1_a;
2837         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2838
2839         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2840         val32 &= ~BIT(27);
2841         if ((x * oldval >> 7) & 0x1)
2842                 val32 |= BIT(27);
2843         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2844
2845         y = result[candidate][5];
2846         if ((y & 0x00000200) != 0)
2847                 y = y | 0xfffffc00;
2848         tx1_c = (y * oldval) >> 8;
2849
2850         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
2851         val32 &= ~0xf0000000;
2852         val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
2853         rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
2854
2855         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2856         val32 &= ~0x003f0000;
2857         val32 |= ((tx1_c & 0x3f) << 16);
2858         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2859
2860         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2861         val32 &= ~BIT(25);
2862         if ((y * oldval >> 7) & 0x1)
2863                 val32 |= BIT(25);
2864         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2865
2866         if (tx_only) {
2867                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2868                 return;
2869         }
2870
2871         reg = result[candidate][6];
2872
2873         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2874         val32 &= ~0x3ff;
2875         val32 |= (reg & 0x3ff);
2876         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2877
2878         reg = result[candidate][7] & 0x3f;
2879
2880         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2881         val32 &= ~0xfc00;
2882         val32 |= ((reg << 10) & 0xfc00);
2883         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2884
2885         reg = (result[candidate][7] >> 6) & 0xf;
2886
2887         val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
2888         val32 &= ~0x0000f000;
2889         val32 |= (reg << 12);
2890         rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
2891 }
2892
2893 #define MAX_TOLERANCE           5
2894
2895 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
2896                                         int result[][8], int c1, int c2)
2897 {
2898         u32 i, j, diff, simubitmap, bound = 0;
2899         int candidate[2] = {-1, -1};    /* for path A and path B */
2900         bool retval = true;
2901
2902         if (priv->tx_paths > 1)
2903                 bound = 8;
2904         else
2905                 bound = 4;
2906
2907         simubitmap = 0;
2908
2909         for (i = 0; i < bound; i++) {
2910                 diff = (result[c1][i] > result[c2][i]) ?
2911                         (result[c1][i] - result[c2][i]) :
2912                         (result[c2][i] - result[c1][i]);
2913                 if (diff > MAX_TOLERANCE) {
2914                         if ((i == 2 || i == 6) && !simubitmap) {
2915                                 if (result[c1][i] + result[c1][i + 1] == 0)
2916                                         candidate[(i / 4)] = c2;
2917                                 else if (result[c2][i] + result[c2][i + 1] == 0)
2918                                         candidate[(i / 4)] = c1;
2919                                 else
2920                                         simubitmap = simubitmap | (1 << i);
2921                         } else {
2922                                 simubitmap = simubitmap | (1 << i);
2923                         }
2924                 }
2925         }
2926
2927         if (simubitmap == 0) {
2928                 for (i = 0; i < (bound / 4); i++) {
2929                         if (candidate[i] >= 0) {
2930                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2931                                         result[3][j] = result[candidate[i]][j];
2932                                 retval = false;
2933                         }
2934                 }
2935                 return retval;
2936         } else if (!(simubitmap & 0x0f)) {
2937                 /* path A OK */
2938                 for (i = 0; i < 4; i++)
2939                         result[3][i] = result[c1][i];
2940         } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
2941                 /* path B OK */
2942                 for (i = 4; i < 8; i++)
2943                         result[3][i] = result[c1][i];
2944         }
2945
2946         return false;
2947 }
2948
2949 static void
2950 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
2951 {
2952         int i;
2953
2954         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
2955                 backup[i] = rtl8xxxu_read8(priv, reg[i]);
2956
2957         backup[i] = rtl8xxxu_read32(priv, reg[i]);
2958 }
2959
2960 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
2961                                       const u32 *reg, u32 *backup)
2962 {
2963         int i;
2964
2965         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
2966                 rtl8xxxu_write8(priv, reg[i], backup[i]);
2967
2968         rtl8xxxu_write32(priv, reg[i], backup[i]);
2969 }
2970
2971 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2972                                u32 *backup, int count)
2973 {
2974         int i;
2975
2976         for (i = 0; i < count; i++)
2977                 backup[i] = rtl8xxxu_read32(priv, regs[i]);
2978 }
2979
2980 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2981                                   u32 *backup, int count)
2982 {
2983         int i;
2984
2985         for (i = 0; i < count; i++)
2986                 rtl8xxxu_write32(priv, regs[i], backup[i]);
2987 }
2988
2989
2990 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
2991                                   bool path_a_on)
2992 {
2993         u32 path_on;
2994         int i;
2995
2996         path_on = path_a_on ? 0x04db25a4 : 0x0b1b25a4;
2997         if (priv->tx_paths == 1) {
2998                 path_on = 0x0bdb25a0;
2999                 rtl8xxxu_write32(priv, regs[0], 0x0b1b25a0);
3000         } else {
3001                 rtl8xxxu_write32(priv, regs[0], path_on);
3002         }
3003
3004         for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3005                 rtl8xxxu_write32(priv, regs[i], path_on);
3006 }
3007
3008 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3009                                      const u32 *regs, u32 *backup)
3010 {
3011         int i = 0;
3012
3013         rtl8xxxu_write8(priv, regs[i], 0x3f);
3014
3015         for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3016                 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3017
3018         rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3019 }
3020
3021 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3022 {
3023         u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3024         int result = 0;
3025
3026         /* path-A IQK setting */
3027         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3028         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3029         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3030
3031         val32 = (priv->rf_paths > 1) ? 0x28160202 :
3032                 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3033                 0x28160502;
3034         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3035
3036         /* path-B IQK setting */
3037         if (priv->rf_paths > 1) {
3038                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3039                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3040                 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3041                 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3042         }
3043
3044         /* LO calibration setting */
3045         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3046
3047         /* One shot, path A LOK & IQK */
3048         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3049         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3050
3051         mdelay(1);
3052
3053         /* Check failed */
3054         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3055         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3056         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3057         reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3058
3059         if (!(reg_eac & BIT(28)) &&
3060             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3061             ((reg_e9c & 0x03ff0000) != 0x00420000))
3062                 result |= 0x01;
3063         else    /* If TX not OK, ignore RX */
3064                 goto out;
3065
3066         /* If TX is OK, check whether RX is OK */
3067         if (!(reg_eac & BIT(27)) &&
3068             ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3069             ((reg_eac & 0x03ff0000) != 0x00360000))
3070                 result |= 0x02;
3071         else
3072                 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3073                          __func__);
3074 out:
3075         return result;
3076 }
3077
3078 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3079 {
3080         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3081         int result = 0;
3082
3083         /* One shot, path B LOK & IQK */
3084         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3085         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3086
3087         mdelay(1);
3088
3089         /* Check failed */
3090         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3091         reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3092         reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3093         reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3094         reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3095
3096         if (!(reg_eac & BIT(31)) &&
3097             ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3098             ((reg_ebc & 0x03ff0000) != 0x00420000))
3099                 result |= 0x01;
3100         else
3101                 goto out;
3102
3103         if (!(reg_eac & BIT(30)) &&
3104             (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3105             (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3106                 result |= 0x02;
3107         else
3108                 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3109                          __func__);
3110 out:
3111         return result;
3112 }
3113
3114 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3115                                      int result[][8], int t)
3116 {
3117         struct device *dev = &priv->udev->dev;
3118         u32 i, val32;
3119         int path_a_ok, path_b_ok;
3120         int retry = 2;
3121         const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3122                 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3123                 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3124                 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3125                 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3126                 REG_TX_TO_TX, REG_RX_CCK,
3127                 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3128                 REG_RX_TO_RX, REG_STANDBY,
3129                 REG_SLEEP, REG_PMPD_ANAEN
3130         };
3131         const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3132                 REG_TXPAUSE, REG_BEACON_CTRL,
3133                 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3134         };
3135         const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3136                 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3137                 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3138                 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3139                 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3140         };
3141
3142         /*
3143          * Note: IQ calibration must be performed after loading
3144          *       PHY_REG.txt , and radio_a, radio_b.txt
3145          */
3146
3147         if (t == 0) {
3148                 /* Save ADDA parameters, turn Path A ADDA on */
3149                 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3150                                    RTL8XXXU_ADDA_REGS);
3151                 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3152                 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3153                                    priv->bb_backup, RTL8XXXU_BB_REGS);
3154         }
3155
3156         rtl8xxxu_path_adda_on(priv, adda_regs, true);
3157
3158         if (t == 0) {
3159                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3160                 if (val32 & FPGA0_HSSI_PARM1_PI)
3161                         priv->pi_enabled = 1;
3162         }
3163
3164         if (!priv->pi_enabled) {
3165                 /* Switch BB to PI mode to do IQ Calibration. */
3166                 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3167                 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3168         }
3169
3170         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3171         val32 &= ~FPGA_RF_MODE_CCK;
3172         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3173
3174         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3175         rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3176         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3177
3178         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3179         val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3180         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3181
3182         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3183         val32 &= ~BIT(10);
3184         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3185         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3186         val32 &= ~BIT(10);
3187         rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3188
3189         if (priv->tx_paths > 1) {
3190                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3191                 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3192         }
3193
3194         /* MAC settings */
3195         rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3196
3197         /* Page B init */
3198         rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3199
3200         if (priv->tx_paths > 1)
3201                 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3202
3203         /* IQ calibration setting */
3204         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3205         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3206         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3207
3208         for (i = 0; i < retry; i++) {
3209                 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3210                 if (path_a_ok == 0x03) {
3211                         val32 = rtl8xxxu_read32(priv,
3212                                                 REG_TX_POWER_BEFORE_IQK_A);
3213                         result[t][0] = (val32 >> 16) & 0x3ff;
3214                         val32 = rtl8xxxu_read32(priv,
3215                                                 REG_TX_POWER_AFTER_IQK_A);
3216                         result[t][1] = (val32 >> 16) & 0x3ff;
3217                         val32 = rtl8xxxu_read32(priv,
3218                                                 REG_RX_POWER_BEFORE_IQK_A_2);
3219                         result[t][2] = (val32 >> 16) & 0x3ff;
3220                         val32 = rtl8xxxu_read32(priv,
3221                                                 REG_RX_POWER_AFTER_IQK_A_2);
3222                         result[t][3] = (val32 >> 16) & 0x3ff;
3223                         break;
3224                 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3225                         /* TX IQK OK */
3226                         dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3227                                 __func__);
3228
3229                         val32 = rtl8xxxu_read32(priv,
3230                                                 REG_TX_POWER_BEFORE_IQK_A);
3231                         result[t][0] = (val32 >> 16) & 0x3ff;
3232                         val32 = rtl8xxxu_read32(priv,
3233                                                 REG_TX_POWER_AFTER_IQK_A);
3234                         result[t][1] = (val32 >> 16) & 0x3ff;
3235                 }
3236         }
3237
3238         if (!path_a_ok)
3239                 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3240
3241         if (priv->tx_paths > 1) {
3242                 /*
3243                  * Path A into standby
3244                  */
3245                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3246                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3247                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3248
3249                 /* Turn Path B ADDA on */
3250                 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3251
3252                 for (i = 0; i < retry; i++) {
3253                         path_b_ok = rtl8xxxu_iqk_path_b(priv);
3254                         if (path_b_ok == 0x03) {
3255                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3256                                 result[t][4] = (val32 >> 16) & 0x3ff;
3257                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3258                                 result[t][5] = (val32 >> 16) & 0x3ff;
3259                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3260                                 result[t][6] = (val32 >> 16) & 0x3ff;
3261                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3262                                 result[t][7] = (val32 >> 16) & 0x3ff;
3263                                 break;
3264                         } else if (i == (retry - 1) && path_b_ok == 0x01) {
3265                                 /* TX IQK OK */
3266                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3267                                 result[t][4] = (val32 >> 16) & 0x3ff;
3268                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3269                                 result[t][5] = (val32 >> 16) & 0x3ff;
3270                         }
3271                 }
3272
3273                 if (!path_b_ok)
3274                         dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3275         }
3276
3277         /* Back to BB mode, load original value */
3278         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3279
3280         if (t) {
3281                 if (!priv->pi_enabled) {
3282                         /*
3283                          * Switch back BB to SI mode after finishing
3284                          * IQ Calibration
3285                          */
3286                         val32 = 0x01000000;
3287                         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3288                         rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3289                 }
3290
3291                 /* Reload ADDA power saving parameters */
3292                 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3293                                       RTL8XXXU_ADDA_REGS);
3294
3295                 /* Reload MAC parameters */
3296                 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3297
3298                 /* Reload BB parameters */
3299                 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3300                                       priv->bb_backup, RTL8XXXU_BB_REGS);
3301
3302                 /* Restore RX initial gain */
3303                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3304
3305                 if (priv->tx_paths > 1) {
3306                         rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3307                                          0x00032ed3);
3308                 }
3309
3310                 /* Load 0xe30 IQC default value */
3311                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3312                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3313         }
3314 }
3315
3316 static void rtl8723a_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3317 {
3318         struct device *dev = &priv->udev->dev;
3319         int result[4][8];       /* last is final result */
3320         int i, candidate;
3321         bool path_a_ok, path_b_ok;
3322         u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3323         u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3324         s32 reg_tmp = 0;
3325         bool simu;
3326
3327         memset(result, 0, sizeof(result));
3328         candidate = -1;
3329
3330         path_a_ok = false;
3331         path_b_ok = false;
3332
3333         rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3334
3335         for (i = 0; i < 3; i++) {
3336                 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3337
3338                 if (i == 1) {
3339                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3340                         if (simu) {
3341                                 candidate = 0;
3342                                 break;
3343                         }
3344                 }
3345
3346                 if (i == 2) {
3347                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3348                         if (simu) {
3349                                 candidate = 0;
3350                                 break;
3351                         }
3352
3353                         simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3354                         if (simu) {
3355                                 candidate = 1;
3356                         } else {
3357                                 for (i = 0; i < 8; i++)
3358                                         reg_tmp += result[3][i];
3359
3360                                 if (reg_tmp)
3361                                         candidate = 3;
3362                                 else
3363                                         candidate = -1;
3364                         }
3365                 }
3366         }
3367
3368         for (i = 0; i < 4; i++) {
3369                 reg_e94 = result[i][0];
3370                 reg_e9c = result[i][1];
3371                 reg_ea4 = result[i][2];
3372                 reg_eac = result[i][3];
3373                 reg_eb4 = result[i][4];
3374                 reg_ebc = result[i][5];
3375                 reg_ec4 = result[i][6];
3376                 reg_ecc = result[i][7];
3377         }
3378
3379         if (candidate >= 0) {
3380                 reg_e94 = result[candidate][0];
3381                 priv->rege94 =  reg_e94;
3382                 reg_e9c = result[candidate][1];
3383                 priv->rege9c = reg_e9c;
3384                 reg_ea4 = result[candidate][2];
3385                 reg_eac = result[candidate][3];
3386                 reg_eb4 = result[candidate][4];
3387                 priv->regeb4 = reg_eb4;
3388                 reg_ebc = result[candidate][5];
3389                 priv->regebc = reg_ebc;
3390                 reg_ec4 = result[candidate][6];
3391                 reg_ecc = result[candidate][7];
3392                 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3393                 dev_dbg(dev,
3394                         "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
3395                         "ecc=%x\n ", __func__, reg_e94, reg_e9c,
3396                         reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3397                 path_a_ok = true;
3398                 path_b_ok = true;
3399         } else {
3400                 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3401                 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3402         }
3403
3404         if (reg_e94 && candidate >= 0)
3405                 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3406                                            candidate, (reg_ea4 == 0));
3407
3408         if (priv->tx_paths > 1 && reg_eb4)
3409                 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3410                                            candidate, (reg_ec4 == 0));
3411
3412         rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
3413                            priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3414 }
3415
3416 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3417 {
3418         u32 val32;
3419         u32 rf_amode, rf_bmode = 0, lstf;
3420
3421         /* Check continuous TX and Packet TX */
3422         lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3423
3424         if (lstf & OFDM_LSTF_MASK) {
3425                 /* Disable all continuous TX */
3426                 val32 = lstf & ~OFDM_LSTF_MASK;
3427                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3428
3429                 /* Read original RF mode Path A */
3430                 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3431
3432                 /* Set RF mode to standby Path A */
3433                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3434                                      (rf_amode & 0x8ffff) | 0x10000);
3435
3436                 /* Path-B */
3437                 if (priv->tx_paths > 1) {
3438                         rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
3439                                                        RF6052_REG_AC);
3440
3441                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3442                                              (rf_bmode & 0x8ffff) | 0x10000);
3443                 }
3444         } else {
3445                 /*  Deal with Packet TX case */
3446                 /*  block all queues */
3447                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3448         }
3449
3450         /* Start LC calibration */
3451         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
3452         val32 |= 0x08000;
3453         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
3454
3455         msleep(100);
3456
3457         /* Restore original parameters */
3458         if (lstf & OFDM_LSTF_MASK) {
3459                 /* Path-A */
3460                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
3461                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
3462
3463                 /* Path-B */
3464                 if (priv->tx_paths > 1)
3465                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3466                                              rf_bmode);
3467         } else /*  Deal with Packet TX case */
3468                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
3469 }
3470
3471 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
3472 {
3473         int i;
3474         u16 reg;
3475
3476         reg = REG_MACID;
3477
3478         for (i = 0; i < ETH_ALEN; i++)
3479                 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
3480
3481         return 0;
3482 }
3483
3484 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
3485 {
3486         int i;
3487         u16 reg;
3488
3489         dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
3490
3491         reg = REG_BSSID;
3492
3493         for (i = 0; i < ETH_ALEN; i++)
3494                 rtl8xxxu_write8(priv, reg + i, bssid[i]);
3495
3496         return 0;
3497 }
3498
3499 static void
3500 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
3501 {
3502         u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
3503         u8 max_agg = 0xf;
3504         int i;
3505
3506         ampdu_factor = 1 << (ampdu_factor + 2);
3507         if (ampdu_factor > max_agg)
3508                 ampdu_factor = max_agg;
3509
3510         for (i = 0; i < 4; i++) {
3511                 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
3512                         vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
3513
3514                 if ((vals[i] & 0x0f) > ampdu_factor)
3515                         vals[i] = (vals[i] & 0xf0) | ampdu_factor;
3516
3517                 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
3518         }
3519 }
3520
3521 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
3522 {
3523         u8 val8;
3524
3525         val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
3526         val8 &= 0xf8;
3527         val8 |= density;
3528         rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
3529 }
3530
3531 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
3532 {
3533         u8 val8;
3534         int count, ret;
3535
3536         /* Start of rtl8723AU_card_enable_flow */
3537         /* Act to Cardemu sequence*/
3538         /* Turn off RF */
3539         rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
3540
3541         /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
3542         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3543         val8 &= ~LEDCFG2_DPDT_SELECT;
3544         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3545
3546         /* 0x0005[1] = 1 turn off MAC by HW state machine*/
3547         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3548         val8 |= BIT(1);
3549         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3550
3551         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3552                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3553                 if ((val8 & BIT(1)) == 0)
3554                         break;
3555                 udelay(10);
3556         }
3557
3558         if (!count) {
3559                 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
3560                          __func__);
3561                 ret = -EBUSY;
3562                 goto exit;
3563         }
3564
3565         /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
3566         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3567         val8 |= SYS_ISO_ANALOG_IPS;
3568         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3569
3570         /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
3571         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3572         val8 &= ~LDOA15_ENABLE;
3573         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3574
3575 exit:
3576         return ret;
3577 }
3578
3579 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
3580 {
3581         u8 val8;
3582         u8 val32;
3583         int count, ret;
3584
3585         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3586
3587         /*
3588          * Poll - wait for RX packet to complete
3589          */
3590         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3591                 val32 = rtl8xxxu_read32(priv, 0x5f8);
3592                 if (!val32)
3593                         break;
3594                 udelay(10);
3595         }
3596
3597         if (!count) {
3598                 dev_warn(&priv->udev->dev,
3599                          "%s: RX poll timed out (0x05f8)\n", __func__);
3600                 ret = -EBUSY;
3601                 goto exit;
3602         }
3603
3604         /* Disable CCK and OFDM, clock gated */
3605         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3606         val8 &= ~SYS_FUNC_BBRSTB;
3607         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3608
3609         udelay(2);
3610
3611         /* Reset baseband */
3612         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3613         val8 &= ~SYS_FUNC_BB_GLB_RSTN;
3614         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3615
3616         /* Reset MAC TRX */
3617         val8 = rtl8xxxu_read8(priv, REG_CR);
3618         val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
3619         rtl8xxxu_write8(priv, REG_CR, val8);
3620
3621         /* Reset MAC TRX */
3622         val8 = rtl8xxxu_read8(priv, REG_CR + 1);
3623         val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
3624         rtl8xxxu_write8(priv, REG_CR + 1, val8);
3625
3626         /* Respond TX OK to scheduler */
3627         val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
3628         val8 |= DUAL_TSF_TX_OK;
3629         rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
3630
3631 exit:
3632         return ret;
3633 }
3634
3635 static void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv)
3636 {
3637         u8 val8;
3638
3639         /* Clear suspend enable and power down enable*/
3640         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3641         val8 &= ~(BIT(3) | BIT(7));
3642         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3643
3644         /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
3645         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3646         val8 &= ~BIT(0);
3647         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3648
3649         /* 0x04[12:11] = 11 enable WL suspend*/
3650         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3651         val8 &= ~(BIT(3) | BIT(4));
3652         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3653 }
3654
3655 static int rtl8xxxu_emu_to_active(struct rtl8xxxu_priv *priv)
3656 {
3657         u8 val8;
3658         u32 val32;
3659         int count, ret = 0;
3660
3661         /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
3662         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3663         val8 |= LDOA15_ENABLE;
3664         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3665
3666         /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
3667         val8 = rtl8xxxu_read8(priv, 0x0067);
3668         val8 &= ~BIT(4);
3669         rtl8xxxu_write8(priv, 0x0067, val8);
3670
3671         mdelay(1);
3672
3673         /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
3674         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3675         val8 &= ~SYS_ISO_ANALOG_IPS;
3676         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3677
3678         /* disable SW LPS 0x04[10]= 0 */
3679         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3680         val8 &= ~BIT(2);
3681         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3682
3683         /* wait till 0x04[17] = 1 power ready*/
3684         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3685                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3686                 if (val32 & BIT(17))
3687                         break;
3688
3689                 udelay(10);
3690         }
3691
3692         if (!count) {
3693                 ret = -EBUSY;
3694                 goto exit;
3695         }
3696
3697         /* We should be able to optimize the following three entries into one */
3698
3699         /* release WLON reset 0x04[16]= 1*/
3700         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
3701         val8 |= BIT(0);
3702         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
3703
3704         /* disable HWPDN 0x04[15]= 0*/
3705         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3706         val8 &= ~BIT(7);
3707         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3708
3709         /* disable WL suspend*/
3710         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3711         val8 &= ~(BIT(3) | BIT(4));
3712         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3713
3714         /* set, then poll until 0 */
3715         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3716         val32 |= APS_FSMCO_MAC_ENABLE;
3717         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
3718
3719         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3720                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3721                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
3722                         ret = 0;
3723                         break;
3724                 }
3725                 udelay(10);
3726         }
3727
3728         if (!count) {
3729                 ret = -EBUSY;
3730                 goto exit;
3731         }
3732
3733         /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
3734         /*
3735          * Note: Vendor driver actually clears this bit, despite the
3736          * documentation claims it's being set!
3737          */
3738         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3739         val8 |= LEDCFG2_DPDT_SELECT;
3740         val8 &= ~LEDCFG2_DPDT_SELECT;
3741         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3742
3743 exit:
3744         return ret;
3745 }
3746
3747 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
3748 {
3749         u8 val8;
3750
3751         /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
3752         rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
3753
3754         /* 0x04[12:11] = 01 enable WL suspend */
3755         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3756         val8 &= ~BIT(4);
3757         val8 |= BIT(3);
3758         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3759
3760         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3761         val8 |= BIT(7);
3762         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3763
3764         /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
3765         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3766         val8 |= BIT(0);
3767         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3768
3769         return 0;
3770 }
3771
3772 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
3773 {
3774         u8 val8;
3775         u16 val16;
3776         u32 val32;
3777         int ret;
3778
3779         /*
3780          * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
3781          */
3782         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
3783
3784         rtl8xxxu_disabled_to_emu(priv);
3785
3786         ret = rtl8xxxu_emu_to_active(priv);
3787         if (ret)
3788                 goto exit;
3789
3790         /*
3791          * 0x0004[19] = 1, reset 8051
3792          */
3793         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
3794         val8 |= BIT(3);
3795         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
3796
3797         /*
3798          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
3799          * Set CR bit10 to enable 32k calibration.
3800          */
3801         val16 = rtl8xxxu_read16(priv, REG_CR);
3802         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
3803                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
3804                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
3805                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
3806                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
3807         rtl8xxxu_write16(priv, REG_CR, val16);
3808
3809         /* For EFuse PG */
3810         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
3811         val32 &= ~(BIT(28) | BIT(29) | BIT(30));
3812         val32 |= (0x06 << 28);
3813         rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
3814 exit:
3815         return ret;
3816 }
3817
3818 static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
3819 {
3820         u8 val8;
3821         u16 val16;
3822         u32 val32;
3823         int i;
3824
3825         for (i = 100; i; i--) {
3826                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
3827                 if (val8 & APS_FSMCO_PFM_ALDN)
3828                         break;
3829         }
3830
3831         if (!i) {
3832                 pr_info("%s: Poll failed\n", __func__);
3833                 return -ENODEV;
3834         }
3835
3836         /*
3837          * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
3838          */
3839         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
3840         rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
3841         udelay(100);
3842
3843         val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
3844         if (!(val8 & LDOV12D_ENABLE)) {
3845                 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
3846                 val8 |= LDOV12D_ENABLE;
3847                 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
3848
3849                 udelay(100);
3850
3851                 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3852                 val8 &= ~SYS_ISO_MD2PP;
3853                 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3854         }
3855
3856         /*
3857          * Auto enable WLAN
3858          */
3859         val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
3860         val16 |= APS_FSMCO_MAC_ENABLE;
3861         rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
3862
3863         for (i = 1000; i; i--) {
3864                 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
3865                 if (!(val16 & APS_FSMCO_MAC_ENABLE))
3866                         break;
3867         }
3868         if (!i) {
3869                 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
3870                 return -EBUSY;
3871         }
3872
3873         /*
3874          * Enable radio, GPIO, LED
3875          */
3876         val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
3877                 APS_FSMCO_PFM_ALDN;
3878         rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
3879
3880         /*
3881          * Release RF digital isolation
3882          */
3883         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
3884         val16 &= ~SYS_ISO_DIOR;
3885         rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
3886
3887         val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
3888         val8 &= ~APSD_CTRL_OFF;
3889         rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
3890         for (i = 200; i; i--) {
3891                 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
3892                 if (!(val8 & APSD_CTRL_OFF_STATUS))
3893                         break;
3894         }
3895
3896         if (!i) {
3897                 pr_info("%s: APSD_CTRL poll failed\n", __func__);
3898                 return -EBUSY;
3899         }
3900
3901         /*
3902          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
3903          */
3904         val16 = rtl8xxxu_read16(priv, REG_CR);
3905         val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
3906                 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
3907                 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
3908         rtl8xxxu_write16(priv, REG_CR, val16);
3909
3910         /*
3911          * Workaround for 8188RU LNA power leakage problem.
3912          */
3913         if (priv->rtlchip == 0x8188c && priv->hi_pa) {
3914                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3915                 val32 &= ~BIT(1);
3916                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3917         }
3918         return 0;
3919 }
3920
3921 static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
3922 {
3923         u8 val8;
3924         u16 val16;
3925         u32 val32;
3926
3927         /*
3928          * Workaround for 8188RU LNA power leakage problem.
3929          */
3930         if (priv->rtlchip == 0x8188c && priv->hi_pa) {
3931                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3932                 val32 |= BIT(1);
3933                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3934         }
3935
3936         rtl8xxxu_active_to_lps(priv);
3937
3938         /* Turn off RF */
3939         rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
3940
3941         /* Reset Firmware if running in RAM */
3942         if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
3943                 rtl8xxxu_firmware_self_reset(priv);
3944
3945         /* Reset MCU */
3946         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3947         val16 &= ~SYS_FUNC_CPU_ENABLE;
3948         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3949
3950         /* Reset MCU ready status */
3951         rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
3952
3953         rtl8xxxu_active_to_emu(priv);
3954         rtl8xxxu_emu_to_disabled(priv);
3955
3956         /* Reset MCU IO Wrapper */
3957         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3958         val8 &= ~BIT(0);
3959         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3960
3961         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3962         val8 |= BIT(0);
3963         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3964
3965         /* RSV_CTRL 0x1C[7:0] = 0x0e  lock ISO/CLK/Power control register */
3966         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
3967 }
3968
3969 static void rtl8xxxu_init_bt(struct rtl8xxxu_priv *priv)
3970 {
3971         if (!priv->has_bluetooth)
3972                 return;
3973 }
3974
3975 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
3976 {
3977         struct rtl8xxxu_priv *priv = hw->priv;
3978         struct device *dev = &priv->udev->dev;
3979         struct rtl8xxxu_rfregval *rftable;
3980         bool macpower;
3981         int ret;
3982         u8 val8;
3983         u16 val16;
3984         u32 val32;
3985
3986         /* Check if MAC is already powered on */
3987         val8 = rtl8xxxu_read8(priv, REG_CR);
3988
3989         /*
3990          * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
3991          * initialized. First MAC returns 0xea, second MAC returns 0x00
3992          */
3993         if (val8 == 0xea)
3994                 macpower = false;
3995         else
3996                 macpower = true;
3997
3998         ret = priv->fops->power_on(priv);
3999         if (ret < 0) {
4000                 dev_warn(dev, "%s: Failed power on\n", __func__);
4001                 goto exit;
4002         }
4003
4004         dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4005         if (!macpower) {
4006                 ret = rtl8xxxu_init_llt_table(priv, TX_TOTAL_PAGE_NUM);
4007                 if (ret) {
4008                         dev_warn(dev, "%s: LLT table init failed\n", __func__);
4009                         goto exit;
4010                 }
4011         }
4012
4013         ret = rtl8xxxu_download_firmware(priv);
4014         dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
4015         if (ret)
4016                 goto exit;
4017         ret = rtl8xxxu_start_firmware(priv);
4018         dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
4019         if (ret)
4020                 goto exit;
4021
4022         ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
4023         dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
4024         if (ret)
4025                 goto exit;
4026
4027         ret = rtl8xxxu_init_phy_bb(priv);
4028         dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
4029         if (ret)
4030                 goto exit;
4031
4032         switch(priv->rtlchip) {
4033         case 0x8723a:
4034                 rftable = rtl8723au_radioa_1t_init_table;
4035                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4036                 break;
4037         case 0x8188c:
4038                 if (priv->hi_pa)
4039                         rftable = rtl8188ru_radioa_1t_highpa_table;
4040                 else
4041                         rftable = rtl8192cu_radioa_1t_init_table;
4042                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4043                 break;
4044         case 0x8191c:
4045                 rftable = rtl8192cu_radioa_1t_init_table;
4046                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4047                 break;
4048         case 0x8192c:
4049                 rftable = rtl8192cu_radioa_2t_init_table;
4050                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4051                 if (ret)
4052                         break;
4053                 rftable = rtl8192cu_radiob_2t_init_table;
4054                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
4055                 break;
4056         default:
4057                 ret = -EINVAL;
4058         }
4059
4060         if (ret)
4061                 goto exit;
4062
4063         /* Reduce 80M spur */
4064         rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
4065         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4066         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
4067         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4068
4069         /* RFSW Control - clear bit 14 ?? */
4070         rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
4071         /* 0x07000760 */
4072         val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
4073                 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
4074                 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
4075                  FPGA0_RF_BD_CTRL_SHIFT);
4076         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4077         /* 0x860[6:5]= 00 - why? - this sets antenna B */
4078         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
4079
4080         priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
4081                                                   RF6052_REG_MODE_AG);
4082
4083         dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4084         if (!macpower) {
4085                 if (priv->ep_tx_normal_queue)
4086                         val8 = TX_PAGE_NUM_NORM_PQ;
4087                 else
4088                         val8 = 0;
4089
4090                 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
4091
4092                 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
4093
4094                 if (priv->ep_tx_high_queue)
4095                         val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
4096                 if (priv->ep_tx_low_queue)
4097                         val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
4098
4099                 rtl8xxxu_write32(priv, REG_RQPN, val32);
4100
4101                 /*
4102                  * Set TX buffer boundary
4103                  */
4104                 val8 = TX_TOTAL_PAGE_NUM + 1;
4105                 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
4106                 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
4107                 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
4108                 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
4109                 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
4110         }
4111
4112         ret = rtl8xxxu_init_queue_priority(priv);
4113         dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
4114         if (ret)
4115                 goto exit;
4116
4117         /*
4118          * Set RX page boundary
4119          */
4120         rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
4121         /*
4122          * Transfer page size is always 128
4123          */
4124         val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
4125                 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
4126         rtl8xxxu_write8(priv, REG_PBP, val8);
4127
4128         /*
4129          * Unit in 8 bytes, not obvious what it is used for
4130          */
4131         rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4132
4133         /*
4134          * Enable all interrupts - not obvious USB needs to do this
4135          */
4136         rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4137         rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4138
4139         rtl8xxxu_set_mac(priv);
4140         rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4141
4142         /*
4143          * Configure initial WMAC settings
4144          */
4145         val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
4146                 /* RCR_CHECK_BSSID_MATCH | RCR_CHECK_BSSID_BEACON | */
4147                 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4148                 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4149         rtl8xxxu_write32(priv, REG_RCR, val32);
4150
4151         /*
4152          * Accept all multicast
4153          */
4154         rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4155         rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4156
4157         /*
4158          * Init adaptive controls
4159          */
4160         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4161         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4162         val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4163         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4164
4165         /* CCK = 0x0a, OFDM = 0x10 */
4166         rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4167         rtl8xxxu_set_retry(priv, 0x30, 0x30);
4168         rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4169
4170         /*
4171          * Init EDCA
4172          */
4173         rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4174
4175         /* Set CCK SIFS */
4176         rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4177
4178         /* Set OFDM SIFS */
4179         rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4180
4181         /* TXOP */
4182         rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4183         rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4184         rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4185         rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4186
4187         /* Set data auto rate fallback retry count */
4188         rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4189         rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4190         rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4191         rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4192
4193         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4194         val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4195         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4196
4197         /*  Set ACK timeout */
4198         rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4199
4200         /*
4201          * Initialize beacon parameters
4202          */
4203         val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4204         rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4205         rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4206         rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4207         rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4208         rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4209
4210         /*
4211          * Enable CCK and OFDM block
4212          */
4213         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4214         val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4215         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4216
4217         /*
4218          * Invalidate all CAM entries - bit 30 is undocumented
4219          */
4220         rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4221
4222         /*
4223          * Start out with default power levels for channel 6, 20MHz
4224          */
4225         rtl8723a_set_tx_power(priv, 1, false);
4226
4227         /* Let the 8051 take control of antenna setting */
4228         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4229         val8 |= LEDCFG2_DPDT_SELECT;
4230         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4231
4232         rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4233
4234         /* Disable BAR - not sure if this has any effect on USB */
4235         rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4236
4237         rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4238
4239         /*
4240          * Not sure if we should get into this at all
4241          */
4242         if (priv->iqk_initialized) {
4243                 rtl8xxxu_restore_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
4244                                       priv->bb_recovery_backup,
4245                                       RTL8XXXU_BB_REGS);
4246         } else {
4247                 rtl8723a_phy_iq_calibrate(priv);
4248                 priv->iqk_initialized = true;
4249         }
4250
4251         /*
4252          * This should enable thermal meter
4253          */
4254         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4255
4256         rtl8723a_phy_lc_calibrate(priv);
4257
4258         /* fix USB interface interference issue */
4259         rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4260         rtl8xxxu_write8(priv, 0xfe41, 0x8d);
4261         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4262         rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
4263
4264         /* Solve too many protocol error on USB bus */
4265         /* Can't do this for 8188/8192 UMC A cut parts */
4266         rtl8xxxu_write8(priv, 0xfe40, 0xe6);
4267         rtl8xxxu_write8(priv, 0xfe41, 0x94);
4268         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4269
4270         rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4271         rtl8xxxu_write8(priv, 0xfe41, 0x19);
4272         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4273
4274         rtl8xxxu_write8(priv, 0xfe40, 0xe5);
4275         rtl8xxxu_write8(priv, 0xfe41, 0x91);
4276         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4277
4278         rtl8xxxu_write8(priv, 0xfe40, 0xe2);
4279         rtl8xxxu_write8(priv, 0xfe41, 0x81);
4280         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4281
4282         /* Init BT hw config. */
4283         rtl8xxxu_init_bt(priv);
4284
4285         /*
4286          * Not sure if we really need to save these parameters, but the
4287          * vendor driver does
4288          */
4289         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
4290         if (val32 & FPGA0_HSSI_PARM2_CCK_HIGH_PWR)
4291                 priv->path_a_hi_power = 1;
4292
4293         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
4294         priv->path_a_rf_paths = val32 & OFDM_RF_PATH_RX_MASK;
4295
4296         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4297         priv->path_a_ig_value = val32 & OFDM0_X_AGC_CORE1_IGI_MASK;
4298
4299         /* Set NAV_UPPER to 30000us */
4300         val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
4301         rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
4302
4303         /*
4304          * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
4305          * but we need to fin root cause.
4306          */
4307         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4308         if ((val32 & 0xff000000) != 0x83000000) {
4309                 val32 |= FPGA_RF_MODE_CCK;
4310                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4311         }
4312
4313         val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4314         val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
4315         /* ack for xmit mgmt frames. */
4316         rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
4317
4318 exit:
4319         return ret;
4320 }
4321
4322 static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
4323 {
4324         struct rtl8xxxu_priv *priv = hw->priv;
4325
4326         rtl8xxxu_power_off(priv);
4327 }
4328
4329 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
4330                                struct ieee80211_key_conf *key, const u8 *mac)
4331 {
4332         u32 cmd, val32, addr, ctrl;
4333         int j, i, tmp_debug;
4334
4335         tmp_debug = rtl8xxxu_debug;
4336         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
4337                 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
4338
4339         /*
4340          * This is a bit of a hack - the lower bits of the cipher
4341          * suite selector happens to match the cipher index in the CAM
4342          */
4343         addr = key->keyidx << CAM_CMD_KEY_SHIFT;
4344         ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
4345
4346         for (j = 5; j >= 0; j--) {
4347                 switch (j) {
4348                 case 0:
4349                         val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
4350                         break;
4351                 case 1:
4352                         val32 = mac[2] | (mac[3] << 8) |
4353                                 (mac[4] << 16) | (mac[5] << 24);
4354                         break;
4355                 default:
4356                         i = (j - 2) << 2;
4357                         val32 = key->key[i] | (key->key[i + 1] << 8) |
4358                                 key->key[i + 2] << 16 | key->key[i + 3] << 24;
4359                         break;
4360                 }
4361
4362                 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
4363                 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
4364                 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
4365                 udelay(100);
4366         }
4367
4368         rtl8xxxu_debug = tmp_debug;
4369 }
4370
4371 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
4372                                    struct ieee80211_vif *vif, const u8* mac)
4373 {
4374         struct rtl8xxxu_priv *priv = hw->priv;
4375         u8 val8;
4376
4377         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4378         val8 |= BEACON_DISABLE_TSF_UPDATE;
4379         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4380 }
4381
4382 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
4383                                       struct ieee80211_vif *vif)
4384 {
4385         struct rtl8xxxu_priv *priv = hw->priv;
4386         u8 val8;
4387
4388         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4389         val8 &= ~BEACON_DISABLE_TSF_UPDATE;
4390         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4391 }
4392
4393 static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
4394                                       u32 ramask, int sgi)
4395 {
4396         struct h2c_cmd h2c;
4397
4398         h2c.ramask.cmd = H2C_SET_RATE_MASK;
4399         h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
4400         h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
4401
4402         h2c.ramask.arg = 0x80;
4403         if (sgi)
4404                 h2c.ramask.arg |= 0x20;
4405
4406         dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x\n", __func__,
4407                 ramask, h2c.ramask.arg);
4408         rtl8723a_h2c_cmd(priv, &h2c);
4409 }
4410
4411 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
4412 {
4413         u32 val32;
4414         u8 rate_idx = 0;
4415
4416         rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
4417
4418         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4419         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4420         val32 |= rate_cfg;
4421         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4422
4423         dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
4424
4425         while (rate_cfg) {
4426                 rate_cfg = (rate_cfg >> 1);
4427                 rate_idx++;
4428         }
4429         rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
4430 }
4431
4432 static void
4433 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4434                           struct ieee80211_bss_conf *bss_conf, u32 changed)
4435 {
4436         struct rtl8xxxu_priv *priv = hw->priv;
4437         struct device *dev = &priv->udev->dev;
4438         struct ieee80211_sta *sta;
4439         u32 val32;
4440         u8 val8;
4441
4442         if (changed & BSS_CHANGED_ASSOC) {
4443                 struct h2c_cmd h2c;
4444
4445                 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
4446
4447                 memset(&h2c, 0, sizeof(struct h2c_cmd));
4448                 rtl8xxxu_set_linktype(priv, vif->type);
4449
4450                 if (bss_conf->assoc) {
4451                         u32 ramask;
4452                         int sgi = 0;
4453
4454                         rcu_read_lock();
4455                         sta = ieee80211_find_sta(vif, bss_conf->bssid);
4456                         if (!sta) {
4457                                 dev_info(dev, "%s: ASSOC no sta found\n",
4458                                          __func__);
4459                                 rcu_read_unlock();
4460                                 goto error;
4461                         }
4462
4463                         if (sta->ht_cap.ht_supported)
4464                                 dev_info(dev, "%s: HT supported\n", __func__);
4465                         if (sta->vht_cap.vht_supported)
4466                                 dev_info(dev, "%s: VHT supported\n", __func__);
4467
4468                         /* TODO: Set bits 28-31 for rate adaptive id */
4469                         ramask = (sta->supp_rates[0] & 0xfff) |
4470                                 sta->ht_cap.mcs.rx_mask[0] << 12 |
4471                                 sta->ht_cap.mcs.rx_mask[1] << 20;
4472                         if (sta->ht_cap.cap &
4473                             (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
4474                                 sgi = 1;
4475                         rcu_read_unlock();
4476
4477                         rtl8xxxu_update_rate_mask(priv, ramask, sgi);
4478
4479                         val32 = rtl8xxxu_read32(priv, REG_RCR);
4480                         val32 |= RCR_CHECK_BSSID_MATCH | RCR_CHECK_BSSID_BEACON;
4481                         rtl8xxxu_write32(priv, REG_RCR, val32);
4482
4483                         /* Enable RX of data frames */
4484                         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
4485
4486                         rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
4487
4488                         rtl8723a_stop_tx_beacon(priv);
4489
4490                         /* joinbss sequence */
4491                         rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
4492                                          0xc000 | bss_conf->aid);
4493
4494                         h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
4495                 } else {
4496                         val32 = rtl8xxxu_read32(priv, REG_RCR);
4497                         val32 &= ~(RCR_CHECK_BSSID_MATCH |
4498                                    RCR_CHECK_BSSID_BEACON);
4499                         rtl8xxxu_write32(priv, REG_RCR, val32);
4500
4501                         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4502                         val8 |= BEACON_DISABLE_TSF_UPDATE;
4503                         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4504
4505                         /* Disable RX of data frames */
4506                         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
4507                         h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
4508                 }
4509                 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
4510                 rtl8723a_h2c_cmd(priv, &h2c);
4511         }
4512
4513         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4514                 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
4515                         bss_conf->use_short_preamble);
4516                 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4517                 if (bss_conf->use_short_preamble)
4518                         val32 |= RSR_ACK_SHORT_PREAMBLE;
4519                 else
4520                         val32 &= ~RSR_ACK_SHORT_PREAMBLE;
4521                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4522         }
4523
4524         if (changed & BSS_CHANGED_ERP_SLOT) {
4525                 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
4526                         bss_conf->use_short_slot);
4527
4528                 if (bss_conf->use_short_slot)
4529                         val8 = 9;
4530                 else
4531                         val8 = 20;
4532                 rtl8xxxu_write8(priv, REG_SLOT, val8);
4533         }
4534
4535         if (changed & BSS_CHANGED_BSSID) {
4536                 dev_dbg(dev, "Changed BSSID!\n");
4537                 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
4538         }
4539
4540         if (changed & BSS_CHANGED_BASIC_RATES) {
4541                 dev_dbg(dev, "Changed BASIC_RATES!\n");
4542                 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
4543         }
4544 error:
4545         return;
4546 }
4547
4548 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
4549 {
4550         u32 rtlqueue;
4551
4552         switch (queue) {
4553         case IEEE80211_AC_VO:
4554                 rtlqueue = TXDESC_QUEUE_VO;
4555                 break;
4556         case IEEE80211_AC_VI:
4557                 rtlqueue = TXDESC_QUEUE_VI;
4558                 break;
4559         case IEEE80211_AC_BE:
4560                 rtlqueue = TXDESC_QUEUE_BE;
4561                 break;
4562         case IEEE80211_AC_BK:
4563                 rtlqueue = TXDESC_QUEUE_BK;
4564                 break;
4565         default:
4566                 rtlqueue = TXDESC_QUEUE_BE;
4567         }
4568
4569         return rtlqueue;
4570 }
4571
4572 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
4573 {
4574         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4575         u32 queue;
4576
4577         if (ieee80211_is_mgmt(hdr->frame_control))
4578                 queue = TXDESC_QUEUE_MGNT;
4579         else
4580                 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
4581
4582         return queue;
4583 }
4584
4585 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc)
4586 {
4587         __le16 *ptr = (__le16 *)tx_desc;
4588         u16 csum = 0;
4589         int i;
4590
4591         /*
4592          * Clear csum field before calculation, as the csum field is
4593          * in the middle of the struct.
4594          */
4595         tx_desc->csum = cpu_to_le16(0);
4596
4597         for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++)
4598                 csum = csum ^ le16_to_cpu(ptr[i]);
4599
4600         tx_desc->csum |= cpu_to_le16(csum);
4601 }
4602
4603 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
4604 {
4605         struct rtl8xxxu_tx_urb *tx_urb, *tmp;
4606         unsigned long flags;
4607
4608         spin_lock_irqsave(&priv->tx_urb_lock, flags);
4609         list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
4610                 list_del(&tx_urb->list);
4611                 priv->tx_urb_free_count--;
4612                 usb_free_urb(&tx_urb->urb);
4613         }
4614         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4615 }
4616
4617 static struct rtl8xxxu_tx_urb *
4618 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
4619 {
4620         struct rtl8xxxu_tx_urb *tx_urb;
4621         unsigned long flags;
4622
4623         spin_lock_irqsave(&priv->tx_urb_lock, flags);
4624         tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
4625                                           struct rtl8xxxu_tx_urb, list);
4626         if (tx_urb) {
4627                 list_del(&tx_urb->list);
4628                 priv->tx_urb_free_count--;
4629                 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
4630                     !priv->tx_stopped) {
4631                         priv->tx_stopped = true;
4632                         ieee80211_stop_queues(priv->hw);
4633                 }
4634         }
4635
4636         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4637
4638         return tx_urb;
4639 }
4640
4641 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
4642                                  struct rtl8xxxu_tx_urb *tx_urb)
4643 {
4644         unsigned long flags;
4645
4646         INIT_LIST_HEAD(&tx_urb->list);
4647
4648         spin_lock_irqsave(&priv->tx_urb_lock, flags);
4649
4650         list_add(&tx_urb->list, &priv->tx_urb_free_list);
4651         priv->tx_urb_free_count++;
4652         if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
4653             priv->tx_stopped) {
4654                 priv->tx_stopped = false;
4655                 ieee80211_wake_queues(priv->hw);
4656         }
4657
4658         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4659 }
4660
4661 static void rtl8xxxu_tx_complete(struct urb *urb)
4662 {
4663         struct sk_buff *skb = (struct sk_buff *)urb->context;
4664         struct ieee80211_tx_info *tx_info;
4665         struct ieee80211_hw *hw;
4666         struct rtl8xxxu_tx_urb *tx_urb =
4667                 container_of(urb, struct rtl8xxxu_tx_urb, urb);
4668
4669         tx_info = IEEE80211_SKB_CB(skb);
4670         hw = tx_info->rate_driver_data[0];
4671
4672         skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc));
4673
4674         ieee80211_tx_info_clear_status(tx_info);
4675         tx_info->status.rates[0].idx = -1;
4676         tx_info->status.rates[0].count = 0;
4677
4678         if (!urb->status)
4679                 tx_info->flags |= IEEE80211_TX_STAT_ACK;
4680
4681         ieee80211_tx_status_irqsafe(hw, skb);
4682
4683         rtl8xxxu_free_tx_urb(hw->priv, tx_urb);
4684 }
4685
4686 static void rtl8xxxu_dump_action(struct device *dev,
4687                                  struct ieee80211_hdr *hdr)
4688 {
4689         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
4690         u16 cap, timeout;
4691
4692         if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
4693                 return;
4694
4695         switch (mgmt->u.action.u.addba_resp.action_code) {
4696         case WLAN_ACTION_ADDBA_RESP:
4697                 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
4698                 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
4699                 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
4700                          "timeout %i, tid %02x, buf_size %02x, policy %02x, "
4701                          "status %02x\n",
4702                          timeout,
4703                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4704                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4705                          (cap >> 1) & 0x1,
4706                          le16_to_cpu(mgmt->u.action.u.addba_resp.status));
4707                 break;
4708         case WLAN_ACTION_ADDBA_REQ:
4709                 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
4710                 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
4711                 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
4712                          "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
4713                          timeout,
4714                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4715                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4716                          (cap >> 1) & 0x1);
4717                 break;
4718         default:
4719                 dev_info(dev, "action frame %02x\n",
4720                          mgmt->u.action.u.addba_resp.action_code);
4721                 break;
4722         }
4723 }
4724
4725 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
4726                         struct ieee80211_tx_control *control,
4727                         struct sk_buff *skb)
4728 {
4729         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4730         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
4731         struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
4732         struct rtl8xxxu_priv *priv = hw->priv;
4733         struct rtl8xxxu_tx_desc *tx_desc;
4734         struct rtl8xxxu_tx_urb *tx_urb;
4735         struct ieee80211_sta *sta = NULL;
4736         struct ieee80211_vif *vif = tx_info->control.vif;
4737         struct device *dev = &priv->udev->dev;
4738         u32 queue, rate;
4739         u16 pktlen = skb->len;
4740         u16 seq_number;
4741         u16 rate_flag = tx_info->control.rates[0].flags;
4742         int ret;
4743
4744         if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) {
4745                 dev_warn(dev,
4746                          "%s: Not enough headroom (%i) for tx descriptor\n",
4747                          __func__, skb_headroom(skb));
4748                 goto error;
4749         }
4750
4751         if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) {
4752                 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
4753                          __func__, skb->len);
4754                 goto error;
4755         }
4756
4757         tx_urb = rtl8xxxu_alloc_tx_urb(priv);
4758         if (!tx_urb) {
4759                 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
4760                 goto error;
4761         }
4762
4763         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
4764                 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
4765                          __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
4766
4767         if (ieee80211_is_action(hdr->frame_control))
4768                 rtl8xxxu_dump_action(dev, hdr);
4769
4770         tx_info->rate_driver_data[0] = hw;
4771
4772         if (control && control->sta)
4773                 sta = control->sta;
4774
4775         tx_desc = (struct rtl8xxxu_tx_desc *)
4776                 skb_push(skb, sizeof(struct rtl8xxxu_tx_desc));
4777
4778         memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc));
4779         tx_desc->pkt_size = cpu_to_le16(pktlen);
4780         tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc);
4781
4782         tx_desc->txdw0 =
4783                 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
4784         if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
4785             is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
4786                 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
4787
4788         queue = rtl8xxxu_queue_select(hw, skb);
4789         tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
4790
4791         if (tx_info->control.hw_key) {
4792                 switch (tx_info->control.hw_key->cipher) {
4793                 case WLAN_CIPHER_SUITE_WEP40:
4794                 case WLAN_CIPHER_SUITE_WEP104:
4795                 case WLAN_CIPHER_SUITE_TKIP:
4796                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
4797                         break;
4798                 case WLAN_CIPHER_SUITE_CCMP:
4799                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
4800                         break;
4801                 default:
4802                         break;
4803                 }
4804         }
4805
4806         seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4807         tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
4808
4809         if (rate_flag & IEEE80211_TX_RC_MCS)
4810                 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
4811         else
4812                 rate = tx_rate->hw_value;
4813         tx_desc->txdw5 = cpu_to_le32(rate);
4814
4815         if (ieee80211_is_data(hdr->frame_control))
4816                 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
4817
4818         /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
4819         if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
4820                 if (sta->ht_cap.ht_supported) {
4821                         u32 ampdu, val32;
4822
4823                         ampdu = (u32)sta->ht_cap.ampdu_density;
4824                         val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
4825                         tx_desc->txdw2 |= cpu_to_le32(val32);
4826                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE);
4827                 } else
4828                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
4829         } else
4830                 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
4831
4832         if (ieee80211_is_data_qos(hdr->frame_control))
4833                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
4834         if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
4835             (sta && vif && vif->bss_conf.use_short_preamble))
4836                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
4837         if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
4838             (ieee80211_is_data_qos(hdr->frame_control) &&
4839              sta && sta->ht_cap.cap &
4840              (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
4841                 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
4842         }
4843         if (ieee80211_is_mgmt(hdr->frame_control)) {
4844                 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
4845                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE);
4846                 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT);
4847                 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE);
4848         }
4849
4850         if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
4851                 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
4852                 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
4853                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE);
4854                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE);
4855         }
4856
4857         rtl8xxxu_calc_tx_desc_csum(tx_desc);
4858
4859         usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
4860                           skb->data, skb->len, rtl8xxxu_tx_complete, skb);
4861
4862         usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
4863         ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
4864         if (ret) {
4865                 usb_unanchor_urb(&tx_urb->urb);
4866                 rtl8xxxu_free_tx_urb(priv, tx_urb);
4867                 goto error;
4868         }
4869         return;
4870 error:
4871         dev_kfree_skb(skb);
4872 }
4873
4874 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
4875                                        struct ieee80211_rx_status *rx_status,
4876                                        struct rtl8xxxu_rx_desc *rx_desc,
4877                                        struct rtl8723au_phy_stats *phy_stats)
4878 {
4879         if (phy_stats->sgi_en)
4880                 rx_status->flag |= RX_FLAG_SHORT_GI;
4881
4882         if (rx_desc->rxmcs < DESC_RATE_6M) {
4883                 /*
4884                  * Handle PHY stats for CCK rates
4885                  */
4886                 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
4887
4888                 switch (cck_agc_rpt & 0xc0) {
4889                 case 0xc0:
4890                         rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
4891                         break;
4892                 case 0x80:
4893                         rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
4894                         break;
4895                 case 0x40:
4896                         rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
4897                         break;
4898                 case 0x00:
4899                         rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
4900                         break;
4901                 }
4902         } else {
4903                 rx_status->signal =
4904                         (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
4905         }
4906 }
4907
4908 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
4909 {
4910         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
4911         unsigned long flags;
4912
4913         spin_lock_irqsave(&priv->rx_urb_lock, flags);
4914
4915         list_for_each_entry_safe(rx_urb, tmp,
4916                                  &priv->rx_urb_pending_list, list) {
4917                 list_del(&rx_urb->list);
4918                 priv->rx_urb_pending_count--;
4919                 usb_free_urb(&rx_urb->urb);
4920         }
4921
4922         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
4923 }
4924
4925 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
4926                                   struct rtl8xxxu_rx_urb *rx_urb)
4927 {
4928         struct sk_buff *skb;
4929         unsigned long flags;
4930         int pending = 0;
4931
4932         spin_lock_irqsave(&priv->rx_urb_lock, flags);
4933
4934         if (!priv->shutdown) {
4935                 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
4936                 priv->rx_urb_pending_count++;
4937                 pending = priv->rx_urb_pending_count;
4938         } else {
4939                 skb = (struct sk_buff *)rx_urb->urb.context;
4940                 dev_kfree_skb(skb);
4941                 usb_free_urb(&rx_urb->urb);
4942         }
4943
4944         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
4945
4946         if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
4947                 schedule_work(&priv->rx_urb_wq);
4948 }
4949
4950 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
4951 {
4952         struct rtl8xxxu_priv *priv;
4953         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
4954         struct list_head local;
4955         struct sk_buff *skb;
4956         unsigned long flags;
4957         int ret;
4958
4959         priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
4960         INIT_LIST_HEAD(&local);
4961
4962         spin_lock_irqsave(&priv->rx_urb_lock, flags);
4963
4964         list_splice_init(&priv->rx_urb_pending_list, &local);
4965         priv->rx_urb_pending_count = 0;
4966
4967         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
4968
4969         list_for_each_entry_safe(rx_urb, tmp, &local, list) {
4970                 list_del_init(&rx_urb->list);
4971                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
4972                 /*
4973                  * If out of memory or temporary error, put it back on the
4974                  * queue and try again. Otherwise the device is dead/gone
4975                  * and we should drop it.
4976                  */
4977                 switch (ret) {
4978                 case 0:
4979                         break;
4980                 case -ENOMEM:
4981                 case -EAGAIN:
4982                         rtl8xxxu_queue_rx_urb(priv, rx_urb);
4983                         break;
4984                 default:
4985                         pr_info("failed to requeue urb %i\n", ret);
4986                         skb = (struct sk_buff *)rx_urb->urb.context;
4987                         dev_kfree_skb(skb);
4988                         usb_free_urb(&rx_urb->urb);
4989                 }
4990         }
4991 }
4992
4993 static void rtl8xxxu_rx_complete(struct urb *urb)
4994 {
4995         struct rtl8xxxu_rx_urb *rx_urb =
4996                 container_of(urb, struct rtl8xxxu_rx_urb, urb);
4997         struct ieee80211_hw *hw = rx_urb->hw;
4998         struct rtl8xxxu_priv *priv = hw->priv;
4999         struct sk_buff *skb = (struct sk_buff *)urb->context;
5000         struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
5001         struct rtl8723au_phy_stats *phy_stats;
5002         struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
5003         struct ieee80211_mgmt *mgmt;
5004         struct device *dev = &priv->udev->dev;
5005         __le32 *_rx_desc_le = (__le32 *)skb->data;
5006         u32 *_rx_desc = (u32 *)skb->data;
5007         int cnt, len, drvinfo_sz, desc_shift, i;
5008
5009         for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
5010                 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5011
5012         cnt = rx_desc->frag;
5013         len = rx_desc->pktlen;
5014         drvinfo_sz = rx_desc->drvinfo_sz * 8;
5015         desc_shift = rx_desc->shift;
5016         skb_put(skb, urb->actual_length);
5017
5018         if (urb->status == 0) {
5019                 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
5020                 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5021
5022                 skb_pull(skb, drvinfo_sz + desc_shift);
5023
5024                 mgmt = (struct ieee80211_mgmt *)skb->data;
5025
5026                 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5027
5028                 if (rx_desc->phy_stats)
5029                         rtl8xxxu_rx_parse_phystats(priv, rx_status,
5030                                                    rx_desc, phy_stats);
5031
5032                 rx_status->freq = hw->conf.chandef.chan->center_freq;
5033                 rx_status->band = hw->conf.chandef.chan->band;
5034
5035                 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
5036                 rx_status->flag |= RX_FLAG_MACTIME_START;
5037
5038                 if (!rx_desc->swdec)
5039                         rx_status->flag |= RX_FLAG_DECRYPTED;
5040                 if (rx_desc->crc32)
5041                         rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5042                 if (rx_desc->bw)
5043                         rx_status->flag |= RX_FLAG_40MHZ;
5044
5045                 if (rx_desc->rxht) {
5046                         rx_status->flag |= RX_FLAG_HT;
5047                         rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5048                 } else {
5049                         rx_status->rate_idx = rx_desc->rxmcs;
5050                 }
5051
5052                 ieee80211_rx_irqsafe(hw, skb);
5053                 skb = NULL;
5054                 rx_urb->urb.context = NULL;
5055                 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5056         } else {
5057                 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5058                 goto cleanup;
5059         }
5060         return;
5061
5062 cleanup:
5063         usb_free_urb(urb);
5064         dev_kfree_skb(skb);
5065         return;
5066 }
5067
5068 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
5069                                   struct rtl8xxxu_rx_urb *rx_urb)
5070 {
5071         struct sk_buff *skb;
5072         int skb_size;
5073         int ret;
5074
5075         skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
5076         skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
5077         if (!skb)
5078                 return -ENOMEM;
5079
5080         memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
5081         usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
5082                           skb_size, rtl8xxxu_rx_complete, skb);
5083         usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
5084         ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
5085         if (ret)
5086                 usb_unanchor_urb(&rx_urb->urb);
5087         return ret;
5088 }
5089
5090 static void rtl8xxxu_int_complete(struct urb *urb)
5091 {
5092         struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
5093         struct device *dev = &priv->udev->dev;
5094         int ret;
5095
5096         dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5097         if (urb->status == 0) {
5098                 usb_anchor_urb(urb, &priv->int_anchor);
5099                 ret = usb_submit_urb(urb, GFP_ATOMIC);
5100                 if (ret)
5101                         usb_unanchor_urb(urb);
5102         } else {
5103                 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
5104         }
5105 }
5106
5107
5108 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
5109 {
5110         struct rtl8xxxu_priv *priv = hw->priv;
5111         struct urb *urb;
5112         u32 val32;
5113         int ret;
5114
5115         urb = usb_alloc_urb(0, GFP_KERNEL);
5116         if (!urb)
5117                 return -ENOMEM;
5118
5119         usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
5120                          priv->int_buf, USB_INTR_CONTENT_LENGTH,
5121                          rtl8xxxu_int_complete, priv, 1);
5122         usb_anchor_urb(urb, &priv->int_anchor);
5123         ret = usb_submit_urb(urb, GFP_KERNEL);
5124         if (ret) {
5125                 usb_unanchor_urb(urb);
5126                 goto error;
5127         }
5128
5129         val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
5130         val32 |= USB_HIMR_CPWM;
5131         rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
5132
5133 error:
5134         return ret;
5135 }
5136
5137 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
5138                                   struct ieee80211_vif *vif)
5139 {
5140         struct rtl8xxxu_priv *priv = hw->priv;
5141         int ret;
5142         u8 val8;
5143
5144         switch (vif->type) {
5145         case NL80211_IFTYPE_STATION:
5146                 rtl8723a_stop_tx_beacon(priv);
5147
5148                 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5149                 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
5150                         BEACON_DISABLE_TSF_UPDATE;
5151                 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5152                 ret = 0;
5153                 break;
5154         default:
5155                 ret = -EOPNOTSUPP;
5156         }
5157
5158         rtl8xxxu_set_linktype(priv, vif->type);
5159
5160         return ret;
5161 }
5162
5163 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
5164                                       struct ieee80211_vif *vif)
5165 {
5166         struct rtl8xxxu_priv *priv = hw->priv;
5167
5168         dev_dbg(&priv->udev->dev, "%s\n", __func__);
5169 }
5170
5171 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
5172 {
5173         struct rtl8xxxu_priv *priv = hw->priv;
5174         struct device *dev = &priv->udev->dev;
5175         u16 val16;
5176         int ret = 0, channel;
5177         bool ht40;
5178
5179         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
5180                 dev_info(dev,
5181                          "%s: channel: %i (changed %08x chandef.width %02x)\n",
5182                          __func__, hw->conf.chandef.chan->hw_value,
5183                          changed, hw->conf.chandef.width);
5184
5185         if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
5186                 val16 = ((hw->conf.long_frame_max_tx_count <<
5187                           RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
5188                         ((hw->conf.short_frame_max_tx_count <<
5189                           RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
5190                 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
5191         }
5192
5193         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
5194                 switch (hw->conf.chandef.width) {
5195                 case NL80211_CHAN_WIDTH_20_NOHT:
5196                 case NL80211_CHAN_WIDTH_20:
5197                         ht40 = false;
5198                         break;
5199                 case NL80211_CHAN_WIDTH_40:
5200                         ht40 = true;
5201                         break;
5202                 default:
5203                         ret = -ENOTSUPP;
5204                         goto exit;
5205                 }
5206
5207                 channel = hw->conf.chandef.chan->hw_value;
5208
5209                 rtl8723a_set_tx_power(priv, channel, ht40);
5210
5211                 rtl8723au_config_channel(hw);
5212         }
5213
5214 exit:
5215         return ret;
5216 }
5217
5218 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
5219                             struct ieee80211_vif *vif, u16 queue,
5220                             const struct ieee80211_tx_queue_params *param)
5221 {
5222         struct rtl8xxxu_priv *priv = hw->priv;
5223         struct device *dev = &priv->udev->dev;
5224         u32 val32;
5225         u8 aifs, acm_ctrl, acm_bit;
5226
5227         aifs = param->aifs;
5228
5229         val32 = aifs |
5230                 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
5231                 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
5232                 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
5233
5234         acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
5235         dev_dbg(dev,
5236                 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
5237                 __func__, queue, val32, param->acm, acm_ctrl);
5238
5239         switch (queue) {
5240         case IEEE80211_AC_VO:
5241                 acm_bit = ACM_HW_CTRL_VO;
5242                 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
5243                 break;
5244         case IEEE80211_AC_VI:
5245                 acm_bit = ACM_HW_CTRL_VI;
5246                 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
5247                 break;
5248         case IEEE80211_AC_BE:
5249                 acm_bit = ACM_HW_CTRL_BE;
5250                 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
5251                 break;
5252         case IEEE80211_AC_BK:
5253                 acm_bit = ACM_HW_CTRL_BK;
5254                 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
5255                 break;
5256         default:
5257                 acm_bit = 0;
5258                 break;
5259         }
5260
5261         if (param->acm)
5262                 acm_ctrl |= acm_bit;
5263         else
5264                 acm_ctrl &= ~acm_bit;
5265         rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
5266
5267         return 0;
5268 }
5269
5270 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
5271                                       unsigned int changed_flags,
5272                                       unsigned int *total_flags, u64 multicast)
5273 {
5274         struct rtl8xxxu_priv *priv = hw->priv;
5275
5276         dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
5277                 __func__, changed_flags, *total_flags);
5278
5279         *total_flags &= (FIF_ALLMULTI | FIF_CONTROL | FIF_BCN_PRBRESP_PROMISC);
5280 }
5281
5282 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
5283 {
5284         if (rts > 2347)
5285                 return -EINVAL;
5286
5287         return 0;
5288 }
5289
5290 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5291                             struct ieee80211_vif *vif,
5292                             struct ieee80211_sta *sta,
5293                             struct ieee80211_key_conf *key)
5294 {
5295         struct rtl8xxxu_priv *priv = hw->priv;
5296         struct device *dev = &priv->udev->dev;
5297         u8 mac_addr[ETH_ALEN];
5298         u8 val8;
5299         u16 val16;
5300         u32 val32;
5301         int retval = -EOPNOTSUPP;
5302
5303         dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
5304                 __func__, cmd, key->cipher, key->keyidx);
5305
5306         if (vif->type != NL80211_IFTYPE_STATION)
5307                 return -EOPNOTSUPP;
5308
5309         if (key->keyidx > 3)
5310                 return -EOPNOTSUPP;
5311
5312         switch (key->cipher) {
5313         case WLAN_CIPHER_SUITE_WEP40:
5314         case WLAN_CIPHER_SUITE_WEP104:
5315
5316                 break;
5317         case WLAN_CIPHER_SUITE_CCMP:
5318                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
5319                 break;
5320         case WLAN_CIPHER_SUITE_TKIP:
5321                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
5322         default:
5323                 return -EOPNOTSUPP;
5324         }
5325
5326         if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
5327                 dev_dbg(dev, "%s: pairwise key\n", __func__);
5328                 ether_addr_copy(mac_addr, sta->addr);
5329         } else {
5330                 dev_dbg(dev, "%s: group key\n", __func__);
5331                 eth_broadcast_addr(mac_addr);
5332         }
5333
5334         val16 = rtl8xxxu_read16(priv, REG_CR);
5335         val16 |= CR_SECURITY_ENABLE;
5336         rtl8xxxu_write16(priv, REG_CR, val16);
5337
5338         val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
5339                 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
5340         val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
5341         rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
5342
5343         switch (cmd) {
5344         case SET_KEY:
5345                 key->hw_key_idx = key->keyidx;
5346                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
5347                 rtl8xxxu_cam_write(priv, key, mac_addr);
5348                 retval = 0;
5349                 break;
5350         case DISABLE_KEY:
5351                 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
5352                 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
5353                         key->keyidx << CAM_CMD_KEY_SHIFT;
5354                 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
5355                 retval = 0;
5356                 break;
5357         default:
5358                 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
5359         }
5360
5361         return retval;
5362 }
5363
5364 static int
5365 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5366                       enum ieee80211_ampdu_mlme_action action,
5367                       struct ieee80211_sta *sta, u16 tid, u16 *ssn, u8 buf_size,
5368                       bool amsdu)
5369 {
5370         struct rtl8xxxu_priv *priv = hw->priv;
5371         struct device *dev = &priv->udev->dev;
5372         u8 ampdu_factor, ampdu_density;
5373
5374         switch (action) {
5375         case IEEE80211_AMPDU_TX_START:
5376                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
5377                 ampdu_factor = sta->ht_cap.ampdu_factor;
5378                 ampdu_density = sta->ht_cap.ampdu_density;
5379                 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
5380                 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
5381                 dev_dbg(dev,
5382                         "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
5383                         ampdu_factor, ampdu_density);
5384                 break;
5385         case IEEE80211_AMPDU_TX_STOP_FLUSH:
5386                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
5387                 rtl8xxxu_set_ampdu_factor(priv, 0);
5388                 rtl8xxxu_set_ampdu_min_space(priv, 0);
5389                 break;
5390         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
5391                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
5392                          __func__);
5393                 rtl8xxxu_set_ampdu_factor(priv, 0);
5394                 rtl8xxxu_set_ampdu_min_space(priv, 0);
5395                 break;
5396         case IEEE80211_AMPDU_RX_START:
5397                 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
5398                 break;
5399         case IEEE80211_AMPDU_RX_STOP:
5400                 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
5401                 break;
5402         default:
5403                 break;
5404         }
5405         return 0;
5406 }
5407
5408 static int rtl8xxxu_start(struct ieee80211_hw *hw)
5409 {
5410         struct rtl8xxxu_priv *priv = hw->priv;
5411         struct rtl8xxxu_rx_urb *rx_urb;
5412         struct rtl8xxxu_tx_urb *tx_urb;
5413         unsigned long flags;
5414         int ret, i;
5415
5416         ret = 0;
5417
5418         init_usb_anchor(&priv->rx_anchor);
5419         init_usb_anchor(&priv->tx_anchor);
5420         init_usb_anchor(&priv->int_anchor);
5421
5422         rtl8723a_enable_rf(priv);
5423         ret = rtl8xxxu_submit_int_urb(hw);
5424         if (ret)
5425                 goto exit;
5426
5427         for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
5428                 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
5429                 if (!tx_urb) {
5430                         if (!i)
5431                                 ret = -ENOMEM;
5432
5433                         goto error_out;
5434                 }
5435                 usb_init_urb(&tx_urb->urb);
5436                 INIT_LIST_HEAD(&tx_urb->list);
5437                 tx_urb->hw = hw;
5438                 list_add(&tx_urb->list, &priv->tx_urb_free_list);
5439                 priv->tx_urb_free_count++;
5440         }
5441
5442         priv->tx_stopped = false;
5443
5444         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5445         priv->shutdown = false;
5446         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5447
5448         for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
5449                 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
5450                 if (!rx_urb) {
5451                         if (!i)
5452                                 ret = -ENOMEM;
5453
5454                         goto error_out;
5455                 }
5456                 usb_init_urb(&rx_urb->urb);
5457                 INIT_LIST_HEAD(&rx_urb->list);
5458                 rx_urb->hw = hw;
5459
5460                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5461         }
5462 exit:
5463         /*
5464          * Disable all data frames
5465          */
5466         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5467         /*
5468          * Accept all mgmt frames
5469          */
5470         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
5471
5472         rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
5473
5474         return ret;
5475
5476 error_out:
5477         rtl8xxxu_free_tx_resources(priv);
5478         /*
5479          * Disable all data and mgmt frames
5480          */
5481         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5482         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5483
5484         return ret;
5485 }
5486
5487 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
5488 {
5489         struct rtl8xxxu_priv *priv = hw->priv;
5490         unsigned long flags;
5491
5492         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5493
5494         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5495         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5496
5497         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5498         priv->shutdown = true;
5499         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5500
5501         usb_kill_anchored_urbs(&priv->rx_anchor);
5502         usb_kill_anchored_urbs(&priv->tx_anchor);
5503         usb_kill_anchored_urbs(&priv->int_anchor);
5504
5505         rtl8723a_disable_rf(priv);
5506
5507         /*
5508          * Disable interrupts
5509          */
5510         rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
5511
5512         rtl8xxxu_free_rx_resources(priv);
5513         rtl8xxxu_free_tx_resources(priv);
5514 }
5515
5516 static const struct ieee80211_ops rtl8xxxu_ops = {
5517         .tx = rtl8xxxu_tx,
5518         .add_interface = rtl8xxxu_add_interface,
5519         .remove_interface = rtl8xxxu_remove_interface,
5520         .config = rtl8xxxu_config,
5521         .conf_tx = rtl8xxxu_conf_tx,
5522         .bss_info_changed = rtl8xxxu_bss_info_changed,
5523         .configure_filter = rtl8xxxu_configure_filter,
5524         .set_rts_threshold = rtl8xxxu_set_rts_threshold,
5525         .start = rtl8xxxu_start,
5526         .stop = rtl8xxxu_stop,
5527         .sw_scan_start = rtl8xxxu_sw_scan_start,
5528         .sw_scan_complete = rtl8xxxu_sw_scan_complete,
5529         .set_key = rtl8xxxu_set_key,
5530         .ampdu_action = rtl8xxxu_ampdu_action,
5531 };
5532
5533 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
5534                               struct usb_interface *interface)
5535 {
5536         struct usb_interface_descriptor *interface_desc;
5537         struct usb_host_interface *host_interface;
5538         struct usb_endpoint_descriptor *endpoint;
5539         struct device *dev = &priv->udev->dev;
5540         int i, j = 0, endpoints;
5541         u8 dir, xtype, num;
5542         int ret = 0;
5543
5544         host_interface = &interface->altsetting[0];
5545         interface_desc = &host_interface->desc;
5546         endpoints = interface_desc->bNumEndpoints;
5547
5548         for (i = 0; i < endpoints; i++) {
5549                 endpoint = &host_interface->endpoint[i].desc;
5550
5551                 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
5552                 num = usb_endpoint_num(endpoint);
5553                 xtype = usb_endpoint_type(endpoint);
5554                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5555                         dev_dbg(dev,
5556                                 "%s: endpoint: dir %02x, # %02x, type %02x\n",
5557                                 __func__, dir, num, xtype);
5558                 if (usb_endpoint_dir_in(endpoint) &&
5559                     usb_endpoint_xfer_bulk(endpoint)) {
5560                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5561                                 dev_dbg(dev, "%s: in endpoint num %i\n",
5562                                         __func__, num);
5563
5564                         if (priv->pipe_in) {
5565                                 dev_warn(dev,
5566                                          "%s: Too many IN pipes\n", __func__);
5567                                 ret = -EINVAL;
5568                                 goto exit;
5569                         }
5570
5571                         priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
5572                 }
5573
5574                 if (usb_endpoint_dir_in(endpoint) &&
5575                     usb_endpoint_xfer_int(endpoint)) {
5576                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5577                                 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
5578                                         __func__, num);
5579
5580                         if (priv->pipe_interrupt) {
5581                                 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
5582                                          __func__);
5583                                 ret = -EINVAL;
5584                                 goto exit;
5585                         }
5586
5587                         priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
5588                 }
5589
5590                 if (usb_endpoint_dir_out(endpoint) &&
5591                     usb_endpoint_xfer_bulk(endpoint)) {
5592                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5593                                 dev_dbg(dev, "%s: out endpoint num %i\n",
5594                                         __func__, num);
5595                         if (j >= RTL8XXXU_OUT_ENDPOINTS) {
5596                                 dev_warn(dev,
5597                                          "%s: Too many OUT pipes\n", __func__);
5598                                 ret = -EINVAL;
5599                                 goto exit;
5600                         }
5601                         priv->out_ep[j++] = num;
5602                 }
5603         }
5604 exit:
5605         priv->nr_out_eps = j;
5606         return ret;
5607 }
5608
5609 static int rtl8xxxu_probe(struct usb_interface *interface,
5610                           const struct usb_device_id *id)
5611 {
5612         struct rtl8xxxu_priv *priv;
5613         struct ieee80211_hw *hw;
5614         struct usb_device *udev;
5615         struct ieee80211_supported_band *sband;
5616         int ret = 0;
5617         int untested = 1;
5618
5619         udev = usb_get_dev(interface_to_usbdev(interface));
5620
5621         switch (id->idVendor) {
5622         case USB_VENDOR_ID_REALTEK:
5623                 switch(id->idProduct) {
5624                 case 0x1724:
5625                 case 0x8176:
5626                 case 0x8178:
5627                 case 0x817f:
5628                         untested = 0;
5629                         break;
5630                 }
5631                 break;
5632         case 0x7392:
5633                 if (id->idProduct == 0x7811)
5634                         untested = 0;
5635                 break;
5636         default:
5637                 break;
5638         }
5639
5640         if (untested) {
5641                 rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
5642                 dev_info(&udev->dev,
5643                          "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
5644                          id->idVendor, id->idProduct);
5645                 dev_info(&udev->dev,
5646                          "Please report results to Jes.Sorensen@gmail.com\n");
5647         }
5648
5649         hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
5650         if (!hw) {
5651                 ret = -ENOMEM;
5652                 goto exit;
5653         }
5654
5655         priv = hw->priv;
5656         priv->hw = hw;
5657         priv->udev = udev;
5658         priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
5659         mutex_init(&priv->usb_buf_mutex);
5660         mutex_init(&priv->h2c_mutex);
5661         INIT_LIST_HEAD(&priv->tx_urb_free_list);
5662         spin_lock_init(&priv->tx_urb_lock);
5663         INIT_LIST_HEAD(&priv->rx_urb_pending_list);
5664         spin_lock_init(&priv->rx_urb_lock);
5665         INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
5666
5667         usb_set_intfdata(interface, hw);
5668
5669         ret = rtl8xxxu_parse_usb(priv, interface);
5670         if (ret)
5671                 goto exit;
5672
5673         ret = rtl8xxxu_identify_chip(priv);
5674         if (ret) {
5675                 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
5676                 goto exit;
5677         }
5678
5679         ret = rtl8xxxu_read_efuse(priv);
5680         if (ret) {
5681                 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
5682                 goto exit;
5683         }
5684
5685         ret = priv->fops->parse_efuse(priv);
5686         if (ret) {
5687                 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
5688                 goto exit;
5689         }
5690
5691         rtl8xxxu_print_chipinfo(priv);
5692
5693         ret = priv->fops->load_firmware(priv);
5694         if (ret) {
5695                 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
5696                 goto exit;
5697         }
5698
5699         ret = rtl8xxxu_init_device(hw);
5700
5701         hw->wiphy->max_scan_ssids = 1;
5702         hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
5703         hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
5704         hw->queues = 4;
5705
5706         sband = &rtl8xxxu_supported_band;
5707         sband->ht_cap.ht_supported = true;
5708         sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
5709         sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
5710         sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
5711         memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
5712         sband->ht_cap.mcs.rx_mask[0] = 0xff;
5713         sband->ht_cap.mcs.rx_mask[4] = 0x01;
5714         if (priv->rf_paths > 1) {
5715                 sband->ht_cap.mcs.rx_mask[1] = 0xff;
5716                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
5717         }
5718         sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
5719         /*
5720          * Some APs will negotiate HT20_40 in a noisy environment leading
5721          * to miserable performance. Rather than defaulting to this, only
5722          * enable it if explicitly requested at module load time.
5723          */
5724         if (rtl8xxxu_ht40_2g) {
5725                 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
5726                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
5727         }
5728         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
5729
5730         hw->wiphy->rts_threshold = 2347;
5731
5732         SET_IEEE80211_DEV(priv->hw, &interface->dev);
5733         SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
5734
5735         hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc);
5736         ieee80211_hw_set(hw, SIGNAL_DBM);
5737         /*
5738          * The firmware handles rate control
5739          */
5740         ieee80211_hw_set(hw, HAS_RATE_CONTROL);
5741         ieee80211_hw_set(hw, AMPDU_AGGREGATION);
5742
5743         ret = ieee80211_register_hw(priv->hw);
5744         if (ret) {
5745                 dev_err(&udev->dev, "%s: Failed to register: %i\n",
5746                         __func__, ret);
5747                 goto exit;
5748         }
5749
5750 exit:
5751         if (ret < 0)
5752                 usb_put_dev(udev);
5753         return ret;
5754 }
5755
5756 static void rtl8xxxu_disconnect(struct usb_interface *interface)
5757 {
5758         struct rtl8xxxu_priv *priv;
5759         struct ieee80211_hw *hw;
5760
5761         hw = usb_get_intfdata(interface);
5762         priv = hw->priv;
5763
5764         rtl8xxxu_disable_device(hw);
5765         usb_set_intfdata(interface, NULL);
5766
5767         dev_info(&priv->udev->dev, "disconnecting\n");
5768
5769         ieee80211_unregister_hw(hw);
5770
5771         kfree(priv->fw_data);
5772         mutex_destroy(&priv->usb_buf_mutex);
5773         mutex_destroy(&priv->h2c_mutex);
5774
5775         usb_put_dev(priv->udev);
5776         ieee80211_free_hw(hw);
5777 }
5778
5779 static struct rtl8xxxu_fileops rtl8723au_fops = {
5780         .parse_efuse = rtl8723au_parse_efuse,
5781         .load_firmware = rtl8723au_load_firmware,
5782         .power_on = rtl8723au_power_on,
5783         .writeN_block_size = 1024,
5784 };
5785
5786 static struct rtl8xxxu_fileops rtl8192cu_fops = {
5787         .parse_efuse = rtl8192cu_parse_efuse,
5788         .load_firmware = rtl8192cu_load_firmware,
5789         .power_on = rtl8192cu_power_on,
5790         .writeN_block_size = 128,
5791 };
5792
5793 static struct usb_device_id dev_table[] = {
5794 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
5795         .driver_info = (unsigned long)&rtl8723au_fops},
5796 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
5797         .driver_info = (unsigned long)&rtl8723au_fops},
5798 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
5799         .driver_info = (unsigned long)&rtl8723au_fops},
5800 #ifdef CONFIG_RTL8XXXU_UNTESTED
5801 /* Still supported by rtlwifi */
5802 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
5803         .driver_info = (unsigned long)&rtl8192cu_fops},
5804 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
5805         .driver_info = (unsigned long)&rtl8192cu_fops},
5806 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
5807         .driver_info = (unsigned long)&rtl8192cu_fops},
5808 /* Tested by Larry Finger */
5809 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
5810         .driver_info = (unsigned long)&rtl8192cu_fops},
5811 /* Currently untested 8188 series devices */
5812 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
5813         .driver_info = (unsigned long)&rtl8192cu_fops},
5814 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
5815         .driver_info = (unsigned long)&rtl8192cu_fops},
5816 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
5817         .driver_info = (unsigned long)&rtl8192cu_fops},
5818 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
5819         .driver_info = (unsigned long)&rtl8192cu_fops},
5820 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
5821         .driver_info = (unsigned long)&rtl8192cu_fops},
5822 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
5823         .driver_info = (unsigned long)&rtl8192cu_fops},
5824 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
5825         .driver_info = (unsigned long)&rtl8192cu_fops},
5826 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
5827         .driver_info = (unsigned long)&rtl8192cu_fops},
5828 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
5829         .driver_info = (unsigned long)&rtl8192cu_fops},
5830 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
5831         .driver_info = (unsigned long)&rtl8192cu_fops},
5832 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
5833         .driver_info = (unsigned long)&rtl8192cu_fops},
5834 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
5835         .driver_info = (unsigned long)&rtl8192cu_fops},
5836 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
5837         .driver_info = (unsigned long)&rtl8192cu_fops},
5838 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
5839         .driver_info = (unsigned long)&rtl8192cu_fops},
5840 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
5841         .driver_info = (unsigned long)&rtl8192cu_fops},
5842 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
5843         .driver_info = (unsigned long)&rtl8192cu_fops},
5844 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
5845         .driver_info = (unsigned long)&rtl8192cu_fops},
5846 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
5847         .driver_info = (unsigned long)&rtl8192cu_fops},
5848 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
5849         .driver_info = (unsigned long)&rtl8192cu_fops},
5850 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
5851         .driver_info = (unsigned long)&rtl8192cu_fops},
5852 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
5853         .driver_info = (unsigned long)&rtl8192cu_fops},
5854 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
5855         .driver_info = (unsigned long)&rtl8192cu_fops},
5856 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
5857         .driver_info = (unsigned long)&rtl8192cu_fops},
5858 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
5859         .driver_info = (unsigned long)&rtl8192cu_fops},
5860 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
5861         .driver_info = (unsigned long)&rtl8192cu_fops},
5862 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
5863         .driver_info = (unsigned long)&rtl8192cu_fops},
5864 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
5865         .driver_info = (unsigned long)&rtl8192cu_fops},
5866 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
5867         .driver_info = (unsigned long)&rtl8192cu_fops},
5868 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
5869         .driver_info = (unsigned long)&rtl8192cu_fops},
5870 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
5871         .driver_info = (unsigned long)&rtl8192cu_fops},
5872 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
5873         .driver_info = (unsigned long)&rtl8192cu_fops},
5874 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
5875         .driver_info = (unsigned long)&rtl8192cu_fops},
5876 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
5877         .driver_info = (unsigned long)&rtl8192cu_fops},
5878 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
5879         .driver_info = (unsigned long)&rtl8192cu_fops}, /* Netcore 8188RU */
5880 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
5881         .driver_info = (unsigned long)&rtl8192cu_fops},
5882 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
5883         .driver_info = (unsigned long)&rtl8192cu_fops},
5884 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
5885         .driver_info = (unsigned long)&rtl8192cu_fops},
5886 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
5887         .driver_info = (unsigned long)&rtl8192cu_fops},
5888 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
5889         .driver_info = (unsigned long)&rtl8192cu_fops},
5890 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
5891         .driver_info = (unsigned long)&rtl8192cu_fops},
5892 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
5893         .driver_info = (unsigned long)&rtl8192cu_fops},
5894 /* Currently untested 8192 series devices */
5895 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
5896         .driver_info = (unsigned long)&rtl8192cu_fops},
5897 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
5898         .driver_info = (unsigned long)&rtl8192cu_fops},
5899 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
5900         .driver_info = (unsigned long)&rtl8192cu_fops},
5901 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
5902         .driver_info = (unsigned long)&rtl8192cu_fops},
5903 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
5904         .driver_info = (unsigned long)&rtl8192cu_fops},
5905 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
5906         .driver_info = (unsigned long)&rtl8192cu_fops},
5907 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
5908         .driver_info = (unsigned long)&rtl8192cu_fops},
5909 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
5910         .driver_info = (unsigned long)&rtl8192cu_fops},
5911 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
5912         .driver_info = (unsigned long)&rtl8192cu_fops},
5913 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
5914         .driver_info = (unsigned long)&rtl8192cu_fops},
5915 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
5916         .driver_info = (unsigned long)&rtl8192cu_fops},
5917 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
5918         .driver_info = (unsigned long)&rtl8192cu_fops},
5919 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
5920         .driver_info = (unsigned long)&rtl8192cu_fops},
5921 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
5922         .driver_info = (unsigned long)&rtl8192cu_fops},
5923 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
5924         .driver_info = (unsigned long)&rtl8192cu_fops},
5925 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
5926         .driver_info = (unsigned long)&rtl8192cu_fops},
5927 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
5928         .driver_info = (unsigned long)&rtl8192cu_fops},
5929 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
5930         .driver_info = (unsigned long)&rtl8192cu_fops},
5931 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
5932         .driver_info = (unsigned long)&rtl8192cu_fops},
5933 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
5934         .driver_info = (unsigned long)&rtl8192cu_fops},
5935 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
5936         .driver_info = (unsigned long)&rtl8192cu_fops},
5937 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
5938         .driver_info = (unsigned long)&rtl8192cu_fops},
5939 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
5940         .driver_info = (unsigned long)&rtl8192cu_fops},
5941 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
5942         .driver_info = (unsigned long)&rtl8192cu_fops},
5943 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
5944         .driver_info = (unsigned long)&rtl8192cu_fops},
5945 #endif
5946 { }
5947 };
5948
5949 static struct usb_driver rtl8xxxu_driver = {
5950         .name = DRIVER_NAME,
5951         .probe = rtl8xxxu_probe,
5952         .disconnect = rtl8xxxu_disconnect,
5953         .id_table = dev_table,
5954         .disable_hub_initiated_lpm = 1,
5955 };
5956
5957 static int __init rtl8xxxu_module_init(void)
5958 {
5959         int res;
5960
5961         res = usb_register(&rtl8xxxu_driver);
5962         if (res < 0)
5963                 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
5964
5965         return res;
5966 }
5967
5968 static void __exit rtl8xxxu_module_exit(void)
5969 {
5970         usb_deregister(&rtl8xxxu_driver);
5971 }
5972
5973
5974 MODULE_DEVICE_TABLE(usb, dev_table);
5975
5976 module_init(rtl8xxxu_module_init);
5977 module_exit(rtl8xxxu_module_exit);