drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c

   1 /*
   2  * RTL8XXXU mac80211 USB driver
   3  *
   4  * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
   5  *
   6  * Portions, notably calibration code:
   7  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   8  *
   9  * This driver was written as a replacement for the vendor provided
  10  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
  11  * their programming interface, I have started adding support for
  12  * additional 8xxx chips like the 8192cu, 8188cus, etc.
  13  *
  14  * This program is free software; you can redistribute it and/or modify it
  15  * under the terms of version 2 of the GNU General Public License as
  16  * published by the Free Software Foundation.
  17  *
  18  * This program is distributed in the hope that it will be useful, but WITHOUT
  19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  21  * more details.
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/kernel.h>
  26 #include <linux/sched.h>
  27 #include <linux/errno.h>
  28 #include <linux/slab.h>
  29 #include <linux/module.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/list.h>
  32 #include <linux/usb.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/wireless.h>
  37 #include <linux/firmware.h>
  38 #include <linux/moduleparam.h>
  39 #include <net/mac80211.h>
  40 #include "rtl8xxxu.h"
  41 #include "rtl8xxxu_regs.h"
  42
  43 #define DRIVER_NAME "rtl8xxxu"
  44
  45 static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
  46 static bool rtl8xxxu_ht40_2g;
  47
  48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
  49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
  50 MODULE_LICENSE("GPL");
  51 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
  52 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
  53 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
  54 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
  55 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
  56 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
  57 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
  58 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
  59 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
  60
  61 module_param_named(debug, rtl8xxxu_debug, int, 0600);
  62 MODULE_PARM_DESC(debug, "Set debug mask");
  63 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
  64 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
  65
  66 #define USB_VENDOR_ID_REALTEK           0x0bda
  67 /* Minimum IEEE80211_MAX_FRAME_LEN */
  68 #define RTL_RX_BUFFER_SIZE              IEEE80211_MAX_FRAME_LEN
  69 #define RTL8XXXU_RX_URBS                32
  70 #define RTL8XXXU_RX_URB_PENDING_WATER   8
  71 #define RTL8XXXU_TX_URBS                64
  72 #define RTL8XXXU_TX_URB_LOW_WATER       25
  73 #define RTL8XXXU_TX_URB_HIGH_WATER      32
  74
  75 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
  76                                   struct rtl8xxxu_rx_urb *rx_urb);
  77
  78 static struct ieee80211_rate rtl8xxxu_rates[] = {
  79         { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
  80         { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
  81         { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
  82         { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
  83         { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
  84         { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
  85         { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
  86         { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
  87         { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
  88         { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
  89         { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
  90         { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
  91 };
  92
  93 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
  94         { .band = NL80211_BAND_2GHZ, .center_freq = 2412,
  95           .hw_value = 1, .max_power = 30 },
  96         { .band = NL80211_BAND_2GHZ, .center_freq = 2417,
  97           .hw_value = 2, .max_power = 30 },
  98         { .band = NL80211_BAND_2GHZ, .center_freq = 2422,
  99           .hw_value = 3, .max_power = 30 },
 100         { .band = NL80211_BAND_2GHZ, .center_freq = 2427,
 101           .hw_value = 4, .max_power = 30 },
 102         { .band = NL80211_BAND_2GHZ, .center_freq = 2432,
 103           .hw_value = 5, .max_power = 30 },
 104         { .band = NL80211_BAND_2GHZ, .center_freq = 2437,
 105           .hw_value = 6, .max_power = 30 },
 106         { .band = NL80211_BAND_2GHZ, .center_freq = 2442,
 107           .hw_value = 7, .max_power = 30 },
 108         { .band = NL80211_BAND_2GHZ, .center_freq = 2447,
 109           .hw_value = 8, .max_power = 30 },
 110         { .band = NL80211_BAND_2GHZ, .center_freq = 2452,
 111           .hw_value = 9, .max_power = 30 },
 112         { .band = NL80211_BAND_2GHZ, .center_freq = 2457,
 113           .hw_value = 10, .max_power = 30 },
 114         { .band = NL80211_BAND_2GHZ, .center_freq = 2462,
 115           .hw_value = 11, .max_power = 30 },
 116         { .band = NL80211_BAND_2GHZ, .center_freq = 2467,
 117           .hw_value = 12, .max_power = 30 },
 118         { .band = NL80211_BAND_2GHZ, .center_freq = 2472,
 119           .hw_value = 13, .max_power = 30 },
 120         { .band = NL80211_BAND_2GHZ, .center_freq = 2484,
 121           .hw_value = 14, .max_power = 30 }
 122 };
 123
 124 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
 125         .channels = rtl8xxxu_channels_2g,
 126         .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
 127         .bitrates = rtl8xxxu_rates,
 128         .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
 129 };
 130
 131 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
 132         {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
 133         {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
 134         {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
 135         {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
 136         {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
 137         {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
 138         {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
 139         {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
 140         {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
 141         {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
 142         {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
 143         {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
 144         {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
 145         {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
 146         {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
 147         {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
 148         {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
 149         {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
 150         {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
 151         {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
 152         {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
 153         {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
 154 };
 155
 156 static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
 157         {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
 158         {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
 159         {0x430, 0x00}, {0x431, 0x00},
 160         {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
 161         {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
 162         {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
 163         {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
 164         {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
 165         {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
 166         {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
 167         {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
 168         {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
 169         {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
 170         {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
 171         {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
 172         {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
 173         {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
 174         {0x516, 0x0a}, {0x525, 0x4f},
 175         {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
 176         {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
 177         {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
 178         {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
 179         {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
 180         {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
 181         {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
 182         {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
 183         {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
 184         {0xffff, 0xff},
 185 };
 186
 187 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
 188         {0x800, 0x80040000}, {0x804, 0x00000003},
 189         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 190         {0x810, 0x10001331}, {0x814, 0x020c3d10},
 191         {0x818, 0x02200385}, {0x81c, 0x00000000},
 192         {0x820, 0x01000100}, {0x824, 0x00390004},
 193         {0x828, 0x00000000}, {0x82c, 0x00000000},
 194         {0x830, 0x00000000}, {0x834, 0x00000000},
 195         {0x838, 0x00000000}, {0x83c, 0x00000000},
 196         {0x840, 0x00010000}, {0x844, 0x00000000},
 197         {0x848, 0x00000000}, {0x84c, 0x00000000},
 198         {0x850, 0x00000000}, {0x854, 0x00000000},
 199         {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
 200         {0x860, 0x66f60110}, {0x864, 0x061f0130},
 201         {0x868, 0x00000000}, {0x86c, 0x32323200},
 202         {0x870, 0x07000760}, {0x874, 0x22004000},
 203         {0x878, 0x00000808}, {0x87c, 0x00000000},
 204         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 205         {0x888, 0x00000000}, {0x88c, 0xccc000c0},
 206         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 207         {0x898, 0x40302010}, {0x89c, 0x00706050},
 208         {0x900, 0x00000000}, {0x904, 0x00000023},
 209         {0x908, 0x00000000}, {0x90c, 0x81121111},
 210         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 211         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 212         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 213         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 214         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 215         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 216         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 217         {0xa78, 0x00000900},
 218         {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
 219         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 220         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 221         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 222         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 223         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 224         {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
 225         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 226         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 227         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 228         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 229         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 230         {0xc60, 0x00000000}, {0xc64, 0x7112848b},
 231         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 232         {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
 233         {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
 234         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 235         {0xc88, 0x40000100}, {0xc8c, 0x20200000},
 236         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 237         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 238         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 239         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 240         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 241         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 242         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 243         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 244         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 245         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 246         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 247         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 248         {0xd00, 0x00080740}, {0xd04, 0x00020401},
 249         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 250         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 251         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 252         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 253         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 254         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 255         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 256         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 257         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 258         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 259         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 260         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 261         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 262         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 263         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 264         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 265         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 266         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 267         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 268         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 269         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 270         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 271         {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
 272         {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
 273         {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
 274         {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
 275         {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
 276         {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
 277         {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
 278         {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
 279         {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
 280         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 281         {0xf00, 0x00000300},
 282         {0xffff, 0xffffffff},
 283 };
 284
 285 static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
 286         {0x800, 0x80040000}, {0x804, 0x00000003},
 287         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 288         {0x810, 0x10001331}, {0x814, 0x020c3d10},
 289         {0x818, 0x02200385}, {0x81c, 0x00000000},
 290         {0x820, 0x01000100}, {0x824, 0x00190204},
 291         {0x828, 0x00000000}, {0x82c, 0x00000000},
 292         {0x830, 0x00000000}, {0x834, 0x00000000},
 293         {0x838, 0x00000000}, {0x83c, 0x00000000},
 294         {0x840, 0x00010000}, {0x844, 0x00000000},
 295         {0x848, 0x00000000}, {0x84c, 0x00000000},
 296         {0x850, 0x00000000}, {0x854, 0x00000000},
 297         {0x858, 0x569a11a9}, {0x85c, 0x01000014},
 298         {0x860, 0x66f60110}, {0x864, 0x061f0649},
 299         {0x868, 0x00000000}, {0x86c, 0x27272700},
 300         {0x870, 0x07000760}, {0x874, 0x25004000},
 301         {0x878, 0x00000808}, {0x87c, 0x00000000},
 302         {0x880, 0xb0000c1c}, {0x884, 0x00000001},
 303         {0x888, 0x00000000}, {0x88c, 0xccc000c0},
 304         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 305         {0x898, 0x40302010}, {0x89c, 0x00706050},
 306         {0x900, 0x00000000}, {0x904, 0x00000023},
 307         {0x908, 0x00000000}, {0x90c, 0x81121111},
 308         {0x910, 0x00000002}, {0x914, 0x00000201},
 309         {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
 310         {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
 311         {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
 312         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 313         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 314         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 315         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 316         {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
 317         {0xa80, 0x21806490}, {0xb2c, 0x00000000},
 318         {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
 319         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 320         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 321         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 322         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 323         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 324         {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
 325         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 326         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 327         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 328         {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
 329         {0xc58, 0x00013149}, {0xc5c, 0x00250492},
 330         {0xc60, 0x00000000}, {0xc64, 0x7112848b},
 331         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 332         {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
 333         {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
 334         {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
 335         {0xc88, 0x40000100}, {0xc8c, 0x20200000},
 336         {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
 337         {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
 338         {0xca0, 0x00000000}, {0xca4, 0x000300a0},
 339         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 340         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 341         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 342         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 343         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 344         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 345         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 346         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 347         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 348         {0xd00, 0x00000740}, {0xd04, 0x40020401},
 349         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 350         {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
 351         {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
 352         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 353         {0xd38, 0x00000000}, {0xd3c, 0x00127353},
 354         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 355         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 356         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 357         {0xd58, 0x00000282}, {0xd5c, 0x30032064},
 358         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 359         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 360         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 361         {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
 362         {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
 363         {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
 364         {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
 365         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 366         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 367         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 368         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 369         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 370         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 371         {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
 372         {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
 373         {0xe70, 0x00c00096}, {0xe74, 0x01000056},
 374         {0xe78, 0x01000014}, {0xe7c, 0x01000056},
 375         {0xe80, 0x01000014}, {0xe84, 0x00c00096},
 376         {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
 377         {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
 378         {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
 379         {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
 380         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 381         {0xf00, 0x00000300},
 382         {0x820, 0x01000100}, {0x800, 0x83040000},
 383         {0xffff, 0xffffffff},
 384 };
 385
 386 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
 387         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 388         {0x800, 0x80040002}, {0x804, 0x00000003},
 389         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 390         {0x810, 0x10000330}, {0x814, 0x020c3d10},
 391         {0x818, 0x02200385}, {0x81c, 0x00000000},
 392         {0x820, 0x01000100}, {0x824, 0x00390004},
 393         {0x828, 0x01000100}, {0x82c, 0x00390004},
 394         {0x830, 0x27272727}, {0x834, 0x27272727},
 395         {0x838, 0x27272727}, {0x83c, 0x27272727},
 396         {0x840, 0x00010000}, {0x844, 0x00010000},
 397         {0x848, 0x27272727}, {0x84c, 0x27272727},
 398         {0x850, 0x00000000}, {0x854, 0x00000000},
 399         {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
 400         {0x860, 0x66e60230}, {0x864, 0x061f0130},
 401         {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
 402         {0x870, 0x07000700}, {0x874, 0x22184000},
 403         {0x878, 0x08080808}, {0x87c, 0x00000000},
 404         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 405         {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
 406         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 407         {0x898, 0x40302010}, {0x89c, 0x00706050},
 408         {0x900, 0x00000000}, {0x904, 0x00000023},
 409         {0x908, 0x00000000}, {0x90c, 0x81121313},
 410         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 411         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 412         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 413         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 414         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 415         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 416         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 417         {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
 418         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 419         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 420         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 421         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 422         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 423         {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
 424         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 425         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 426         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 427         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 428         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 429         {0xc60, 0x00000000}, {0xc64, 0x5116848b},
 430         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 431         {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
 432         {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
 433         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 434         {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
 435         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 436         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 437         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 438         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 439         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 440         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 441         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 442         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 443         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 444         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 445         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 446         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 447         {0xd00, 0x00080740}, {0xd04, 0x00020403},
 448         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 449         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 450         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 451         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 452         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 453         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 454         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 455         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 456         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 457         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 458         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 459         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 460         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 461         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 462         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 463         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 464         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 465         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 466         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 467         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 468         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 469         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 470         {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
 471         {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
 472         {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
 473         {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
 474         {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
 475         {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
 476         {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
 477         {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
 478         {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
 479         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 480         {0xf00, 0x00000300},
 481         {0xffff, 0xffffffff},
 482 };
 483
 484 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
 485         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 486         {0x040, 0x000c0004}, {0x800, 0x80040000},
 487         {0x804, 0x00000001}, {0x808, 0x0000fc00},
 488         {0x80c, 0x0000000a}, {0x810, 0x10005388},
 489         {0x814, 0x020c3d10}, {0x818, 0x02200385},
 490         {0x81c, 0x00000000}, {0x820, 0x01000100},
 491         {0x824, 0x00390204}, {0x828, 0x00000000},
 492         {0x82c, 0x00000000}, {0x830, 0x00000000},
 493         {0x834, 0x00000000}, {0x838, 0x00000000},
 494         {0x83c, 0x00000000}, {0x840, 0x00010000},
 495         {0x844, 0x00000000}, {0x848, 0x00000000},
 496         {0x84c, 0x00000000}, {0x850, 0x00000000},
 497         {0x854, 0x00000000}, {0x858, 0x569a569a},
 498         {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
 499         {0x864, 0x061f0130}, {0x868, 0x00000000},
 500         {0x86c, 0x20202000}, {0x870, 0x03000300},
 501         {0x874, 0x22004000}, {0x878, 0x00000808},
 502         {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
 503         {0x884, 0x000004d5}, {0x888, 0x00000000},
 504         {0x88c, 0xccc000c0}, {0x890, 0x00000800},
 505         {0x894, 0xfffffffe}, {0x898, 0x40302010},
 506         {0x89c, 0x00706050}, {0x900, 0x00000000},
 507         {0x904, 0x00000023}, {0x908, 0x00000000},
 508         {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
 509         {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
 510         {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
 511         {0xa14, 0x11144028}, {0xa18, 0x00881117},
 512         {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
 513         {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
 514         {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
 515         {0xa74, 0x00000007}, {0xc00, 0x48071d40},
 516         {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
 517         {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
 518         {0xc14, 0x40000100}, {0xc18, 0x08800000},
 519         {0xc1c, 0x40000100}, {0xc20, 0x00000000},
 520         {0xc24, 0x00000000}, {0xc28, 0x00000000},
 521         {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
 522         {0xc34, 0x469652cf}, {0xc38, 0x49795994},
 523         {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
 524         {0xc44, 0x000100b7}, {0xc48, 0xec020107},
 525         {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
 526         {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
 527         {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
 528         {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
 529         {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
 530         {0xc74, 0x018610db}, {0xc78, 0x0000001f},
 531         {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
 532         {0xc84, 0x20f60000}, {0xc88, 0x24000090},
 533         {0xc8c, 0x20200000}, {0xc90, 0x00121820},
 534         {0xc94, 0x00000000}, {0xc98, 0x00121820},
 535         {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
 536         {0xca4, 0x00000080}, {0xca8, 0x00000000},
 537         {0xcac, 0x00000000}, {0xcb0, 0x00000000},
 538         {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
 539         {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
 540         {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
 541         {0xccc, 0x00000000}, {0xcd0, 0x00000000},
 542         {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
 543         {0xcdc, 0x00766932}, {0xce0, 0x00222222},
 544         {0xce4, 0x00000000}, {0xce8, 0x37644302},
 545         {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
 546         {0xd04, 0x00020401}, {0xd08, 0x0000907f},
 547         {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
 548         {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
 549         {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
 550         {0xd34, 0x80608000}, {0xd38, 0x00000000},
 551         {0xd3c, 0x00027293}, {0xd40, 0x00000000},
 552         {0xd44, 0x00000000}, {0xd48, 0x00000000},
 553         {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
 554         {0xd54, 0x00000000}, {0xd58, 0x00000000},
 555         {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
 556         {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
 557         {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
 558         {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
 559         {0xe00, 0x24242424}, {0xe04, 0x24242424},
 560         {0xe08, 0x03902024}, {0xe10, 0x24242424},
 561         {0xe14, 0x24242424}, {0xe18, 0x24242424},
 562         {0xe1c, 0x24242424}, {0xe28, 0x00000000},
 563         {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
 564         {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
 565         {0xe40, 0x01007c00}, {0xe44, 0x01004800},
 566         {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
 567         {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
 568         {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
 569         {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
 570         {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
 571         {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
 572         {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
 573         {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
 574         {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
 575         {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
 576         {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
 577         {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
 578         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 579         {0xf00, 0x00000300},
 580         {0xffff, 0xffffffff},
 581 };
 582
 583 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
 584         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 585         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 586         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 587         {0xc78, 0x7a060001}, {0xc78, 0x79070001},
 588         {0xc78, 0x78080001}, {0xc78, 0x77090001},
 589         {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
 590         {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
 591         {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
 592         {0xc78, 0x70100001}, {0xc78, 0x6f110001},
 593         {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
 594         {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
 595         {0xc78, 0x6a160001}, {0xc78, 0x69170001},
 596         {0xc78, 0x68180001}, {0xc78, 0x67190001},
 597         {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
 598         {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
 599         {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
 600         {0xc78, 0x60200001}, {0xc78, 0x49210001},
 601         {0xc78, 0x48220001}, {0xc78, 0x47230001},
 602         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 603         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 604         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 605         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 606         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 607         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 608         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 609         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 610         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 611         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 612         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 613         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 614         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 615         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 616         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 617         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 618         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 619         {0xc78, 0x7a460001}, {0xc78, 0x79470001},
 620         {0xc78, 0x78480001}, {0xc78, 0x77490001},
 621         {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
 622         {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
 623         {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
 624         {0xc78, 0x70500001}, {0xc78, 0x6f510001},
 625         {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
 626         {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
 627         {0xc78, 0x6a560001}, {0xc78, 0x69570001},
 628         {0xc78, 0x68580001}, {0xc78, 0x67590001},
 629         {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
 630         {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
 631         {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
 632         {0xc78, 0x60600001}, {0xc78, 0x49610001},
 633         {0xc78, 0x48620001}, {0xc78, 0x47630001},
 634         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 635         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 636         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 637         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 638         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 639         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 640         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 641         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 642         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 643         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 644         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 645         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 646         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 647         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 648         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 649         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 650         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 651         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 652         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 653         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 654         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 655         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 656         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 657         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 658         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 659         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 660         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 661         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 662         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 663         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 664         {0xffff, 0xffffffff}
 665 };
 666
 667 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
 668         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 669         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 670         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 671         {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
 672         {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
 673         {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
 674         {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
 675         {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
 676         {0xc78, 0x73100001}, {0xc78, 0x72110001},
 677         {0xc78, 0x71120001}, {0xc78, 0x70130001},
 678         {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
 679         {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
 680         {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
 681         {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
 682         {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
 683         {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
 684         {0xc78, 0x63200001}, {0xc78, 0x62210001},
 685         {0xc78, 0x61220001}, {0xc78, 0x60230001},
 686         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 687         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 688         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 689         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 690         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 691         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 692         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 693         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 694         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 695         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 696         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 697         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 698         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 699         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 700         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 701         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 702         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 703         {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
 704         {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
 705         {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
 706         {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
 707         {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
 708         {0xc78, 0x73500001}, {0xc78, 0x72510001},
 709         {0xc78, 0x71520001}, {0xc78, 0x70530001},
 710         {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
 711         {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
 712         {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
 713         {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
 714         {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
 715         {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
 716         {0xc78, 0x63600001}, {0xc78, 0x62610001},
 717         {0xc78, 0x61620001}, {0xc78, 0x60630001},
 718         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 719         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 720         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 721         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 722         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 723         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 724         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 725         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 726         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 727         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 728         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 729         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 730         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 731         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 732         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 733         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 734         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 735         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 736         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 737         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 738         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 739         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 740         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 741         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 742         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 743         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 744         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 745         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 746         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 747         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 748         {0xffff, 0xffffffff}
 749 };
 750
 751 static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
 752         {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
 753         {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
 754         {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
 755         {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
 756         {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
 757         {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
 758         {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
 759         {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
 760         {0xc78, 0xed100001}, {0xc78, 0xec110001},
 761         {0xc78, 0xeb120001}, {0xc78, 0xea130001},
 762         {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
 763         {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
 764         {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
 765         {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
 766         {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
 767         {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
 768         {0xc78, 0x65200001}, {0xc78, 0x64210001},
 769         {0xc78, 0x63220001}, {0xc78, 0x4a230001},
 770         {0xc78, 0x49240001}, {0xc78, 0x48250001},
 771         {0xc78, 0x47260001}, {0xc78, 0x46270001},
 772         {0xc78, 0x45280001}, {0xc78, 0x44290001},
 773         {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
 774         {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
 775         {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
 776         {0xc78, 0x0a300001}, {0xc78, 0x09310001},
 777         {0xc78, 0x08320001}, {0xc78, 0x07330001},
 778         {0xc78, 0x06340001}, {0xc78, 0x05350001},
 779         {0xc78, 0x04360001}, {0xc78, 0x03370001},
 780         {0xc78, 0x02380001}, {0xc78, 0x01390001},
 781         {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
 782         {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
 783         {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
 784         {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
 785         {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
 786         {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
 787         {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
 788         {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
 789         {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
 790         {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
 791         {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
 792         {0xc78, 0xec500001}, {0xc78, 0xeb510001},
 793         {0xc78, 0xea520001}, {0xc78, 0xe9530001},
 794         {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
 795         {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
 796         {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
 797         {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
 798         {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
 799         {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
 800         {0xc78, 0x65600001}, {0xc78, 0x64610001},
 801         {0xc78, 0x63620001}, {0xc78, 0x62630001},
 802         {0xc78, 0x61640001}, {0xc78, 0x48650001},
 803         {0xc78, 0x47660001}, {0xc78, 0x46670001},
 804         {0xc78, 0x45680001}, {0xc78, 0x44690001},
 805         {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
 806         {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
 807         {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
 808         {0xc78, 0x24700001}, {0xc78, 0x09710001},
 809         {0xc78, 0x08720001}, {0xc78, 0x07730001},
 810         {0xc78, 0x06740001}, {0xc78, 0x05750001},
 811         {0xc78, 0x04760001}, {0xc78, 0x03770001},
 812         {0xc78, 0x02780001}, {0xc78, 0x01790001},
 813         {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
 814         {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
 815         {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
 816         {0xc50, 0x69553422},
 817         {0xc50, 0x69553420},
 818         {0x824, 0x00390204},
 819         {0xffff, 0xffffffff}
 820 };
 821
 822 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
 823         {0x00, 0x00030159}, {0x01, 0x00031284},
 824         {0x02, 0x00098000}, {0x03, 0x00039c63},
 825         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 826         {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
 827         {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
 828         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 829         {0x19, 0x00000000}, {0x1a, 0x00030355},
 830         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 831         {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
 832         {0x1f, 0x00000000}, {0x20, 0x0000b614},
 833         {0x21, 0x0006c000}, {0x22, 0x00000000},
 834         {0x23, 0x00001558}, {0x24, 0x00000060},
 835         {0x25, 0x00000483}, {0x26, 0x0004f000},
 836         {0x27, 0x000ec7d9}, {0x28, 0x00057730},
 837         {0x29, 0x00004783}, {0x2a, 0x00000001},
 838         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 839         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 840         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 841         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 842         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 843         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 844         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 845         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 846         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 847         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 848         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 849         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 850         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 851         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 852         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 853         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 854         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 855         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 856         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 857         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 858         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 859         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 860         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 861         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 862         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 863         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 864         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 865         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 866         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 867         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 868         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 869         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 870         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 871         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 872         {0x10, 0x00000000}, {0x11, 0x00000000},
 873         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 874         {0x10, 0x0009000f}, {0x11, 0x00023100},
 875         {0x12, 0x00032000}, {0x12, 0x00071000},
 876         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 877         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 878         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 879         {0x13, 0x00018493}, {0x13, 0x0001429b},
 880         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 881         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 882         {0x13, 0x00000020}, {0x14, 0x0001944c},
 883         {0x14, 0x00059444}, {0x14, 0x0009944c},
 884         {0x14, 0x000d9444}, {0x15, 0x0000f474},
 885         {0x15, 0x0004f477}, {0x15, 0x0008f455},
 886         {0x15, 0x000cf455}, {0x16, 0x00000339},
 887         {0x16, 0x00040339}, {0x16, 0x00080339},
 888         {0x16, 0x000c0366}, {0x00, 0x00010159},
 889         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 890         {0xfe, 0x00000000}, {0x1f, 0x00000003},
 891         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 892         {0x1e, 0x00000247}, {0x1f, 0x00000000},
 893         {0x00, 0x00030159},
 894         {0xff, 0xffffffff}
 895 };
 896
 897 static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
 898         {0x00, 0x00010000}, {0xb0, 0x000dffe0},
 899         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 900         {0xfe, 0x00000000}, {0xb1, 0x00000018},
 901         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 902         {0xfe, 0x00000000}, {0xb2, 0x00084c00},
 903         {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
 904         {0xb7, 0x00000010}, {0xb8, 0x0000907f},
 905         {0x5c, 0x00000002}, {0x7c, 0x00000002},
 906         {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
 907         {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
 908         {0x1e, 0x00000000}, {0xdf, 0x00000780},
 909         {0x50, 0x00067435},
 910         /*
 911          * The 8723bu vendor driver indicates that bit 8 should be set in
 912          * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
 913          * they never actually check the package type - and just default
 914          * to not setting it.
 915          */
 916         {0x51, 0x0006b04e},
 917         {0x52, 0x000007d2}, {0x53, 0x00000000},
 918         {0x54, 0x00050400}, {0x55, 0x0004026e},
 919         {0xdd, 0x0000004c}, {0x70, 0x00067435},
 920         /*
 921          * 0x71 has same package type condition as for register 0x51
 922          */
 923         {0x71, 0x0006b04e},
 924         {0x72, 0x000007d2}, {0x73, 0x00000000},
 925         {0x74, 0x00050400}, {0x75, 0x0004026e},
 926         {0xef, 0x00000100}, {0x34, 0x0000add7},
 927         {0x35, 0x00005c00}, {0x34, 0x00009dd4},
 928         {0x35, 0x00005000}, {0x34, 0x00008dd1},
 929         {0x35, 0x00004400}, {0x34, 0x00007dce},
 930         {0x35, 0x00003800}, {0x34, 0x00006cd1},
 931         {0x35, 0x00004400}, {0x34, 0x00005cce},
 932         {0x35, 0x00003800}, {0x34, 0x000048ce},
 933         {0x35, 0x00004400}, {0x34, 0x000034ce},
 934         {0x35, 0x00003800}, {0x34, 0x00002451},
 935         {0x35, 0x00004400}, {0x34, 0x0000144e},
 936         {0x35, 0x00003800}, {0x34, 0x00000051},
 937         {0x35, 0x00004400}, {0xef, 0x00000000},
 938         {0xef, 0x00000100}, {0xed, 0x00000010},
 939         {0x44, 0x0000add7}, {0x44, 0x00009dd4},
 940         {0x44, 0x00008dd1}, {0x44, 0x00007dce},
 941         {0x44, 0x00006cc1}, {0x44, 0x00005cce},
 942         {0x44, 0x000044d1}, {0x44, 0x000034ce},
 943         {0x44, 0x00002451}, {0x44, 0x0000144e},
 944         {0x44, 0x00000051}, {0xef, 0x00000000},
 945         {0xed, 0x00000000}, {0x7f, 0x00020080},
 946         {0xef, 0x00002000}, {0x3b, 0x000380ef},
 947         {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
 948         {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
 949         {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
 950         {0x3b, 0x00000900}, {0xef, 0x00000000},
 951         {0xed, 0x00000001}, {0x40, 0x000380ef},
 952         {0x40, 0x000302fe}, {0x40, 0x00028ce6},
 953         {0x40, 0x000200bc}, {0x40, 0x000188a5},
 954         {0x40, 0x00010fbc}, {0x40, 0x00008f71},
 955         {0x40, 0x00000900}, {0xed, 0x00000000},
 956         {0x82, 0x00080000}, {0x83, 0x00008000},
 957         {0x84, 0x00048d80}, {0x85, 0x00068000},
 958         {0xa2, 0x00080000}, {0xa3, 0x00008000},
 959         {0xa4, 0x00048d80}, {0xa5, 0x00068000},
 960         {0xed, 0x00000002}, {0xef, 0x00000002},
 961         {0x56, 0x00000032}, {0x76, 0x00000032},
 962         {0x01, 0x00000780},
 963         {0xff, 0xffffffff}
 964 };
 965
 966 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
 967         {0x00, 0x00030159}, {0x01, 0x00031284},
 968         {0x02, 0x00098000}, {0x03, 0x00018c63},
 969         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 970         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 971         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 972         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 973         {0x19, 0x00000000}, {0x1a, 0x00010255},
 974         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 975         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
 976         {0x1f, 0x00080001}, {0x20, 0x0000b614},
 977         {0x21, 0x0006c000}, {0x22, 0x00000000},
 978         {0x23, 0x00001558}, {0x24, 0x00000060},
 979         {0x25, 0x00000483}, {0x26, 0x0004f000},
 980         {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
 981         {0x29, 0x00004783}, {0x2a, 0x00000001},
 982         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 983         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 984         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 985         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 986         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 987         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 988         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 989         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 990         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 991         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 992         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 993         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 994         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 995         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 996         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 997         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 998         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 999         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1000         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1001         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1002         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1003         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1004         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1005         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1006         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1007         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1008         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1009         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1010         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1011         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1012         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1013         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1014         {0x10, 0x0002000f}, {0x11, 0x000203f9},
1015         {0x10, 0x0003000f}, {0x11, 0x000ff500},
1016         {0x10, 0x00000000}, {0x11, 0x00000000},
1017         {0x10, 0x0008000f}, {0x11, 0x0003f100},
1018         {0x10, 0x0009000f}, {0x11, 0x00023100},
1019         {0x12, 0x00032000}, {0x12, 0x00071000},
1020         {0x12, 0x000b0000}, {0x12, 0x000fc000},
1021         {0x13, 0x000287b3}, {0x13, 0x000244b7},
1022         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1023         {0x13, 0x00018493}, {0x13, 0x0001429b},
1024         {0x13, 0x00010299}, {0x13, 0x0000c29c},
1025         {0x13, 0x000081a0}, {0x13, 0x000040ac},
1026         {0x13, 0x00000020}, {0x14, 0x0001944c},
1027         {0x14, 0x00059444}, {0x14, 0x0009944c},
1028         {0x14, 0x000d9444}, {0x15, 0x0000f424},
1029         {0x15, 0x0004f424}, {0x15, 0x0008f424},
1030         {0x15, 0x000cf424}, {0x16, 0x000e0330},
1031         {0x16, 0x000a0330}, {0x16, 0x00060330},
1032         {0x16, 0x00020330}, {0x00, 0x00010159},
1033         {0x18, 0x0000f401}, {0xfe, 0x00000000},
1034         {0xfe, 0x00000000}, {0x1f, 0x00080003},
1035         {0xfe, 0x00000000}, {0xfe, 0x00000000},
1036         {0x1e, 0x00044457}, {0x1f, 0x00080000},
1037         {0x00, 0x00030159},
1038         {0xff, 0xffffffff}
1039 };
1040
1041 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
1042         {0x00, 0x00030159}, {0x01, 0x00031284},
1043         {0x02, 0x00098000}, {0x03, 0x00018c63},
1044         {0x04, 0x000210e7}, {0x09, 0x0002044f},
1045         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1046         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1047         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1048         {0x12, 0x00032000}, {0x12, 0x00071000},
1049         {0x12, 0x000b0000}, {0x12, 0x000fc000},
1050         {0x13, 0x000287af}, {0x13, 0x000244b7},
1051         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1052         {0x13, 0x00018493}, {0x13, 0x00014297},
1053         {0x13, 0x00010295}, {0x13, 0x0000c298},
1054         {0x13, 0x0000819c}, {0x13, 0x000040a8},
1055         {0x13, 0x0000001c}, {0x14, 0x0001944c},
1056         {0x14, 0x00059444}, {0x14, 0x0009944c},
1057         {0x14, 0x000d9444}, {0x15, 0x0000f424},
1058         {0x15, 0x0004f424}, {0x15, 0x0008f424},
1059         {0x15, 0x000cf424}, {0x16, 0x000e0330},
1060         {0x16, 0x000a0330}, {0x16, 0x00060330},
1061         {0x16, 0x00020330},
1062         {0xff, 0xffffffff}
1063 };
1064
1065 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
1066         {0x00, 0x00030159}, {0x01, 0x00031284},
1067         {0x02, 0x00098000}, {0x03, 0x00018c63},
1068         {0x04, 0x000210e7}, {0x09, 0x0002044f},
1069         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1070         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1071         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1072         {0x19, 0x00000000}, {0x1a, 0x00010255},
1073         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1074         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1075         {0x1f, 0x00080001}, {0x20, 0x0000b614},
1076         {0x21, 0x0006c000}, {0x22, 0x00000000},
1077         {0x23, 0x00001558}, {0x24, 0x00000060},
1078         {0x25, 0x00000483}, {0x26, 0x0004f000},
1079         {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1080         {0x29, 0x00004783}, {0x2a, 0x00000001},
1081         {0x2b, 0x00021334}, {0x2a, 0x00000000},
1082         {0x2b, 0x00000054}, {0x2a, 0x00000001},
1083         {0x2b, 0x00000808}, {0x2b, 0x00053333},
1084         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1085         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1086         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1087         {0x2b, 0x00000808}, {0x2b, 0x00063333},
1088         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1089         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1090         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1091         {0x2b, 0x00000808}, {0x2b, 0x00073333},
1092         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1093         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1094         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1095         {0x2b, 0x00000709}, {0x2b, 0x00063333},
1096         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1097         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1098         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1099         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1100         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1101         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1102         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1103         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1104         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1105         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1106         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1107         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1108         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1109         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1110         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1111         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1112         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1113         {0x10, 0x0002000f}, {0x11, 0x000203f9},
1114         {0x10, 0x0003000f}, {0x11, 0x000ff500},
1115         {0x10, 0x00000000}, {0x11, 0x00000000},
1116         {0x10, 0x0008000f}, {0x11, 0x0003f100},
1117         {0x10, 0x0009000f}, {0x11, 0x00023100},
1118         {0x12, 0x00032000}, {0x12, 0x00071000},
1119         {0x12, 0x000b0000}, {0x12, 0x000fc000},
1120         {0x13, 0x000287b3}, {0x13, 0x000244b7},
1121         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1122         {0x13, 0x00018493}, {0x13, 0x0001429b},
1123         {0x13, 0x00010299}, {0x13, 0x0000c29c},
1124         {0x13, 0x000081a0}, {0x13, 0x000040ac},
1125         {0x13, 0x00000020}, {0x14, 0x0001944c},
1126         {0x14, 0x00059444}, {0x14, 0x0009944c},
1127         {0x14, 0x000d9444}, {0x15, 0x0000f405},
1128         {0x15, 0x0004f405}, {0x15, 0x0008f405},
1129         {0x15, 0x000cf405}, {0x16, 0x000e0330},
1130         {0x16, 0x000a0330}, {0x16, 0x00060330},
1131         {0x16, 0x00020330}, {0x00, 0x00010159},
1132         {0x18, 0x0000f401}, {0xfe, 0x00000000},
1133         {0xfe, 0x00000000}, {0x1f, 0x00080003},
1134         {0xfe, 0x00000000}, {0xfe, 0x00000000},
1135         {0x1e, 0x00044457}, {0x1f, 0x00080000},
1136         {0x00, 0x00030159},
1137         {0xff, 0xffffffff}
1138 };
1139
1140 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
1141         {0x00, 0x00030159}, {0x01, 0x00031284},
1142         {0x02, 0x00098000}, {0x03, 0x00018c63},
1143         {0x04, 0x000210e7}, {0x09, 0x0002044f},
1144         {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1145         {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1146         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1147         {0x19, 0x00000000}, {0x1a, 0x00000255},
1148         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1149         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1150         {0x1f, 0x00080001}, {0x20, 0x0000b614},
1151         {0x21, 0x0006c000}, {0x22, 0x0000083c},
1152         {0x23, 0x00001558}, {0x24, 0x00000060},
1153         {0x25, 0x00000483}, {0x26, 0x0004f000},
1154         {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1155         {0x29, 0x00004783}, {0x2a, 0x00000001},
1156         {0x2b, 0x00021334}, {0x2a, 0x00000000},
1157         {0x2b, 0x00000054}, {0x2a, 0x00000001},
1158         {0x2b, 0x00000808}, {0x2b, 0x00053333},
1159         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1160         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1161         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1162         {0x2b, 0x00000808}, {0x2b, 0x00063333},
1163         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1164         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1165         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1166         {0x2b, 0x00000808}, {0x2b, 0x00073333},
1167         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1168         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1169         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1170         {0x2b, 0x00000709}, {0x2b, 0x00063333},
1171         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1172         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1173         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1174         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1175         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1176         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1177         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1178         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1179         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1180         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1181         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1182         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1183         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1184         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1185         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1186         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1187         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1188         {0x10, 0x0002000f}, {0x11, 0x000203f9},
1189         {0x10, 0x0003000f}, {0x11, 0x000ff500},
1190         {0x10, 0x00000000}, {0x11, 0x00000000},
1191         {0x10, 0x0008000f}, {0x11, 0x0003f100},
1192         {0x10, 0x0009000f}, {0x11, 0x00023100},
1193         {0x12, 0x000d8000}, {0x12, 0x00090000},
1194         {0x12, 0x00051000}, {0x12, 0x00012000},
1195         {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1196         {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1197         {0x13, 0x000183a4}, {0x13, 0x00014398},
1198         {0x13, 0x000101a4}, {0x13, 0x0000c198},
1199         {0x13, 0x000080a4}, {0x13, 0x00004098},
1200         {0x13, 0x00000000}, {0x14, 0x0001944c},
1201         {0x14, 0x00059444}, {0x14, 0x0009944c},
1202         {0x14, 0x000d9444}, {0x15, 0x0000f405},
1203         {0x15, 0x0004f405}, {0x15, 0x0008f405},
1204         {0x15, 0x000cf405}, {0x16, 0x000e0330},
1205         {0x16, 0x000a0330}, {0x16, 0x00060330},
1206         {0x16, 0x00020330}, {0x00, 0x00010159},
1207         {0x18, 0x0000f401}, {0xfe, 0x00000000},
1208         {0xfe, 0x00000000}, {0x1f, 0x00080003},
1209         {0xfe, 0x00000000}, {0xfe, 0x00000000},
1210         {0x1e, 0x00044457}, {0x1f, 0x00080000},
1211         {0x00, 0x00030159},
1212         {0xff, 0xffffffff}
1213 };
1214
1215 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
1216         {       /* RF_A */
1217                 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
1218                 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
1219                 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
1220                 .hspiread = REG_HSPI_XA_READBACK,
1221                 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
1222                 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
1223         },
1224         {       /* RF_B */
1225                 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
1226                 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
1227                 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
1228                 .hspiread = REG_HSPI_XB_READBACK,
1229                 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
1230                 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
1231         },
1232 };
1233
1234 static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
1235         REG_OFDM0_XA_RX_IQ_IMBALANCE,
1236         REG_OFDM0_XB_RX_IQ_IMBALANCE,
1237         REG_OFDM0_ENERGY_CCA_THRES,
1238         REG_OFDM0_AGCR_SSI_TABLE,
1239         REG_OFDM0_XA_TX_IQ_IMBALANCE,
1240         REG_OFDM0_XB_TX_IQ_IMBALANCE,
1241         REG_OFDM0_XC_TX_AFE,
1242         REG_OFDM0_XD_TX_AFE,
1243         REG_OFDM0_RX_IQ_EXT_ANTA
1244 };
1245
1246 static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
1247 {
1248         struct usb_device *udev = priv->udev;
1249         int len;
1250         u8 data;
1251
1252         mutex_lock(&priv->usb_buf_mutex);
1253         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1254                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1255                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
1256                               RTW_USB_CONTROL_MSG_TIMEOUT);
1257         data = priv->usb_buf.val8;
1258         mutex_unlock(&priv->usb_buf_mutex);
1259
1260         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1261                 dev_info(&udev->dev, "%s(%04x)   = 0x%02x, len %i\n",
1262                          __func__, addr, data, len);
1263         return data;
1264 }
1265
1266 static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
1267 {
1268         struct usb_device *udev = priv->udev;
1269         int len;
1270         u16 data;
1271
1272         mutex_lock(&priv->usb_buf_mutex);
1273         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1274                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1275                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
1276                               RTW_USB_CONTROL_MSG_TIMEOUT);
1277         data = le16_to_cpu(priv->usb_buf.val16);
1278         mutex_unlock(&priv->usb_buf_mutex);
1279
1280         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1281                 dev_info(&udev->dev, "%s(%04x)  = 0x%04x, len %i\n",
1282                          __func__, addr, data, len);
1283         return data;
1284 }
1285
1286 static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1287 {
1288         struct usb_device *udev = priv->udev;
1289         int len;
1290         u32 data;
1291
1292         mutex_lock(&priv->usb_buf_mutex);
1293         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1294                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1295                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
1296                               RTW_USB_CONTROL_MSG_TIMEOUT);
1297         data = le32_to_cpu(priv->usb_buf.val32);
1298         mutex_unlock(&priv->usb_buf_mutex);
1299
1300         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1301                 dev_info(&udev->dev, "%s(%04x)  = 0x%08x, len %i\n",
1302                          __func__, addr, data, len);
1303         return data;
1304 }
1305
1306 static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1307 {
1308         struct usb_device *udev = priv->udev;
1309         int ret;
1310
1311         mutex_lock(&priv->usb_buf_mutex);
1312         priv->usb_buf.val8 = val;
1313         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1314                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1315                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
1316                               RTW_USB_CONTROL_MSG_TIMEOUT);
1317
1318         mutex_unlock(&priv->usb_buf_mutex);
1319
1320         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1321                 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1322                          __func__, addr, val);
1323         return ret;
1324 }
1325
1326 static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1327 {
1328         struct usb_device *udev = priv->udev;
1329         int ret;
1330
1331         mutex_lock(&priv->usb_buf_mutex);
1332         priv->usb_buf.val16 = cpu_to_le16(val);
1333         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1334                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1335                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
1336                               RTW_USB_CONTROL_MSG_TIMEOUT);
1337         mutex_unlock(&priv->usb_buf_mutex);
1338
1339         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1340                 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1341                          __func__, addr, val);
1342         return ret;
1343 }
1344
1345 static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1346 {
1347         struct usb_device *udev = priv->udev;
1348         int ret;
1349
1350         mutex_lock(&priv->usb_buf_mutex);
1351         priv->usb_buf.val32 = cpu_to_le32(val);
1352         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1353                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1354                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
1355                               RTW_USB_CONTROL_MSG_TIMEOUT);
1356         mutex_unlock(&priv->usb_buf_mutex);
1357
1358         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1359                 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1360                          __func__, addr, val);
1361         return ret;
1362 }
1363
1364 static int
1365 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1366 {
1367         struct usb_device *udev = priv->udev;
1368         int blocksize = priv->fops->writeN_block_size;
1369         int ret, i, count, remainder;
1370
1371         count = len / blocksize;
1372         remainder = len % blocksize;
1373
1374         for (i = 0; i < count; i++) {
1375                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1376                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1377                                       addr, 0, buf, blocksize,
1378                                       RTW_USB_CONTROL_MSG_TIMEOUT);
1379                 if (ret != blocksize)
1380                         goto write_error;
1381
1382                 addr += blocksize;
1383                 buf += blocksize;
1384         }
1385
1386         if (remainder) {
1387                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1388                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1389                                       addr, 0, buf, remainder,
1390                                       RTW_USB_CONTROL_MSG_TIMEOUT);
1391                 if (ret != remainder)
1392                         goto write_error;
1393         }
1394
1395         return len;
1396
1397 write_error:
1398         dev_info(&udev->dev,
1399                  "%s: Failed to write block at addr: %04x size: %04x\n",
1400                  __func__, addr, blocksize);
1401         return -EAGAIN;
1402 }
1403
1404 static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1405                                enum rtl8xxxu_rfpath path, u8 reg)
1406 {
1407         u32 hssia, val32, retval;
1408
1409         hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1410         if (path != RF_A)
1411                 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1412         else
1413                 val32 = hssia;
1414
1415         val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1416         val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1417         val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1418         hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1419         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1420
1421         udelay(10);
1422
1423         rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1424         udelay(100);
1425
1426         hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1427         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1428         udelay(10);
1429
1430         val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1431         if (val32 & FPGA0_HSSI_PARM1_PI)
1432                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1433         else
1434                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1435
1436         retval &= 0xfffff;
1437
1438         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1439                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1440                          __func__, reg, retval);
1441         return retval;
1442 }
1443
1444 /*
1445  * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1446  * have write issues in high temperature conditions. We may have to
1447  * retry writing them.
1448  */
1449 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1450                                 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1451 {
1452         int ret, retval;
1453         u32 dataaddr;
1454
1455         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1456                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1457                          __func__, reg, data);
1458
1459         data &= FPGA0_LSSI_PARM_DATA_MASK;
1460         dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1461
1462         /* Use XB for path B */
1463         ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1464         if (ret != sizeof(dataaddr))
1465                 retval = -EIO;
1466         else
1467                 retval = 0;
1468
1469         udelay(1);
1470
1471         return retval;
1472 }
1473
1474 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv,
1475                             struct h2c_cmd *h2c, int len)
1476 {
1477         struct device *dev = &priv->udev->dev;
1478         int mbox_nr, retry, retval = 0;
1479         int mbox_reg, mbox_ext_reg;
1480         u8 val8;
1481
1482         mutex_lock(&priv->h2c_mutex);
1483
1484         mbox_nr = priv->next_mbox;
1485         mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1486         mbox_ext_reg = priv->fops->mbox_ext_reg +
1487                 (mbox_nr * priv->fops->mbox_ext_width);
1488
1489         /*
1490          * MBOX ready?
1491          */
1492         retry = 100;
1493         do {
1494                 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1495                 if (!(val8 & BIT(mbox_nr)))
1496                         break;
1497         } while (retry--);
1498
1499         if (!retry) {
1500                 dev_info(dev, "%s: Mailbox busy\n", __func__);
1501                 retval = -EBUSY;
1502                 goto error;
1503         }
1504
1505         /*
1506          * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1507          */
1508         if (len > sizeof(u32)) {
1509                 if (priv->fops->mbox_ext_width == 4) {
1510                         rtl8xxxu_write32(priv, mbox_ext_reg,
1511                                          le32_to_cpu(h2c->raw_wide.ext));
1512                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1513                                 dev_info(dev, "H2C_EXT %08x\n",
1514                                          le32_to_cpu(h2c->raw_wide.ext));
1515                 } else {
1516                         rtl8xxxu_write16(priv, mbox_ext_reg,
1517                                          le16_to_cpu(h2c->raw.ext));
1518                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1519                                 dev_info(dev, "H2C_EXT %04x\n",
1520                                          le16_to_cpu(h2c->raw.ext));
1521                 }
1522         }
1523         rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1524         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1525                 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1526
1527         priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1528
1529 error:
1530         mutex_unlock(&priv->h2c_mutex);
1531         return retval;
1532 }
1533
1534 static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data)
1535 {
1536         struct h2c_cmd h2c;
1537         int reqnum = 0;
1538
1539         memset(&h2c, 0, sizeof(struct h2c_cmd));
1540         h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1541         h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1542         h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1543         h2c.bt_mp_oper.data = data;
1544         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
1545
1546         reqnum++;
1547         memset(&h2c, 0, sizeof(struct h2c_cmd));
1548         h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1549         h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1550         h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1551         h2c.bt_mp_oper.addr = reg;
1552         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
1553 }
1554
1555 static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1556 {
1557         u8 val8;
1558         u32 val32;
1559
1560         val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1561         val8 |= BIT(0) | BIT(3);
1562         rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1563
1564         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1565         val32 &= ~(BIT(4) | BIT(5));
1566         val32 |= BIT(3);
1567         if (priv->rf_paths == 2) {
1568                 val32 &= ~(BIT(20) | BIT(21));
1569                 val32 |= BIT(19);
1570         }
1571         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1572
1573         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1574         val32 &= ~OFDM_RF_PATH_TX_MASK;
1575         if (priv->tx_paths == 2)
1576                 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1577         else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C)
1578                 val32 |= OFDM_RF_PATH_TX_B;
1579         else
1580                 val32 |= OFDM_RF_PATH_TX_A;
1581         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1582
1583         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1584         val32 &= ~FPGA_RF_MODE_JAPAN;
1585         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1586
1587         if (priv->rf_paths == 2)
1588                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1589         else
1590                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1591
1592         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1593         if (priv->rf_paths == 2)
1594                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1595
1596         rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1597 }
1598
1599 static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1600 {
1601         u8 sps0;
1602         u32 val32;
1603
1604         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1605
1606         sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1607
1608         /* RF RX code for preamble power saving */
1609         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1610         val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1611         if (priv->rf_paths == 2)
1612                 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1613         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1614
1615         /* Disable TX for four paths */
1616         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1617         val32 &= ~OFDM_RF_PATH_TX_MASK;
1618         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1619
1620         /* Enable power saving */
1621         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1622         val32 |= FPGA_RF_MODE_JAPAN;
1623         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1624
1625         /* AFE control register to power down bits [30:22] */
1626         if (priv->rf_paths == 2)
1627                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1628         else
1629                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1630
1631         /* Power down RF module */
1632         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1633         if (priv->rf_paths == 2)
1634                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1635
1636         sps0 &= ~(BIT(0) | BIT(3));
1637         rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1638 }
1639
1640
1641 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1642 {
1643         u8 val8;
1644
1645         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1646         val8 &= ~BIT(6);
1647         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1648
1649         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1650         val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1651         val8 &= ~BIT(0);
1652         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1653 }
1654
1655
1656 /*
1657  * The rtl8723a has 3 channel groups for it's efuse settings. It only
1658  * supports the 2.4GHz band, so channels 1 - 14:
1659  *  group 0: channels 1 - 3
1660  *  group 1: channels 4 - 9
1661  *  group 2: channels 10 - 14
1662  *
1663  * Note: We index from 0 in the code
1664  */
1665 static int rtl8723a_channel_to_group(int channel)
1666 {
1667         int group;
1668
1669         if (channel < 4)
1670                 group = 0;
1671         else if (channel < 10)
1672                 group = 1;
1673         else
1674                 group = 2;
1675
1676         return group;
1677 }
1678
1679 static int rtl8723b_channel_to_group(int channel)
1680 {
1681         int group;
1682
1683         if (channel < 3)
1684                 group = 0;
1685         else if (channel < 6)
1686                 group = 1;
1687         else if (channel < 9)
1688                 group = 2;
1689         else if (channel < 12)
1690                 group = 3;
1691         else
1692                 group = 4;
1693
1694         return group;
1695 }
1696
1697 static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1698 {
1699         struct rtl8xxxu_priv *priv = hw->priv;
1700         u32 val32, rsr;
1701         u8 val8, opmode;
1702         bool ht = true;
1703         int sec_ch_above, channel;
1704         int i;
1705
1706         opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1707         rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1708         channel = hw->conf.chandef.chan->hw_value;
1709
1710         switch (hw->conf.chandef.width) {
1711         case NL80211_CHAN_WIDTH_20_NOHT:
1712                 ht = false;
1713         case NL80211_CHAN_WIDTH_20:
1714                 opmode |= BW_OPMODE_20MHZ;
1715                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1716
1717                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1718                 val32 &= ~FPGA_RF_MODE;
1719                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1720
1721                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1722                 val32 &= ~FPGA_RF_MODE;
1723                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1724
1725                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1726                 val32 |= FPGA0_ANALOG2_20MHZ;
1727                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1728                 break;
1729         case NL80211_CHAN_WIDTH_40:
1730                 if (hw->conf.chandef.center_freq1 >
1731                     hw->conf.chandef.chan->center_freq) {
1732                         sec_ch_above = 1;
1733                         channel += 2;
1734                 } else {
1735                         sec_ch_above = 0;
1736                         channel -= 2;
1737                 }
1738
1739                 opmode &= ~BW_OPMODE_20MHZ;
1740                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1741                 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1742                 if (sec_ch_above)
1743                         rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1744                 else
1745                         rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1746                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1747
1748                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1749                 val32 |= FPGA_RF_MODE;
1750                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1751
1752                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1753                 val32 |= FPGA_RF_MODE;
1754                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1755
1756                 /*
1757                  * Set Control channel to upper or lower. These settings
1758                  * are required only for 40MHz
1759                  */
1760                 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1761                 val32 &= ~CCK0_SIDEBAND;
1762                 if (!sec_ch_above)
1763                         val32 |= CCK0_SIDEBAND;
1764                 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1765
1766                 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1767                 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1768                 if (sec_ch_above)
1769                         val32 |= OFDM_LSTF_PRIME_CH_LOW;
1770                 else
1771                         val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1772                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1773
1774                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1775                 val32 &= ~FPGA0_ANALOG2_20MHZ;
1776                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1777
1778                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1779                 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1780                 if (sec_ch_above)
1781                         val32 |= FPGA0_PS_UPPER_CHANNEL;
1782                 else
1783                         val32 |= FPGA0_PS_LOWER_CHANNEL;
1784                 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1785                 break;
1786
1787         default:
1788                 break;
1789         }
1790
1791         for (i = RF_A; i < priv->rf_paths; i++) {
1792                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1793                 val32 &= ~MODE_AG_CHANNEL_MASK;
1794                 val32 |= channel;
1795                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1796         }
1797
1798         if (ht)
1799                 val8 = 0x0e;
1800         else
1801                 val8 = 0x0a;
1802
1803         rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1804         rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1805
1806         rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1807         rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1808
1809         for (i = RF_A; i < priv->rf_paths; i++) {
1810                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1811                 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1812                         val32 &= ~MODE_AG_CHANNEL_20MHZ;
1813                 else
1814                         val32 |= MODE_AG_CHANNEL_20MHZ;
1815                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1816         }
1817 }
1818
1819 static void rtl8723bu_config_channel(struct ieee80211_hw *hw)
1820 {
1821         struct rtl8xxxu_priv *priv = hw->priv;
1822         u32 val32, rsr;
1823         u8 val8, subchannel;
1824         u16 rf_mode_bw;
1825         bool ht = true;
1826         int sec_ch_above, channel;
1827         int i;
1828
1829         rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
1830         rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
1831         rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1832         channel = hw->conf.chandef.chan->hw_value;
1833
1834 /* Hack */
1835         subchannel = 0;
1836
1837         switch (hw->conf.chandef.width) {
1838         case NL80211_CHAN_WIDTH_20_NOHT:
1839                 ht = false;
1840         case NL80211_CHAN_WIDTH_20:
1841                 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
1842                 subchannel = 0;
1843
1844                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1845                 val32 &= ~FPGA_RF_MODE;
1846                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1847
1848                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1849                 val32 &= ~FPGA_RF_MODE;
1850                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1851
1852                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
1853                 val32 &= ~(BIT(30) | BIT(31));
1854                 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
1855
1856                 break;
1857         case NL80211_CHAN_WIDTH_40:
1858                 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
1859
1860                 if (hw->conf.chandef.center_freq1 >
1861                     hw->conf.chandef.chan->center_freq) {
1862                         sec_ch_above = 1;
1863                         channel += 2;
1864                 } else {
1865                         sec_ch_above = 0;
1866                         channel -= 2;
1867                 }
1868
1869                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1870                 val32 |= FPGA_RF_MODE;
1871                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1872
1873                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1874                 val32 |= FPGA_RF_MODE;
1875                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1876
1877                 /*
1878                  * Set Control channel to upper or lower. These settings
1879                  * are required only for 40MHz
1880                  */
1881                 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1882                 val32 &= ~CCK0_SIDEBAND;
1883                 if (!sec_ch_above)
1884                         val32 |= CCK0_SIDEBAND;
1885                 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1886
1887                 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1888                 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1889                 if (sec_ch_above)
1890                         val32 |= OFDM_LSTF_PRIME_CH_LOW;
1891                 else
1892                         val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1893                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1894
1895                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1896                 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1897                 if (sec_ch_above)
1898                         val32 |= FPGA0_PS_UPPER_CHANNEL;
1899                 else
1900                         val32 |= FPGA0_PS_LOWER_CHANNEL;
1901                 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1902                 break;
1903         case NL80211_CHAN_WIDTH_80:
1904                 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
1905                 break;
1906         default:
1907                 break;
1908         }
1909
1910         for (i = RF_A; i < priv->rf_paths; i++) {
1911                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1912                 val32 &= ~MODE_AG_CHANNEL_MASK;
1913                 val32 |= channel;
1914                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1915         }
1916
1917         rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
1918         rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
1919
1920         if (ht)
1921                 val8 = 0x0e;
1922         else
1923                 val8 = 0x0a;
1924
1925         rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1926         rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1927
1928         rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1929         rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1930
1931         for (i = RF_A; i < priv->rf_paths; i++) {
1932                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1933                 val32 &= ~MODE_AG_BW_MASK;
1934                 switch(hw->conf.chandef.width) {
1935                 case NL80211_CHAN_WIDTH_80:
1936                         val32 |= MODE_AG_BW_80MHZ_8723B;
1937                         break;
1938                 case NL80211_CHAN_WIDTH_40:
1939                         val32 |= MODE_AG_BW_40MHZ_8723B;
1940                         break;
1941                 default:
1942                         val32 |= MODE_AG_BW_20MHZ_8723B;
1943                         break;
1944                 }
1945                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1946         }
1947 }
1948
1949 static void
1950 rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1951 {
1952         u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1953         u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1954         u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1955         u8 val8;
1956         int group, i;
1957
1958         group = rtl8723a_channel_to_group(channel);
1959
1960         cck[0] = priv->cck_tx_power_index_A[group];
1961         cck[1] = priv->cck_tx_power_index_B[group];
1962
1963         ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1964         ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1965
1966         ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1967         ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1968
1969         mcsbase[0] = ofdm[0];
1970         mcsbase[1] = ofdm[1];
1971         if (!ht40) {
1972                 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1973                 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1974         }
1975
1976         if (priv->tx_paths > 1) {
1977                 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1978                         ofdm[0] -=  priv->ht40_2s_tx_power_index_diff[group].a;
1979                 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1980                         ofdm[1] -=  priv->ht40_2s_tx_power_index_diff[group].b;
1981         }
1982
1983         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1984                 dev_info(&priv->udev->dev,
1985                          "%s: Setting TX power CCK A: %02x, "
1986                          "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1987                          __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1988
1989         for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1990                 if (cck[i] > RF6052_MAX_TX_PWR)
1991                         cck[i] = RF6052_MAX_TX_PWR;
1992                 if (ofdm[i] > RF6052_MAX_TX_PWR)
1993                         ofdm[i] = RF6052_MAX_TX_PWR;
1994         }
1995
1996         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1997         val32 &= 0xffff00ff;
1998         val32 |= (cck[0] << 8);
1999         rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
2000
2001         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2002         val32 &= 0xff;
2003         val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
2004         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2005
2006         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2007         val32 &= 0xffffff00;
2008         val32 |= cck[1];
2009         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2010
2011         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
2012         val32 &= 0xff;
2013         val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
2014         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
2015
2016         ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
2017                 ofdmbase[0] << 16 | ofdmbase[0] << 24;
2018         ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
2019                 ofdmbase[1] << 16 | ofdmbase[1] << 24;
2020         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
2021         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
2022
2023         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
2024         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
2025
2026         mcs_a = mcsbase[0] | mcsbase[0] << 8 |
2027                 mcsbase[0] << 16 | mcsbase[0] << 24;
2028         mcs_b = mcsbase[1] | mcsbase[1] << 8 |
2029                 mcsbase[1] << 16 | mcsbase[1] << 24;
2030
2031         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
2032         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
2033
2034         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
2035         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
2036
2037         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
2038         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
2039
2040         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
2041         for (i = 0; i < 3; i++) {
2042                 if (i != 2)
2043                         val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
2044                 else
2045                         val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
2046                 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
2047         }
2048         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
2049         for (i = 0; i < 3; i++) {
2050                 if (i != 2)
2051                         val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
2052                 else
2053                         val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
2054                 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
2055         }
2056 }
2057
2058 static void
2059 rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
2060 {
2061         u32 val32, ofdm, mcs;
2062         u8 cck, ofdmbase, mcsbase;
2063         int group, tx_idx;
2064
2065         tx_idx = 0;
2066         group = rtl8723b_channel_to_group(channel);
2067
2068         cck = priv->cck_tx_power_index_B[group];
2069         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
2070         val32 &= 0xffff00ff;
2071         val32 |= (cck << 8);
2072         rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
2073
2074         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2075         val32 &= 0xff;
2076         val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
2077         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2078
2079         ofdmbase = priv->ht40_1s_tx_power_index_B[group];
2080         ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b;
2081         ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
2082
2083         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
2084         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
2085
2086         mcsbase = priv->ht40_1s_tx_power_index_B[group];
2087         if (ht40)
2088                 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b;
2089         else
2090                 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b;
2091         mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
2092
2093         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
2094         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
2095 }
2096
2097 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
2098                                   enum nl80211_iftype linktype)
2099 {
2100         u8 val8;
2101
2102         val8 = rtl8xxxu_read8(priv, REG_MSR);
2103         val8 &= ~MSR_LINKTYPE_MASK;
2104
2105         switch (linktype) {
2106         case NL80211_IFTYPE_UNSPECIFIED:
2107                 val8 |= MSR_LINKTYPE_NONE;
2108                 break;
2109         case NL80211_IFTYPE_ADHOC:
2110                 val8 |= MSR_LINKTYPE_ADHOC;
2111                 break;
2112         case NL80211_IFTYPE_STATION:
2113                 val8 |= MSR_LINKTYPE_STATION;
2114                 break;
2115         case NL80211_IFTYPE_AP:
2116                 val8 |= MSR_LINKTYPE_AP;
2117                 break;
2118         default:
2119                 goto out;
2120         }
2121
2122         rtl8xxxu_write8(priv, REG_MSR, val8);
2123 out:
2124         return;
2125 }
2126
2127 static void
2128 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
2129 {
2130         u16 val16;
2131
2132         val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
2133                  RETRY_LIMIT_SHORT_MASK) |
2134                 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
2135                  RETRY_LIMIT_LONG_MASK);
2136
2137         rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
2138 }
2139
2140 static void
2141 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
2142 {
2143         u16 val16;
2144
2145         val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
2146                 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
2147
2148         rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
2149 }
2150
2151 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
2152 {
2153         struct device *dev = &priv->udev->dev;
2154         char *cut;
2155
2156         switch (priv->chip_cut) {
2157         case 0:
2158                 cut = "A";
2159                 break;
2160         case 1:
2161                 cut = "B";
2162                 break;
2163         case 2:
2164                 cut = "C";
2165                 break;
2166         case 3:
2167                 cut = "D";
2168                 break;
2169         case 4:
2170                 cut = "E";
2171                 break;
2172         default:
2173                 cut = "unknown";
2174         }
2175
2176         dev_info(dev,
2177                  "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
2178                  priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
2179                  priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
2180                  priv->has_bluetooth, priv->has_gps, priv->hi_pa);
2181
2182         dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
2183 }
2184
2185 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
2186 {
2187         struct device *dev = &priv->udev->dev;
2188         u32 val32, bonding;
2189         u16 val16;
2190
2191         val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
2192         priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
2193                 SYS_CFG_CHIP_VERSION_SHIFT;
2194         if (val32 & SYS_CFG_TRP_VAUX_EN) {
2195                 dev_info(dev, "Unsupported test chip\n");
2196                 return -ENOTSUPP;
2197         }
2198
2199         if (val32 & SYS_CFG_BT_FUNC) {
2200                 if (priv->chip_cut >= 3) {
2201                         sprintf(priv->chip_name, "8723BU");
2202                         priv->rtl_chip = RTL8723B;
2203                 } else {
2204                         sprintf(priv->chip_name, "8723AU");
2205                         priv->usb_interrupts = 1;
2206                         priv->rtl_chip = RTL8723A;
2207                 }
2208
2209                 priv->rf_paths = 1;
2210                 priv->rx_paths = 1;
2211                 priv->tx_paths = 1;
2212
2213                 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
2214                 if (val32 & MULTI_WIFI_FUNC_EN)
2215                         priv->has_wifi = 1;
2216                 if (val32 & MULTI_BT_FUNC_EN)
2217                         priv->has_bluetooth = 1;
2218                 if (val32 & MULTI_GPS_FUNC_EN)
2219                         priv->has_gps = 1;
2220                 priv->is_multi_func = 1;
2221         } else if (val32 & SYS_CFG_TYPE_ID) {
2222                 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
2223                 bonding &= HPON_FSM_BONDING_MASK;
2224                 if (priv->fops->has_s0s1) {
2225                         if (bonding == HPON_FSM_BONDING_1T2R) {
2226                                 sprintf(priv->chip_name, "8191EU");
2227                                 priv->rf_paths = 2;
2228                                 priv->rx_paths = 2;
2229                                 priv->tx_paths = 1;
2230                                 priv->rtl_chip = RTL8191E;
2231                         } else {
2232                                 sprintf(priv->chip_name, "8192EU");
2233                                 priv->rf_paths = 2;
2234                                 priv->rx_paths = 2;
2235                                 priv->tx_paths = 2;
2236                                 priv->rtl_chip = RTL8192E;
2237                         }
2238                 } else if (bonding == HPON_FSM_BONDING_1T2R) {
2239                         sprintf(priv->chip_name, "8191CU");
2240                         priv->rf_paths = 2;
2241                         priv->rx_paths = 2;
2242                         priv->tx_paths = 1;
2243                         priv->usb_interrupts = 1;
2244                         priv->rtl_chip = RTL8191C;
2245                 } else {
2246                         sprintf(priv->chip_name, "8192CU");
2247                         priv->rf_paths = 2;
2248                         priv->rx_paths = 2;
2249                         priv->tx_paths = 2;
2250                         priv->usb_interrupts = 1;
2251                         priv->rtl_chip = RTL8192C;
2252                 }
2253                 priv->has_wifi = 1;
2254         } else {
2255                 sprintf(priv->chip_name, "8188CU");
2256                 priv->rf_paths = 1;
2257                 priv->rx_paths = 1;
2258                 priv->tx_paths = 1;
2259                 priv->rtl_chip = RTL8188C;
2260                 priv->usb_interrupts = 1;
2261                 priv->has_wifi = 1;
2262         }
2263
2264         switch (priv->rtl_chip) {
2265         case RTL8188E:
2266         case RTL8192E:
2267         case RTL8723B:
2268                 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
2269                 case SYS_CFG_VENDOR_ID_TSMC:
2270                         sprintf(priv->chip_vendor, "TSMC");
2271                         break;
2272                 case SYS_CFG_VENDOR_ID_SMIC:
2273                         sprintf(priv->chip_vendor, "SMIC");
2274                         priv->vendor_smic = 1;
2275                         break;
2276                 case SYS_CFG_VENDOR_ID_UMC:
2277                         sprintf(priv->chip_vendor, "UMC");
2278                         priv->vendor_umc = 1;
2279                         break;
2280                 default:
2281                         sprintf(priv->chip_vendor, "unknown");
2282                 }
2283                 break;
2284         default:
2285                 if (val32 & SYS_CFG_VENDOR_ID) {
2286                         sprintf(priv->chip_vendor, "UMC");
2287                         priv->vendor_umc = 1;
2288                 } else {
2289                         sprintf(priv->chip_vendor, "TSMC");
2290                 }
2291         }
2292
2293         val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
2294         priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
2295
2296         val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
2297         if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
2298                 priv->ep_tx_high_queue = 1;
2299                 priv->ep_tx_count++;
2300         }
2301
2302         if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
2303                 priv->ep_tx_normal_queue = 1;
2304                 priv->ep_tx_count++;
2305         }
2306
2307         if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
2308                 priv->ep_tx_low_queue = 1;
2309                 priv->ep_tx_count++;
2310         }
2311
2312         /*
2313          * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2314          */
2315         if (!priv->ep_tx_count) {
2316                 switch (priv->nr_out_eps) {
2317                 case 4:
2318                 case 3:
2319                         priv->ep_tx_low_queue = 1;
2320                         priv->ep_tx_count++;
2321                 case 2:
2322                         priv->ep_tx_normal_queue = 1;
2323                         priv->ep_tx_count++;
2324                 case 1:
2325                         priv->ep_tx_high_queue = 1;
2326                         priv->ep_tx_count++;
2327                         break;
2328                 default:
2329                         dev_info(dev, "Unsupported USB TX end-points\n");
2330                         return -ENOTSUPP;
2331                 }
2332         }
2333
2334         return 0;
2335 }
2336
2337 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
2338 {
2339         struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
2340
2341         if (efuse->rtl_id != cpu_to_le16(0x8129))
2342                 return -EINVAL;
2343
2344         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2345
2346         memcpy(priv->cck_tx_power_index_A,
2347                efuse->cck_tx_power_index_A,
2348                sizeof(efuse->cck_tx_power_index_A));
2349         memcpy(priv->cck_tx_power_index_B,
2350                efuse->cck_tx_power_index_B,
2351                sizeof(efuse->cck_tx_power_index_B));
2352
2353         memcpy(priv->ht40_1s_tx_power_index_A,
2354                efuse->ht40_1s_tx_power_index_A,
2355                sizeof(efuse->ht40_1s_tx_power_index_A));
2356         memcpy(priv->ht40_1s_tx_power_index_B,
2357                efuse->ht40_1s_tx_power_index_B,
2358                sizeof(efuse->ht40_1s_tx_power_index_B));
2359
2360         memcpy(priv->ht20_tx_power_index_diff,
2361                efuse->ht20_tx_power_index_diff,
2362                sizeof(efuse->ht20_tx_power_index_diff));
2363         memcpy(priv->ofdm_tx_power_index_diff,
2364                efuse->ofdm_tx_power_index_diff,
2365                sizeof(efuse->ofdm_tx_power_index_diff));
2366
2367         memcpy(priv->ht40_max_power_offset,
2368                efuse->ht40_max_power_offset,
2369                sizeof(efuse->ht40_max_power_offset));
2370         memcpy(priv->ht20_max_power_offset,
2371                efuse->ht20_max_power_offset,
2372                sizeof(efuse->ht20_max_power_offset));
2373
2374         if (priv->efuse_wifi.efuse8723.version >= 0x01) {
2375                 priv->has_xtalk = 1;
2376                 priv->xtalk = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2377         }
2378         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2379                  efuse->vendor_name);
2380         dev_info(&priv->udev->dev, "Product: %.41s\n",
2381                  efuse->device_name);
2382         return 0;
2383 }
2384
2385 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
2386 {
2387         struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu;
2388         int i;
2389
2390         if (efuse->rtl_id != cpu_to_le16(0x8129))
2391                 return -EINVAL;
2392
2393         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2394
2395         memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
2396                sizeof(efuse->tx_power_index_A.cck_base));
2397         memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
2398                sizeof(efuse->tx_power_index_B.cck_base));
2399
2400         memcpy(priv->ht40_1s_tx_power_index_A,
2401                efuse->tx_power_index_A.ht40_base,
2402                sizeof(efuse->tx_power_index_A.ht40_base));
2403         memcpy(priv->ht40_1s_tx_power_index_B,
2404                efuse->tx_power_index_B.ht40_base,
2405                sizeof(efuse->tx_power_index_B.ht40_base));
2406
2407         priv->ofdm_tx_power_diff[0].a =
2408                 efuse->tx_power_index_A.ht20_ofdm_1s_diff.a;
2409         priv->ofdm_tx_power_diff[0].b =
2410                 efuse->tx_power_index_B.ht20_ofdm_1s_diff.a;
2411
2412         priv->ht20_tx_power_diff[0].a =
2413                 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
2414         priv->ht20_tx_power_diff[0].b =
2415                 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
2416
2417         priv->ht40_tx_power_diff[0].a = 0;
2418         priv->ht40_tx_power_diff[0].b = 0;
2419
2420         for (i = 1; i < RTL8723B_TX_COUNT; i++) {
2421                 priv->ofdm_tx_power_diff[i].a =
2422                         efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
2423                 priv->ofdm_tx_power_diff[i].b =
2424                         efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
2425
2426                 priv->ht20_tx_power_diff[i].a =
2427                         efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
2428                 priv->ht20_tx_power_diff[i].b =
2429                         efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
2430
2431                 priv->ht40_tx_power_diff[i].a =
2432                         efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
2433                 priv->ht40_tx_power_diff[i].b =
2434                         efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
2435         }
2436
2437         priv->has_xtalk = 1;
2438         priv->xtalk = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f;
2439
2440         dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2441         dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name);
2442
2443         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2444                 int i;
2445                 unsigned char *raw = priv->efuse_wifi.raw;
2446
2447                 dev_info(&priv->udev->dev,
2448                          "%s: dumping efuse (0x%02zx bytes):\n",
2449                          __func__, sizeof(struct rtl8723bu_efuse));
2450                 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) {
2451                         dev_info(&priv->udev->dev, "%02x: "
2452                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2453                                  raw[i], raw[i + 1], raw[i + 2],
2454                                  raw[i + 3], raw[i + 4], raw[i + 5],
2455                                  raw[i + 6], raw[i + 7]);
2456                 }
2457         }
2458
2459         return 0;
2460 }
2461
2462 #ifdef CONFIG_RTL8XXXU_UNTESTED
2463
2464 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
2465 {
2466         struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192;
2467         int i;
2468
2469         if (efuse->rtl_id != cpu_to_le16(0x8129))
2470                 return -EINVAL;
2471
2472         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2473
2474         memcpy(priv->cck_tx_power_index_A,
2475                efuse->cck_tx_power_index_A,
2476                sizeof(efuse->cck_tx_power_index_A));
2477         memcpy(priv->cck_tx_power_index_B,
2478                efuse->cck_tx_power_index_B,
2479                sizeof(efuse->cck_tx_power_index_B));
2480
2481         memcpy(priv->ht40_1s_tx_power_index_A,
2482                efuse->ht40_1s_tx_power_index_A,
2483                sizeof(efuse->ht40_1s_tx_power_index_A));
2484         memcpy(priv->ht40_1s_tx_power_index_B,
2485                efuse->ht40_1s_tx_power_index_B,
2486                sizeof(efuse->ht40_1s_tx_power_index_B));
2487         memcpy(priv->ht40_2s_tx_power_index_diff,
2488                efuse->ht40_2s_tx_power_index_diff,
2489                sizeof(efuse->ht40_2s_tx_power_index_diff));
2490
2491         memcpy(priv->ht20_tx_power_index_diff,
2492                efuse->ht20_tx_power_index_diff,
2493                sizeof(efuse->ht20_tx_power_index_diff));
2494         memcpy(priv->ofdm_tx_power_index_diff,
2495                efuse->ofdm_tx_power_index_diff,
2496                sizeof(efuse->ofdm_tx_power_index_diff));
2497
2498         memcpy(priv->ht40_max_power_offset,
2499                efuse->ht40_max_power_offset,
2500                sizeof(efuse->ht40_max_power_offset));
2501         memcpy(priv->ht20_max_power_offset,
2502                efuse->ht20_max_power_offset,
2503                sizeof(efuse->ht20_max_power_offset));
2504
2505         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2506                  efuse->vendor_name);
2507         dev_info(&priv->udev->dev, "Product: %.20s\n",
2508                  efuse->device_name);
2509
2510         if (efuse->rf_regulatory & 0x20) {
2511                 sprintf(priv->chip_name, "8188RU");
2512                 priv->hi_pa = 1;
2513         }
2514
2515         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2516                 unsigned char *raw = priv->efuse_wifi.raw;
2517
2518                 dev_info(&priv->udev->dev,
2519                          "%s: dumping efuse (0x%02zx bytes):\n",
2520                          __func__, sizeof(struct rtl8192cu_efuse));
2521                 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
2522                         dev_info(&priv->udev->dev, "%02x: "
2523                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2524                                  raw[i], raw[i + 1], raw[i + 2],
2525                                  raw[i + 3], raw[i + 4], raw[i + 5],
2526                                  raw[i + 6], raw[i + 7]);
2527                 }
2528         }
2529         return 0;
2530 }
2531
2532 #endif
2533
2534 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
2535 {
2536         struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu;
2537         int i;
2538
2539         if (efuse->rtl_id != cpu_to_le16(0x8129))
2540                 return -EINVAL;
2541
2542         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2543
2544         priv->has_xtalk = 1;
2545         priv->xtalk = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f;
2546
2547         dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2548         dev_info(&priv->udev->dev, "Product: %.11s\n", efuse->device_name);
2549         dev_info(&priv->udev->dev, "Serial: %.11s\n", efuse->serial);
2550
2551         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2552                 unsigned char *raw = priv->efuse_wifi.raw;
2553
2554                 dev_info(&priv->udev->dev,
2555                          "%s: dumping efuse (0x%02zx bytes):\n",
2556                          __func__, sizeof(struct rtl8192eu_efuse));
2557                 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) {
2558                         dev_info(&priv->udev->dev, "%02x: "
2559                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2560                                  raw[i], raw[i + 1], raw[i + 2],
2561                                  raw[i + 3], raw[i + 4], raw[i + 5],
2562                                  raw[i + 6], raw[i + 7]);
2563                 }
2564         }
2565         /*
2566          * Temporarily disable 8192eu support
2567          */
2568         return -EINVAL;
2569         return 0;
2570 }
2571
2572 static int
2573 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
2574 {
2575         int i;
2576         u8 val8;
2577         u32 val32;
2578
2579         /* Write Address */
2580         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
2581         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
2582         val8 &= 0xfc;
2583         val8 |= (offset >> 8) & 0x03;
2584         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
2585
2586         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
2587         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
2588
2589         /* Poll for data read */
2590         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2591         for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
2592                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2593                 if (val32 & BIT(31))
2594                         break;
2595         }
2596
2597         if (i == RTL8XXXU_MAX_REG_POLL)
2598                 return -EIO;
2599
2600         udelay(50);
2601         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2602
2603         *data = val32 & 0xff;
2604         return 0;
2605 }
2606
2607 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
2608 {
2609         struct device *dev = &priv->udev->dev;
2610         int i, ret = 0;
2611         u8 val8, word_mask, header, extheader;
2612         u16 val16, efuse_addr, offset;
2613         u32 val32;
2614
2615         val16 = rtl8xxxu_read16(priv, REG_9346CR);
2616         if (val16 & EEPROM_ENABLE)
2617                 priv->has_eeprom = 1;
2618         if (val16 & EEPROM_BOOT)
2619                 priv->boot_eeprom = 1;
2620
2621         if (priv->is_multi_func) {
2622                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
2623                 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
2624                 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
2625         }
2626
2627         dev_dbg(dev, "Booting from %s\n",
2628                 priv->boot_eeprom ? "EEPROM" : "EFUSE");
2629
2630         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
2631
2632         /*  1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2633         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
2634         if (!(val16 & SYS_ISO_PWC_EV12V)) {
2635                 val16 |= SYS_ISO_PWC_EV12V;
2636                 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
2637         }
2638         /*  Reset: 0x0000[28], default valid */
2639         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2640         if (!(val16 & SYS_FUNC_ELDR)) {
2641                 val16 |= SYS_FUNC_ELDR;
2642                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2643         }
2644
2645         /*
2646          * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2647          */
2648         val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
2649         if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
2650                 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
2651                 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
2652         }
2653
2654         /* Default value is 0xff */
2655         memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
2656
2657         efuse_addr = 0;
2658         while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
2659                 u16 map_addr;
2660
2661                 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
2662                 if (ret || header == 0xff)
2663                         goto exit;
2664
2665                 if ((header & 0x1f) == 0x0f) {  /* extended header */
2666                         offset = (header & 0xe0) >> 5;
2667
2668                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
2669                                                    &extheader);
2670                         if (ret)
2671                                 goto exit;
2672                         /* All words disabled */
2673                         if ((extheader & 0x0f) == 0x0f)
2674                                 continue;
2675
2676                         offset |= ((extheader & 0xf0) >> 1);
2677                         word_mask = extheader & 0x0f;
2678                 } else {
2679                         offset = (header >> 4) & 0x0f;
2680                         word_mask = header & 0x0f;
2681                 }
2682
2683                 /* Get word enable value from PG header */
2684
2685                 /* We have 8 bits to indicate validity */
2686                 map_addr = offset * 8;
2687                 if (map_addr >= EFUSE_MAP_LEN) {
2688                         dev_warn(dev, "%s: Illegal map_addr (%04x), "
2689                                  "efuse corrupt!\n",
2690                                  __func__, map_addr);
2691                         ret = -EINVAL;
2692                         goto exit;
2693                 }
2694                 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2695                         /* Check word enable condition in the section */
2696                         if (word_mask & BIT(i)) {
2697                                 map_addr += 2;
2698                                 continue;
2699                         }
2700
2701                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2702                         if (ret)
2703                                 goto exit;
2704                         priv->efuse_wifi.raw[map_addr++] = val8;
2705
2706                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2707                         if (ret)
2708                                 goto exit;
2709                         priv->efuse_wifi.raw[map_addr++] = val8;
2710                 }
2711         }
2712
2713 exit:
2714         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2715
2716         return ret;
2717 }
2718
2719 static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
2720 {
2721         u8 val8;
2722         u16 sys_func;
2723
2724         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2725         val8 &= ~BIT(0);
2726         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2727
2728         sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2729         sys_func &= ~SYS_FUNC_CPU_ENABLE;
2730         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2731
2732         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2733         val8 |= BIT(0);
2734         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2735
2736         sys_func |= SYS_FUNC_CPU_ENABLE;
2737         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2738 }
2739
2740 static void rtl8723bu_reset_8051(struct rtl8xxxu_priv *priv)
2741 {
2742         u8 val8;
2743         u16 sys_func;
2744
2745         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
2746         val8 &= ~BIT(1);
2747         rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
2748
2749         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2750         val8 &= ~BIT(0);
2751         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2752
2753         sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2754         sys_func &= ~SYS_FUNC_CPU_ENABLE;
2755         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2756
2757         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
2758         val8 &= ~BIT(1);
2759         rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
2760
2761         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2762         val8 |= BIT(0);
2763         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2764
2765         sys_func |= SYS_FUNC_CPU_ENABLE;
2766         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2767 }
2768
2769 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2770 {
2771         struct device *dev = &priv->udev->dev;
2772         int ret = 0, i;
2773         u32 val32;
2774
2775         /* Poll checksum report */
2776         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2777                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2778                 if (val32 & MCU_FW_DL_CSUM_REPORT)
2779                         break;
2780         }
2781
2782         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2783                 dev_warn(dev, "Firmware checksum poll timed out\n");
2784                 ret = -EAGAIN;
2785                 goto exit;
2786         }
2787
2788         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2789         val32 |= MCU_FW_DL_READY;
2790         val32 &= ~MCU_WINT_INIT_READY;
2791         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2792
2793         /*
2794          * Reset the 8051 in order for the firmware to start running,
2795          * otherwise it won't come up on the 8192eu
2796          */
2797         priv->fops->reset_8051(priv);
2798
2799         /* Wait for firmware to become ready */
2800         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2801                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2802                 if (val32 & MCU_WINT_INIT_READY)
2803                         break;
2804
2805                 udelay(100);
2806         }
2807
2808         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2809                 dev_warn(dev, "Firmware failed to start\n");
2810                 ret = -EAGAIN;
2811                 goto exit;
2812         }
2813
2814         /*
2815          * Init H2C command
2816          */
2817         if (priv->rtl_chip == RTL8723B)
2818                 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
2819 exit:
2820         return ret;
2821 }
2822
2823 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2824 {
2825         int pages, remainder, i, ret;
2826         u8 val8;
2827         u16 val16;
2828         u32 val32;
2829         u8 *fwptr;
2830
2831         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2832         val8 |= 4;
2833         rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2834
2835         /* 8051 enable */
2836         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2837         val16 |= SYS_FUNC_CPU_ENABLE;
2838         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2839
2840         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2841         if (val8 & MCU_FW_RAM_SEL) {
2842                 pr_info("do the RAM reset\n");
2843                 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
2844                 priv->fops->reset_8051(priv);
2845         }
2846
2847         /* MCU firmware download enable */
2848         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2849         val8 |= MCU_FW_DL_ENABLE;
2850         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2851
2852         /* 8051 reset */
2853         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2854         val32 &= ~BIT(19);
2855         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2856
2857         /* Reset firmware download checksum */
2858         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2859         val8 |= MCU_FW_DL_CSUM_REPORT;
2860         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2861
2862         pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2863         remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2864
2865         fwptr = priv->fw_data->data;
2866
2867         for (i = 0; i < pages; i++) {
2868                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2869                 val8 |= i;
2870                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2871
2872                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2873                                       fwptr, RTL_FW_PAGE_SIZE);
2874                 if (ret != RTL_FW_PAGE_SIZE) {
2875                         ret = -EAGAIN;
2876                         goto fw_abort;
2877                 }
2878
2879                 fwptr += RTL_FW_PAGE_SIZE;
2880         }
2881
2882         if (remainder) {
2883                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2884                 val8 |= i;
2885                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2886                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2887                                       fwptr, remainder);
2888                 if (ret != remainder) {
2889                         ret = -EAGAIN;
2890                         goto fw_abort;
2891                 }
2892         }
2893
2894         ret = 0;
2895 fw_abort:
2896         /* MCU firmware download disable */
2897         val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2898         val16 &= ~MCU_FW_DL_ENABLE;
2899         rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
2900
2901         return ret;
2902 }
2903
2904 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2905 {
2906         struct device *dev = &priv->udev->dev;
2907         const struct firmware *fw;
2908         int ret = 0;
2909         u16 signature;
2910
2911         dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2912         if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2913                 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2914                 ret = -EAGAIN;
2915                 goto exit;
2916         }
2917         if (!fw) {
2918                 dev_warn(dev, "Firmware data not available\n");
2919                 ret = -EINVAL;
2920                 goto exit;
2921         }
2922
2923         priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2924         if (!priv->fw_data) {
2925                 ret = -ENOMEM;
2926                 goto exit;
2927         }
2928         priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2929
2930         signature = le16_to_cpu(priv->fw_data->signature);
2931         switch (signature & 0xfff0) {
2932         case 0x92e0:
2933         case 0x92c0:
2934         case 0x88c0:
2935         case 0x5300:
2936         case 0x2300:
2937                 break;
2938         default:
2939                 ret = -EINVAL;
2940                 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2941                          __func__, signature);
2942         }
2943
2944         dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2945                  le16_to_cpu(priv->fw_data->major_version),
2946                  priv->fw_data->minor_version, signature);
2947
2948 exit:
2949         release_firmware(fw);
2950         return ret;
2951 }
2952
2953 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2954 {
2955         char *fw_name;
2956         int ret;
2957
2958         switch (priv->chip_cut) {
2959         case 0:
2960                 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2961                 break;
2962         case 1:
2963                 if (priv->enable_bluetooth)
2964                         fw_name = "rtlwifi/rtl8723aufw_B.bin";
2965                 else
2966                         fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2967
2968                 break;
2969         default:
2970                 return -EINVAL;
2971         }
2972
2973         ret = rtl8xxxu_load_firmware(priv, fw_name);
2974         return ret;
2975 }
2976
2977 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
2978 {
2979         char *fw_name;
2980         int ret;
2981
2982         if (priv->enable_bluetooth)
2983                 fw_name = "rtlwifi/rtl8723bu_bt.bin";
2984         else
2985                 fw_name = "rtlwifi/rtl8723bu_nic.bin";
2986
2987         ret = rtl8xxxu_load_firmware(priv, fw_name);
2988         return ret;
2989 }
2990
2991 #ifdef CONFIG_RTL8XXXU_UNTESTED
2992
2993 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2994 {
2995         char *fw_name;
2996         int ret;
2997
2998         if (!priv->vendor_umc)
2999                 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
3000         else if (priv->chip_cut || priv->rtl_chip == RTL8192C)
3001                 fw_name = "rtlwifi/rtl8192cufw_B.bin";
3002         else
3003                 fw_name = "rtlwifi/rtl8192cufw_A.bin";
3004
3005         ret = rtl8xxxu_load_firmware(priv, fw_name);
3006
3007         return ret;
3008 }
3009
3010 #endif
3011
3012 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
3013 {
3014         char *fw_name;
3015         int ret;
3016
3017         fw_name = "rtlwifi/rtl8192eu_nic.bin";
3018
3019         ret = rtl8xxxu_load_firmware(priv, fw_name);
3020
3021         return ret;
3022 }
3023
3024 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
3025 {
3026         u16 val16;
3027         int i = 100;
3028
3029         /* Inform 8051 to perform reset */
3030         rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
3031
3032         for (i = 100; i > 0; i--) {
3033                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3034
3035                 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
3036                         dev_dbg(&priv->udev->dev,
3037                                 "%s: Firmware self reset success!\n", __func__);
3038                         break;
3039                 }
3040                 udelay(50);
3041         }
3042
3043         if (!i) {
3044                 /* Force firmware reset */
3045                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3046                 val16 &= ~SYS_FUNC_CPU_ENABLE;
3047                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3048         }
3049 }
3050
3051 static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
3052 {
3053         u32 val32;
3054
3055         val32 = rtl8xxxu_read32(priv, 0x64);
3056         val32 &= ~(BIT(20) | BIT(24));
3057         rtl8xxxu_write32(priv, 0x64, val32);
3058
3059         val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
3060         val32 &= ~BIT(4);
3061         rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
3062
3063         val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
3064         val32 |= BIT(3);
3065         rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
3066
3067         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
3068         val32 |= BIT(24);
3069         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
3070
3071         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
3072         val32 &= ~BIT(23);
3073         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
3074
3075         val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
3076         val32 |= (BIT(0) | BIT(1));
3077         rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
3078
3079         val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC);
3080         val32 &= 0xffffff00;
3081         val32 |= 0x77;
3082         rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32);
3083
3084         val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
3085         val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
3086         rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
3087 }
3088
3089 static int
3090 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
3091 {
3092         int i, ret;
3093         u16 reg;
3094         u8 val;
3095
3096         for (i = 0; ; i++) {
3097                 reg = array[i].reg;
3098                 val = array[i].val;
3099
3100                 if (reg == 0xffff && val == 0xff)
3101                         break;
3102
3103                 ret = rtl8xxxu_write8(priv, reg, val);
3104                 if (ret != 1) {
3105                         dev_warn(&priv->udev->dev,
3106                                  "Failed to initialize MAC\n");
3107                         return -EAGAIN;
3108                 }
3109         }
3110
3111         if (priv->rtl_chip != RTL8723B)
3112                 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
3113
3114         return 0;
3115 }
3116
3117 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
3118                                   struct rtl8xxxu_reg32val *array)
3119 {
3120         int i, ret;
3121         u16 reg;
3122         u32 val;
3123
3124         for (i = 0; ; i++) {
3125                 reg = array[i].reg;
3126                 val = array[i].val;
3127
3128                 if (reg == 0xffff && val == 0xffffffff)
3129                         break;
3130
3131                 ret = rtl8xxxu_write32(priv, reg, val);
3132                 if (ret != sizeof(val)) {
3133                         dev_warn(&priv->udev->dev,
3134                                  "Failed to initialize PHY\n");
3135                         return -EAGAIN;
3136                 }
3137                 udelay(1);
3138         }
3139
3140         return 0;
3141 }
3142
3143 /*
3144  * Most of this is black magic retrieved from the old rtl8723au driver
3145  */
3146 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
3147 {
3148         u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
3149         u16 val16;
3150         u32 val32;
3151
3152         /*
3153          * Todo: The vendor driver maintains a table of PHY register
3154          *       addresses, which is initialized here. Do we need this?
3155          */
3156
3157         if (priv->rtl_chip == RTL8723B) {
3158                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3159                 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB |
3160                         SYS_FUNC_DIO_RF;
3161                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3162
3163                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
3164         } else {
3165                 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
3166                 udelay(2);
3167                 val8 |= AFE_PLL_320_ENABLE;
3168                 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
3169                 udelay(2);
3170
3171                 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
3172                 udelay(2);
3173
3174                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3175                 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
3176                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3177         }
3178
3179         if (priv->rtl_chip != RTL8723B) {
3180                 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
3181                 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
3182                 val32 &= ~AFE_XTAL_RF_GATE;
3183                 if (priv->has_bluetooth)
3184                         val32 &= ~AFE_XTAL_BT_GATE;
3185                 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
3186         }
3187
3188         /* 6. 0x1f[7:0] = 0x07 */
3189         val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3190         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3191
3192         if (priv->hi_pa)
3193                 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
3194         else if (priv->tx_paths == 2)
3195                 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
3196         else if (priv->rtl_chip == RTL8723B) {
3197                 /*
3198                  * Why?
3199                  */
3200                 rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3);
3201                 rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80);
3202                 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
3203         } else
3204                 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
3205
3206
3207         if (priv->rtl_chip == RTL8188C && priv->hi_pa &&
3208             priv->vendor_umc && priv->chip_cut == 1)
3209                 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
3210
3211         if (priv->tx_paths == 1 && priv->rx_paths == 2) {
3212                 /*
3213                  * For 1T2R boards, patch the registers.
3214                  *
3215                  * It looks like 8191/2 1T2R boards use path B for TX
3216                  */
3217                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
3218                 val32 &= ~(BIT(0) | BIT(1));
3219                 val32 |= BIT(1);
3220                 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
3221
3222                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
3223                 val32 &= ~0x300033;
3224                 val32 |= 0x200022;
3225                 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
3226
3227                 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
3228                 val32 &= 0xff000000;
3229                 val32 |= 0x45000000;
3230                 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
3231
3232                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
3233                 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
3234                 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
3235                           OFDM_RF_PATH_TX_B);
3236                 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
3237
3238                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
3239                 val32 &= ~(BIT(4) | BIT(5));
3240                 val32 |= BIT(4);
3241                 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
3242
3243                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
3244                 val32 &= ~(BIT(27) | BIT(26));
3245                 val32 |= BIT(27);
3246                 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
3247
3248                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
3249                 val32 &= ~(BIT(27) | BIT(26));
3250                 val32 |= BIT(27);
3251                 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
3252
3253                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
3254                 val32 &= ~(BIT(27) | BIT(26));
3255                 val32 |= BIT(27);
3256                 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
3257
3258                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
3259                 val32 &= ~(BIT(27) | BIT(26));
3260                 val32 |= BIT(27);
3261                 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
3262
3263                 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
3264                 val32 &= ~(BIT(27) | BIT(26));
3265                 val32 |= BIT(27);
3266                 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
3267         }
3268
3269         if (priv->rtl_chip == RTL8723B)
3270                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
3271         else if (priv->hi_pa)
3272                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
3273         else
3274                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
3275
3276         if (priv->has_xtalk) {
3277                 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
3278
3279                 val8 = priv->xtalk;
3280                 val32 &= 0xff000fff;
3281                 val32 |= ((val8 | (val8 << 6)) << 12);
3282
3283                 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
3284         }
3285
3286         if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E) {
3287                 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
3288                 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
3289                 ldohci12 = 0x57;
3290                 lpldo = 1;
3291                 val32 = (lpldo << 24) | (ldohci12 << 16) |
3292                         (ldov12d << 8) | ldoa15;
3293
3294                 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
3295         }
3296
3297         return 0;
3298 }
3299
3300 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
3301                                  struct rtl8xxxu_rfregval *array,
3302                                  enum rtl8xxxu_rfpath path)
3303 {
3304         int i, ret;
3305         u8 reg;
3306         u32 val;
3307
3308         for (i = 0; ; i++) {
3309                 reg = array[i].reg;
3310                 val = array[i].val;
3311
3312                 if (reg == 0xff && val == 0xffffffff)
3313                         break;
3314
3315                 switch (reg) {
3316                 case 0xfe:
3317                         msleep(50);
3318                         continue;
3319                 case 0xfd:
3320                         mdelay(5);
3321                         continue;
3322                 case 0xfc:
3323                         mdelay(1);
3324                         continue;
3325                 case 0xfb:
3326                         udelay(50);
3327                         continue;
3328                 case 0xfa:
3329                         udelay(5);
3330                         continue;
3331                 case 0xf9:
3332                         udelay(1);
3333                         continue;
3334                 }
3335
3336                 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
3337                 if (ret) {
3338                         dev_warn(&priv->udev->dev,
3339                                  "Failed to initialize RF\n");
3340                         return -EAGAIN;
3341                 }
3342                 udelay(1);
3343         }
3344
3345         return 0;
3346 }
3347
3348 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
3349                                 struct rtl8xxxu_rfregval *table,
3350                                 enum rtl8xxxu_rfpath path)
3351 {
3352         u32 val32;
3353         u16 val16, rfsi_rfenv;
3354         u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
3355
3356         switch (path) {
3357         case RF_A:
3358                 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
3359                 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
3360                 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
3361                 break;
3362         case RF_B:
3363                 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
3364                 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
3365                 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
3366                 break;
3367         default:
3368                 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
3369                         __func__, path + 'A');
3370                 return -EINVAL;
3371         }
3372         /* For path B, use XB */
3373         rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
3374         rfsi_rfenv &= FPGA0_RF_RFENV;
3375
3376         /*
3377          * These two we might be able to optimize into one
3378          */
3379         val32 = rtl8xxxu_read32(priv, reg_int_oe);
3380         val32 |= BIT(20);       /* 0x10 << 16 */
3381         rtl8xxxu_write32(priv, reg_int_oe, val32);
3382         udelay(1);
3383
3384         val32 = rtl8xxxu_read32(priv, reg_int_oe);
3385         val32 |= BIT(4);
3386         rtl8xxxu_write32(priv, reg_int_oe, val32);
3387         udelay(1);
3388
3389         /*
3390          * These two we might be able to optimize into one
3391          */
3392         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3393         val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
3394         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3395         udelay(1);
3396
3397         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3398         val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
3399         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3400         udelay(1);
3401
3402         rtl8xxxu_init_rf_regs(priv, table, path);
3403
3404         /* For path B, use XB */
3405         val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
3406         val16 &= ~FPGA0_RF_RFENV;
3407         val16 |= rfsi_rfenv;
3408         rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
3409
3410         return 0;
3411 }
3412
3413 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
3414 {
3415         int ret = -EBUSY;
3416         int count = 0;
3417         u32 value;
3418
3419         value = LLT_OP_WRITE | address << 8 | data;
3420
3421         rtl8xxxu_write32(priv, REG_LLT_INIT, value);
3422
3423         do {
3424                 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
3425                 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
3426                         ret = 0;
3427                         break;
3428                 }
3429         } while (count++ < 20);
3430
3431         return ret;
3432 }
3433
3434 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3435 {
3436         int ret;
3437         int i;
3438
3439         for (i = 0; i < last_tx_page; i++) {
3440                 ret = rtl8xxxu_llt_write(priv, i, i + 1);
3441                 if (ret)
3442                         goto exit;
3443         }
3444
3445         ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
3446         if (ret)
3447                 goto exit;
3448
3449         /* Mark remaining pages as a ring buffer */
3450         for (i = last_tx_page + 1; i < 0xff; i++) {
3451                 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
3452                 if (ret)
3453                         goto exit;
3454         }
3455
3456         /*  Let last entry point to the start entry of ring buffer */
3457         ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
3458         if (ret)
3459                 goto exit;
3460
3461 exit:
3462         return ret;
3463 }
3464
3465 static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3466 {
3467         u32 val32;
3468         int ret = 0;
3469         int i;
3470
3471         val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3472         val32 |= AUTO_LLT_INIT_LLT;
3473         rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
3474
3475         for (i = 500; i; i--) {
3476                 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3477                 if (!(val32 & AUTO_LLT_INIT_LLT))
3478                         break;
3479                 usleep_range(2, 4);
3480         }
3481
3482         if (!i) {
3483                 ret = -EBUSY;
3484                 dev_warn(&priv->udev->dev, "LLT table init failed\n");
3485         }
3486
3487         return ret;
3488 }
3489
3490 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
3491 {
3492         u16 val16, hi, lo;
3493         u16 hiq, mgq, bkq, beq, viq, voq;
3494         int hip, mgp, bkp, bep, vip, vop;
3495         int ret = 0;
3496
3497         switch (priv->ep_tx_count) {
3498         case 1:
3499                 if (priv->ep_tx_high_queue) {
3500                         hi = TRXDMA_QUEUE_HIGH;
3501                 } else if (priv->ep_tx_low_queue) {
3502                         hi = TRXDMA_QUEUE_LOW;
3503                 } else if (priv->ep_tx_normal_queue) {
3504                         hi = TRXDMA_QUEUE_NORMAL;
3505                 } else {
3506                         hi = 0;
3507                         ret = -EINVAL;
3508                 }
3509
3510                 hiq = hi;
3511                 mgq = hi;
3512                 bkq = hi;
3513                 beq = hi;
3514                 viq = hi;
3515                 voq = hi;
3516
3517                 hip = 0;
3518                 mgp = 0;
3519                 bkp = 0;
3520                 bep = 0;
3521                 vip = 0;
3522                 vop = 0;
3523                 break;
3524         case 2:
3525                 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
3526                         hi = TRXDMA_QUEUE_HIGH;
3527                         lo = TRXDMA_QUEUE_LOW;
3528                 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
3529                         hi = TRXDMA_QUEUE_NORMAL;
3530                         lo = TRXDMA_QUEUE_LOW;
3531                 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
3532                         hi = TRXDMA_QUEUE_HIGH;
3533                         lo = TRXDMA_QUEUE_NORMAL;
3534                 } else {
3535                         ret = -EINVAL;
3536                         hi = 0;
3537                         lo = 0;
3538                 }
3539
3540                 hiq = hi;
3541                 mgq = hi;
3542                 bkq = lo;
3543                 beq = lo;
3544                 viq = hi;
3545                 voq = hi;
3546
3547                 hip = 0;
3548                 mgp = 0;
3549                 bkp = 1;
3550                 bep = 1;
3551                 vip = 0;
3552                 vop = 0;
3553                 break;
3554         case 3:
3555                 beq = TRXDMA_QUEUE_LOW;
3556                 bkq = TRXDMA_QUEUE_LOW;
3557                 viq = TRXDMA_QUEUE_NORMAL;
3558                 voq = TRXDMA_QUEUE_HIGH;
3559                 mgq = TRXDMA_QUEUE_HIGH;
3560                 hiq = TRXDMA_QUEUE_HIGH;
3561
3562                 hip = hiq ^ 3;
3563                 mgp = mgq ^ 3;
3564                 bkp = bkq ^ 3;
3565                 bep = beq ^ 3;
3566                 vip = viq ^ 3;
3567                 vop = viq ^ 3;
3568                 break;
3569         default:
3570                 ret = -EINVAL;
3571         }
3572
3573         /*
3574          * None of the vendor drivers are configuring the beacon
3575          * queue here .... why?
3576          */
3577         if (!ret) {
3578                 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
3579                 val16 &= 0x7;
3580                 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
3581                         (viq << TRXDMA_CTRL_VIQ_SHIFT) |
3582                         (beq << TRXDMA_CTRL_BEQ_SHIFT) |
3583                         (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
3584                         (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
3585                         (hiq << TRXDMA_CTRL_HIQ_SHIFT);
3586                 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
3587
3588                 priv->pipe_out[TXDESC_QUEUE_VO] =
3589                         usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
3590                 priv->pipe_out[TXDESC_QUEUE_VI] =
3591                         usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
3592                 priv->pipe_out[TXDESC_QUEUE_BE] =
3593                         usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
3594                 priv->pipe_out[TXDESC_QUEUE_BK] =
3595                         usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
3596                 priv->pipe_out[TXDESC_QUEUE_BEACON] =
3597                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3598                 priv->pipe_out[TXDESC_QUEUE_MGNT] =
3599                         usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
3600                 priv->pipe_out[TXDESC_QUEUE_HIGH] =
3601                         usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
3602                 priv->pipe_out[TXDESC_QUEUE_CMD] =
3603                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3604         }
3605
3606         return ret;
3607 }
3608
3609 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
3610                                        bool iqk_ok, int result[][8],
3611                                        int candidate, bool tx_only)
3612 {
3613         u32 oldval, x, tx0_a, reg;
3614         int y, tx0_c;
3615         u32 val32;
3616
3617         if (!iqk_ok)
3618                 return;
3619
3620         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3621         oldval = val32 >> 22;
3622
3623         x = result[candidate][0];
3624         if ((x & 0x00000200) != 0)
3625                 x = x | 0xfffffc00;
3626         tx0_a = (x * oldval) >> 8;
3627
3628         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3629         val32 &= ~0x3ff;
3630         val32 |= tx0_a;
3631         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3632
3633         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3634         val32 &= ~BIT(31);
3635         if ((x * oldval >> 7) & 0x1)
3636                 val32 |= BIT(31);
3637         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3638
3639         y = result[candidate][1];
3640         if ((y & 0x00000200) != 0)
3641                 y = y | 0xfffffc00;
3642         tx0_c = (y * oldval) >> 8;
3643
3644         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
3645         val32 &= ~0xf0000000;
3646         val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
3647         rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
3648
3649         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3650         val32 &= ~0x003f0000;
3651         val32 |= ((tx0_c & 0x3f) << 16);
3652         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3653
3654         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3655         val32 &= ~BIT(29);
3656         if ((y * oldval >> 7) & 0x1)
3657                 val32 |= BIT(29);
3658         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3659
3660         if (tx_only) {
3661                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3662                 return;
3663         }
3664
3665         reg = result[candidate][2];
3666
3667         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3668         val32 &= ~0x3ff;
3669         val32 |= (reg & 0x3ff);
3670         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3671
3672         reg = result[candidate][3] & 0x3F;
3673
3674         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3675         val32 &= ~0xfc00;
3676         val32 |= ((reg << 10) & 0xfc00);
3677         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3678
3679         reg = (result[candidate][3] >> 6) & 0xF;
3680
3681         val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
3682         val32 &= ~0xf0000000;
3683         val32 |= (reg << 28);
3684         rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
3685 }
3686
3687 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
3688                                        bool iqk_ok, int result[][8],
3689                                        int candidate, bool tx_only)
3690 {
3691         u32 oldval, x, tx1_a, reg;
3692         int y, tx1_c;
3693         u32 val32;
3694
3695         if (!iqk_ok)
3696                 return;
3697
3698         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3699         oldval = val32 >> 22;
3700
3701         x = result[candidate][4];
3702         if ((x & 0x00000200) != 0)
3703                 x = x | 0xfffffc00;
3704         tx1_a = (x * oldval) >> 8;
3705
3706         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3707         val32 &= ~0x3ff;
3708         val32 |= tx1_a;
3709         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3710
3711         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3712         val32 &= ~BIT(27);
3713         if ((x * oldval >> 7) & 0x1)
3714                 val32 |= BIT(27);
3715         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3716
3717         y = result[candidate][5];
3718         if ((y & 0x00000200) != 0)
3719                 y = y | 0xfffffc00;
3720         tx1_c = (y * oldval) >> 8;
3721
3722         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
3723         val32 &= ~0xf0000000;
3724         val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
3725         rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
3726
3727         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3728         val32 &= ~0x003f0000;
3729         val32 |= ((tx1_c & 0x3f) << 16);
3730         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3731
3732         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3733         val32 &= ~BIT(25);
3734         if ((y * oldval >> 7) & 0x1)
3735                 val32 |= BIT(25);
3736         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3737
3738         if (tx_only) {
3739                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3740                 return;
3741         }
3742
3743         reg = result[candidate][6];
3744
3745         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3746         val32 &= ~0x3ff;
3747         val32 |= (reg & 0x3ff);
3748         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3749
3750         reg = result[candidate][7] & 0x3f;
3751
3752         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3753         val32 &= ~0xfc00;
3754         val32 |= ((reg << 10) & 0xfc00);
3755         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3756
3757         reg = (result[candidate][7] >> 6) & 0xf;
3758
3759         val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
3760         val32 &= ~0x0000f000;
3761         val32 |= (reg << 12);
3762         rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
3763 }
3764
3765 #define MAX_TOLERANCE           5
3766
3767 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
3768                                         int result[][8], int c1, int c2)
3769 {
3770         u32 i, j, diff, simubitmap, bound = 0;
3771         int candidate[2] = {-1, -1};    /* for path A and path B */
3772         bool retval = true;
3773
3774         if (priv->tx_paths > 1)
3775                 bound = 8;
3776         else
3777                 bound = 4;
3778
3779         simubitmap = 0;
3780
3781         for (i = 0; i < bound; i++) {
3782                 diff = (result[c1][i] > result[c2][i]) ?
3783                         (result[c1][i] - result[c2][i]) :
3784                         (result[c2][i] - result[c1][i]);
3785                 if (diff > MAX_TOLERANCE) {
3786                         if ((i == 2 || i == 6) && !simubitmap) {
3787                                 if (result[c1][i] + result[c1][i + 1] == 0)
3788                                         candidate[(i / 4)] = c2;
3789                                 else if (result[c2][i] + result[c2][i + 1] == 0)
3790                                         candidate[(i / 4)] = c1;
3791                                 else
3792                                         simubitmap = simubitmap | (1 << i);
3793                         } else {
3794                                 simubitmap = simubitmap | (1 << i);
3795                         }
3796                 }
3797         }
3798
3799         if (simubitmap == 0) {
3800                 for (i = 0; i < (bound / 4); i++) {
3801                         if (candidate[i] >= 0) {
3802                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3803                                         result[3][j] = result[candidate[i]][j];
3804                                 retval = false;
3805                         }
3806                 }
3807                 return retval;
3808         } else if (!(simubitmap & 0x0f)) {
3809                 /* path A OK */
3810                 for (i = 0; i < 4; i++)
3811                         result[3][i] = result[c1][i];
3812         } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
3813                 /* path B OK */
3814                 for (i = 4; i < 8; i++)
3815                         result[3][i] = result[c1][i];
3816         }
3817
3818         return false;
3819 }
3820
3821 static bool rtl8723bu_simularity_compare(struct rtl8xxxu_priv *priv,
3822                                          int result[][8], int c1, int c2)
3823 {
3824         u32 i, j, diff, simubitmap, bound = 0;
3825         int candidate[2] = {-1, -1};    /* for path A and path B */
3826         int tmp1, tmp2;
3827         bool retval = true;
3828
3829         if (priv->tx_paths > 1)
3830                 bound = 8;
3831         else
3832                 bound = 4;
3833
3834         simubitmap = 0;
3835
3836         for (i = 0; i < bound; i++) {
3837                 if (i & 1) {
3838                         if ((result[c1][i] & 0x00000200))
3839                                 tmp1 = result[c1][i] | 0xfffffc00;
3840                         else
3841                                 tmp1 = result[c1][i];
3842
3843                         if ((result[c2][i]& 0x00000200))
3844                                 tmp2 = result[c2][i] | 0xfffffc00;
3845                         else
3846                                 tmp2 = result[c2][i];
3847                 } else {
3848                         tmp1 = result[c1][i];
3849                         tmp2 = result[c2][i];
3850                 }
3851
3852                 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
3853
3854                 if (diff > MAX_TOLERANCE) {
3855                         if ((i == 2 || i == 6) && !simubitmap) {
3856                                 if (result[c1][i] + result[c1][i + 1] == 0)
3857                                         candidate[(i / 4)] = c2;
3858                                 else if (result[c2][i] + result[c2][i + 1] == 0)
3859                                         candidate[(i / 4)] = c1;
3860                                 else
3861                                         simubitmap = simubitmap | (1 << i);
3862                         } else {
3863                                 simubitmap = simubitmap | (1 << i);
3864                         }
3865                 }
3866         }
3867
3868         if (simubitmap == 0) {
3869                 for (i = 0; i < (bound / 4); i++) {
3870                         if (candidate[i] >= 0) {
3871                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3872                                         result[3][j] = result[candidate[i]][j];
3873                                 retval = false;
3874                         }
3875                 }
3876                 return retval;
3877         } else {
3878                 if (!(simubitmap & 0x03)) {
3879                         /* path A TX OK */
3880                         for (i = 0; i < 2; i++)
3881                                 result[3][i] = result[c1][i];
3882                 }
3883
3884                 if (!(simubitmap & 0x0c)) {
3885                         /* path A RX OK */
3886                         for (i = 2; i < 4; i++)
3887                                 result[3][i] = result[c1][i];
3888                 }
3889
3890                 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3891                         /* path B RX OK */
3892                         for (i = 4; i < 6; i++)
3893                                 result[3][i] = result[c1][i];
3894                 }
3895
3896                 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3897                         /* path B RX OK */
3898                         for (i = 6; i < 8; i++)
3899                                 result[3][i] = result[c1][i];
3900                 }
3901         }
3902
3903         return false;
3904 }
3905
3906 static void
3907 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3908 {
3909         int i;
3910
3911         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3912                 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3913
3914         backup[i] = rtl8xxxu_read32(priv, reg[i]);
3915 }
3916
3917 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3918                                       const u32 *reg, u32 *backup)
3919 {
3920         int i;
3921
3922         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3923                 rtl8xxxu_write8(priv, reg[i], backup[i]);
3924
3925         rtl8xxxu_write32(priv, reg[i], backup[i]);
3926 }
3927
3928 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3929                                u32 *backup, int count)
3930 {
3931         int i;
3932
3933         for (i = 0; i < count; i++)
3934                 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3935 }
3936
3937 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3938                                   u32 *backup, int count)
3939 {
3940         int i;
3941
3942         for (i = 0; i < count; i++)
3943                 rtl8xxxu_write32(priv, regs[i], backup[i]);
3944 }
3945
3946
3947 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3948                                   bool path_a_on)
3949 {
3950         u32 path_on;
3951         int i;
3952
3953         if (priv->tx_paths == 1) {
3954                 path_on = priv->fops->adda_1t_path_on;
3955                 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
3956         } else {
3957                 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
3958                         priv->fops->adda_2t_path_on_b;
3959
3960                 rtl8xxxu_write32(priv, regs[0], path_on);
3961         }
3962
3963         for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3964                 rtl8xxxu_write32(priv, regs[i], path_on);
3965 }
3966
3967 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3968                                      const u32 *regs, u32 *backup)
3969 {
3970         int i = 0;
3971
3972         rtl8xxxu_write8(priv, regs[i], 0x3f);
3973
3974         for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3975                 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3976
3977         rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3978 }
3979
3980 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3981 {
3982         u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3983         int result = 0;
3984
3985         /* path-A IQK setting */
3986         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3987         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3988         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3989
3990         val32 = (priv->rf_paths > 1) ? 0x28160202 :
3991                 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3992                 0x28160502;
3993         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3994
3995         /* path-B IQK setting */
3996         if (priv->rf_paths > 1) {
3997                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3998                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3999                 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
4000                 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
4001         }
4002
4003         /* LO calibration setting */
4004         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
4005
4006         /* One shot, path A LOK & IQK */
4007         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4008         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4009
4010         mdelay(1);
4011
4012         /* Check failed */
4013         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4014         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4015         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4016         reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
4017
4018         if (!(reg_eac & BIT(28)) &&
4019             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4020             ((reg_e9c & 0x03ff0000) != 0x00420000))
4021                 result |= 0x01;
4022         else    /* If TX not OK, ignore RX */
4023                 goto out;
4024
4025         /* If TX is OK, check whether RX is OK */
4026         if (!(reg_eac & BIT(27)) &&
4027             ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
4028             ((reg_eac & 0x03ff0000) != 0x00360000))
4029                 result |= 0x02;
4030         else
4031                 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
4032                          __func__);
4033 out:
4034         return result;
4035 }
4036
4037 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
4038 {
4039         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4040         int result = 0;
4041
4042         /* One shot, path B LOK & IQK */
4043         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
4044         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
4045
4046         mdelay(1);
4047
4048         /* Check failed */
4049         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4050         reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4051         reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4052         reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4053         reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4054
4055         if (!(reg_eac & BIT(31)) &&
4056             ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
4057             ((reg_ebc & 0x03ff0000) != 0x00420000))
4058                 result |= 0x01;
4059         else
4060                 goto out;
4061
4062         if (!(reg_eac & BIT(30)) &&
4063             (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4064             (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4065                 result |= 0x02;
4066         else
4067                 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4068                          __func__);
4069 out:
4070         return result;
4071 }
4072
4073 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv)
4074 {
4075         u32 reg_eac, reg_e94, reg_e9c, path_sel, val32;
4076         int result = 0;
4077
4078         path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4079
4080         /*
4081          * Leave IQK mode
4082          */
4083         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4084         val32 &= 0x000000ff;
4085         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4086
4087         /*
4088          * Enable path A PA in TX IQK mode
4089          */
4090         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4091         val32 |= 0x80000;
4092         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4093         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
4094         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f);
4095         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87);
4096
4097         /*
4098          * Tx IQK setting
4099          */
4100         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4101         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4102
4103         /* path-A IQK setting */
4104         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4105         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4106         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4107         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4108
4109         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea);
4110         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4111         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4112         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4113
4114         /* LO calibration setting */
4115         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
4116
4117         /*
4118          * Enter IQK mode
4119          */
4120         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4121         val32 &= 0x000000ff;
4122         val32 |= 0x80800000;
4123         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4124
4125         /*
4126          * The vendor driver indicates the USB module is always using
4127          * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4128          */
4129         if (priv->rf_paths > 1)
4130                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4131         else
4132                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4133
4134         /*
4135          * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4136          * No trace of this in the 8192eu or 8188eu vendor drivers.
4137          */
4138         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4139
4140         /* One shot, path A LOK & IQK */
4141         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4142         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4143
4144         mdelay(1);
4145
4146         /* Restore Ant Path */
4147         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4148 #ifdef RTL8723BU_BT
4149         /* GNT_BT = 1 */
4150         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4151 #endif
4152
4153         /*
4154          * Leave IQK mode
4155          */
4156         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4157         val32 &= 0x000000ff;
4158         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4159
4160         /* Check failed */
4161         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4162         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4163         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4164
4165         val32 = (reg_e9c >> 16) & 0x3ff;
4166         if (val32 & 0x200)
4167                 val32 = 0x400 - val32;
4168
4169         if (!(reg_eac & BIT(28)) &&
4170             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4171             ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4172             ((reg_e94 & 0x03ff0000)  < 0x01100000) &&
4173             ((reg_e94 & 0x03ff0000)  > 0x00f00000) &&
4174             val32 < 0xf)
4175                 result |= 0x01;
4176         else    /* If TX not OK, ignore RX */
4177                 goto out;
4178
4179 out:
4180         return result;
4181 }
4182
4183 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
4184 {
4185         u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32;
4186         int result = 0;
4187
4188         path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4189
4190         /*
4191          * Leave IQK mode
4192          */
4193         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4194         val32 &= 0x000000ff;
4195         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4196
4197         /*
4198          * Enable path A PA in TX IQK mode
4199          */
4200         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4201         val32 |= 0x80000;
4202         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4203         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4204         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4205         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4206
4207         /*
4208          * Tx IQK setting
4209          */
4210         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4211         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4212
4213         /* path-A IQK setting */
4214         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4215         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4216         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4217         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4218
4219         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0);
4220         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4221         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4222         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4223
4224         /* LO calibration setting */
4225         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
4226
4227         /*
4228          * Enter IQK mode
4229          */
4230         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4231         val32 &= 0x000000ff;
4232         val32 |= 0x80800000;
4233         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4234
4235         /*
4236          * The vendor driver indicates the USB module is always using
4237          * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4238          */
4239         if (priv->rf_paths > 1)
4240                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4241         else
4242                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4243
4244         /*
4245          * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4246          * No trace of this in the 8192eu or 8188eu vendor drivers.
4247          */
4248         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4249
4250         /* One shot, path A LOK & IQK */
4251         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4252         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4253
4254         mdelay(1);
4255
4256         /* Restore Ant Path */
4257         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4258 #ifdef RTL8723BU_BT
4259         /* GNT_BT = 1 */
4260         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4261 #endif
4262
4263         /*
4264          * Leave IQK mode
4265          */
4266         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4267         val32 &= 0x000000ff;
4268         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4269
4270         /* Check failed */
4271         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4272         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4273         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4274
4275         val32 = (reg_e9c >> 16) & 0x3ff;
4276         if (val32 & 0x200)
4277                 val32 = 0x400 - val32;
4278
4279         if (!(reg_eac & BIT(28)) &&
4280             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4281             ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4282             ((reg_e94 & 0x03ff0000)  < 0x01100000) &&
4283             ((reg_e94 & 0x03ff0000)  > 0x00f00000) &&
4284             val32 < 0xf)
4285                 result |= 0x01;
4286         else    /* If TX not OK, ignore RX */
4287                 goto out;
4288
4289         val32 = 0x80007c00 | (reg_e94 &0x3ff0000) |
4290                 ((reg_e9c & 0x3ff0000) >> 16);
4291         rtl8xxxu_write32(priv, REG_TX_IQK, val32);
4292
4293         /*
4294          * Modify RX IQK mode
4295          */
4296         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4297         val32 &= 0x000000ff;
4298         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4299         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4300         val32 |= 0x80000;
4301         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4302         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4303         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4304         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77);
4305
4306         /*
4307          * PA, PAD setting
4308          */
4309         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80);
4310         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f);
4311
4312         /*
4313          * RX IQK setting
4314          */
4315         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4316
4317         /* path-A IQK setting */
4318         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
4319         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
4320         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4321         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4322
4323         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000);
4324         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f);
4325         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4326         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4327
4328         /* LO calibration setting */
4329         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1);
4330
4331         /*
4332          * Enter IQK mode
4333          */
4334         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4335         val32 &= 0x000000ff;
4336         val32 |= 0x80800000;
4337         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4338
4339         if (priv->rf_paths > 1)
4340                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4341         else
4342                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4343
4344         /*
4345          * Disable BT
4346          */
4347         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4348
4349         /* One shot, path A LOK & IQK */
4350         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4351         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4352
4353         mdelay(1);
4354
4355         /* Restore Ant Path */
4356         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4357 #ifdef RTL8723BU_BT
4358         /* GNT_BT = 1 */
4359         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4360 #endif
4361
4362         /*
4363          * Leave IQK mode
4364          */
4365         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4366         val32 &= 0x000000ff;
4367         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4368
4369         /* Check failed */
4370         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4371         reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
4372
4373         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780);
4374
4375         val32 = (reg_eac >> 16) & 0x3ff;
4376         if (val32 & 0x200)
4377                 val32 = 0x400 - val32;
4378
4379         if (!(reg_eac & BIT(27)) &&
4380             ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
4381             ((reg_eac & 0x03ff0000) != 0x00360000) &&
4382             ((reg_ea4 & 0x03ff0000)  < 0x01100000) &&
4383             ((reg_ea4 & 0x03ff0000)  > 0x00f00000) &&
4384             val32 < 0xf)
4385                 result |= 0x02;
4386         else    /* If TX not OK, ignore RX */
4387                 goto out;
4388 out:
4389         return result;
4390 }
4391
4392 #ifdef RTL8723BU_PATH_B
4393 static int rtl8723bu_iqk_path_b(struct rtl8xxxu_priv *priv)
4394 {
4395         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, path_sel;
4396         int result = 0;
4397
4398         path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4399
4400         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4401         val32 &= 0x000000ff;
4402         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4403
4404         /* One shot, path B LOK & IQK */
4405         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
4406         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
4407
4408         mdelay(1);
4409
4410         /* Check failed */
4411         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4412         reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4413         reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4414         reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4415         reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4416
4417         if (!(reg_eac & BIT(31)) &&
4418             ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
4419             ((reg_ebc & 0x03ff0000) != 0x00420000))
4420                 result |= 0x01;
4421         else
4422                 goto out;
4423
4424         if (!(reg_eac & BIT(30)) &&
4425             (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4426             (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4427                 result |= 0x02;
4428         else
4429                 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4430                          __func__);
4431 out:
4432         return result;
4433 }
4434 #endif
4435
4436 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4437                                      int result[][8], int t)
4438 {
4439         struct device *dev = &priv->udev->dev;
4440         u32 i, val32;
4441         int path_a_ok, path_b_ok;
4442         int retry = 2;
4443         const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4444                 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4445                 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4446                 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4447                 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4448                 REG_TX_TO_TX, REG_RX_CCK,
4449                 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4450                 REG_RX_TO_RX, REG_STANDBY,
4451                 REG_SLEEP, REG_PMPD_ANAEN
4452         };
4453         const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4454                 REG_TXPAUSE, REG_BEACON_CTRL,
4455                 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4456         };
4457         const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4458                 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4459                 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4460                 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4461                 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4462         };
4463
4464         /*
4465          * Note: IQ calibration must be performed after loading
4466          *       PHY_REG.txt , and radio_a, radio_b.txt
4467          */
4468
4469         if (t == 0) {
4470                 /* Save ADDA parameters, turn Path A ADDA on */
4471                 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4472                                    RTL8XXXU_ADDA_REGS);
4473                 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4474                 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4475                                    priv->bb_backup, RTL8XXXU_BB_REGS);
4476         }
4477
4478         rtl8xxxu_path_adda_on(priv, adda_regs, true);
4479
4480         if (t == 0) {
4481                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
4482                 if (val32 & FPGA0_HSSI_PARM1_PI)
4483                         priv->pi_enabled = 1;
4484         }
4485
4486         if (!priv->pi_enabled) {
4487                 /* Switch BB to PI mode to do IQ Calibration. */
4488                 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
4489                 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
4490         }
4491
4492         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4493         val32 &= ~FPGA_RF_MODE_CCK;
4494         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4495
4496         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4497         rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4498         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4499
4500         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
4501         val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
4502         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4503
4504         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
4505         val32 &= ~BIT(10);
4506         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
4507         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
4508         val32 &= ~BIT(10);
4509         rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
4510
4511         if (priv->tx_paths > 1) {
4512                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4513                 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
4514         }
4515
4516         /* MAC settings */
4517         rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4518
4519         /* Page B init */
4520         rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
4521
4522         if (priv->tx_paths > 1)
4523                 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
4524
4525         /* IQ calibration setting */
4526         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4527         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4528         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4529
4530         for (i = 0; i < retry; i++) {
4531                 path_a_ok = rtl8xxxu_iqk_path_a(priv);
4532                 if (path_a_ok == 0x03) {
4533                         val32 = rtl8xxxu_read32(priv,
4534                                                 REG_TX_POWER_BEFORE_IQK_A);
4535                         result[t][0] = (val32 >> 16) & 0x3ff;
4536                         val32 = rtl8xxxu_read32(priv,
4537                                                 REG_TX_POWER_AFTER_IQK_A);
4538                         result[t][1] = (val32 >> 16) & 0x3ff;
4539                         val32 = rtl8xxxu_read32(priv,
4540                                                 REG_RX_POWER_BEFORE_IQK_A_2);
4541                         result[t][2] = (val32 >> 16) & 0x3ff;
4542                         val32 = rtl8xxxu_read32(priv,
4543                                                 REG_RX_POWER_AFTER_IQK_A_2);
4544                         result[t][3] = (val32 >> 16) & 0x3ff;
4545                         break;
4546                 } else if (i == (retry - 1) && path_a_ok == 0x01) {
4547                         /* TX IQK OK */
4548                         dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
4549                                 __func__);
4550
4551                         val32 = rtl8xxxu_read32(priv,
4552                                                 REG_TX_POWER_BEFORE_IQK_A);
4553                         result[t][0] = (val32 >> 16) & 0x3ff;
4554                         val32 = rtl8xxxu_read32(priv,
4555                                                 REG_TX_POWER_AFTER_IQK_A);
4556                         result[t][1] = (val32 >> 16) & 0x3ff;
4557                 }
4558         }
4559
4560         if (!path_a_ok)
4561                 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
4562
4563         if (priv->tx_paths > 1) {
4564                 /*
4565                  * Path A into standby
4566                  */
4567                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
4568                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4569                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4570
4571                 /* Turn Path B ADDA on */
4572                 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4573
4574                 for (i = 0; i < retry; i++) {
4575                         path_b_ok = rtl8xxxu_iqk_path_b(priv);
4576                         if (path_b_ok == 0x03) {
4577                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4578                                 result[t][4] = (val32 >> 16) & 0x3ff;
4579                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4580                                 result[t][5] = (val32 >> 16) & 0x3ff;
4581                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4582                                 result[t][6] = (val32 >> 16) & 0x3ff;
4583                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4584                                 result[t][7] = (val32 >> 16) & 0x3ff;
4585                                 break;
4586                         } else if (i == (retry - 1) && path_b_ok == 0x01) {
4587                                 /* TX IQK OK */
4588                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4589                                 result[t][4] = (val32 >> 16) & 0x3ff;
4590                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4591                                 result[t][5] = (val32 >> 16) & 0x3ff;
4592                         }
4593                 }
4594
4595                 if (!path_b_ok)
4596                         dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4597         }
4598
4599         /* Back to BB mode, load original value */
4600         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
4601
4602         if (t) {
4603                 if (!priv->pi_enabled) {
4604                         /*
4605                          * Switch back BB to SI mode after finishing
4606                          * IQ Calibration
4607                          */
4608                         val32 = 0x01000000;
4609                         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
4610                         rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
4611                 }
4612
4613                 /* Reload ADDA power saving parameters */
4614                 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4615                                       RTL8XXXU_ADDA_REGS);
4616
4617                 /* Reload MAC parameters */
4618                 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4619
4620                 /* Reload BB parameters */
4621                 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4622                                       priv->bb_backup, RTL8XXXU_BB_REGS);
4623
4624                 /* Restore RX initial gain */
4625                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
4626
4627                 if (priv->tx_paths > 1) {
4628                         rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
4629                                          0x00032ed3);
4630                 }
4631
4632                 /* Load 0xe30 IQC default value */
4633                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4634                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4635         }
4636 }
4637
4638 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4639                                       int result[][8], int t)
4640 {
4641         struct device *dev = &priv->udev->dev;
4642         u32 i, val32;
4643         int path_a_ok /*, path_b_ok */;
4644         int retry = 2;
4645         const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4646                 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4647                 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4648                 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4649                 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4650                 REG_TX_TO_TX, REG_RX_CCK,
4651                 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4652                 REG_RX_TO_RX, REG_STANDBY,
4653                 REG_SLEEP, REG_PMPD_ANAEN
4654         };
4655         const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4656                 REG_TXPAUSE, REG_BEACON_CTRL,
4657                 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4658         };
4659         const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4660                 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4661                 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4662                 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4663                 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4664         };
4665         u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
4666         u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
4667
4668         /*
4669          * Note: IQ calibration must be performed after loading
4670          *       PHY_REG.txt , and radio_a, radio_b.txt
4671          */
4672
4673         if (t == 0) {
4674                 /* Save ADDA parameters, turn Path A ADDA on */
4675                 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4676                                    RTL8XXXU_ADDA_REGS);
4677                 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4678                 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4679                                    priv->bb_backup, RTL8XXXU_BB_REGS);
4680         }
4681
4682         rtl8xxxu_path_adda_on(priv, adda_regs, true);
4683
4684         /* MAC settings */
4685         rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4686
4687         val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
4688         val32 |= 0x0f000000;
4689         rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
4690
4691         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4692         rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4693         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4694
4695 #ifdef RTL8723BU_PATH_B
4696         /* Set RF mode to standby Path B */
4697         if (priv->tx_paths > 1)
4698                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x10000);
4699 #endif
4700
4701 #if 0
4702         /* Page B init */
4703         rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x0f600000);
4704
4705         if (priv->tx_paths > 1)
4706                 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x0f600000);
4707 #endif
4708
4709         /*
4710          * RX IQ calibration setting for 8723B D cut large current issue
4711          * when leaving IPS
4712          */
4713         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4714         val32 &= 0x000000ff;
4715         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4716
4717         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4718         val32 |= 0x80000;
4719         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4720
4721         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4722         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4723         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4724
4725         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
4726         val32 |= 0x20;
4727         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
4728
4729         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd);
4730
4731         for (i = 0; i < retry; i++) {
4732                 path_a_ok = rtl8723bu_iqk_path_a(priv);
4733                 if (path_a_ok == 0x01) {
4734                         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4735                         val32 &= 0x000000ff;
4736                         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4737
4738 #if 0 /* Only needed in restore case, we may need this when going to suspend */
4739                         priv->RFCalibrateInfo.TxLOK[RF_A] =
4740                                 rtl8xxxu_read_rfreg(priv, RF_A,
4741                                                     RF6052_REG_TXM_IDAC);
4742 #endif
4743
4744                         val32 = rtl8xxxu_read32(priv,
4745                                                 REG_TX_POWER_BEFORE_IQK_A);
4746                         result[t][0] = (val32 >> 16) & 0x3ff;
4747                         val32 = rtl8xxxu_read32(priv,
4748                                                 REG_TX_POWER_AFTER_IQK_A);
4749                         result[t][1] = (val32 >> 16) & 0x3ff;
4750
4751                         break;
4752                 }
4753         }
4754
4755         if (!path_a_ok)
4756                 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
4757
4758         for (i = 0; i < retry; i++) {
4759                 path_a_ok = rtl8723bu_rx_iqk_path_a(priv);
4760                 if (path_a_ok == 0x03) {
4761                         val32 = rtl8xxxu_read32(priv,
4762                                                 REG_RX_POWER_BEFORE_IQK_A_2);
4763                         result[t][2] = (val32 >> 16) & 0x3ff;
4764                         val32 = rtl8xxxu_read32(priv,
4765                                                 REG_RX_POWER_AFTER_IQK_A_2);
4766                         result[t][3] = (val32 >> 16) & 0x3ff;
4767
4768                         break;
4769                 }
4770         }
4771
4772         if (!path_a_ok)
4773                 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
4774
4775         if (priv->tx_paths > 1) {
4776 #if 1
4777                 dev_warn(dev, "%s: Path B not supported\n", __func__);
4778 #else
4779
4780                 /*
4781                  * Path A into standby
4782                  */
4783                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4784                 val32 &= 0x000000ff;
4785                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4786                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
4787
4788                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4789                 val32 &= 0x000000ff;
4790                 val32 |= 0x80800000;
4791                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4792
4793                 /* Turn Path B ADDA on */
4794                 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4795
4796                 for (i = 0; i < retry; i++) {
4797                         path_b_ok = rtl8xxxu_iqk_path_b(priv);
4798                         if (path_b_ok == 0x03) {
4799                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4800                                 result[t][4] = (val32 >> 16) & 0x3ff;
4801                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4802                                 result[t][5] = (val32 >> 16) & 0x3ff;
4803                                 break;
4804                         }
4805                 }
4806
4807                 if (!path_b_ok)
4808                         dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4809
4810                 for (i = 0; i < retry; i++) {
4811                         path_b_ok = rtl8723bu_rx_iqk_path_b(priv);
4812                         if (path_a_ok == 0x03) {
4813                                 val32 = rtl8xxxu_read32(priv,
4814                                                         REG_RX_POWER_BEFORE_IQK_B_2);
4815                                 result[t][6] = (val32 >> 16) & 0x3ff;
4816                                 val32 = rtl8xxxu_read32(priv,
4817                                                         REG_RX_POWER_AFTER_IQK_B_2);
4818                                 result[t][7] = (val32 >> 16) & 0x3ff;
4819                                 break;
4820                         }
4821                 }
4822
4823                 if (!path_b_ok)
4824                         dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
4825 #endif
4826         }
4827
4828         /* Back to BB mode, load original value */
4829         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4830         val32 &= 0x000000ff;
4831         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4832
4833         if (t) {
4834                 /* Reload ADDA power saving parameters */
4835                 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4836                                       RTL8XXXU_ADDA_REGS);
4837
4838                 /* Reload MAC parameters */
4839                 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4840
4841                 /* Reload BB parameters */
4842                 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4843                                       priv->bb_backup, RTL8XXXU_BB_REGS);
4844
4845                 /* Restore RX initial gain */
4846                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4847                 val32 &= 0xffffff00;
4848                 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
4849                 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
4850
4851                 if (priv->tx_paths > 1) {
4852                         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
4853                         val32 &= 0xffffff00;
4854                         rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4855                                          val32 | 0x50);
4856                         rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4857                                          val32 | xb_agc);
4858                 }
4859
4860                 /* Load 0xe30 IQC default value */
4861                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4862                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4863         }
4864 }
4865
4866 static void rtl8xxxu_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
4867 {
4868         struct h2c_cmd h2c;
4869
4870         if (priv->fops->mbox_ext_width < 4)
4871                 return;
4872
4873         memset(&h2c, 0, sizeof(struct h2c_cmd));
4874         h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
4875         h2c.bt_wlan_calibration.data = start;
4876
4877         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
4878 }
4879
4880 static void rtl8723au_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
4881 {
4882         struct device *dev = &priv->udev->dev;
4883         int result[4][8];       /* last is final result */
4884         int i, candidate;
4885         bool path_a_ok, path_b_ok;
4886         u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
4887         u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4888         s32 reg_tmp = 0;
4889         bool simu;
4890
4891         rtl8xxxu_prepare_calibrate(priv, 1);
4892
4893         memset(result, 0, sizeof(result));
4894         candidate = -1;
4895
4896         path_a_ok = false;
4897         path_b_ok = false;
4898
4899         rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4900
4901         for (i = 0; i < 3; i++) {
4902                 rtl8xxxu_phy_iqcalibrate(priv, result, i);
4903
4904                 if (i == 1) {
4905                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
4906                         if (simu) {
4907                                 candidate = 0;
4908                                 break;
4909                         }
4910                 }
4911
4912                 if (i == 2) {
4913                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
4914                         if (simu) {
4915                                 candidate = 0;
4916                                 break;
4917                         }
4918
4919                         simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
4920                         if (simu) {
4921                                 candidate = 1;
4922                         } else {
4923                                 for (i = 0; i < 8; i++)
4924                                         reg_tmp += result[3][i];
4925
4926                                 if (reg_tmp)
4927                                         candidate = 3;
4928                                 else
4929                                         candidate = -1;
4930                         }
4931                 }
4932         }
4933
4934         for (i = 0; i < 4; i++) {
4935                 reg_e94 = result[i][0];
4936                 reg_e9c = result[i][1];
4937                 reg_ea4 = result[i][2];
4938                 reg_eac = result[i][3];
4939                 reg_eb4 = result[i][4];
4940                 reg_ebc = result[i][5];
4941                 reg_ec4 = result[i][6];
4942                 reg_ecc = result[i][7];
4943         }
4944
4945         if (candidate >= 0) {
4946                 reg_e94 = result[candidate][0];
4947                 priv->rege94 =  reg_e94;
4948                 reg_e9c = result[candidate][1];
4949                 priv->rege9c = reg_e9c;
4950                 reg_ea4 = result[candidate][2];
4951                 reg_eac = result[candidate][3];
4952                 reg_eb4 = result[candidate][4];
4953                 priv->regeb4 = reg_eb4;
4954                 reg_ebc = result[candidate][5];
4955                 priv->regebc = reg_ebc;
4956                 reg_ec4 = result[candidate][6];
4957                 reg_ecc = result[candidate][7];
4958                 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
4959                 dev_dbg(dev,
4960                         "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
4961                         "ecc=%x\n ", __func__, reg_e94, reg_e9c,
4962                         reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
4963                 path_a_ok = true;
4964                 path_b_ok = true;
4965         } else {
4966                 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
4967                 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
4968         }
4969
4970         if (reg_e94 && candidate >= 0)
4971                 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
4972                                            candidate, (reg_ea4 == 0));
4973
4974         if (priv->tx_paths > 1 && reg_eb4)
4975                 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
4976                                            candidate, (reg_ec4 == 0));
4977
4978         rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
4979                            priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
4980
4981         rtl8xxxu_prepare_calibrate(priv, 0);
4982 }
4983
4984 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
4985 {
4986         struct device *dev = &priv->udev->dev;
4987         int result[4][8];       /* last is final result */
4988         int i, candidate;
4989         bool path_a_ok, path_b_ok;
4990         u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
4991         u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4992         u32 val32, bt_control;
4993         s32 reg_tmp = 0;
4994         bool simu;
4995
4996         rtl8xxxu_prepare_calibrate(priv, 1);
4997
4998         memset(result, 0, sizeof(result));
4999         candidate = -1;
5000
5001         path_a_ok = false;
5002         path_b_ok = false;
5003
5004         bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU);
5005
5006         for (i = 0; i < 3; i++) {
5007                 rtl8723bu_phy_iqcalibrate(priv, result, i);
5008
5009                 if (i == 1) {
5010                         simu = rtl8723bu_simularity_compare(priv, result, 0, 1);
5011                         if (simu) {
5012                                 candidate = 0;
5013                                 break;
5014                         }
5015                 }
5016
5017                 if (i == 2) {
5018                         simu = rtl8723bu_simularity_compare(priv, result, 0, 2);
5019                         if (simu) {
5020                                 candidate = 0;
5021                                 break;
5022                         }
5023
5024                         simu = rtl8723bu_simularity_compare(priv, result, 1, 2);
5025                         if (simu) {
5026                                 candidate = 1;
5027                         } else {
5028                                 for (i = 0; i < 8; i++)
5029                                         reg_tmp += result[3][i];
5030
5031                                 if (reg_tmp)
5032                                         candidate = 3;
5033                                 else
5034                                         candidate = -1;
5035                         }
5036                 }
5037         }
5038
5039         for (i = 0; i < 4; i++) {
5040                 reg_e94 = result[i][0];
5041                 reg_e9c = result[i][1];
5042                 reg_ea4 = result[i][2];
5043                 reg_eac = result[i][3];
5044                 reg_eb4 = result[i][4];
5045                 reg_ebc = result[i][5];
5046                 reg_ec4 = result[i][6];
5047                 reg_ecc = result[i][7];
5048         }
5049
5050         if (candidate >= 0) {
5051                 reg_e94 = result[candidate][0];
5052                 priv->rege94 =  reg_e94;
5053                 reg_e9c = result[candidate][1];
5054                 priv->rege9c = reg_e9c;
5055                 reg_ea4 = result[candidate][2];
5056                 reg_eac = result[candidate][3];
5057                 reg_eb4 = result[candidate][4];
5058                 priv->regeb4 = reg_eb4;
5059                 reg_ebc = result[candidate][5];
5060                 priv->regebc = reg_ebc;
5061                 reg_ec4 = result[candidate][6];
5062                 reg_ecc = result[candidate][7];
5063                 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
5064                 dev_dbg(dev,
5065                         "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
5066                         "ecc=%x\n ", __func__, reg_e94, reg_e9c,
5067                         reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
5068                 path_a_ok = true;
5069                 path_b_ok = true;
5070         } else {
5071                 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
5072                 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
5073         }
5074
5075         if (reg_e94 && candidate >= 0)
5076                 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
5077                                            candidate, (reg_ea4 == 0));
5078
5079         if (priv->tx_paths > 1 && reg_eb4)
5080                 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
5081                                            candidate, (reg_ec4 == 0));
5082
5083         rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
5084                            priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
5085
5086         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control);
5087
5088         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
5089         val32 |= 0x80000;
5090         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
5091         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000);
5092         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
5093         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177);
5094         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
5095         val32 |= 0x20;
5096         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
5097         rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd);
5098
5099         if (priv->rf_paths > 1) {
5100                 dev_dbg(dev, "%s: beware 2T not yet supported\n", __func__);
5101 #ifdef RTL8723BU_PATH_B
5102                 if (RF_Path == 0x0)     //S1
5103                         ODM_SetIQCbyRFpath(pDM_Odm, 0);
5104                 else    //S0
5105                         ODM_SetIQCbyRFpath(pDM_Odm, 1);
5106 #endif
5107         }
5108         rtl8xxxu_prepare_calibrate(priv, 0);
5109 }
5110
5111 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
5112 {
5113         u32 val32;
5114         u32 rf_amode, rf_bmode = 0, lstf;
5115
5116         /* Check continuous TX and Packet TX */
5117         lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
5118
5119         if (lstf & OFDM_LSTF_MASK) {
5120                 /* Disable all continuous TX */
5121                 val32 = lstf & ~OFDM_LSTF_MASK;
5122                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
5123
5124                 /* Read original RF mode Path A */
5125                 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
5126
5127                 /* Set RF mode to standby Path A */
5128                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
5129                                      (rf_amode & 0x8ffff) | 0x10000);
5130
5131                 /* Path-B */
5132                 if (priv->tx_paths > 1) {
5133                         rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
5134                                                        RF6052_REG_AC);
5135
5136                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
5137                                              (rf_bmode & 0x8ffff) | 0x10000);
5138                 }
5139         } else {
5140                 /*  Deal with Packet TX case */
5141                 /*  block all queues */
5142                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5143         }
5144
5145         /* Start LC calibration */
5146         if (priv->fops->has_s0s1)
5147                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
5148         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
5149         val32 |= 0x08000;
5150         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
5151
5152         msleep(100);
5153
5154         if (priv->fops->has_s0s1)
5155                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
5156
5157         /* Restore original parameters */
5158         if (lstf & OFDM_LSTF_MASK) {
5159                 /* Path-A */
5160                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
5161                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
5162
5163                 /* Path-B */
5164                 if (priv->tx_paths > 1)
5165                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
5166                                              rf_bmode);
5167         } else /*  Deal with Packet TX case */
5168                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
5169 }
5170
5171 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
5172 {
5173         int i;
5174         u16 reg;
5175
5176         reg = REG_MACID;
5177
5178         for (i = 0; i < ETH_ALEN; i++)
5179                 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
5180
5181         return 0;
5182 }
5183
5184 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
5185 {
5186         int i;
5187         u16 reg;
5188
5189         dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
5190
5191         reg = REG_BSSID;
5192
5193         for (i = 0; i < ETH_ALEN; i++)
5194                 rtl8xxxu_write8(priv, reg + i, bssid[i]);
5195
5196         return 0;
5197 }
5198
5199 static void
5200 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
5201 {
5202         u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
5203         u8 max_agg = 0xf;
5204         int i;
5205
5206         ampdu_factor = 1 << (ampdu_factor + 2);
5207         if (ampdu_factor > max_agg)
5208                 ampdu_factor = max_agg;
5209
5210         for (i = 0; i < 4; i++) {
5211                 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
5212                         vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
5213
5214                 if ((vals[i] & 0x0f) > ampdu_factor)
5215                         vals[i] = (vals[i] & 0xf0) | ampdu_factor;
5216
5217                 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
5218         }
5219 }
5220
5221 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
5222 {
5223         u8 val8;
5224
5225         val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
5226         val8 &= 0xf8;
5227         val8 |= density;
5228         rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
5229 }
5230
5231 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
5232 {
5233         u8 val8;
5234         int count, ret;
5235
5236         /* Start of rtl8723AU_card_enable_flow */
5237         /* Act to Cardemu sequence*/
5238         /* Turn off RF */
5239         rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
5240
5241         /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
5242         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5243         val8 &= ~LEDCFG2_DPDT_SELECT;
5244         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5245
5246         /* 0x0005[1] = 1 turn off MAC by HW state machine*/
5247         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5248         val8 |= BIT(1);
5249         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5250
5251         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5252                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5253                 if ((val8 & BIT(1)) == 0)
5254                         break;
5255                 udelay(10);
5256         }
5257
5258         if (!count) {
5259                 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
5260                          __func__);
5261                 ret = -EBUSY;
5262                 goto exit;
5263         }
5264
5265         /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
5266         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5267         val8 |= SYS_ISO_ANALOG_IPS;
5268         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5269
5270         /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
5271         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5272         val8 &= ~LDOA15_ENABLE;
5273         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5274
5275 exit:
5276         return ret;
5277 }
5278
5279 static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv *priv)
5280 {
5281         u8 val8;
5282         u16 val16;
5283         u32 val32;
5284         int count, ret;
5285
5286         /* Turn off RF */
5287         rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
5288
5289         /* Enable rising edge triggering interrupt */
5290         val16 = rtl8xxxu_read16(priv, REG_GPIO_INTM);
5291         val16 &= ~GPIO_INTM_EDGE_TRIG_IRQ;
5292         rtl8xxxu_write16(priv, REG_GPIO_INTM, val16);
5293
5294         /* Release WLON reset 0x04[16]= 1*/
5295         val32 = rtl8xxxu_read32(priv, REG_GPIO_INTM);
5296         val32 |= APS_FSMCO_WLON_RESET;
5297         rtl8xxxu_write32(priv, REG_GPIO_INTM, val32);
5298
5299         /* 0x0005[1] = 1 turn off MAC by HW state machine*/
5300         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5301         val8 |= BIT(1);
5302         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5303
5304         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5305                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5306                 if ((val8 & BIT(1)) == 0)
5307                         break;
5308                 udelay(10);
5309         }
5310
5311         if (!count) {
5312                 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
5313                          __func__);
5314                 ret = -EBUSY;
5315                 goto exit;
5316         }
5317
5318         /* Enable BT control XTAL setting */
5319         val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
5320         val8 &= ~AFE_MISC_WL_XTAL_CTRL;
5321         rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
5322
5323         /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
5324         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5325         val8 |= SYS_ISO_ANALOG_IPS;
5326         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5327
5328         /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
5329         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5330         val8 &= ~LDOA15_ENABLE;
5331         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5332
5333 exit:
5334         return ret;
5335 }
5336
5337 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
5338 {
5339         u8 val8;
5340         u8 val32;
5341         int count, ret;
5342
5343         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5344
5345         /*
5346          * Poll - wait for RX packet to complete
5347          */
5348         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5349                 val32 = rtl8xxxu_read32(priv, 0x5f8);
5350                 if (!val32)
5351                         break;
5352                 udelay(10);
5353         }
5354
5355         if (!count) {
5356                 dev_warn(&priv->udev->dev,
5357                          "%s: RX poll timed out (0x05f8)\n", __func__);
5358                 ret = -EBUSY;
5359                 goto exit;
5360         }
5361
5362         /* Disable CCK and OFDM, clock gated */
5363         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5364         val8 &= ~SYS_FUNC_BBRSTB;
5365         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5366
5367         udelay(2);
5368
5369         /* Reset baseband */
5370         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5371         val8 &= ~SYS_FUNC_BB_GLB_RSTN;
5372         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5373
5374         /* Reset MAC TRX */
5375         val8 = rtl8xxxu_read8(priv, REG_CR);
5376         val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
5377         rtl8xxxu_write8(priv, REG_CR, val8);
5378
5379         /* Reset MAC TRX */
5380         val8 = rtl8xxxu_read8(priv, REG_CR + 1);
5381         val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
5382         rtl8xxxu_write8(priv, REG_CR + 1, val8);
5383
5384         /* Respond TX OK to scheduler */
5385         val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
5386         val8 |= DUAL_TSF_TX_OK;
5387         rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
5388
5389 exit:
5390         return ret;
5391 }
5392
5393 static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv)
5394 {
5395         u8 val8;
5396
5397         /* Clear suspend enable and power down enable*/
5398         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5399         val8 &= ~(BIT(3) | BIT(7));
5400         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5401
5402         /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
5403         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5404         val8 &= ~BIT(0);
5405         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5406
5407         /* 0x04[12:11] = 11 enable WL suspend*/
5408         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5409         val8 &= ~(BIT(3) | BIT(4));
5410         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5411 }
5412
5413 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
5414 {
5415         u8 val8;
5416
5417         /* Clear suspend enable and power down enable*/
5418         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5419         val8 &= ~(BIT(3) | BIT(4));
5420         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5421 }
5422
5423 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
5424 {
5425         u8 val8;
5426         u32 val32;
5427         int count, ret = 0;
5428
5429         /* disable HWPDN 0x04[15]=0*/
5430         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5431         val8 &= ~BIT(7);
5432         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5433
5434         /* disable SW LPS 0x04[10]= 0 */
5435         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5436         val8 &= ~BIT(2);
5437         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5438
5439         /* disable WL suspend*/
5440         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5441         val8 &= ~(BIT(3) | BIT(4));
5442         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5443
5444         /* wait till 0x04[17] = 1 power ready*/
5445         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5446                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5447                 if (val32 & BIT(17))
5448                         break;
5449
5450                 udelay(10);
5451         }
5452
5453         if (!count) {
5454                 ret = -EBUSY;
5455                 goto exit;
5456         }
5457
5458         /* We should be able to optimize the following three entries into one */
5459
5460         /* release WLON reset 0x04[16]= 1*/
5461         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5462         val8 |= BIT(0);
5463         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5464
5465         /* set, then poll until 0 */
5466         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5467         val32 |= APS_FSMCO_MAC_ENABLE;
5468         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5469
5470         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5471                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5472                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5473                         ret = 0;
5474                         break;
5475                 }
5476                 udelay(10);
5477         }
5478
5479         if (!count) {
5480                 ret = -EBUSY;
5481                 goto exit;
5482         }
5483
5484 exit:
5485         return ret;
5486 }
5487
5488 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
5489 {
5490         u8 val8;
5491         u32 val32;
5492         int count, ret = 0;
5493
5494         /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
5495         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5496         val8 |= LDOA15_ENABLE;
5497         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5498
5499         /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5500         val8 = rtl8xxxu_read8(priv, 0x0067);
5501         val8 &= ~BIT(4);
5502         rtl8xxxu_write8(priv, 0x0067, val8);
5503
5504         mdelay(1);
5505
5506         /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5507         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5508         val8 &= ~SYS_ISO_ANALOG_IPS;
5509         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5510
5511         /* disable SW LPS 0x04[10]= 0 */
5512         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5513         val8 &= ~BIT(2);
5514         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5515
5516         /* wait till 0x04[17] = 1 power ready*/
5517         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5518                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5519                 if (val32 & BIT(17))
5520                         break;
5521
5522                 udelay(10);
5523         }
5524
5525         if (!count) {
5526                 ret = -EBUSY;
5527                 goto exit;
5528         }
5529
5530         /* We should be able to optimize the following three entries into one */
5531
5532         /* release WLON reset 0x04[16]= 1*/
5533         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5534         val8 |= BIT(0);
5535         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5536
5537         /* disable HWPDN 0x04[15]= 0*/
5538         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5539         val8 &= ~BIT(7);
5540         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5541
5542         /* disable WL suspend*/
5543         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5544         val8 &= ~(BIT(3) | BIT(4));
5545         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5546
5547         /* set, then poll until 0 */
5548         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5549         val32 |= APS_FSMCO_MAC_ENABLE;
5550         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5551
5552         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5553                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5554                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5555                         ret = 0;
5556                         break;
5557                 }
5558                 udelay(10);
5559         }
5560
5561         if (!count) {
5562                 ret = -EBUSY;
5563                 goto exit;
5564         }
5565
5566         /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
5567         /*
5568          * Note: Vendor driver actually clears this bit, despite the
5569          * documentation claims it's being set!
5570          */
5571         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5572         val8 |= LEDCFG2_DPDT_SELECT;
5573         val8 &= ~LEDCFG2_DPDT_SELECT;
5574         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5575
5576 exit:
5577         return ret;
5578 }
5579
5580 static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv)
5581 {
5582         u8 val8;
5583         u32 val32;
5584         int count, ret = 0;
5585
5586         /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */
5587         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5588         val8 |= LDOA15_ENABLE;
5589         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5590
5591         /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5592         val8 = rtl8xxxu_read8(priv, 0x0067);
5593         val8 &= ~BIT(4);
5594         rtl8xxxu_write8(priv, 0x0067, val8);
5595
5596         mdelay(1);
5597
5598         /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5599         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5600         val8 &= ~SYS_ISO_ANALOG_IPS;
5601         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5602
5603         /* Disable SW LPS 0x04[10]= 0 */
5604         val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
5605         val32 &= ~APS_FSMCO_SW_LPS;
5606         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5607
5608         /* Wait until 0x04[17] = 1 power ready */
5609         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5610                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5611                 if (val32 & BIT(17))
5612                         break;
5613
5614                 udelay(10);
5615         }
5616
5617         if (!count) {
5618                 ret = -EBUSY;
5619                 goto exit;
5620         }
5621
5622         /* We should be able to optimize the following three entries into one */
5623
5624         /* Release WLON reset 0x04[16]= 1*/
5625         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5626         val32 |= APS_FSMCO_WLON_RESET;
5627         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5628
5629         /* Disable HWPDN 0x04[15]= 0*/
5630         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5631         val32 &= ~APS_FSMCO_HW_POWERDOWN;
5632         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5633
5634         /* Disable WL suspend*/
5635         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5636         val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE);
5637         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5638
5639         /* Set, then poll until 0 */
5640         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5641         val32 |= APS_FSMCO_MAC_ENABLE;
5642         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5643
5644         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5645                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5646                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5647                         ret = 0;
5648                         break;
5649                 }
5650                 udelay(10);
5651         }
5652
5653         if (!count) {
5654                 ret = -EBUSY;
5655                 goto exit;
5656         }
5657
5658         /* Enable WL control XTAL setting */
5659         val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
5660         val8 |= AFE_MISC_WL_XTAL_CTRL;
5661         rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
5662
5663         /* Enable falling edge triggering interrupt */
5664         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1);
5665         val8 |= BIT(1);
5666         rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8);
5667
5668         /* Enable GPIO9 interrupt mode */
5669         val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1);
5670         val8 |= BIT(1);
5671         rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8);
5672
5673         /* Enable GPIO9 input mode */
5674         val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2);
5675         val8 &= ~BIT(1);
5676         rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8);
5677
5678         /* Enable HSISR GPIO[C:0] interrupt */
5679         val8 = rtl8xxxu_read8(priv, REG_HSIMR);
5680         val8 |= BIT(0);
5681         rtl8xxxu_write8(priv, REG_HSIMR, val8);
5682
5683         /* Enable HSISR GPIO9 interrupt */
5684         val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2);
5685         val8 |= BIT(1);
5686         rtl8xxxu_write8(priv, REG_HSIMR + 2, val8);
5687
5688         val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL);
5689         val8 |= MULTI_WIFI_HW_ROF_EN;
5690         rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8);
5691
5692         /* For GPIO9 internal pull high setting BIT(14) */
5693         val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1);
5694         val8 |= BIT(6);
5695         rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8);
5696
5697 exit:
5698         return ret;
5699 }
5700
5701 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
5702 {
5703         u8 val8;
5704
5705         /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
5706         rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
5707
5708         /* 0x04[12:11] = 01 enable WL suspend */
5709         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5710         val8 &= ~BIT(4);
5711         val8 |= BIT(3);
5712         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5713
5714         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5715         val8 |= BIT(7);
5716         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5717
5718         /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
5719         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5720         val8 |= BIT(0);
5721         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5722
5723         return 0;
5724 }
5725
5726 static int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv)
5727 {
5728         struct device *dev = &priv->udev->dev;
5729         u32 val32;
5730         int retry, retval;
5731
5732         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5733
5734         val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
5735         val32 |= RXPKT_NUM_RW_RELEASE_EN;
5736         rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32);
5737
5738         retry = 100;
5739         retval = -EBUSY;
5740
5741         do {
5742                 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
5743                 if (val32 & RXPKT_NUM_RXDMA_IDLE) {
5744                         retval = 0;
5745                         break;
5746                 }
5747         } while (retry--);
5748
5749         rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0);
5750         rtl8xxxu_write32(priv, REG_RQPN, 0x80000000);
5751         mdelay(2);
5752
5753         if (!retry)
5754                 dev_warn(dev, "Failed to flush FIFO\n");
5755
5756         return retval;
5757 }
5758
5759 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
5760 {
5761         u8 val8;
5762         u16 val16;
5763         u32 val32;
5764         int ret;
5765
5766         /*
5767          * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5768          */
5769         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5770
5771         rtl8723a_disabled_to_emu(priv);
5772
5773         ret = rtl8723a_emu_to_active(priv);
5774         if (ret)
5775                 goto exit;
5776
5777         /*
5778          * 0x0004[19] = 1, reset 8051
5779          */
5780         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5781         val8 |= BIT(3);
5782         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5783
5784         /*
5785          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5786          * Set CR bit10 to enable 32k calibration.
5787          */
5788         val16 = rtl8xxxu_read16(priv, REG_CR);
5789         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5790                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5791                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5792                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5793                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5794         rtl8xxxu_write16(priv, REG_CR, val16);
5795
5796         /* For EFuse PG */
5797         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
5798         val32 &= ~(BIT(28) | BIT(29) | BIT(30));
5799         val32 |= (0x06 << 28);
5800         rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
5801 exit:
5802         return ret;
5803 }
5804
5805 static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv)
5806 {
5807         u8 val8;
5808         u16 val16;
5809         u32 val32;
5810         int ret;
5811
5812         rtl8723a_disabled_to_emu(priv);
5813
5814         ret = rtl8723b_emu_to_active(priv);
5815         if (ret)
5816                 goto exit;
5817
5818         /*
5819          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5820          * Set CR bit10 to enable 32k calibration.
5821          */
5822         val16 = rtl8xxxu_read16(priv, REG_CR);
5823         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5824                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5825                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5826                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5827                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5828         rtl8xxxu_write16(priv, REG_CR, val16);
5829
5830         /*
5831          * BT coexist power on settings. This is identical for 1 and 2
5832          * antenna parts.
5833          */
5834         rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20);
5835
5836         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
5837         val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN;
5838         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
5839
5840         rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18);
5841         rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
5842         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
5843         /* Antenna inverse */
5844         rtl8xxxu_write8(priv, 0xfe08, 0x01);
5845
5846         val16 = rtl8xxxu_read16(priv, REG_PWR_DATA);
5847         val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
5848         rtl8xxxu_write16(priv, REG_PWR_DATA, val16);
5849
5850         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
5851         val32 |= LEDCFG0_DPDT_SELECT;
5852         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
5853
5854         val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
5855         val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA;
5856         rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
5857 exit:
5858         return ret;
5859 }
5860
5861 #ifdef CONFIG_RTL8XXXU_UNTESTED
5862
5863 static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
5864 {
5865         u8 val8;
5866         u16 val16;
5867         u32 val32;
5868         int i;
5869
5870         for (i = 100; i; i--) {
5871                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
5872                 if (val8 & APS_FSMCO_PFM_ALDN)
5873                         break;
5874         }
5875
5876         if (!i) {
5877                 pr_info("%s: Poll failed\n", __func__);
5878                 return -ENODEV;
5879         }
5880
5881         /*
5882          * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5883          */
5884         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5885         rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
5886         udelay(100);
5887
5888         val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
5889         if (!(val8 & LDOV12D_ENABLE)) {
5890                 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
5891                 val8 |= LDOV12D_ENABLE;
5892                 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
5893
5894                 udelay(100);
5895
5896                 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5897                 val8 &= ~SYS_ISO_MD2PP;
5898                 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5899         }
5900
5901         /*
5902          * Auto enable WLAN
5903          */
5904         val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5905         val16 |= APS_FSMCO_MAC_ENABLE;
5906         rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5907
5908         for (i = 1000; i; i--) {
5909                 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5910                 if (!(val16 & APS_FSMCO_MAC_ENABLE))
5911                         break;
5912         }
5913         if (!i) {
5914                 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
5915                 return -EBUSY;
5916         }
5917
5918         /*
5919          * Enable radio, GPIO, LED
5920          */
5921         val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
5922                 APS_FSMCO_PFM_ALDN;
5923         rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5924
5925         /*
5926          * Release RF digital isolation
5927          */
5928         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
5929         val16 &= ~SYS_ISO_DIOR;
5930         rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
5931
5932         val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5933         val8 &= ~APSD_CTRL_OFF;
5934         rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
5935         for (i = 200; i; i--) {
5936                 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5937                 if (!(val8 & APSD_CTRL_OFF_STATUS))
5938                         break;
5939         }
5940
5941         if (!i) {
5942                 pr_info("%s: APSD_CTRL poll failed\n", __func__);
5943                 return -EBUSY;
5944         }
5945
5946         /*
5947          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5948          */
5949         val16 = rtl8xxxu_read16(priv, REG_CR);
5950         val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5951                 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
5952                 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
5953         rtl8xxxu_write16(priv, REG_CR, val16);
5954
5955         /*
5956          * Workaround for 8188RU LNA power leakage problem.
5957          */
5958         if (priv->rtl_chip == RTL8188C && priv->hi_pa) {
5959                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
5960                 val32 &= ~BIT(1);
5961                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
5962         }
5963         return 0;
5964 }
5965
5966 #endif
5967
5968 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
5969 {
5970         u16 val16;
5971         u32 val32;
5972         int ret;
5973
5974         ret = 0;
5975
5976         val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
5977         if (val32 & SYS_CFG_SPS_LDO_SEL) {
5978                 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
5979         } else {
5980                 /*
5981                  * Raise 1.2V voltage
5982                  */
5983                 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
5984                 val32 &= 0xff0fffff;
5985                 val32 |= 0x00500000;
5986                 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
5987                 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
5988         }
5989
5990         rtl8192e_disabled_to_emu(priv);
5991
5992         ret = rtl8192e_emu_to_active(priv);
5993         if (ret)
5994                 goto exit;
5995
5996         rtl8xxxu_write16(priv, REG_CR, 0x0000);
5997
5998         /*
5999          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
6000          * Set CR bit10 to enable 32k calibration.
6001          */
6002         val16 = rtl8xxxu_read16(priv, REG_CR);
6003         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
6004                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
6005                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
6006                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
6007                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
6008         rtl8xxxu_write16(priv, REG_CR, val16);
6009
6010 exit:
6011         return ret;
6012 }
6013
6014 static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
6015 {
6016         u8 val8;
6017         u16 val16;
6018         u32 val32;
6019
6020         /*
6021          * Workaround for 8188RU LNA power leakage problem.
6022          */
6023         if (priv->rtl_chip == RTL8188C && priv->hi_pa) {
6024                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
6025                 val32 |= BIT(1);
6026                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
6027         }
6028
6029         rtl8xxxu_flush_fifo(priv);
6030
6031         rtl8xxxu_active_to_lps(priv);
6032
6033         /* Turn off RF */
6034         rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
6035
6036         /* Reset Firmware if running in RAM */
6037         if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
6038                 rtl8xxxu_firmware_self_reset(priv);
6039
6040         /* Reset MCU */
6041         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
6042         val16 &= ~SYS_FUNC_CPU_ENABLE;
6043         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
6044
6045         /* Reset MCU ready status */
6046         rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
6047
6048         rtl8xxxu_active_to_emu(priv);
6049         rtl8xxxu_emu_to_disabled(priv);
6050
6051         /* Reset MCU IO Wrapper */
6052         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
6053         val8 &= ~BIT(0);
6054         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
6055
6056         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
6057         val8 |= BIT(0);
6058         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
6059
6060         /* RSV_CTRL 0x1C[7:0] = 0x0e  lock ISO/CLK/Power control register */
6061         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
6062 }
6063
6064 static void rtl8723bu_power_off(struct rtl8xxxu_priv *priv)
6065 {
6066         u8 val8;
6067         u16 val16;
6068
6069         rtl8xxxu_flush_fifo(priv);
6070
6071         /*
6072          * Disable TX report timer
6073          */
6074         val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
6075         val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;
6076         rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
6077
6078         rtl8xxxu_write16(priv, REG_CR, 0x0000);
6079
6080         rtl8xxxu_active_to_lps(priv);
6081
6082         /* Reset Firmware if running in RAM */
6083         if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
6084                 rtl8xxxu_firmware_self_reset(priv);
6085
6086         /* Reset MCU */
6087         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
6088         val16 &= ~SYS_FUNC_CPU_ENABLE;
6089         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
6090
6091         /* Reset MCU ready status */
6092         rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
6093
6094         rtl8723bu_active_to_emu(priv);
6095         rtl8xxxu_emu_to_disabled(priv);
6096 }
6097
6098 #ifdef NEED_PS_TDMA
6099 static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
6100                                   u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
6101 {
6102         struct h2c_cmd h2c;
6103
6104         memset(&h2c, 0, sizeof(struct h2c_cmd));
6105         h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
6106         h2c.b_type_dma.data1 = arg1;
6107         h2c.b_type_dma.data2 = arg2;
6108         h2c.b_type_dma.data3 = arg3;
6109         h2c.b_type_dma.data4 = arg4;
6110         h2c.b_type_dma.data5 = arg5;
6111         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
6112 }
6113 #endif
6114
6115 static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv)
6116 {
6117         struct h2c_cmd h2c;
6118         u32 val32;
6119         u8 val8;
6120
6121         /*
6122          * No indication anywhere as to what 0x0790 does. The 2 antenna
6123          * vendor code preserves bits 6-7 here.
6124          */
6125         rtl8xxxu_write8(priv, 0x0790, 0x05);
6126         /*
6127          * 0x0778 seems to be related to enabling the number of antennas
6128          * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
6129          * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
6130          */
6131         rtl8xxxu_write8(priv, 0x0778, 0x01);
6132
6133         val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
6134         val8 |= BIT(5);
6135         rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
6136
6137         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780);
6138
6139         rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */
6140
6141         /*
6142          * Set BT grant to low
6143          */
6144         memset(&h2c, 0, sizeof(struct h2c_cmd));
6145         h2c.bt_grant.cmd = H2C_8723B_BT_GRANT;
6146         h2c.bt_grant.data = 0;
6147         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant));
6148
6149         /*
6150          * WLAN action by PTA
6151          */
6152         rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
6153
6154         /*
6155          * BT select S0/S1 controlled by WiFi
6156          */
6157         val8 = rtl8xxxu_read8(priv, 0x0067);
6158         val8 |= BIT(5);
6159         rtl8xxxu_write8(priv, 0x0067, val8);
6160
6161         val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
6162         val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
6163         rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
6164
6165         /*
6166          * Bits 6/7 are marked in/out ... but for what?
6167          */
6168         rtl8xxxu_write8(priv, 0x0974, 0xff);
6169
6170         val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
6171         val32 |= (BIT(0) | BIT(1));
6172         rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
6173
6174         rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
6175
6176         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
6177         val32 &= ~BIT(24);
6178         val32 |= BIT(23);
6179         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
6180
6181         /*
6182          * Fix external switch Main->S1, Aux->S0
6183          */
6184         val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
6185         val8 &= ~BIT(0);
6186         rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
6187
6188         memset(&h2c, 0, sizeof(struct h2c_cmd));
6189         h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV;
6190         h2c.ant_sel_rsv.ant_inverse = 1;
6191         h2c.ant_sel_rsv.int_switch_type = 0;
6192         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv));
6193
6194         /*
6195          * 0x280, 0x00, 0x200, 0x80 - not clear
6196          */
6197         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
6198
6199         /*
6200          * Software control, antenna at WiFi side
6201          */
6202 #ifdef NEED_PS_TDMA
6203         rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00);
6204 #endif
6205
6206         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
6207         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555);
6208         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
6209         rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
6210
6211         memset(&h2c, 0, sizeof(struct h2c_cmd));
6212         h2c.bt_info.cmd = H2C_8723B_BT_INFO;
6213         h2c.bt_info.data = BIT(0);
6214         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info));
6215
6216         memset(&h2c, 0, sizeof(struct h2c_cmd));
6217         h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT;
6218         h2c.ignore_wlan.data = 0;
6219         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan));
6220 }
6221
6222 static void rtl8723b_disable_rf(struct rtl8xxxu_priv *priv)
6223 {
6224         u32 val32;
6225
6226         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
6227
6228         val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
6229         val32 &= ~(BIT(22) | BIT(23));
6230         rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
6231 }
6232
6233 static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv)
6234 {
6235         u32 agg_rx;
6236         u8 agg_ctrl;
6237
6238         /*
6239          * For now simply disable RX aggregation
6240          */
6241         agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
6242         agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
6243
6244         agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);
6245         agg_rx &= ~RXDMA_USB_AGG_ENABLE;
6246         agg_rx &= ~0xff0f;
6247
6248         rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
6249         rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx);
6250 }
6251
6252 static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv)
6253 {
6254         u32 val32;
6255
6256         /* Time duration for NHM unit: 4us, 0x2710=40ms */
6257         rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710);
6258         rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff);
6259         rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52);
6260         rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff);
6261         /* TH8 */
6262         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
6263         val32 |= 0xff;
6264         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
6265         /* Enable CCK */
6266         val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);
6267         val32 |= BIT(8) | BIT(9) | BIT(10);
6268         rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32);
6269         /* Max power amongst all RX antennas */
6270         val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);
6271         val32 |= BIT(7);
6272         rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);
6273 }
6274
6275 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
6276 {
6277         struct rtl8xxxu_priv *priv = hw->priv;
6278         struct device *dev = &priv->udev->dev;
6279         struct rtl8xxxu_rfregval *rftable;
6280         bool macpower;
6281         int ret;
6282         u8 val8;
6283         u16 val16;
6284         u32 val32;
6285
6286         /* Check if MAC is already powered on */
6287         val8 = rtl8xxxu_read8(priv, REG_CR);
6288
6289         /*
6290          * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
6291          * initialized. First MAC returns 0xea, second MAC returns 0x00
6292          */
6293         if (val8 == 0xea)
6294                 macpower = false;
6295         else
6296                 macpower = true;
6297
6298         ret = priv->fops->power_on(priv);
6299         if (ret < 0) {
6300                 dev_warn(dev, "%s: Failed power on\n", __func__);
6301                 goto exit;
6302         }
6303
6304         dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
6305         if (!macpower) {
6306                 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
6307                 if (ret) {
6308                         dev_warn(dev, "%s: LLT table init failed\n", __func__);
6309                         goto exit;
6310                 }
6311
6312                 /*
6313                  * Presumably this is for 8188EU as well
6314                  * Enable TX report and TX report timer
6315                  */
6316                 if (priv->rtl_chip == RTL8723B) {
6317                         val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
6318                         val8 |= TX_REPORT_CTRL_TIMER_ENABLE;
6319                         rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
6320                         /* Set MAX RPT MACID */
6321                         rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
6322                         /* TX report Timer. Unit: 32us */
6323                         rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
6324
6325                         /* tmp ps ? */
6326                         val8 = rtl8xxxu_read8(priv, 0xa3);
6327                         val8 &= 0xf8;
6328                         rtl8xxxu_write8(priv, 0xa3, val8);
6329                 }
6330         }
6331
6332         ret = rtl8xxxu_download_firmware(priv);
6333         dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
6334         if (ret)
6335                 goto exit;
6336         ret = rtl8xxxu_start_firmware(priv);
6337         dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
6338         if (ret)
6339                 goto exit;
6340
6341         /* Solve too many protocol error on USB bus */
6342         /* Can't do this for 8188/8192 UMC A cut parts */
6343         if (priv->rtl_chip == RTL8723A ||
6344             ((priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C ||
6345               priv->rtl_chip == RTL8188C) &&
6346              (priv->chip_cut || !priv->vendor_umc))) {
6347                 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
6348                 rtl8xxxu_write8(priv, 0xfe41, 0x94);
6349                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6350
6351                 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6352                 rtl8xxxu_write8(priv, 0xfe41, 0x19);
6353                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6354
6355                 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
6356                 rtl8xxxu_write8(priv, 0xfe41, 0x91);
6357                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6358
6359                 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
6360                 rtl8xxxu_write8(priv, 0xfe41, 0x81);
6361                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6362         }
6363
6364         if (priv->rtl_chip == RTL8192E) {
6365                 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
6366                 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
6367         }
6368
6369         if (priv->fops->phy_init_antenna_selection)
6370                 priv->fops->phy_init_antenna_selection(priv);
6371
6372         if (priv->rtl_chip == RTL8723B)
6373                 ret = rtl8xxxu_init_mac(priv, rtl8723b_mac_init_table);
6374         else
6375                 ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
6376
6377         dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
6378         if (ret)
6379                 goto exit;
6380
6381         ret = rtl8xxxu_init_phy_bb(priv);
6382         dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
6383         if (ret)
6384                 goto exit;
6385
6386         switch(priv->rtl_chip) {
6387         case RTL8723A:
6388                 rftable = rtl8723au_radioa_1t_init_table;
6389                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6390                 break;
6391         case RTL8723B:
6392                 rftable = rtl8723bu_radioa_1t_init_table;
6393                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6394                 /*
6395                  * PHY LCK
6396                  */
6397                 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0);
6398                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01);
6399                 msleep(200);
6400                 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0);
6401                 break;
6402         case RTL8188C:
6403                 if (priv->hi_pa)
6404                         rftable = rtl8188ru_radioa_1t_highpa_table;
6405                 else
6406                         rftable = rtl8192cu_radioa_1t_init_table;
6407                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6408                 break;
6409         case RTL8191C:
6410                 rftable = rtl8192cu_radioa_1t_init_table;
6411                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6412                 break;
6413         case RTL8192C:
6414                 rftable = rtl8192cu_radioa_2t_init_table;
6415                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6416                 if (ret)
6417                         break;
6418                 rftable = rtl8192cu_radiob_2t_init_table;
6419                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
6420                 break;
6421         default:
6422                 ret = -EINVAL;
6423         }
6424
6425         if (ret)
6426                 goto exit;
6427
6428         /*
6429          * Chip specific quirks
6430          */
6431         if (priv->rtl_chip == RTL8723A) {
6432                 /* Fix USB interface interference issue */
6433                 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6434                 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
6435                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6436                 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
6437
6438                 /* Reduce 80M spur */
6439                 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
6440                 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
6441                 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
6442                 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
6443         } else {
6444                 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
6445                 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
6446                 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
6447         }
6448
6449         if (!macpower) {
6450                 if (priv->ep_tx_normal_queue)
6451                         val8 = TX_PAGE_NUM_NORM_PQ;
6452                 else
6453                         val8 = 0;
6454
6455                 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
6456
6457                 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
6458
6459                 if (priv->ep_tx_high_queue)
6460                         val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
6461                 if (priv->ep_tx_low_queue)
6462                         val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
6463
6464                 rtl8xxxu_write32(priv, REG_RQPN, val32);
6465
6466                 /*
6467                  * Set TX buffer boundary
6468                  */
6469                 val8 = TX_TOTAL_PAGE_NUM + 1;
6470
6471                 if (priv->rtl_chip == RTL8723B)
6472                         val8 -= 1;
6473
6474                 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
6475                 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
6476                 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
6477                 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
6478                 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
6479         }
6480
6481         ret = rtl8xxxu_init_queue_priority(priv);
6482         dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
6483         if (ret)
6484                 goto exit;
6485
6486         /* RFSW Control - clear bit 14 ?? */
6487         if (priv->rtl_chip != RTL8723B)
6488                 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
6489         /* 0x07000760 */
6490         val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
6491                 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
6492                 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
6493                  FPGA0_RF_BD_CTRL_SHIFT);
6494         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
6495         /* 0x860[6:5]= 00 - why? - this sets antenna B */
6496         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
6497
6498         priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
6499                                                   RF6052_REG_MODE_AG);
6500
6501         /*
6502          * Set RX page boundary
6503          */
6504         if (priv->rtl_chip == RTL8723B)
6505                 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x3f7f);
6506         else
6507                 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
6508         /*
6509          * Transfer page size is always 128
6510          */
6511         if (priv->rtl_chip == RTL8723B)
6512                 val8 = (PBP_PAGE_SIZE_256 << PBP_PAGE_SIZE_RX_SHIFT) |
6513                         (PBP_PAGE_SIZE_256 << PBP_PAGE_SIZE_TX_SHIFT);
6514         else
6515                 val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
6516                         (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
6517         rtl8xxxu_write8(priv, REG_PBP, val8);
6518
6519         /*
6520          * Unit in 8 bytes, not obvious what it is used for
6521          */
6522         rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
6523
6524         /*
6525          * Enable all interrupts - not obvious USB needs to do this
6526          */
6527         rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
6528         rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
6529
6530         rtl8xxxu_set_mac(priv);
6531         rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
6532
6533         /*
6534          * Configure initial WMAC settings
6535          */
6536         val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
6537                 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
6538                 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
6539         rtl8xxxu_write32(priv, REG_RCR, val32);
6540
6541         /*
6542          * Accept all multicast
6543          */
6544         rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
6545         rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
6546
6547         /*
6548          * Init adaptive controls
6549          */
6550         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6551         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
6552         val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
6553         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6554
6555         /* CCK = 0x0a, OFDM = 0x10 */
6556         rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
6557         rtl8xxxu_set_retry(priv, 0x30, 0x30);
6558         rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
6559
6560         /*
6561          * Init EDCA
6562          */
6563         rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
6564
6565         /* Set CCK SIFS */
6566         rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
6567
6568         /* Set OFDM SIFS */
6569         rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
6570
6571         /* TXOP */
6572         rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
6573         rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
6574         rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
6575         rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
6576
6577         /* Set data auto rate fallback retry count */
6578         rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
6579         rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
6580         rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
6581         rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
6582
6583         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
6584         val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
6585         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
6586
6587         /*  Set ACK timeout */
6588         rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
6589
6590         /*
6591          * Initialize beacon parameters
6592          */
6593         val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
6594         rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
6595         rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
6596         rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
6597         rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
6598         rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
6599
6600         /*
6601          * Initialize burst parameters
6602          */
6603         if (priv->rtl_chip == RTL8723B) {
6604                 /*
6605                  * For USB high speed set 512B packets
6606                  */
6607                 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
6608                 val8 &= ~(BIT(4) | BIT(5));
6609                 val8 |= BIT(4);
6610                 val8 |= BIT(1) | BIT(2) | BIT(3);
6611                 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
6612
6613                 /*
6614                  * For USB high speed set 512B packets
6615                  */
6616                 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
6617                 val8 |= BIT(7);
6618                 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
6619
6620                 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
6621                 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e);
6622                 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
6623                 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
6624                 rtl8xxxu_write8(priv, REG_PIFS, 0x00);
6625                 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50);
6626                 rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50);
6627
6628                 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
6629                 val8 |= BIT(5) | BIT(6);
6630                 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
6631         }
6632
6633         if (priv->fops->init_aggregation)
6634                 priv->fops->init_aggregation(priv);
6635
6636         /*
6637          * Enable CCK and OFDM block
6638          */
6639         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6640         val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
6641         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6642
6643         /*
6644          * Invalidate all CAM entries - bit 30 is undocumented
6645          */
6646         rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
6647
6648         /*
6649          * Start out with default power levels for channel 6, 20MHz
6650          */
6651         priv->fops->set_tx_power(priv, 1, false);
6652
6653         /* Let the 8051 take control of antenna setting */
6654         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
6655         val8 |= LEDCFG2_DPDT_SELECT;
6656         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
6657
6658         rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
6659
6660         /* Disable BAR - not sure if this has any effect on USB */
6661         rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
6662
6663         rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
6664
6665         if (priv->fops->init_statistics)
6666                 priv->fops->init_statistics(priv);
6667
6668         rtl8723a_phy_lc_calibrate(priv);
6669
6670         priv->fops->phy_iq_calibrate(priv);
6671
6672         /*
6673          * This should enable thermal meter
6674          */
6675         if (priv->fops->has_s0s1)
6676                 rtl8xxxu_write_rfreg(priv,
6677                                      RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);
6678         else
6679                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
6680
6681         /* Set NAV_UPPER to 30000us */
6682         val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
6683         rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
6684
6685         if (priv->rtl_chip == RTL8723A) {
6686                 /*
6687                  * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
6688                  * but we need to find root cause.
6689                  * This is 8723au only.
6690                  */
6691                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6692                 if ((val32 & 0xff000000) != 0x83000000) {
6693                         val32 |= FPGA_RF_MODE_CCK;
6694                         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6695                 }
6696         }
6697
6698         val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
6699         val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
6700         /* ack for xmit mgmt frames. */
6701         rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
6702
6703 exit:
6704         return ret;
6705 }
6706
6707 static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
6708 {
6709         struct rtl8xxxu_priv *priv = hw->priv;
6710
6711         priv->fops->power_off(priv);
6712 }
6713
6714 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
6715                                struct ieee80211_key_conf *key, const u8 *mac)
6716 {
6717         u32 cmd, val32, addr, ctrl;
6718         int j, i, tmp_debug;
6719
6720         tmp_debug = rtl8xxxu_debug;
6721         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
6722                 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
6723
6724         /*
6725          * This is a bit of a hack - the lower bits of the cipher
6726          * suite selector happens to match the cipher index in the CAM
6727          */
6728         addr = key->keyidx << CAM_CMD_KEY_SHIFT;
6729         ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
6730
6731         for (j = 5; j >= 0; j--) {
6732                 switch (j) {
6733                 case 0:
6734                         val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
6735                         break;
6736                 case 1:
6737                         val32 = mac[2] | (mac[3] << 8) |
6738                                 (mac[4] << 16) | (mac[5] << 24);
6739                         break;
6740                 default:
6741                         i = (j - 2) << 2;
6742                         val32 = key->key[i] | (key->key[i + 1] << 8) |
6743                                 key->key[i + 2] << 16 | key->key[i + 3] << 24;
6744                         break;
6745                 }
6746
6747                 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
6748                 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
6749                 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
6750                 udelay(100);
6751         }
6752
6753         rtl8xxxu_debug = tmp_debug;
6754 }
6755
6756 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
6757                                    struct ieee80211_vif *vif, const u8 *mac)
6758 {
6759         struct rtl8xxxu_priv *priv = hw->priv;
6760         u8 val8;
6761
6762         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6763         val8 |= BEACON_DISABLE_TSF_UPDATE;
6764         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6765 }
6766
6767 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
6768                                       struct ieee80211_vif *vif)
6769 {
6770         struct rtl8xxxu_priv *priv = hw->priv;
6771         u8 val8;
6772
6773         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6774         val8 &= ~BEACON_DISABLE_TSF_UPDATE;
6775         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6776 }
6777
6778 static void rtl8723au_update_rate_mask(struct rtl8xxxu_priv *priv,
6779                                        u32 ramask, int sgi)
6780 {
6781         struct h2c_cmd h2c;
6782
6783         memset(&h2c, 0, sizeof(struct h2c_cmd));
6784
6785         h2c.ramask.cmd = H2C_SET_RATE_MASK;
6786         h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
6787         h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
6788
6789         h2c.ramask.arg = 0x80;
6790         if (sgi)
6791                 h2c.ramask.arg |= 0x20;
6792
6793         dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
6794                 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
6795         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
6796 }
6797
6798 static void rtl8723bu_update_rate_mask(struct rtl8xxxu_priv *priv,
6799                                        u32 ramask, int sgi)
6800 {
6801         struct h2c_cmd h2c;
6802         u8 bw = 0;
6803
6804         memset(&h2c, 0, sizeof(struct h2c_cmd));
6805
6806         h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID;
6807         h2c.b_macid_cfg.ramask0 = ramask & 0xff;
6808         h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff;
6809         h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff;
6810         h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff;
6811
6812         h2c.ramask.arg = 0x80;
6813         h2c.b_macid_cfg.data1 = 0;
6814         if (sgi)
6815                 h2c.b_macid_cfg.data1 |= BIT(7);
6816
6817         h2c.b_macid_cfg.data2 = bw;
6818
6819         dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
6820                 __func__, ramask, h2c.ramask.arg, sizeof(h2c.b_macid_cfg));
6821         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg));
6822 }
6823
6824 static void rtl8723au_report_connect(struct rtl8xxxu_priv *priv,
6825                                      u8 macid, bool connect)
6826 {
6827         struct h2c_cmd h2c;
6828
6829         memset(&h2c, 0, sizeof(struct h2c_cmd));
6830
6831         h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
6832
6833         if (connect)
6834                 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
6835         else
6836                 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
6837
6838         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
6839 }
6840
6841 static void rtl8723bu_report_connect(struct rtl8xxxu_priv *priv,
6842                                      u8 macid, bool connect)
6843 {
6844         struct h2c_cmd h2c;
6845
6846         memset(&h2c, 0, sizeof(struct h2c_cmd));
6847
6848         h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT;
6849         if (connect)
6850                 h2c.media_status_rpt.parm |= BIT(0);
6851         else
6852                 h2c.media_status_rpt.parm &= ~BIT(0);
6853
6854         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt));
6855 }
6856
6857 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
6858 {
6859         u32 val32;
6860         u8 rate_idx = 0;
6861
6862         rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
6863
6864         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6865         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
6866         val32 |= rate_cfg;
6867         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6868
6869         dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
6870
6871         while (rate_cfg) {
6872                 rate_cfg = (rate_cfg >> 1);
6873                 rate_idx++;
6874         }
6875         rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
6876 }
6877
6878 static void
6879 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6880                           struct ieee80211_bss_conf *bss_conf, u32 changed)
6881 {
6882         struct rtl8xxxu_priv *priv = hw->priv;
6883         struct device *dev = &priv->udev->dev;
6884         struct ieee80211_sta *sta;
6885         u32 val32;
6886         u8 val8;
6887
6888         if (changed & BSS_CHANGED_ASSOC) {
6889                 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
6890
6891                 rtl8xxxu_set_linktype(priv, vif->type);
6892
6893                 if (bss_conf->assoc) {
6894                         u32 ramask;
6895                         int sgi = 0;
6896
6897                         rcu_read_lock();
6898                         sta = ieee80211_find_sta(vif, bss_conf->bssid);
6899                         if (!sta) {
6900                                 dev_info(dev, "%s: ASSOC no sta found\n",
6901                                          __func__);
6902                                 rcu_read_unlock();
6903                                 goto error;
6904                         }
6905
6906                         if (sta->ht_cap.ht_supported)
6907                                 dev_info(dev, "%s: HT supported\n", __func__);
6908                         if (sta->vht_cap.vht_supported)
6909                                 dev_info(dev, "%s: VHT supported\n", __func__);
6910
6911                         /* TODO: Set bits 28-31 for rate adaptive id */
6912                         ramask = (sta->supp_rates[0] & 0xfff) |
6913                                 sta->ht_cap.mcs.rx_mask[0] << 12 |
6914                                 sta->ht_cap.mcs.rx_mask[1] << 20;
6915                         if (sta->ht_cap.cap &
6916                             (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
6917                                 sgi = 1;
6918                         rcu_read_unlock();
6919
6920                         priv->fops->update_rate_mask(priv, ramask, sgi);
6921
6922                         rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
6923
6924                         rtl8723a_stop_tx_beacon(priv);
6925
6926                         /* joinbss sequence */
6927                         rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
6928                                          0xc000 | bss_conf->aid);
6929
6930                         priv->fops->report_connect(priv, 0, true);
6931                 } else {
6932                         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6933                         val8 |= BEACON_DISABLE_TSF_UPDATE;
6934                         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6935
6936                         priv->fops->report_connect(priv, 0, false);
6937                 }
6938         }
6939
6940         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
6941                 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
6942                         bss_conf->use_short_preamble);
6943                 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6944                 if (bss_conf->use_short_preamble)
6945                         val32 |= RSR_ACK_SHORT_PREAMBLE;
6946                 else
6947                         val32 &= ~RSR_ACK_SHORT_PREAMBLE;
6948                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6949         }
6950
6951         if (changed & BSS_CHANGED_ERP_SLOT) {
6952                 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
6953                         bss_conf->use_short_slot);
6954
6955                 if (bss_conf->use_short_slot)
6956                         val8 = 9;
6957                 else
6958                         val8 = 20;
6959                 rtl8xxxu_write8(priv, REG_SLOT, val8);
6960         }
6961
6962         if (changed & BSS_CHANGED_BSSID) {
6963                 dev_dbg(dev, "Changed BSSID!\n");
6964                 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
6965         }
6966
6967         if (changed & BSS_CHANGED_BASIC_RATES) {
6968                 dev_dbg(dev, "Changed BASIC_RATES!\n");
6969                 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
6970         }
6971 error:
6972         return;
6973 }
6974
6975 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
6976 {
6977         u32 rtlqueue;
6978
6979         switch (queue) {
6980         case IEEE80211_AC_VO:
6981                 rtlqueue = TXDESC_QUEUE_VO;
6982                 break;
6983         case IEEE80211_AC_VI:
6984                 rtlqueue = TXDESC_QUEUE_VI;
6985                 break;
6986         case IEEE80211_AC_BE:
6987                 rtlqueue = TXDESC_QUEUE_BE;
6988                 break;
6989         case IEEE80211_AC_BK:
6990                 rtlqueue = TXDESC_QUEUE_BK;
6991                 break;
6992         default:
6993                 rtlqueue = TXDESC_QUEUE_BE;
6994         }
6995
6996         return rtlqueue;
6997 }
6998
6999 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
7000 {
7001         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
7002         u32 queue;
7003
7004         if (ieee80211_is_mgmt(hdr->frame_control))
7005                 queue = TXDESC_QUEUE_MGNT;
7006         else
7007                 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
7008
7009         return queue;
7010 }
7011
7012 /*
7013  * Despite newer chips 8723b/8812/8821 having a larger TX descriptor
7014  * format. The descriptor checksum is still only calculated over the
7015  * initial 32 bytes of the descriptor!
7016  */
7017 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc)
7018 {
7019         __le16 *ptr = (__le16 *)tx_desc;
7020         u16 csum = 0;
7021         int i;
7022
7023         /*
7024          * Clear csum field before calculation, as the csum field is
7025          * in the middle of the struct.
7026          */
7027         tx_desc->csum = cpu_to_le16(0);
7028
7029         for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++)
7030                 csum = csum ^ le16_to_cpu(ptr[i]);
7031
7032         tx_desc->csum |= cpu_to_le16(csum);
7033 }
7034
7035 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
7036 {
7037         struct rtl8xxxu_tx_urb *tx_urb, *tmp;
7038         unsigned long flags;
7039
7040         spin_lock_irqsave(&priv->tx_urb_lock, flags);
7041         list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
7042                 list_del(&tx_urb->list);
7043                 priv->tx_urb_free_count--;
7044                 usb_free_urb(&tx_urb->urb);
7045         }
7046         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
7047 }
7048
7049 static struct rtl8xxxu_tx_urb *
7050 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
7051 {
7052         struct rtl8xxxu_tx_urb *tx_urb;
7053         unsigned long flags;
7054
7055         spin_lock_irqsave(&priv->tx_urb_lock, flags);
7056         tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
7057                                           struct rtl8xxxu_tx_urb, list);
7058         if (tx_urb) {
7059                 list_del(&tx_urb->list);
7060                 priv->tx_urb_free_count--;
7061                 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
7062                     !priv->tx_stopped) {
7063                         priv->tx_stopped = true;
7064                         ieee80211_stop_queues(priv->hw);
7065                 }
7066         }
7067
7068         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
7069
7070         return tx_urb;
7071 }
7072
7073 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
7074                                  struct rtl8xxxu_tx_urb *tx_urb)
7075 {
7076         unsigned long flags;
7077
7078         INIT_LIST_HEAD(&tx_urb->list);
7079
7080         spin_lock_irqsave(&priv->tx_urb_lock, flags);
7081
7082         list_add(&tx_urb->list, &priv->tx_urb_free_list);
7083         priv->tx_urb_free_count++;
7084         if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
7085             priv->tx_stopped) {
7086                 priv->tx_stopped = false;
7087                 ieee80211_wake_queues(priv->hw);
7088         }
7089
7090         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
7091 }
7092
7093 static void rtl8xxxu_tx_complete(struct urb *urb)
7094 {
7095         struct sk_buff *skb = (struct sk_buff *)urb->context;
7096         struct ieee80211_tx_info *tx_info;
7097         struct ieee80211_hw *hw;
7098         struct rtl8xxxu_priv *priv;
7099         struct rtl8xxxu_tx_urb *tx_urb =
7100                 container_of(urb, struct rtl8xxxu_tx_urb, urb);
7101
7102         tx_info = IEEE80211_SKB_CB(skb);
7103         hw = tx_info->rate_driver_data[0];
7104         priv = hw->priv;
7105
7106         skb_pull(skb, priv->fops->tx_desc_size);
7107
7108         ieee80211_tx_info_clear_status(tx_info);
7109         tx_info->status.rates[0].idx = -1;
7110         tx_info->status.rates[0].count = 0;
7111
7112         if (!urb->status)
7113                 tx_info->flags |= IEEE80211_TX_STAT_ACK;
7114
7115         ieee80211_tx_status_irqsafe(hw, skb);
7116
7117         rtl8xxxu_free_tx_urb(priv, tx_urb);
7118 }
7119
7120 static void rtl8xxxu_dump_action(struct device *dev,
7121                                  struct ieee80211_hdr *hdr)
7122 {
7123         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
7124         u16 cap, timeout;
7125
7126         if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
7127                 return;
7128
7129         switch (mgmt->u.action.u.addba_resp.action_code) {
7130         case WLAN_ACTION_ADDBA_RESP:
7131                 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
7132                 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
7133                 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
7134                          "timeout %i, tid %02x, buf_size %02x, policy %02x, "
7135                          "status %02x\n",
7136                          timeout,
7137                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
7138                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
7139                          (cap >> 1) & 0x1,
7140                          le16_to_cpu(mgmt->u.action.u.addba_resp.status));
7141                 break;
7142         case WLAN_ACTION_ADDBA_REQ:
7143                 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
7144                 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
7145                 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
7146                          "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
7147                          timeout,
7148                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
7149                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
7150                          (cap >> 1) & 0x1);
7151                 break;
7152         default:
7153                 dev_info(dev, "action frame %02x\n",
7154                          mgmt->u.action.u.addba_resp.action_code);
7155                 break;
7156         }
7157 }
7158
7159 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
7160                         struct ieee80211_tx_control *control,
7161                         struct sk_buff *skb)
7162 {
7163         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
7164         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
7165         struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
7166         struct rtl8xxxu_priv *priv = hw->priv;
7167         struct rtl8xxxu_txdesc32 *tx_desc;
7168         struct rtl8xxxu_txdesc40 *tx_desc40;
7169         struct rtl8xxxu_tx_urb *tx_urb;
7170         struct ieee80211_sta *sta = NULL;
7171         struct ieee80211_vif *vif = tx_info->control.vif;
7172         struct device *dev = &priv->udev->dev;
7173         u32 queue, rate;
7174         u16 pktlen = skb->len;
7175         u16 seq_number;
7176         u16 rate_flag = tx_info->control.rates[0].flags;
7177         int tx_desc_size = priv->fops->tx_desc_size;
7178         int ret;
7179         bool usedesc40, ampdu_enable;
7180
7181         if (skb_headroom(skb) < tx_desc_size) {
7182                 dev_warn(dev,
7183                          "%s: Not enough headroom (%i) for tx descriptor\n",
7184                          __func__, skb_headroom(skb));
7185                 goto error;
7186         }
7187
7188         if (unlikely(skb->len > (65535 - tx_desc_size))) {
7189                 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
7190                          __func__, skb->len);
7191                 goto error;
7192         }
7193
7194         tx_urb = rtl8xxxu_alloc_tx_urb(priv);
7195         if (!tx_urb) {
7196                 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
7197                 goto error;
7198         }
7199
7200         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
7201                 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
7202                          __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
7203
7204         if (ieee80211_is_action(hdr->frame_control))
7205                 rtl8xxxu_dump_action(dev, hdr);
7206
7207         usedesc40 = (tx_desc_size == 40);
7208         tx_info->rate_driver_data[0] = hw;
7209
7210         if (control && control->sta)
7211                 sta = control->sta;
7212
7213         tx_desc = (struct rtl8xxxu_txdesc32 *)skb_push(skb, tx_desc_size);
7214
7215         memset(tx_desc, 0, tx_desc_size);
7216         tx_desc->pkt_size = cpu_to_le16(pktlen);
7217         tx_desc->pkt_offset = tx_desc_size;
7218
7219         tx_desc->txdw0 =
7220                 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
7221         if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
7222             is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
7223                 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
7224
7225         queue = rtl8xxxu_queue_select(hw, skb);
7226         tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
7227
7228         if (tx_info->control.hw_key) {
7229                 switch (tx_info->control.hw_key->cipher) {
7230                 case WLAN_CIPHER_SUITE_WEP40:
7231                 case WLAN_CIPHER_SUITE_WEP104:
7232                 case WLAN_CIPHER_SUITE_TKIP:
7233                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
7234                         break;
7235                 case WLAN_CIPHER_SUITE_CCMP:
7236                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
7237                         break;
7238                 default:
7239                         break;
7240                 }
7241         }
7242
7243         /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
7244         ampdu_enable = false;
7245         if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
7246                 if (sta->ht_cap.ht_supported) {
7247                         u32 ampdu, val32;
7248
7249                         ampdu = (u32)sta->ht_cap.ampdu_density;
7250                         val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
7251                         tx_desc->txdw2 |= cpu_to_le32(val32);
7252
7253                         ampdu_enable = true;
7254                 }
7255         }
7256
7257         if (rate_flag & IEEE80211_TX_RC_MCS)
7258                 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
7259         else
7260                 rate = tx_rate->hw_value;
7261
7262         seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
7263         if (!usedesc40) {
7264                 tx_desc->txdw5 = cpu_to_le32(rate);
7265
7266                 if (ieee80211_is_data(hdr->frame_control))
7267                         tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
7268
7269                 tx_desc->txdw3 =
7270                         cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
7271
7272                 if (ampdu_enable)
7273                         tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE);
7274                 else
7275                         tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK);
7276
7277                 if (ieee80211_is_mgmt(hdr->frame_control)) {
7278                         tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
7279                         tx_desc->txdw4 |=
7280                                 cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
7281                         tx_desc->txdw5 |=
7282                                 cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
7283                         tx_desc->txdw5 |=
7284                                 cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
7285                 }
7286
7287                 if (ieee80211_is_data_qos(hdr->frame_control))
7288                         tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
7289
7290                 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
7291                     (sta && vif && vif->bss_conf.use_short_preamble))
7292                         tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
7293
7294                 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
7295                     (ieee80211_is_data_qos(hdr->frame_control) &&
7296                      sta && sta->ht_cap.cap &
7297                      (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
7298                         tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
7299                 }
7300
7301                 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
7302                         /*
7303                          * Use RTS rate 24M - does the mac80211 tell
7304                          * us which to use?
7305                          */
7306                         tx_desc->txdw4 |=
7307                                 cpu_to_le32(DESC_RATE_24M <<
7308                                             TXDESC32_RTS_RATE_SHIFT);
7309                         tx_desc->txdw4 |=
7310                                 cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
7311                         tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
7312                 }
7313         } else {
7314                 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc;
7315
7316                 tx_desc40->txdw4 = cpu_to_le32(rate);
7317                 if (ieee80211_is_data(hdr->frame_control)) {
7318                         tx_desc->txdw4 |=
7319                                 cpu_to_le32(0x1f <<
7320                                             TXDESC40_DATA_RATE_FB_SHIFT);
7321                 }
7322
7323                 tx_desc40->txdw9 =
7324                         cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT);
7325
7326                 if (ampdu_enable)
7327                         tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);
7328                 else
7329                         tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);
7330
7331                 if (ieee80211_is_mgmt(hdr->frame_control)) {
7332                         tx_desc40->txdw4 = cpu_to_le32(tx_rate->hw_value);
7333                         tx_desc40->txdw3 |=
7334                                 cpu_to_le32(TXDESC40_USE_DRIVER_RATE);
7335                         tx_desc40->txdw4 |=
7336                                 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT);
7337                         tx_desc40->txdw4 |=
7338                                 cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE);
7339                 }
7340
7341                 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
7342                     (sta && vif && vif->bss_conf.use_short_preamble))
7343                         tx_desc40->txdw5 |=
7344                                 cpu_to_le32(TXDESC40_SHORT_PREAMBLE);
7345
7346                 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
7347                         /*
7348                          * Use RTS rate 24M - does the mac80211 tell
7349                          * us which to use?
7350                          */
7351                         tx_desc->txdw4 |=
7352                                 cpu_to_le32(DESC_RATE_24M <<
7353                                             TXDESC40_RTS_RATE_SHIFT);
7354                         tx_desc->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE);
7355                         tx_desc->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE);
7356                 }
7357         }
7358
7359         rtl8xxxu_calc_tx_desc_csum(tx_desc);
7360
7361         usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
7362                           skb->data, skb->len, rtl8xxxu_tx_complete, skb);
7363
7364         usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
7365         ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
7366         if (ret) {
7367                 usb_unanchor_urb(&tx_urb->urb);
7368                 rtl8xxxu_free_tx_urb(priv, tx_urb);
7369                 goto error;
7370         }
7371         return;
7372 error:
7373         dev_kfree_skb(skb);
7374 }
7375
7376 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
7377                                        struct ieee80211_rx_status *rx_status,
7378                                        struct rtl8723au_phy_stats *phy_stats,
7379                                        u32 rxmcs)
7380 {
7381         if (phy_stats->sgi_en)
7382                 rx_status->flag |= RX_FLAG_SHORT_GI;
7383
7384         if (rxmcs < DESC_RATE_6M) {
7385                 /*
7386                  * Handle PHY stats for CCK rates
7387                  */
7388                 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
7389
7390                 switch (cck_agc_rpt & 0xc0) {
7391                 case 0xc0:
7392                         rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
7393                         break;
7394                 case 0x80:
7395                         rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
7396                         break;
7397                 case 0x40:
7398                         rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
7399                         break;
7400                 case 0x00:
7401                         rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
7402                         break;
7403                 }
7404         } else {
7405                 rx_status->signal =
7406                         (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
7407         }
7408 }
7409
7410 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
7411 {
7412         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
7413         unsigned long flags;
7414
7415         spin_lock_irqsave(&priv->rx_urb_lock, flags);
7416
7417         list_for_each_entry_safe(rx_urb, tmp,
7418                                  &priv->rx_urb_pending_list, list) {
7419                 list_del(&rx_urb->list);
7420                 priv->rx_urb_pending_count--;
7421                 usb_free_urb(&rx_urb->urb);
7422         }
7423
7424         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7425 }
7426
7427 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
7428                                   struct rtl8xxxu_rx_urb *rx_urb)
7429 {
7430         struct sk_buff *skb;
7431         unsigned long flags;
7432         int pending = 0;
7433
7434         spin_lock_irqsave(&priv->rx_urb_lock, flags);
7435
7436         if (!priv->shutdown) {
7437                 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
7438                 priv->rx_urb_pending_count++;
7439                 pending = priv->rx_urb_pending_count;
7440         } else {
7441                 skb = (struct sk_buff *)rx_urb->urb.context;
7442                 dev_kfree_skb(skb);
7443                 usb_free_urb(&rx_urb->urb);
7444         }
7445
7446         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7447
7448         if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
7449                 schedule_work(&priv->rx_urb_wq);
7450 }
7451
7452 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
7453 {
7454         struct rtl8xxxu_priv *priv;
7455         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
7456         struct list_head local;
7457         struct sk_buff *skb;
7458         unsigned long flags;
7459         int ret;
7460
7461         priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
7462         INIT_LIST_HEAD(&local);
7463
7464         spin_lock_irqsave(&priv->rx_urb_lock, flags);
7465
7466         list_splice_init(&priv->rx_urb_pending_list, &local);
7467         priv->rx_urb_pending_count = 0;
7468
7469         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7470
7471         list_for_each_entry_safe(rx_urb, tmp, &local, list) {
7472                 list_del_init(&rx_urb->list);
7473                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7474                 /*
7475                  * If out of memory or temporary error, put it back on the
7476                  * queue and try again. Otherwise the device is dead/gone
7477                  * and we should drop it.
7478                  */
7479                 switch (ret) {
7480                 case 0:
7481                         break;
7482                 case -ENOMEM:
7483                 case -EAGAIN:
7484                         rtl8xxxu_queue_rx_urb(priv, rx_urb);
7485                         break;
7486                 default:
7487                         pr_info("failed to requeue urb %i\n", ret);
7488                         skb = (struct sk_buff *)rx_urb->urb.context;
7489                         dev_kfree_skb(skb);
7490                         usb_free_urb(&rx_urb->urb);
7491                 }
7492         }
7493 }
7494
7495 static int rtl8723au_parse_rx_desc(struct rtl8xxxu_priv *priv,
7496                                    struct sk_buff *skb,
7497                                    struct ieee80211_rx_status *rx_status)
7498 {
7499         struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
7500         struct rtl8723au_phy_stats *phy_stats;
7501         int drvinfo_sz, desc_shift;
7502
7503         skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
7504
7505         phy_stats = (struct rtl8723au_phy_stats *)skb->data;
7506
7507         drvinfo_sz = rx_desc->drvinfo_sz * 8;
7508         desc_shift = rx_desc->shift;
7509         skb_pull(skb, drvinfo_sz + desc_shift);
7510
7511         if (rx_desc->phy_stats)
7512                 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
7513                                            rx_desc->rxmcs);
7514
7515         rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
7516         rx_status->flag |= RX_FLAG_MACTIME_START;
7517
7518         if (!rx_desc->swdec)
7519                 rx_status->flag |= RX_FLAG_DECRYPTED;
7520         if (rx_desc->crc32)
7521                 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7522         if (rx_desc->bw)
7523                 rx_status->flag |= RX_FLAG_40MHZ;
7524
7525         if (rx_desc->rxht) {
7526                 rx_status->flag |= RX_FLAG_HT;
7527                 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
7528         } else {
7529                 rx_status->rate_idx = rx_desc->rxmcs;
7530         }
7531
7532         return RX_TYPE_DATA_PKT;
7533 }
7534
7535 static int rtl8723bu_parse_rx_desc(struct rtl8xxxu_priv *priv,
7536                                    struct sk_buff *skb,
7537                                    struct ieee80211_rx_status *rx_status)
7538 {
7539         struct rtl8723bu_rx_desc *rx_desc =
7540                 (struct rtl8723bu_rx_desc *)skb->data;
7541         struct rtl8723au_phy_stats *phy_stats;
7542         int drvinfo_sz, desc_shift;
7543
7544         skb_pull(skb, sizeof(struct rtl8723bu_rx_desc));
7545
7546         phy_stats = (struct rtl8723au_phy_stats *)skb->data;
7547
7548         drvinfo_sz = rx_desc->drvinfo_sz * 8;
7549         desc_shift = rx_desc->shift;
7550         skb_pull(skb, drvinfo_sz + desc_shift);
7551
7552         if (rx_desc->rpt_sel) {
7553                 struct device *dev = &priv->udev->dev;
7554                 dev_dbg(dev, "%s: C2H packet\n", __func__);
7555                 return RX_TYPE_C2H;
7556         }
7557
7558         if (rx_desc->phy_stats)
7559                 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
7560                                            rx_desc->rxmcs);
7561
7562         rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
7563         rx_status->flag |= RX_FLAG_MACTIME_START;
7564
7565         if (!rx_desc->swdec)
7566                 rx_status->flag |= RX_FLAG_DECRYPTED;
7567         if (rx_desc->crc32)
7568                 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7569         if (rx_desc->bw)
7570                 rx_status->flag |= RX_FLAG_40MHZ;
7571
7572         if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
7573                 rx_status->flag |= RX_FLAG_HT;
7574                 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
7575         } else {
7576                 rx_status->rate_idx = rx_desc->rxmcs;
7577         }
7578
7579         return RX_TYPE_DATA_PKT;
7580 }
7581
7582 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
7583                                  struct sk_buff *skb)
7584 {
7585         struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
7586         struct device *dev = &priv->udev->dev;
7587         int len;
7588
7589         len = skb->len - 2;
7590
7591         dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
7592                 c2h->id, c2h->seq, len, c2h->bt_info.response_source);
7593
7594         switch(c2h->id) {
7595         case C2H_8723B_BT_INFO:
7596                 if (c2h->bt_info.response_source >
7597                     BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
7598                         dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n");
7599                 else
7600                         dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
7601
7602                 if (c2h->bt_info.bt_has_reset)
7603                         dev_dbg(dev, "BT has been reset\n");
7604                 if (c2h->bt_info.tx_rx_mask)
7605                         dev_dbg(dev, "BT TRx mask\n");
7606
7607                 break;
7608         case C2H_8723B_BT_MP_INFO:
7609                 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
7610                         c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
7611                 break;
7612         case C2H_8723B_RA_REPORT:
7613                 dev_dbg(dev,
7614                         "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n",
7615                         c2h->ra_report.rate, c2h->ra_report.dummy0_0,
7616                         c2h->ra_report.macid, c2h->ra_report.noisy_state);
7617                 break;
7618         default:
7619                 dev_info(dev, "Unhandled C2H event %02x seq %02x\n",
7620                          c2h->id, c2h->seq);
7621                 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE,
7622                                16, 1, c2h->raw.payload, len, false);
7623                 break;
7624         }
7625 }
7626
7627 static void rtl8xxxu_rx_complete(struct urb *urb)
7628 {
7629         struct rtl8xxxu_rx_urb *rx_urb =
7630                 container_of(urb, struct rtl8xxxu_rx_urb, urb);
7631         struct ieee80211_hw *hw = rx_urb->hw;
7632         struct rtl8xxxu_priv *priv = hw->priv;
7633         struct sk_buff *skb = (struct sk_buff *)urb->context;
7634         struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
7635         struct device *dev = &priv->udev->dev;
7636         __le32 *_rx_desc_le = (__le32 *)skb->data;
7637         u32 *_rx_desc = (u32 *)skb->data;
7638         int rx_type, i;
7639
7640         for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
7641                 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
7642
7643         skb_put(skb, urb->actual_length);
7644
7645         if (urb->status == 0) {
7646                 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
7647
7648                 rx_type = priv->fops->parse_rx_desc(priv, skb, rx_status);
7649
7650                 rx_status->freq = hw->conf.chandef.chan->center_freq;
7651                 rx_status->band = hw->conf.chandef.chan->band;
7652
7653                 if (rx_type == RX_TYPE_DATA_PKT)
7654                         ieee80211_rx_irqsafe(hw, skb);
7655                 else {
7656                         rtl8723bu_handle_c2h(priv, skb);
7657                         dev_kfree_skb(skb);
7658                 }
7659
7660                 skb = NULL;
7661                 rx_urb->urb.context = NULL;
7662                 rtl8xxxu_queue_rx_urb(priv, rx_urb);
7663         } else {
7664                 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
7665                 goto cleanup;
7666         }
7667         return;
7668
7669 cleanup:
7670         usb_free_urb(urb);
7671         dev_kfree_skb(skb);
7672         return;
7673 }
7674
7675 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
7676                                   struct rtl8xxxu_rx_urb *rx_urb)
7677 {
7678         struct sk_buff *skb;
7679         int skb_size;
7680         int ret;
7681
7682         skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
7683         skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
7684         if (!skb)
7685                 return -ENOMEM;
7686
7687         memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
7688         usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
7689                           skb_size, rtl8xxxu_rx_complete, skb);
7690         usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
7691         ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
7692         if (ret)
7693                 usb_unanchor_urb(&rx_urb->urb);
7694         return ret;
7695 }
7696
7697 static void rtl8xxxu_int_complete(struct urb *urb)
7698 {
7699         struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
7700         struct device *dev = &priv->udev->dev;
7701         int ret;
7702
7703         dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
7704         if (urb->status == 0) {
7705                 usb_anchor_urb(urb, &priv->int_anchor);
7706                 ret = usb_submit_urb(urb, GFP_ATOMIC);
7707                 if (ret)
7708                         usb_unanchor_urb(urb);
7709         } else {
7710                 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
7711         }
7712 }
7713
7714
7715 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
7716 {
7717         struct rtl8xxxu_priv *priv = hw->priv;
7718         struct urb *urb;
7719         u32 val32;
7720         int ret;
7721
7722         urb = usb_alloc_urb(0, GFP_KERNEL);
7723         if (!urb)
7724                 return -ENOMEM;
7725
7726         usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
7727                          priv->int_buf, USB_INTR_CONTENT_LENGTH,
7728                          rtl8xxxu_int_complete, priv, 1);
7729         usb_anchor_urb(urb, &priv->int_anchor);
7730         ret = usb_submit_urb(urb, GFP_KERNEL);
7731         if (ret) {
7732                 usb_unanchor_urb(urb);
7733                 goto error;
7734         }
7735
7736         val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
7737         val32 |= USB_HIMR_CPWM;
7738         rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
7739
7740 error:
7741         return ret;
7742 }
7743
7744 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
7745                                   struct ieee80211_vif *vif)
7746 {
7747         struct rtl8xxxu_priv *priv = hw->priv;
7748         int ret;
7749         u8 val8;
7750
7751         switch (vif->type) {
7752         case NL80211_IFTYPE_STATION:
7753                 rtl8723a_stop_tx_beacon(priv);
7754
7755                 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
7756                 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
7757                         BEACON_DISABLE_TSF_UPDATE;
7758                 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
7759                 ret = 0;
7760                 break;
7761         default:
7762                 ret = -EOPNOTSUPP;
7763         }
7764
7765         rtl8xxxu_set_linktype(priv, vif->type);
7766
7767         return ret;
7768 }
7769
7770 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
7771                                       struct ieee80211_vif *vif)
7772 {
7773         struct rtl8xxxu_priv *priv = hw->priv;
7774
7775         dev_dbg(&priv->udev->dev, "%s\n", __func__);
7776 }
7777
7778 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
7779 {
7780         struct rtl8xxxu_priv *priv = hw->priv;
7781         struct device *dev = &priv->udev->dev;
7782         u16 val16;
7783         int ret = 0, channel;
7784         bool ht40;
7785
7786         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
7787                 dev_info(dev,
7788                          "%s: channel: %i (changed %08x chandef.width %02x)\n",
7789                          __func__, hw->conf.chandef.chan->hw_value,
7790                          changed, hw->conf.chandef.width);
7791
7792         if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
7793                 val16 = ((hw->conf.long_frame_max_tx_count <<
7794                           RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
7795                         ((hw->conf.short_frame_max_tx_count <<
7796                           RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
7797                 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
7798         }
7799
7800         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
7801                 switch (hw->conf.chandef.width) {
7802                 case NL80211_CHAN_WIDTH_20_NOHT:
7803                 case NL80211_CHAN_WIDTH_20:
7804                         ht40 = false;
7805                         break;
7806                 case NL80211_CHAN_WIDTH_40:
7807                         ht40 = true;
7808                         break;
7809                 default:
7810                         ret = -ENOTSUPP;
7811                         goto exit;
7812                 }
7813
7814                 channel = hw->conf.chandef.chan->hw_value;
7815
7816                 priv->fops->set_tx_power(priv, channel, ht40);
7817
7818                 priv->fops->config_channel(hw);
7819         }
7820
7821 exit:
7822         return ret;
7823 }
7824
7825 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
7826                             struct ieee80211_vif *vif, u16 queue,
7827                             const struct ieee80211_tx_queue_params *param)
7828 {
7829         struct rtl8xxxu_priv *priv = hw->priv;
7830         struct device *dev = &priv->udev->dev;
7831         u32 val32;
7832         u8 aifs, acm_ctrl, acm_bit;
7833
7834         aifs = param->aifs;
7835
7836         val32 = aifs |
7837                 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
7838                 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
7839                 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
7840
7841         acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
7842         dev_dbg(dev,
7843                 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
7844                 __func__, queue, val32, param->acm, acm_ctrl);
7845
7846         switch (queue) {
7847         case IEEE80211_AC_VO:
7848                 acm_bit = ACM_HW_CTRL_VO;
7849                 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
7850                 break;
7851         case IEEE80211_AC_VI:
7852                 acm_bit = ACM_HW_CTRL_VI;
7853                 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
7854                 break;
7855         case IEEE80211_AC_BE:
7856                 acm_bit = ACM_HW_CTRL_BE;
7857                 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
7858                 break;
7859         case IEEE80211_AC_BK:
7860                 acm_bit = ACM_HW_CTRL_BK;
7861                 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
7862                 break;
7863         default:
7864                 acm_bit = 0;
7865                 break;
7866         }
7867
7868         if (param->acm)
7869                 acm_ctrl |= acm_bit;
7870         else
7871                 acm_ctrl &= ~acm_bit;
7872         rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
7873
7874         return 0;
7875 }
7876
7877 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
7878                                       unsigned int changed_flags,
7879                                       unsigned int *total_flags, u64 multicast)
7880 {
7881         struct rtl8xxxu_priv *priv = hw->priv;
7882         u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
7883
7884         dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
7885                 __func__, changed_flags, *total_flags);
7886
7887         /*
7888          * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
7889          */
7890
7891         if (*total_flags & FIF_FCSFAIL)
7892                 rcr |= RCR_ACCEPT_CRC32;
7893         else
7894                 rcr &= ~RCR_ACCEPT_CRC32;
7895
7896         /*
7897          * FIF_PLCPFAIL not supported?
7898          */
7899
7900         if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
7901                 rcr &= ~RCR_CHECK_BSSID_BEACON;
7902         else
7903                 rcr |= RCR_CHECK_BSSID_BEACON;
7904
7905         if (*total_flags & FIF_CONTROL)
7906                 rcr |= RCR_ACCEPT_CTRL_FRAME;
7907         else
7908                 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
7909
7910         if (*total_flags & FIF_OTHER_BSS) {
7911                 rcr |= RCR_ACCEPT_AP;
7912                 rcr &= ~RCR_CHECK_BSSID_MATCH;
7913         } else {
7914                 rcr &= ~RCR_ACCEPT_AP;
7915                 rcr |= RCR_CHECK_BSSID_MATCH;
7916         }
7917
7918         if (*total_flags & FIF_PSPOLL)
7919                 rcr |= RCR_ACCEPT_PM;
7920         else
7921                 rcr &= ~RCR_ACCEPT_PM;
7922
7923         /*
7924          * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
7925          */
7926
7927         rtl8xxxu_write32(priv, REG_RCR, rcr);
7928
7929         *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
7930                          FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
7931                          FIF_PROBE_REQ);
7932 }
7933
7934 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
7935 {
7936         if (rts > 2347)
7937                 return -EINVAL;
7938
7939         return 0;
7940 }
7941
7942 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
7943                             struct ieee80211_vif *vif,
7944                             struct ieee80211_sta *sta,
7945                             struct ieee80211_key_conf *key)
7946 {
7947         struct rtl8xxxu_priv *priv = hw->priv;
7948         struct device *dev = &priv->udev->dev;
7949         u8 mac_addr[ETH_ALEN];
7950         u8 val8;
7951         u16 val16;
7952         u32 val32;
7953         int retval = -EOPNOTSUPP;
7954
7955         dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
7956                 __func__, cmd, key->cipher, key->keyidx);
7957
7958         if (vif->type != NL80211_IFTYPE_STATION)
7959                 return -EOPNOTSUPP;
7960
7961         if (key->keyidx > 3)
7962                 return -EOPNOTSUPP;
7963
7964         switch (key->cipher) {
7965         case WLAN_CIPHER_SUITE_WEP40:
7966         case WLAN_CIPHER_SUITE_WEP104:
7967
7968                 break;
7969         case WLAN_CIPHER_SUITE_CCMP:
7970                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
7971                 break;
7972         case WLAN_CIPHER_SUITE_TKIP:
7973                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
7974         default:
7975                 return -EOPNOTSUPP;
7976         }
7977
7978         if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
7979                 dev_dbg(dev, "%s: pairwise key\n", __func__);
7980                 ether_addr_copy(mac_addr, sta->addr);
7981         } else {
7982                 dev_dbg(dev, "%s: group key\n", __func__);
7983                 eth_broadcast_addr(mac_addr);
7984         }
7985
7986         val16 = rtl8xxxu_read16(priv, REG_CR);
7987         val16 |= CR_SECURITY_ENABLE;
7988         rtl8xxxu_write16(priv, REG_CR, val16);
7989
7990         val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
7991                 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
7992         val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
7993         rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
7994
7995         switch (cmd) {
7996         case SET_KEY:
7997                 key->hw_key_idx = key->keyidx;
7998                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7999                 rtl8xxxu_cam_write(priv, key, mac_addr);
8000                 retval = 0;
8001                 break;
8002         case DISABLE_KEY:
8003                 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
8004                 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
8005                         key->keyidx << CAM_CMD_KEY_SHIFT;
8006                 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
8007                 retval = 0;
8008                 break;
8009         default:
8010                 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
8011         }
8012
8013         return retval;
8014 }
8015
8016 static int
8017 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
8018                       struct ieee80211_ampdu_params *params)
8019 {
8020         struct rtl8xxxu_priv *priv = hw->priv;
8021         struct device *dev = &priv->udev->dev;
8022         u8 ampdu_factor, ampdu_density;
8023         struct ieee80211_sta *sta = params->sta;
8024         enum ieee80211_ampdu_mlme_action action = params->action;
8025
8026         switch (action) {
8027         case IEEE80211_AMPDU_TX_START:
8028                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
8029                 ampdu_factor = sta->ht_cap.ampdu_factor;
8030                 ampdu_density = sta->ht_cap.ampdu_density;
8031                 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
8032                 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
8033                 dev_dbg(dev,
8034                         "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
8035                         ampdu_factor, ampdu_density);
8036                 break;
8037         case IEEE80211_AMPDU_TX_STOP_FLUSH:
8038                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
8039                 rtl8xxxu_set_ampdu_factor(priv, 0);
8040                 rtl8xxxu_set_ampdu_min_space(priv, 0);
8041                 break;
8042         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
8043                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
8044                          __func__);
8045                 rtl8xxxu_set_ampdu_factor(priv, 0);
8046                 rtl8xxxu_set_ampdu_min_space(priv, 0);
8047                 break;
8048         case IEEE80211_AMPDU_RX_START:
8049                 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
8050                 break;
8051         case IEEE80211_AMPDU_RX_STOP:
8052                 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
8053                 break;
8054         default:
8055                 break;
8056         }
8057         return 0;
8058 }
8059
8060 static int rtl8xxxu_start(struct ieee80211_hw *hw)
8061 {
8062         struct rtl8xxxu_priv *priv = hw->priv;
8063         struct rtl8xxxu_rx_urb *rx_urb;
8064         struct rtl8xxxu_tx_urb *tx_urb;
8065         unsigned long flags;
8066         int ret, i;
8067
8068         ret = 0;
8069
8070         init_usb_anchor(&priv->rx_anchor);
8071         init_usb_anchor(&priv->tx_anchor);
8072         init_usb_anchor(&priv->int_anchor);
8073
8074         priv->fops->enable_rf(priv);
8075         if (priv->usb_interrupts) {
8076                 ret = rtl8xxxu_submit_int_urb(hw);
8077                 if (ret)
8078                         goto exit;
8079         }
8080
8081         for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
8082                 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
8083                 if (!tx_urb) {
8084                         if (!i)
8085                                 ret = -ENOMEM;
8086
8087                         goto error_out;
8088                 }
8089                 usb_init_urb(&tx_urb->urb);
8090                 INIT_LIST_HEAD(&tx_urb->list);
8091                 tx_urb->hw = hw;
8092                 list_add(&tx_urb->list, &priv->tx_urb_free_list);
8093                 priv->tx_urb_free_count++;
8094         }
8095
8096         priv->tx_stopped = false;
8097
8098         spin_lock_irqsave(&priv->rx_urb_lock, flags);
8099         priv->shutdown = false;
8100         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
8101
8102         for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
8103                 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
8104                 if (!rx_urb) {
8105                         if (!i)
8106                                 ret = -ENOMEM;
8107
8108                         goto error_out;
8109                 }
8110                 usb_init_urb(&rx_urb->urb);
8111                 INIT_LIST_HEAD(&rx_urb->list);
8112                 rx_urb->hw = hw;
8113
8114                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
8115         }
8116 exit:
8117         /*
8118          * Accept all data and mgmt frames
8119          */
8120         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
8121         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
8122
8123         rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
8124
8125         return ret;
8126
8127 error_out:
8128         rtl8xxxu_free_tx_resources(priv);
8129         /*
8130          * Disable all data and mgmt frames
8131          */
8132         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
8133         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
8134
8135         return ret;
8136 }
8137
8138 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
8139 {
8140         struct rtl8xxxu_priv *priv = hw->priv;
8141         unsigned long flags;
8142
8143         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
8144
8145         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
8146         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
8147
8148         spin_lock_irqsave(&priv->rx_urb_lock, flags);
8149         priv->shutdown = true;
8150         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
8151
8152         usb_kill_anchored_urbs(&priv->rx_anchor);
8153         usb_kill_anchored_urbs(&priv->tx_anchor);
8154         if (priv->usb_interrupts)
8155                 usb_kill_anchored_urbs(&priv->int_anchor);
8156
8157         priv->fops->disable_rf(priv);
8158
8159         /*
8160          * Disable interrupts
8161          */
8162         if (priv->usb_interrupts)
8163                 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
8164
8165         rtl8xxxu_free_rx_resources(priv);
8166         rtl8xxxu_free_tx_resources(priv);
8167 }
8168
8169 static const struct ieee80211_ops rtl8xxxu_ops = {
8170         .tx = rtl8xxxu_tx,
8171         .add_interface = rtl8xxxu_add_interface,
8172         .remove_interface = rtl8xxxu_remove_interface,
8173         .config = rtl8xxxu_config,
8174         .conf_tx = rtl8xxxu_conf_tx,
8175         .bss_info_changed = rtl8xxxu_bss_info_changed,
8176         .configure_filter = rtl8xxxu_configure_filter,
8177         .set_rts_threshold = rtl8xxxu_set_rts_threshold,
8178         .start = rtl8xxxu_start,
8179         .stop = rtl8xxxu_stop,
8180         .sw_scan_start = rtl8xxxu_sw_scan_start,
8181         .sw_scan_complete = rtl8xxxu_sw_scan_complete,
8182         .set_key = rtl8xxxu_set_key,
8183         .ampdu_action = rtl8xxxu_ampdu_action,
8184 };
8185
8186 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
8187                               struct usb_interface *interface)
8188 {
8189         struct usb_interface_descriptor *interface_desc;
8190         struct usb_host_interface *host_interface;
8191         struct usb_endpoint_descriptor *endpoint;
8192         struct device *dev = &priv->udev->dev;
8193         int i, j = 0, endpoints;
8194         u8 dir, xtype, num;
8195         int ret = 0;
8196
8197         host_interface = &interface->altsetting[0];
8198         interface_desc = &host_interface->desc;
8199         endpoints = interface_desc->bNumEndpoints;
8200
8201         for (i = 0; i < endpoints; i++) {
8202                 endpoint = &host_interface->endpoint[i].desc;
8203
8204                 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
8205                 num = usb_endpoint_num(endpoint);
8206                 xtype = usb_endpoint_type(endpoint);
8207                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
8208                         dev_dbg(dev,
8209                                 "%s: endpoint: dir %02x, # %02x, type %02x\n",
8210                                 __func__, dir, num, xtype);
8211                 if (usb_endpoint_dir_in(endpoint) &&
8212                     usb_endpoint_xfer_bulk(endpoint)) {
8213                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
8214                                 dev_dbg(dev, "%s: in endpoint num %i\n",
8215                                         __func__, num);
8216
8217                         if (priv->pipe_in) {
8218                                 dev_warn(dev,
8219                                          "%s: Too many IN pipes\n", __func__);
8220                                 ret = -EINVAL;
8221                                 goto exit;
8222                         }
8223
8224                         priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
8225                 }
8226
8227                 if (usb_endpoint_dir_in(endpoint) &&
8228                     usb_endpoint_xfer_int(endpoint)) {
8229                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
8230                                 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
8231                                         __func__, num);
8232
8233                         if (priv->pipe_interrupt) {
8234                                 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
8235                                          __func__);
8236                                 ret = -EINVAL;
8237                                 goto exit;
8238                         }
8239
8240                         priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
8241                 }
8242
8243                 if (usb_endpoint_dir_out(endpoint) &&
8244                     usb_endpoint_xfer_bulk(endpoint)) {
8245                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
8246                                 dev_dbg(dev, "%s: out endpoint num %i\n",
8247                                         __func__, num);
8248                         if (j >= RTL8XXXU_OUT_ENDPOINTS) {
8249                                 dev_warn(dev,
8250                                          "%s: Too many OUT pipes\n", __func__);
8251                                 ret = -EINVAL;
8252                                 goto exit;
8253                         }
8254                         priv->out_ep[j++] = num;
8255                 }
8256         }
8257 exit:
8258         priv->nr_out_eps = j;
8259         return ret;
8260 }
8261
8262 static int rtl8xxxu_probe(struct usb_interface *interface,
8263                           const struct usb_device_id *id)
8264 {
8265         struct rtl8xxxu_priv *priv;
8266         struct ieee80211_hw *hw;
8267         struct usb_device *udev;
8268         struct ieee80211_supported_band *sband;
8269         int ret = 0;
8270         int untested = 1;
8271
8272         udev = usb_get_dev(interface_to_usbdev(interface));
8273
8274         switch (id->idVendor) {
8275         case USB_VENDOR_ID_REALTEK:
8276                 switch(id->idProduct) {
8277                 case 0x1724:
8278                 case 0x8176:
8279                 case 0x8178:
8280                 case 0x817f:
8281                         untested = 0;
8282                         break;
8283                 }
8284                 break;
8285         case 0x7392:
8286                 if (id->idProduct == 0x7811)
8287                         untested = 0;
8288                 break;
8289         default:
8290                 break;
8291         }
8292
8293         if (untested) {
8294                 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
8295                 dev_info(&udev->dev,
8296                          "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
8297                          id->idVendor, id->idProduct);
8298                 dev_info(&udev->dev,
8299                          "Please report results to Jes.Sorensen@gmail.com\n");
8300         }
8301
8302         hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
8303         if (!hw) {
8304                 ret = -ENOMEM;
8305                 goto exit;
8306         }
8307
8308         priv = hw->priv;
8309         priv->hw = hw;
8310         priv->udev = udev;
8311         priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
8312         mutex_init(&priv->usb_buf_mutex);
8313         mutex_init(&priv->h2c_mutex);
8314         INIT_LIST_HEAD(&priv->tx_urb_free_list);
8315         spin_lock_init(&priv->tx_urb_lock);
8316         INIT_LIST_HEAD(&priv->rx_urb_pending_list);
8317         spin_lock_init(&priv->rx_urb_lock);
8318         INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
8319
8320         usb_set_intfdata(interface, hw);
8321
8322         ret = rtl8xxxu_parse_usb(priv, interface);
8323         if (ret)
8324                 goto exit;
8325
8326         ret = rtl8xxxu_identify_chip(priv);
8327         if (ret) {
8328                 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
8329                 goto exit;
8330         }
8331
8332         ret = rtl8xxxu_read_efuse(priv);
8333         if (ret) {
8334                 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
8335                 goto exit;
8336         }
8337
8338         ret = priv->fops->parse_efuse(priv);
8339         if (ret) {
8340                 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
8341                 goto exit;
8342         }
8343
8344         rtl8xxxu_print_chipinfo(priv);
8345
8346         ret = priv->fops->load_firmware(priv);
8347         if (ret) {
8348                 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
8349                 goto exit;
8350         }
8351
8352         ret = rtl8xxxu_init_device(hw);
8353
8354         hw->wiphy->max_scan_ssids = 1;
8355         hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
8356         hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
8357         hw->queues = 4;
8358
8359         sband = &rtl8xxxu_supported_band;
8360         sband->ht_cap.ht_supported = true;
8361         sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
8362         sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
8363         sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
8364         memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
8365         sband->ht_cap.mcs.rx_mask[0] = 0xff;
8366         sband->ht_cap.mcs.rx_mask[4] = 0x01;
8367         if (priv->rf_paths > 1) {
8368                 sband->ht_cap.mcs.rx_mask[1] = 0xff;
8369                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
8370         }
8371         sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
8372         /*
8373          * Some APs will negotiate HT20_40 in a noisy environment leading
8374          * to miserable performance. Rather than defaulting to this, only
8375          * enable it if explicitly requested at module load time.
8376          */
8377         if (rtl8xxxu_ht40_2g) {
8378                 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
8379                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
8380         }
8381         hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
8382
8383         hw->wiphy->rts_threshold = 2347;
8384
8385         SET_IEEE80211_DEV(priv->hw, &interface->dev);
8386         SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
8387
8388         hw->extra_tx_headroom = priv->fops->tx_desc_size;
8389         ieee80211_hw_set(hw, SIGNAL_DBM);
8390         /*
8391          * The firmware handles rate control
8392          */
8393         ieee80211_hw_set(hw, HAS_RATE_CONTROL);
8394         ieee80211_hw_set(hw, AMPDU_AGGREGATION);
8395
8396         ret = ieee80211_register_hw(priv->hw);
8397         if (ret) {
8398                 dev_err(&udev->dev, "%s: Failed to register: %i\n",
8399                         __func__, ret);
8400                 goto exit;
8401         }
8402
8403 exit:
8404         if (ret < 0)
8405                 usb_put_dev(udev);
8406         return ret;
8407 }
8408
8409 static void rtl8xxxu_disconnect(struct usb_interface *interface)
8410 {
8411         struct rtl8xxxu_priv *priv;
8412         struct ieee80211_hw *hw;
8413
8414         hw = usb_get_intfdata(interface);
8415         priv = hw->priv;
8416
8417         rtl8xxxu_disable_device(hw);
8418         usb_set_intfdata(interface, NULL);
8419
8420         dev_info(&priv->udev->dev, "disconnecting\n");
8421
8422         ieee80211_unregister_hw(hw);
8423
8424         kfree(priv->fw_data);
8425         mutex_destroy(&priv->usb_buf_mutex);
8426         mutex_destroy(&priv->h2c_mutex);
8427
8428         usb_put_dev(priv->udev);
8429         ieee80211_free_hw(hw);
8430 }
8431
8432 static struct rtl8xxxu_fileops rtl8723au_fops = {
8433         .parse_efuse = rtl8723au_parse_efuse,
8434         .load_firmware = rtl8723au_load_firmware,
8435         .power_on = rtl8723au_power_on,
8436         .power_off = rtl8xxxu_power_off,
8437         .reset_8051 = rtl8xxxu_reset_8051,
8438         .llt_init = rtl8xxxu_init_llt_table,
8439         .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
8440         .config_channel = rtl8723au_config_channel,
8441         .parse_rx_desc = rtl8723au_parse_rx_desc,
8442         .enable_rf = rtl8723a_enable_rf,
8443         .disable_rf = rtl8723a_disable_rf,
8444         .set_tx_power = rtl8723a_set_tx_power,
8445         .update_rate_mask = rtl8723au_update_rate_mask,
8446         .report_connect = rtl8723au_report_connect,
8447         .writeN_block_size = 1024,
8448         .mbox_ext_reg = REG_HMBOX_EXT_0,
8449         .mbox_ext_width = 2,
8450         .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32),
8451         .adda_1t_init = 0x0b1b25a0,
8452         .adda_1t_path_on = 0x0bdb25a0,
8453         .adda_2t_path_on_a = 0x04db25a4,
8454         .adda_2t_path_on_b = 0x0b1b25a4,
8455 };
8456
8457 static struct rtl8xxxu_fileops rtl8723bu_fops = {
8458         .parse_efuse = rtl8723bu_parse_efuse,
8459         .load_firmware = rtl8723bu_load_firmware,
8460         .power_on = rtl8723bu_power_on,
8461         .power_off = rtl8723bu_power_off,
8462         .reset_8051 = rtl8723bu_reset_8051,
8463         .llt_init = rtl8xxxu_auto_llt_table,
8464         .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
8465         .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
8466         .config_channel = rtl8723bu_config_channel,
8467         .parse_rx_desc = rtl8723bu_parse_rx_desc,
8468         .init_aggregation = rtl8723bu_init_aggregation,
8469         .init_statistics = rtl8723bu_init_statistics,
8470         .enable_rf = rtl8723b_enable_rf,
8471         .disable_rf = rtl8723b_disable_rf,
8472         .set_tx_power = rtl8723b_set_tx_power,
8473         .update_rate_mask = rtl8723bu_update_rate_mask,
8474         .report_connect = rtl8723bu_report_connect,
8475         .writeN_block_size = 1024,
8476         .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
8477         .mbox_ext_width = 4,
8478         .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
8479         .has_s0s1 = 1,
8480         .adda_1t_init = 0x01c00014,
8481         .adda_1t_path_on = 0x01c00014,
8482         .adda_2t_path_on_a = 0x01c00014,
8483         .adda_2t_path_on_b = 0x01c00014,
8484 };
8485
8486 #ifdef CONFIG_RTL8XXXU_UNTESTED
8487
8488 static struct rtl8xxxu_fileops rtl8192cu_fops = {
8489         .parse_efuse = rtl8192cu_parse_efuse,
8490         .load_firmware = rtl8192cu_load_firmware,
8491         .power_on = rtl8192cu_power_on,
8492         .power_off = rtl8xxxu_power_off,
8493         .reset_8051 = rtl8xxxu_reset_8051,
8494         .llt_init = rtl8xxxu_init_llt_table,
8495         .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
8496         .config_channel = rtl8723au_config_channel,
8497         .parse_rx_desc = rtl8723au_parse_rx_desc,
8498         .enable_rf = rtl8723a_enable_rf,
8499         .disable_rf = rtl8723a_disable_rf,
8500         .set_tx_power = rtl8723a_set_tx_power,
8501         .update_rate_mask = rtl8723au_update_rate_mask,
8502         .report_connect = rtl8723au_report_connect,
8503         .writeN_block_size = 128,
8504         .mbox_ext_reg = REG_HMBOX_EXT_0,
8505         .mbox_ext_width = 2,
8506         .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32),
8507         .adda_1t_init = 0x0b1b25a0,
8508         .adda_1t_path_on = 0x0bdb25a0,
8509         .adda_2t_path_on_a = 0x04db25a4,
8510         .adda_2t_path_on_b = 0x0b1b25a4,
8511 };
8512
8513 #endif
8514
8515 static struct rtl8xxxu_fileops rtl8192eu_fops = {
8516         .parse_efuse = rtl8192eu_parse_efuse,
8517         .load_firmware = rtl8192eu_load_firmware,
8518         .power_on = rtl8192eu_power_on,
8519         .power_off = rtl8xxxu_power_off,
8520         .reset_8051 = rtl8xxxu_reset_8051,
8521         .llt_init = rtl8xxxu_auto_llt_table,
8522         .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
8523         .config_channel = rtl8723bu_config_channel,
8524         .parse_rx_desc = rtl8723bu_parse_rx_desc,
8525         .enable_rf = rtl8723b_enable_rf,
8526         .disable_rf = rtl8723b_disable_rf,
8527         .set_tx_power = rtl8723b_set_tx_power,
8528         .update_rate_mask = rtl8723bu_update_rate_mask,
8529         .report_connect = rtl8723bu_report_connect,
8530         .writeN_block_size = 128,
8531         .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
8532         .mbox_ext_width = 4,
8533         .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
8534         .has_s0s1 = 1,
8535         .adda_1t_init = 0x0fc01616,
8536         .adda_1t_path_on = 0x0fc01616,
8537         .adda_2t_path_on_a = 0x0fc01616,
8538         .adda_2t_path_on_b = 0x0fc01616,
8539 };
8540
8541 static struct usb_device_id dev_table[] = {
8542 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
8543         .driver_info = (unsigned long)&rtl8723au_fops},
8544 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
8545         .driver_info = (unsigned long)&rtl8723au_fops},
8546 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
8547         .driver_info = (unsigned long)&rtl8723au_fops},
8548 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
8549         .driver_info = (unsigned long)&rtl8192eu_fops},
8550 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
8551         .driver_info = (unsigned long)&rtl8723bu_fops},
8552 #ifdef CONFIG_RTL8XXXU_UNTESTED
8553 /* Still supported by rtlwifi */
8554 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
8555         .driver_info = (unsigned long)&rtl8192cu_fops},
8556 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
8557         .driver_info = (unsigned long)&rtl8192cu_fops},
8558 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
8559         .driver_info = (unsigned long)&rtl8192cu_fops},
8560 /* Tested by Larry Finger */
8561 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
8562         .driver_info = (unsigned long)&rtl8192cu_fops},
8563 /* Currently untested 8188 series devices */
8564 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
8565         .driver_info = (unsigned long)&rtl8192cu_fops},
8566 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
8567         .driver_info = (unsigned long)&rtl8192cu_fops},
8568 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
8569         .driver_info = (unsigned long)&rtl8192cu_fops},
8570 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
8571         .driver_info = (unsigned long)&rtl8192cu_fops},
8572 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
8573         .driver_info = (unsigned long)&rtl8192cu_fops},
8574 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
8575         .driver_info = (unsigned long)&rtl8192cu_fops},
8576 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
8577         .driver_info = (unsigned long)&rtl8192cu_fops},
8578 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
8579         .driver_info = (unsigned long)&rtl8192cu_fops},
8580 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
8581         .driver_info = (unsigned long)&rtl8192cu_fops},
8582 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
8583         .driver_info = (unsigned long)&rtl8192cu_fops},
8584 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
8585         .driver_info = (unsigned long)&rtl8192cu_fops},
8586 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
8587         .driver_info = (unsigned long)&rtl8192cu_fops},
8588 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
8589         .driver_info = (unsigned long)&rtl8192cu_fops},
8590 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
8591         .driver_info = (unsigned long)&rtl8192cu_fops},
8592 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
8593         .driver_info = (unsigned long)&rtl8192cu_fops},
8594 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
8595         .driver_info = (unsigned long)&rtl8192cu_fops},
8596 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
8597         .driver_info = (unsigned long)&rtl8192cu_fops},
8598 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
8599         .driver_info = (unsigned long)&rtl8192cu_fops},
8600 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
8601         .driver_info = (unsigned long)&rtl8192cu_fops},
8602 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
8603         .driver_info = (unsigned long)&rtl8192cu_fops},
8604 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
8605         .driver_info = (unsigned long)&rtl8192cu_fops},
8606 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
8607         .driver_info = (unsigned long)&rtl8192cu_fops},
8608 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
8609         .driver_info = (unsigned long)&rtl8192cu_fops},
8610 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
8611         .driver_info = (unsigned long)&rtl8192cu_fops},
8612 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
8613         .driver_info = (unsigned long)&rtl8192cu_fops},
8614 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
8615         .driver_info = (unsigned long)&rtl8192cu_fops},
8616 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
8617         .driver_info = (unsigned long)&rtl8192cu_fops},
8618 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
8619         .driver_info = (unsigned long)&rtl8192cu_fops},
8620 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
8621         .driver_info = (unsigned long)&rtl8192cu_fops},
8622 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
8623         .driver_info = (unsigned long)&rtl8192cu_fops},
8624 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
8625         .driver_info = (unsigned long)&rtl8192cu_fops},
8626 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
8627         .driver_info = (unsigned long)&rtl8192cu_fops},
8628 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
8629         .driver_info = (unsigned long)&rtl8192cu_fops},
8630 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
8631         .driver_info = (unsigned long)&rtl8192cu_fops},
8632 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
8633         .driver_info = (unsigned long)&rtl8192cu_fops},
8634 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
8635         .driver_info = (unsigned long)&rtl8192cu_fops},
8636 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
8637         .driver_info = (unsigned long)&rtl8192cu_fops},
8638 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
8639         .driver_info = (unsigned long)&rtl8192cu_fops},
8640 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
8641         .driver_info = (unsigned long)&rtl8192cu_fops},
8642 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
8643         .driver_info = (unsigned long)&rtl8192cu_fops},
8644 /* Currently untested 8192 series devices */
8645 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
8646         .driver_info = (unsigned long)&rtl8192cu_fops},
8647 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
8648         .driver_info = (unsigned long)&rtl8192cu_fops},
8649 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
8650         .driver_info = (unsigned long)&rtl8192cu_fops},
8651 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
8652         .driver_info = (unsigned long)&rtl8192cu_fops},
8653 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
8654         .driver_info = (unsigned long)&rtl8192cu_fops},
8655 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
8656         .driver_info = (unsigned long)&rtl8192cu_fops},
8657 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
8658         .driver_info = (unsigned long)&rtl8192cu_fops},
8659 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
8660         .driver_info = (unsigned long)&rtl8192cu_fops},
8661 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
8662         .driver_info = (unsigned long)&rtl8192cu_fops},
8663 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
8664         .driver_info = (unsigned long)&rtl8192cu_fops},
8665 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
8666         .driver_info = (unsigned long)&rtl8192cu_fops},
8667 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
8668         .driver_info = (unsigned long)&rtl8192cu_fops},
8669 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
8670         .driver_info = (unsigned long)&rtl8192cu_fops},
8671 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
8672         .driver_info = (unsigned long)&rtl8192cu_fops},
8673 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
8674         .driver_info = (unsigned long)&rtl8192cu_fops},
8675 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
8676         .driver_info = (unsigned long)&rtl8192cu_fops},
8677 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
8678         .driver_info = (unsigned long)&rtl8192cu_fops},
8679 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
8680         .driver_info = (unsigned long)&rtl8192cu_fops},
8681 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
8682         .driver_info = (unsigned long)&rtl8192cu_fops},
8683 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
8684         .driver_info = (unsigned long)&rtl8192cu_fops},
8685 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
8686         .driver_info = (unsigned long)&rtl8192cu_fops},
8687 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
8688         .driver_info = (unsigned long)&rtl8192cu_fops},
8689 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
8690         .driver_info = (unsigned long)&rtl8192cu_fops},
8691 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
8692         .driver_info = (unsigned long)&rtl8192cu_fops},
8693 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
8694         .driver_info = (unsigned long)&rtl8192cu_fops},
8695 #endif
8696 { }
8697 };
8698
8699 static struct usb_driver rtl8xxxu_driver = {
8700         .name = DRIVER_NAME,
8701         .probe = rtl8xxxu_probe,
8702         .disconnect = rtl8xxxu_disconnect,
8703         .id_table = dev_table,
8704         .disable_hub_initiated_lpm = 1,
8705 };
8706
8707 static int __init rtl8xxxu_module_init(void)
8708 {
8709         int res;
8710
8711         res = usb_register(&rtl8xxxu_driver);
8712         if (res < 0)
8713                 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
8714
8715         return res;
8716 }
8717
8718 static void __exit rtl8xxxu_module_exit(void)
8719 {
8720         usb_deregister(&rtl8xxxu_driver);
8721 }
8722
8723
8724 MODULE_DEVICE_TABLE(usb, dev_table);
8725
8726 module_init(rtl8xxxu_module_init);
8727 module_exit(rtl8xxxu_module_exit);