drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../regd.h"
  34 #include "../cam.h"
  35 #include "../ps.h"
  36 #include "../pci.h"
  37 #include "reg.h"
  38 #include "def.h"
  39 #include "phy.h"
  40 #include "dm.h"
  41 #include "fw.h"
  42 #include "led.h"
  43 #include "hw.h"
  44
  45 void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  46 {
  47         struct rtl_priv *rtlpriv = rtl_priv(hw);
  48         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  49         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  50
  51         switch (variable) {
  52         case HW_VAR_RCR: {
  53                         *((u32 *) (val)) = rtlpci->receive_config;
  54                         break;
  55                 }
  56         case HW_VAR_RF_STATE: {
  57                         *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
  58                         break;
  59                 }
  60         case HW_VAR_FW_PSMODE_STATUS: {
  61                         *((bool *) (val)) = ppsc->fw_current_inpsmode;
  62                         break;
  63                 }
  64         case HW_VAR_CORRECT_TSF: {
  65                         u64 tsf;
  66                         u32 *ptsf_low = (u32 *)&tsf;
  67                         u32 *ptsf_high = ((u32 *)&tsf) + 1;
  68
  69                         *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4));
  70                         *ptsf_low = rtl_read_dword(rtlpriv, TSFR);
  71
  72                         *((u64 *) (val)) = tsf;
  73
  74                         break;
  75                 }
  76         case HW_VAR_MRC: {
  77                         *((bool *)(val)) = rtlpriv->dm.current_mrc_switch;
  78                         break;
  79                 }
  80         default: {
  81                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  82                          "switch case %#x not processed\n", variable);
  83                         break;
  84                 }
  85         }
  86 }
  87
  88 void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  89 {
  90         struct rtl_priv *rtlpriv = rtl_priv(hw);
  91         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  92         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  93         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  94         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  95         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  96
  97         switch (variable) {
  98         case HW_VAR_ETHER_ADDR:{
  99                         rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]);
 100                         rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]);
 101                         break;
 102                 }
 103         case HW_VAR_BASIC_RATE:{
 104                         u16 rate_cfg = ((u16 *) val)[0];
 105                         u8 rate_index = 0;
 106
 107                         if (rtlhal->version == VERSION_8192S_ACUT)
 108                                 rate_cfg = rate_cfg & 0x150;
 109                         else
 110                                 rate_cfg = rate_cfg & 0x15f;
 111
 112                         rate_cfg |= 0x01;
 113
 114                         rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff);
 115                         rtl_write_byte(rtlpriv, RRSR + 1,
 116                                        (rate_cfg >> 8) & 0xff);
 117
 118                         while (rate_cfg > 0x1) {
 119                                 rate_cfg = (rate_cfg >> 1);
 120                                 rate_index++;
 121                         }
 122                         rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index);
 123
 124                         break;
 125                 }
 126         case HW_VAR_BSSID:{
 127                         rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]);
 128                         rtl_write_word(rtlpriv, BSSIDR + 4,
 129                                        ((u16 *)(val + 4))[0]);
 130                         break;
 131                 }
 132         case HW_VAR_SIFS:{
 133                         rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]);
 134                         rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]);
 135                         break;
 136                 }
 137         case HW_VAR_SLOT_TIME:{
 138                         u8 e_aci;
 139
 140                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 141                                  "HW_VAR_SLOT_TIME %x\n", val[0]);
 142
 143                         rtl_write_byte(rtlpriv, SLOT_TIME, val[0]);
 144
 145                         for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 146                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 147                                                 HW_VAR_AC_PARAM,
 148                                                 (&e_aci));
 149                         }
 150                         break;
 151                 }
 152         case HW_VAR_ACK_PREAMBLE:{
 153                         u8 reg_tmp;
 154                         u8 short_preamble = (bool) (*val);
 155                         reg_tmp = (mac->cur_40_prime_sc) << 5;
 156                         if (short_preamble)
 157                                 reg_tmp |= 0x80;
 158
 159                         rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp);
 160                         break;
 161                 }
 162         case HW_VAR_AMPDU_MIN_SPACE:{
 163                         u8 min_spacing_to_set;
 164                         u8 sec_min_space;
 165
 166                         min_spacing_to_set = *val;
 167                         if (min_spacing_to_set <= 7) {
 168                                 if (rtlpriv->sec.pairwise_enc_algorithm ==
 169                                     NO_ENCRYPTION)
 170                                         sec_min_space = 0;
 171                                 else
 172                                         sec_min_space = 1;
 173
 174                                 if (min_spacing_to_set < sec_min_space)
 175                                         min_spacing_to_set = sec_min_space;
 176                                 if (min_spacing_to_set > 5)
 177                                         min_spacing_to_set = 5;
 178
 179                                 mac->min_space_cfg =
 180                                                 ((mac->min_space_cfg & 0xf8) |
 181                                                 min_spacing_to_set);
 182
 183                                 *val = min_spacing_to_set;
 184
 185                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 186                                          "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 187                                          mac->min_space_cfg);
 188
 189                                 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
 190                                                mac->min_space_cfg);
 191                         }
 192                         break;
 193                 }
 194         case HW_VAR_SHORTGI_DENSITY:{
 195                         u8 density_to_set;
 196
 197                         density_to_set = *val;
 198                         mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
 199                         mac->min_space_cfg |= (density_to_set << 3);
 200
 201                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 202                                  "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 203                                  mac->min_space_cfg);
 204
 205                         rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
 206                                        mac->min_space_cfg);
 207
 208                         break;
 209                 }
 210         case HW_VAR_AMPDU_FACTOR:{
 211                         u8 factor_toset;
 212                         u8 regtoset;
 213                         u8 factorlevel[18] = {
 214                                 2, 4, 4, 7, 7, 13, 13,
 215                                 13, 2, 7, 7, 13, 13,
 216                                 15, 15, 15, 15, 0};
 217                         u8 index = 0;
 218
 219                         factor_toset = *val;
 220                         if (factor_toset <= 3) {
 221                                 factor_toset = (1 << (factor_toset + 2));
 222                                 if (factor_toset > 0xf)
 223                                         factor_toset = 0xf;
 224
 225                                 for (index = 0; index < 17; index++) {
 226                                         if (factorlevel[index] > factor_toset)
 227                                                 factorlevel[index] =
 228                                                                  factor_toset;
 229                                 }
 230
 231                                 for (index = 0; index < 8; index++) {
 232                                         regtoset = ((factorlevel[index * 2]) |
 233                                                     (factorlevel[index *
 234                                                     2 + 1] << 4));
 235                                         rtl_write_byte(rtlpriv,
 236                                                        AGGLEN_LMT_L + index,
 237                                                        regtoset);
 238                                 }
 239
 240                                 regtoset = ((factorlevel[16]) |
 241                                             (factorlevel[17] << 4));
 242                                 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset);
 243
 244                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 245                                          "Set HW_VAR_AMPDU_FACTOR: %#x\n",
 246                                          factor_toset);
 247                         }
 248                         break;
 249                 }
 250         case HW_VAR_AC_PARAM:{
 251                         u8 e_aci = *val;
 252                         rtl92s_dm_init_edca_turbo(hw);
 253
 254                         if (rtlpci->acm_method != EACMWAY2_SW)
 255                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 256                                                  HW_VAR_ACM_CTRL,
 257                                                  &e_aci);
 258                         break;
 259                 }
 260         case HW_VAR_ACM_CTRL:{
 261                         u8 e_aci = *val;
 262                         union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&(
 263                                                         mac->ac[0].aifs));
 264                         u8 acm = p_aci_aifsn->f.acm;
 265                         u8 acm_ctrl = rtl_read_byte(rtlpriv, AcmHwCtrl);
 266
 267                         acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?
 268                                    0x0 : 0x1);
 269
 270                         if (acm) {
 271                                 switch (e_aci) {
 272                                 case AC0_BE:
 273                                         acm_ctrl |= AcmHw_BeqEn;
 274                                         break;
 275                                 case AC2_VI:
 276                                         acm_ctrl |= AcmHw_ViqEn;
 277                                         break;
 278                                 case AC3_VO:
 279                                         acm_ctrl |= AcmHw_VoqEn;
 280                                         break;
 281                                 default:
 282                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 283                                                  "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 284                                                  acm);
 285                                         break;
 286                                 }
 287                         } else {
 288                                 switch (e_aci) {
 289                                 case AC0_BE:
 290                                         acm_ctrl &= (~AcmHw_BeqEn);
 291                                         break;
 292                                 case AC2_VI:
 293                                         acm_ctrl &= (~AcmHw_ViqEn);
 294                                         break;
 295                                 case AC3_VO:
 296                                         acm_ctrl &= (~AcmHw_VoqEn);
 297                                         break;
 298                                 default:
 299                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 300                                                  "switch case %#x not processed\n",
 301                                                  e_aci);
 302                                         break;
 303                                 }
 304                         }
 305
 306                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 307                                  "HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl);
 308                         rtl_write_byte(rtlpriv, AcmHwCtrl, acm_ctrl);
 309                         break;
 310                 }
 311         case HW_VAR_RCR:{
 312                         rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]);
 313                         rtlpci->receive_config = ((u32 *) (val))[0];
 314                         break;
 315                 }
 316         case HW_VAR_RETRY_LIMIT:{
 317                         u8 retry_limit = val[0];
 318
 319                         rtl_write_word(rtlpriv, RETRY_LIMIT,
 320                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 321                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
 322                         break;
 323                 }
 324         case HW_VAR_DUAL_TSF_RST: {
 325                         break;
 326                 }
 327         case HW_VAR_EFUSE_BYTES: {
 328                         rtlefuse->efuse_usedbytes = *((u16 *) val);
 329                         break;
 330                 }
 331         case HW_VAR_EFUSE_USAGE: {
 332                         rtlefuse->efuse_usedpercentage = *val;
 333                         break;
 334                 }
 335         case HW_VAR_IO_CMD: {
 336                         break;
 337                 }
 338         case HW_VAR_WPA_CONFIG: {
 339                         rtl_write_byte(rtlpriv, REG_SECR, *val);
 340                         break;
 341                 }
 342         case HW_VAR_SET_RPWM:{
 343                         break;
 344                 }
 345         case HW_VAR_H2C_FW_PWRMODE:{
 346                         break;
 347                 }
 348         case HW_VAR_FW_PSMODE_STATUS: {
 349                         ppsc->fw_current_inpsmode = *((bool *) val);
 350                         break;
 351                 }
 352         case HW_VAR_H2C_FW_JOINBSSRPT:{
 353                         break;
 354                 }
 355         case HW_VAR_AID:{
 356                         break;
 357                 }
 358         case HW_VAR_CORRECT_TSF:{
 359                         break;
 360                 }
 361         case HW_VAR_MRC: {
 362                         bool bmrc_toset = *((bool *)val);
 363                         u8 u1bdata = 0;
 364
 365                         if (bmrc_toset) {
 366                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 367                                               MASKBYTE0, 0x33);
 368                                 u1bdata = (u8)rtl_get_bbreg(hw,
 369                                                 ROFDM1_TRXPATHENABLE,
 370                                                 MASKBYTE0);
 371                                 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
 372                                               MASKBYTE0,
 373                                               ((u1bdata & 0xf0) | 0x03));
 374                                 u1bdata = (u8)rtl_get_bbreg(hw,
 375                                                 ROFDM0_TRXPATHENABLE,
 376                                                 MASKBYTE1);
 377                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 378                                               MASKBYTE1,
 379                                               (u1bdata | 0x04));
 380
 381                                 /* Update current settings. */
 382                                 rtlpriv->dm.current_mrc_switch = bmrc_toset;
 383                         } else {
 384                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 385                                               MASKBYTE0, 0x13);
 386                                 u1bdata = (u8)rtl_get_bbreg(hw,
 387                                                  ROFDM1_TRXPATHENABLE,
 388                                                  MASKBYTE0);
 389                                 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
 390                                               MASKBYTE0,
 391                                               ((u1bdata & 0xf0) | 0x01));
 392                                 u1bdata = (u8)rtl_get_bbreg(hw,
 393                                                 ROFDM0_TRXPATHENABLE,
 394                                                 MASKBYTE1);
 395                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 396                                               MASKBYTE1, (u1bdata & 0xfb));
 397
 398                                 /* Update current settings. */
 399                                 rtlpriv->dm.current_mrc_switch = bmrc_toset;
 400                         }
 401
 402                         break;
 403                 }
 404         case HW_VAR_FW_LPS_ACTION: {
 405                 bool enter_fwlps = *((bool *)val);
 406                 u8 rpwm_val, fw_pwrmode;
 407                 bool fw_current_inps;
 408
 409                 if (enter_fwlps) {
 410                         rpwm_val = 0x02;        /* RF off */
 411                         fw_current_inps = true;
 412                         rtlpriv->cfg->ops->set_hw_reg(hw,
 413                                         HW_VAR_FW_PSMODE_STATUS,
 414                                         (u8 *)(&fw_current_inps));
 415                         rtlpriv->cfg->ops->set_hw_reg(hw,
 416                                         HW_VAR_H2C_FW_PWRMODE,
 417                                         &ppsc->fwctrl_psmode);
 418
 419                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 420                                                       &rpwm_val);
 421                 } else {
 422                         rpwm_val = 0x0C;        /* RF on */
 423                         fw_pwrmode = FW_PS_ACTIVE_MODE;
 424                         fw_current_inps = false;
 425                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 426                                                       &rpwm_val);
 427                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 428                                                       &fw_pwrmode);
 429
 430                         rtlpriv->cfg->ops->set_hw_reg(hw,
 431                                         HW_VAR_FW_PSMODE_STATUS,
 432                                         (u8 *)(&fw_current_inps));
 433                 }
 434                 break; }
 435         default:
 436                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 437                          "switch case %#x not processed\n", variable);
 438                 break;
 439         }
 440
 441 }
 442
 443 void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw)
 444 {
 445         struct rtl_priv *rtlpriv = rtl_priv(hw);
 446         u8 sec_reg_value = 0x0;
 447
 448         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 449                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 450                  rtlpriv->sec.pairwise_enc_algorithm,
 451                  rtlpriv->sec.group_enc_algorithm);
 452
 453         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 454                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 455                          "not open hw encryption\n");
 456                 return;
 457         }
 458
 459         sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
 460
 461         if (rtlpriv->sec.use_defaultkey) {
 462                 sec_reg_value |= SCR_TXUSEDK;
 463                 sec_reg_value |= SCR_RXUSEDK;
 464         }
 465
 466         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
 467                  sec_reg_value);
 468
 469         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 470
 471 }
 472
 473 static u8 _rtl92se_halset_sysclk(struct ieee80211_hw *hw, u8 data)
 474 {
 475         struct rtl_priv *rtlpriv = rtl_priv(hw);
 476         u8 waitcount = 100;
 477         bool bresult = false;
 478         u8 tmpvalue;
 479
 480         rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
 481
 482         /* Wait the MAC synchronized. */
 483         udelay(400);
 484
 485         /* Check if it is set ready. */
 486         tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
 487         bresult = ((tmpvalue & BIT(7)) == (data & BIT(7)));
 488
 489         if ((data & (BIT(6) | BIT(7))) == false) {
 490                 waitcount = 100;
 491                 tmpvalue = 0;
 492
 493                 while (1) {
 494                         waitcount--;
 495
 496                         tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
 497                         if ((tmpvalue & BIT(6)))
 498                                 break;
 499
 500                         pr_err("wait for BIT(6) return value %x\n", tmpvalue);
 501                         if (waitcount == 0)
 502                                 break;
 503
 504                         udelay(10);
 505                 }
 506
 507                 if (waitcount == 0)
 508                         bresult = false;
 509                 else
 510                         bresult = true;
 511         }
 512
 513         return bresult;
 514 }
 515
 516 void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw)
 517 {
 518         struct rtl_priv *rtlpriv = rtl_priv(hw);
 519         u8 u1tmp;
 520
 521         /* The following config GPIO function */
 522         rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
 523         u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
 524
 525         /* config GPIO3 to input */
 526         u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
 527         rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
 528
 529 }
 530
 531 static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw)
 532 {
 533         struct rtl_priv *rtlpriv = rtl_priv(hw);
 534         u8 u1tmp;
 535         u8 retval = ERFON;
 536
 537         /* The following config GPIO function */
 538         rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
 539         u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
 540
 541         /* config GPIO3 to input */
 542         u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
 543         rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
 544
 545         /* On some of the platform, driver cannot read correct
 546          * value without delay between Write_GPIO_SEL and Read_GPIO_IN */
 547         mdelay(10);
 548
 549         /* check GPIO3 */
 550         u1tmp = rtl_read_byte(rtlpriv, GPIO_IN_SE);
 551         retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF;
 552
 553         return retval;
 554 }
 555
 556 static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw)
 557 {
 558         struct rtl_priv *rtlpriv = rtl_priv(hw);
 559         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 560         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 561
 562         u8 i;
 563         u8 tmpu1b;
 564         u16 tmpu2b;
 565         u8 pollingcnt = 20;
 566
 567         if (rtlpci->first_init) {
 568                 /* Reset PCIE Digital */
 569                 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 570                 tmpu1b &= 0xFE;
 571                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
 572                 udelay(1);
 573                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0));
 574         }
 575
 576         /* Switch to SW IO control */
 577         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
 578         if (tmpu1b & BIT(7)) {
 579                 tmpu1b &= ~(BIT(6) | BIT(7));
 580
 581                 /* Set failed, return to prevent hang. */
 582                 if (!_rtl92se_halset_sysclk(hw, tmpu1b))
 583                         return;
 584         }
 585
 586         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
 587         udelay(50);
 588         rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
 589         udelay(50);
 590
 591         /* Clear FW RPWM for FW control LPS.*/
 592         rtl_write_byte(rtlpriv, RPWM, 0x0);
 593
 594         /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */
 595         tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 596         tmpu1b &= 0x73;
 597         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
 598         /* wait for BIT 10/11/15 to pull high automatically!! */
 599         mdelay(1);
 600
 601         rtl_write_byte(rtlpriv, CMDR, 0);
 602         rtl_write_byte(rtlpriv, TCR, 0);
 603
 604         /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
 605         tmpu1b = rtl_read_byte(rtlpriv, 0x562);
 606         tmpu1b |= 0x08;
 607         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
 608         tmpu1b &= ~(BIT(3));
 609         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
 610
 611         /* Enable AFE clock source */
 612         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
 613         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
 614         /* Delay 1.5ms */
 615         mdelay(2);
 616         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
 617         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
 618
 619         /* Enable AFE Macro Block's Bandgap */
 620         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
 621         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
 622         mdelay(1);
 623
 624         /* Enable AFE Mbias */
 625         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
 626         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
 627         mdelay(1);
 628
 629         /* Enable LDOA15 block  */
 630         tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
 631         rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
 632
 633         /* Set Digital Vdd to Retention isolation Path. */
 634         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
 635         rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
 636
 637         /* For warm reboot NIC disappera bug. */
 638         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 639         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
 640
 641         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
 642
 643         /* Enable AFE PLL Macro Block */
 644         /* We need to delay 100u before enabling PLL. */
 645         udelay(200);
 646         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
 647         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
 648
 649         /* for divider reset  */
 650         udelay(100);
 651         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) |
 652                        BIT(4) | BIT(6)));
 653         udelay(10);
 654         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
 655         udelay(10);
 656
 657         /* Enable MAC 80MHZ clock  */
 658         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
 659         rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
 660         mdelay(1);
 661
 662         /* Release isolation AFE PLL & MD */
 663         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
 664
 665         /* Enable MAC clock */
 666         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
 667         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
 668
 669         /* Enable Core digital and enable IOREG R/W */
 670         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 671         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
 672
 673         tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 674         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7)));
 675
 676         /* enable REG_EN */
 677         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
 678
 679         /* Switch the control path. */
 680         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
 681         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
 682
 683         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
 684         tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
 685         if (!_rtl92se_halset_sysclk(hw, tmpu1b))
 686                 return; /* Set failed, return to prevent hang. */
 687
 688         rtl_write_word(rtlpriv, CMDR, 0x07FC);
 689
 690         /* MH We must enable the section of code to prevent load IMEM fail. */
 691         /* Load MAC register from WMAc temporarily We simulate macreg. */
 692         /* txt HW will provide MAC txt later  */
 693         rtl_write_byte(rtlpriv, 0x6, 0x30);
 694         rtl_write_byte(rtlpriv, 0x49, 0xf0);
 695
 696         rtl_write_byte(rtlpriv, 0x4b, 0x81);
 697
 698         rtl_write_byte(rtlpriv, 0xb5, 0x21);
 699
 700         rtl_write_byte(rtlpriv, 0xdc, 0xff);
 701         rtl_write_byte(rtlpriv, 0xdd, 0xff);
 702         rtl_write_byte(rtlpriv, 0xde, 0xff);
 703         rtl_write_byte(rtlpriv, 0xdf, 0xff);
 704
 705         rtl_write_byte(rtlpriv, 0x11a, 0x00);
 706         rtl_write_byte(rtlpriv, 0x11b, 0x00);
 707
 708         for (i = 0; i < 32; i++)
 709                 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b);
 710
 711         rtl_write_byte(rtlpriv, 0x236, 0xff);
 712
 713         rtl_write_byte(rtlpriv, 0x503, 0x22);
 714
 715         if (ppsc->support_aspm && !ppsc->support_backdoor)
 716                 rtl_write_byte(rtlpriv, 0x560, 0x40);
 717         else
 718                 rtl_write_byte(rtlpriv, 0x560, 0x00);
 719
 720         rtl_write_byte(rtlpriv, DBG_PORT, 0x91);
 721
 722         /* Set RX Desc Address */
 723         rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
 724         rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma);
 725
 726         /* Set TX Desc Address */
 727         rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma);
 728         rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma);
 729         rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma);
 730         rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma);
 731         rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma);
 732         rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma);
 733         rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma);
 734         rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma);
 735         rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma);
 736
 737         rtl_write_word(rtlpriv, CMDR, 0x37FC);
 738
 739         /* To make sure that TxDMA can ready to download FW. */
 740         /* We should reset TxDMA if IMEM RPT was not ready. */
 741         do {
 742                 tmpu1b = rtl_read_byte(rtlpriv, TCR);
 743                 if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
 744                         break;
 745
 746                 udelay(5);
 747         } while (pollingcnt--);
 748
 749         if (pollingcnt <= 0) {
 750                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 751                          "Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n",
 752                          tmpu1b);
 753                 tmpu1b = rtl_read_byte(rtlpriv, CMDR);
 754                 rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN));
 755                 udelay(2);
 756                 /* Reset TxDMA */
 757                 rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN);
 758         }
 759
 760         /* After MACIO reset,we must refresh LED state. */
 761         if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) ||
 762            (ppsc->rfoff_reason == 0)) {
 763                 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 764                 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 765                 enum rf_pwrstate rfpwr_state_toset;
 766                 rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw);
 767
 768                 if (rfpwr_state_toset == ERFON)
 769                         rtl92se_sw_led_on(hw, pLed0);
 770         }
 771 }
 772
 773 static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw)
 774 {
 775         struct rtl_priv *rtlpriv = rtl_priv(hw);
 776         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 777         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 778         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 779         u8 i;
 780         u16 tmpu2b;
 781
 782         /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */
 783
 784         /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */
 785         /* Turn on 0x40 Command register */
 786         rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN |
 787                         SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN |
 788                         RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN));
 789
 790         /* Set TCR TX DMA pre 2 FULL enable bit */
 791         rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) |
 792                         TXDMAPRE2FULL);
 793
 794         /* Set RCR      */
 795         rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
 796
 797         /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */
 798
 799         /* 4. Timing Control Register  (Offset: 0x0080 - 0x009F) */
 800         /* Set CCK/OFDM SIFS */
 801         /* CCK SIFS shall always be 10us. */
 802         rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a);
 803         rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010);
 804
 805         /* Set AckTimeout */
 806         rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40);
 807
 808         /* Beacon related */
 809         rtl_write_word(rtlpriv, BCN_INTERVAL, 100);
 810         rtl_write_word(rtlpriv, ATIMWND, 2);
 811
 812         /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */
 813         /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */
 814         /* Firmware allocate now, associate with FW internal setting.!!! */
 815
 816         /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */
 817         /* 5.3 Set driver info, we only accept PHY status now. */
 818         /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO  */
 819         rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6));
 820
 821         /* 6. Adaptive Control Register  (Offset: 0x0160 - 0x01CF) */
 822         /* Set RRSR to all legacy rate and HT rate
 823          * CCK rate is supported by default.
 824          * CCK rate will be filtered out only when associated
 825          * AP does not support it.
 826          * Only enable ACK rate to OFDM 24M
 827          * Disable RRSR for CCK rate in A-Cut   */
 828
 829         if (rtlhal->version == VERSION_8192S_ACUT)
 830                 rtl_write_byte(rtlpriv, RRSR, 0xf0);
 831         else if (rtlhal->version == VERSION_8192S_BCUT)
 832                 rtl_write_byte(rtlpriv, RRSR, 0xff);
 833         rtl_write_byte(rtlpriv, RRSR + 1, 0x01);
 834         rtl_write_byte(rtlpriv, RRSR + 2, 0x00);
 835
 836         /* A-Cut IC do not support CCK rate. We forbid ARFR to */
 837         /* fallback to CCK rate */
 838         for (i = 0; i < 8; i++) {
 839                 /*Disable RRSR for CCK rate in A-Cut */
 840                 if (rtlhal->version == VERSION_8192S_ACUT)
 841                         rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0);
 842         }
 843
 844         /* Different rate use different AMPDU size */
 845         /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */
 846         rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f);
 847         /* MCS0/1/2/3 use max AMPDU size 4*2=8K */
 848         rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442);
 849         /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */
 850         rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7);
 851         /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */
 852         rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772);
 853         /* MCS12/13/14/15 use max AMPDU size 15*2=30K */
 854         rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd);
 855
 856         /* Set Data / Response auto rate fallack retry count */
 857         rtl_write_dword(rtlpriv, DARFRC, 0x04010000);
 858         rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605);
 859         rtl_write_dword(rtlpriv, RARFRC, 0x04010000);
 860         rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605);
 861
 862         /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */
 863         /* Set all rate to support SG */
 864         rtl_write_word(rtlpriv, SG_RATE, 0xFFFF);
 865
 866         /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */
 867         /* Set NAV protection length */
 868         rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080);
 869         /* CF-END Threshold */
 870         rtl_write_byte(rtlpriv, CFEND_TH, 0xFF);
 871         /* Set AMPDU minimum space */
 872         rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07);
 873         /* Set TXOP stall control for several queue/HI/BCN/MGT/ */
 874         rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00);
 875
 876         /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */
 877         /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */
 878         /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */
 879         /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */
 880         /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */
 881
 882         /* 14. Set driver info, we only accept PHY status now. */
 883         rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4);
 884
 885         /* 15. For EEPROM R/W Workaround */
 886         /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */
 887         tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
 888         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13));
 889         tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
 890         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8)));
 891
 892         /* 17. For EFUSE */
 893         /* We may R/W EFUSE in EEPROM mode */
 894         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
 895                 u8      tempval;
 896
 897                 tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1);
 898                 tempval &= 0xFE;
 899                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval);
 900
 901                 /* Change Program timing */
 902                 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72);
 903                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "EFUSE CONFIG OK\n");
 904         }
 905
 906         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
 907
 908 }
 909
 910 static void _rtl92se_hw_configure(struct ieee80211_hw *hw)
 911 {
 912         struct rtl_priv *rtlpriv = rtl_priv(hw);
 913         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 914         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 915         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 916
 917         u8 reg_bw_opmode = 0;
 918         u32 reg_rrsr = 0;
 919         u8 regtmp = 0;
 920
 921         reg_bw_opmode = BW_OPMODE_20MHZ;
 922         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 923
 924         regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL);
 925         reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp;
 926         rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr);
 927         rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
 928
 929         /* Set Retry Limit here */
 930         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
 931                         (u8 *)(&rtlpci->shortretry_limit));
 932
 933         rtl_write_byte(rtlpriv, MLT, 0x8f);
 934
 935         /* For Min Spacing configuration. */
 936         switch (rtlphy->rf_type) {
 937         case RF_1T2R:
 938         case RF_1T1R:
 939                 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
 940                 break;
 941         case RF_2T2R:
 942         case RF_2T2R_GREEN:
 943                 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
 944                 break;
 945         }
 946         rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg);
 947 }
 948
 949 int rtl92se_hw_init(struct ieee80211_hw *hw)
 950 {
 951         struct rtl_priv *rtlpriv = rtl_priv(hw);
 952         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 953         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 954         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 955         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 956         u8 tmp_byte = 0;
 957         unsigned long flags;
 958         bool rtstatus = true;
 959         u8 tmp_u1b;
 960         int err = false;
 961         u8 i;
 962         int wdcapra_add[] = {
 963                 EDCAPARA_BE, EDCAPARA_BK,
 964                 EDCAPARA_VI, EDCAPARA_VO};
 965         u8 secr_value = 0x0;
 966
 967         rtlpci->being_init_adapter = true;
 968
 969         /* As this function can take a very long time (up to 350 ms)
 970          * and can be called with irqs disabled, reenable the irqs
 971          * to let the other devices continue being serviced.
 972          *
 973          * It is safe doing so since our own interrupts will only be enabled
 974          * in a subsequent step.
 975          */
 976         local_save_flags(flags);
 977         local_irq_enable();
 978
 979         rtlpriv->intf_ops->disable_aspm(hw);
 980
 981         /* 1. MAC Initialize */
 982         /* Before FW download, we have to set some MAC register */
 983         _rtl92se_macconfig_before_fwdownload(hw);
 984
 985         rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv,
 986                         PMC_FSM) >> 16) & 0xF);
 987
 988         rtl8192se_gpiobit3_cfg_inputmode(hw);
 989
 990         /* 2. download firmware */
 991         rtstatus = rtl92s_download_fw(hw);
 992         if (!rtstatus) {
 993                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 994                          "Failed to download FW. Init HW without FW now... "
 995                          "Please copy FW into /lib/firmware/rtlwifi\n");
 996                 err = 1;
 997                 goto exit;
 998         }
 999
1000         /* After FW download, we have to reset MAC register */
1001         _rtl92se_macconfig_after_fwdownload(hw);
1002
1003         /*Retrieve default FW Cmd IO map. */
1004         rtlhal->fwcmd_iomap =   rtl_read_word(rtlpriv, LBUS_MON_ADDR);
1005         rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK);
1006
1007         /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */
1008         if (!rtl92s_phy_mac_config(hw)) {
1009                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "MAC Config failed\n");
1010                 err = rtstatus;
1011                 goto exit;
1012         }
1013
1014         /* because last function modify RCR, so we update
1015          * rcr var here, or TP will unstable for receive_config
1016          * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1017          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1018          */
1019         rtlpci->receive_config = rtl_read_dword(rtlpriv, RCR);
1020         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1021         rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
1022
1023         /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */
1024         /* We must set flag avoid BB/RF config period later!! */
1025         rtl_write_dword(rtlpriv, CMDR, 0x37FC);
1026
1027         /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */
1028         if (!rtl92s_phy_bb_config(hw)) {
1029                 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "BB Config failed\n");
1030                 err = rtstatus;
1031                 goto exit;
1032         }
1033
1034         /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */
1035         /* Before initalizing RF. We can not use FW to do RF-R/W. */
1036
1037         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1038
1039         /* Before RF-R/W we must execute the IO from Scott's suggestion. */
1040         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB);
1041         if (rtlhal->version == VERSION_8192S_ACUT)
1042                 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07);
1043         else
1044                 rtl_write_byte(rtlpriv, RF_CTRL, 0x07);
1045
1046         if (!rtl92s_phy_rf_config(hw)) {
1047                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RF Config failed\n");
1048                 err = rtstatus;
1049                 goto exit;
1050         }
1051
1052         /* After read predefined TXT, we must set BB/MAC/RF
1053          * register as our requirement */
1054
1055         rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw,
1056                                                            (enum radio_path)0,
1057                                                            RF_CHNLBW,
1058                                                            RFREG_OFFSET_MASK);
1059         rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw,
1060                                                            (enum radio_path)1,
1061                                                            RF_CHNLBW,
1062                                                            RFREG_OFFSET_MASK);
1063
1064         /*---- Set CCK and OFDM Block "ON"----*/
1065         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1066         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1067
1068         /*3 Set Hardware(Do nothing now) */
1069         _rtl92se_hw_configure(hw);
1070
1071         /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1072         /* TX power index for different rate set. */
1073         /* Get original hw reg values */
1074         rtl92s_phy_get_hw_reg_originalvalue(hw);
1075         /* Write correct tx power index */
1076         rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1077
1078         /* We must set MAC address after firmware download. */
1079         for (i = 0; i < 6; i++)
1080                 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1081
1082         /* EEPROM R/W workaround */
1083         tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG);
1084         rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3)));
1085
1086         rtl_write_byte(rtlpriv, 0x4d, 0x0);
1087
1088         if (hal_get_firmwareversion(rtlpriv) >= 0x49) {
1089                 tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4));
1090                 tmp_byte = tmp_byte | BIT(5);
1091                 rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte);
1092                 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF);
1093         }
1094
1095         /* We enable high power and RA related mechanism after NIC
1096          * initialized. */
1097         if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
1098                 /* Fw v.53 and later. */
1099                 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT);
1100         } else if (hal_get_firmwareversion(rtlpriv) == 0x34) {
1101                 /* Fw v.52. */
1102                 rtl_write_dword(rtlpriv, WFM5, FW_RA_INIT);
1103                 rtl92s_phy_chk_fwcmd_iodone(hw);
1104         } else {
1105                 /* Compatible earlier FW version. */
1106                 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
1107                 rtl92s_phy_chk_fwcmd_iodone(hw);
1108                 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
1109                 rtl92s_phy_chk_fwcmd_iodone(hw);
1110                 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
1111                 rtl92s_phy_chk_fwcmd_iodone(hw);
1112         }
1113
1114         /* Add to prevent ASPM bug. */
1115         /* Always enable hst and NIC clock request. */
1116         rtl92s_phy_switch_ephy_parameter(hw);
1117
1118         /* Security related
1119          * 1. Clear all H/W keys.
1120          * 2. Enable H/W encryption/decryption. */
1121         rtl_cam_reset_all_entry(hw);
1122         secr_value |= SCR_TXENCENABLE;
1123         secr_value |= SCR_RXENCENABLE;
1124         secr_value |= SCR_NOSKMC;
1125         rtl_write_byte(rtlpriv, REG_SECR, secr_value);
1126
1127         for (i = 0; i < 4; i++)
1128                 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322);
1129
1130         if (rtlphy->rf_type == RF_1T2R) {
1131                 bool mrc2set = true;
1132                 /* Turn on B-Path */
1133                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set);
1134         }
1135
1136         rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON);
1137         rtl92s_dm_init(hw);
1138 exit:
1139         local_irq_restore(flags);
1140         rtlpci->being_init_adapter = false;
1141         return err;
1142 }
1143
1144 void rtl92se_set_mac_addr(struct rtl_io *io, const u8 *addr)
1145 {
1146         /* This is a stub. */
1147 }
1148
1149 void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1150 {
1151         struct rtl_priv *rtlpriv = rtl_priv(hw);
1152         u32 reg_rcr;
1153
1154         if (rtlpriv->psc.rfpwr_state != ERFON)
1155                 return;
1156
1157         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1158
1159         if (check_bssid) {
1160                 reg_rcr |= (RCR_CBSSID);
1161                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1162         } else if (!check_bssid) {
1163                 reg_rcr &= (~RCR_CBSSID);
1164                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1165         }
1166
1167 }
1168
1169 static int _rtl92se_set_media_status(struct ieee80211_hw *hw,
1170                                      enum nl80211_iftype type)
1171 {
1172         struct rtl_priv *rtlpriv = rtl_priv(hw);
1173         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1174         u32 temp;
1175         bt_msr &= ~MSR_LINK_MASK;
1176
1177         switch (type) {
1178         case NL80211_IFTYPE_UNSPECIFIED:
1179                 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
1180                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1181                          "Set Network type to NO LINK!\n");
1182                 break;
1183         case NL80211_IFTYPE_ADHOC:
1184                 bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
1185                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1186                          "Set Network type to Ad Hoc!\n");
1187                 break;
1188         case NL80211_IFTYPE_STATION:
1189                 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
1190                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1191                          "Set Network type to STA!\n");
1192                 break;
1193         case NL80211_IFTYPE_AP:
1194                 bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
1195                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1196                          "Set Network type to AP!\n");
1197                 break;
1198         default:
1199                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1200                          "Network type %d not supported!\n", type);
1201                 return 1;
1202
1203         }
1204
1205         if (type != NL80211_IFTYPE_AP &&
1206             rtlpriv->mac80211.link_state < MAC80211_LINKED)
1207                 bt_msr = rtl_read_byte(rtlpriv, MSR) & ~MSR_LINK_MASK;
1208         rtl_write_byte(rtlpriv, MSR, bt_msr);
1209
1210         temp = rtl_read_dword(rtlpriv, TCR);
1211         rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8)));
1212         rtl_write_dword(rtlpriv, TCR, temp | BIT(8));
1213
1214
1215         return 0;
1216 }
1217
1218 /* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */
1219 int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1220 {
1221         struct rtl_priv *rtlpriv = rtl_priv(hw);
1222
1223         if (_rtl92se_set_media_status(hw, type))
1224                 return -EOPNOTSUPP;
1225
1226         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1227                 if (type != NL80211_IFTYPE_AP)
1228                         rtl92se_set_check_bssid(hw, true);
1229         } else {
1230                 rtl92se_set_check_bssid(hw, false);
1231         }
1232
1233         return 0;
1234 }
1235
1236 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1237 void rtl92se_set_qos(struct ieee80211_hw *hw, int aci)
1238 {
1239         struct rtl_priv *rtlpriv = rtl_priv(hw);
1240         rtl92s_dm_init_edca_turbo(hw);
1241
1242         switch (aci) {
1243         case AC1_BK:
1244                 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f);
1245                 break;
1246         case AC0_BE:
1247                 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */
1248                 break;
1249         case AC2_VI:
1250                 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322);
1251                 break;
1252         case AC3_VO:
1253                 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222);
1254                 break;
1255         default:
1256                 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1257                 break;
1258         }
1259 }
1260
1261 void rtl92se_enable_interrupt(struct ieee80211_hw *hw)
1262 {
1263         struct rtl_priv *rtlpriv = rtl_priv(hw);
1264         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1265
1266         rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]);
1267         /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */
1268         rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F);
1269         rtlpci->irq_enabled = true;
1270 }
1271
1272 void rtl92se_disable_interrupt(struct ieee80211_hw *hw)
1273 {
1274         struct rtl_priv *rtlpriv;
1275         struct rtl_pci *rtlpci;
1276
1277         rtlpriv = rtl_priv(hw);
1278         /* if firmware not available, no interrupts */
1279         if (!rtlpriv || !rtlpriv->max_fw_size)
1280                 return;
1281         rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1282         rtl_write_dword(rtlpriv, INTA_MASK, 0);
1283         rtl_write_dword(rtlpriv, INTA_MASK + 4, 0);
1284         rtlpci->irq_enabled = false;
1285 }
1286
1287 static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data)
1288 {
1289         struct rtl_priv *rtlpriv = rtl_priv(hw);
1290         u8 waitcnt = 100;
1291         bool result = false;
1292         u8 tmp;
1293
1294         rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
1295
1296         /* Wait the MAC synchronized. */
1297         udelay(400);
1298
1299         /* Check if it is set ready. */
1300         tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1301         result = ((tmp & BIT(7)) == (data & BIT(7)));
1302
1303         if ((data & (BIT(6) | BIT(7))) == false) {
1304                 waitcnt = 100;
1305                 tmp = 0;
1306
1307                 while (1) {
1308                         waitcnt--;
1309                         tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1310
1311                         if ((tmp & BIT(6)))
1312                                 break;
1313
1314                         pr_err("wait for BIT(6) return value %x\n", tmp);
1315
1316                         if (waitcnt == 0)
1317                                 break;
1318                         udelay(10);
1319                 }
1320
1321                 if (waitcnt == 0)
1322                         result = false;
1323                 else
1324                         result = true;
1325         }
1326
1327         return result;
1328 }
1329
1330 static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
1331 {
1332         struct rtl_priv *rtlpriv = rtl_priv(hw);
1333         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1334         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1335         u8 u1btmp;
1336
1337         if (rtlhal->driver_going2unload)
1338                 rtl_write_byte(rtlpriv, 0x560, 0x0);
1339
1340         /* Power save for BB/RF */
1341         u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
1342         u1btmp |= BIT(0);
1343         rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
1344         rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
1345         rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
1346         rtl_write_word(rtlpriv, CMDR, 0x57FC);
1347         udelay(100);
1348         rtl_write_word(rtlpriv, CMDR, 0x77FC);
1349         rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
1350         udelay(10);
1351         rtl_write_word(rtlpriv, CMDR, 0x37FC);
1352         udelay(10);
1353         rtl_write_word(rtlpriv, CMDR, 0x77FC);
1354         udelay(10);
1355         rtl_write_word(rtlpriv, CMDR, 0x57FC);
1356         rtl_write_word(rtlpriv, CMDR, 0x0000);
1357
1358         if (rtlhal->driver_going2unload) {
1359                 u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1));
1360                 u1btmp &= ~(BIT(0));
1361                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp);
1362         }
1363
1364         u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1365
1366         /* Add description. After switch control path. register
1367          * after page1 will be invisible. We can not do any IO
1368          * for register>0x40. After resume&MACIO reset, we need
1369          * to remember previous reg content. */
1370         if (u1btmp & BIT(7)) {
1371                 u1btmp &= ~(BIT(6) | BIT(7));
1372                 if (!_rtl92s_set_sysclk(hw, u1btmp)) {
1373                         pr_err("Switch ctrl path fail\n");
1374                         return;
1375                 }
1376         }
1377
1378         /* Power save for MAC */
1379         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS  &&
1380                 !rtlhal->driver_going2unload) {
1381                 /* enable LED function */
1382                 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1383         /* SW/HW radio off or halt adapter!! For example S3/S4 */
1384         } else {
1385                 /* LED function disable. Power range is about 8mA now. */
1386                 /* if write 0xF1 disconnet_pci power
1387                  *       ifconfig wlan0 down power are both high 35:70 */
1388                 /* if write oxF9 disconnet_pci power
1389                  * ifconfig wlan0 down power are both low  12:45*/
1390                 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1391         }
1392
1393         rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70);
1394         rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68);
1395         rtl_write_byte(rtlpriv,  AFE_PLL_CTRL, 0x00);
1396         rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1397         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E);
1398         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1399
1400 }
1401
1402 static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw)
1403 {
1404         struct rtl_priv *rtlpriv = rtl_priv(hw);
1405         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1406         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1407         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
1408
1409         if (rtlpci->up_first_time == 1)
1410                 return;
1411
1412         if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS)
1413                 rtl92se_sw_led_on(hw, pLed0);
1414         else
1415                 rtl92se_sw_led_off(hw, pLed0);
1416 }
1417
1418
1419 static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
1420 {
1421         struct rtl_priv *rtlpriv = rtl_priv(hw);
1422         u16 tmpu2b;
1423         u8 tmpu1b;
1424
1425         rtlpriv->psc.pwrdomain_protect = true;
1426
1427         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1428         if (tmpu1b & BIT(7)) {
1429                 tmpu1b &= ~(BIT(6) | BIT(7));
1430                 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1431                         rtlpriv->psc.pwrdomain_protect = false;
1432                         return;
1433                 }
1434         }
1435
1436         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
1437         rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1438
1439         /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */
1440         tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1441
1442         /* If IPS we need to turn LED on. So we not
1443          * not disable BIT 3/7 of reg3. */
1444         if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW))
1445                 tmpu1b &= 0xFB;
1446         else
1447                 tmpu1b &= 0x73;
1448
1449         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
1450         /* wait for BIT 10/11/15 to pull high automatically!! */
1451         mdelay(1);
1452
1453         rtl_write_byte(rtlpriv, CMDR, 0);
1454         rtl_write_byte(rtlpriv, TCR, 0);
1455
1456         /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
1457         tmpu1b = rtl_read_byte(rtlpriv, 0x562);
1458         tmpu1b |= 0x08;
1459         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1460         tmpu1b &= ~(BIT(3));
1461         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1462
1463         /* Enable AFE clock source */
1464         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
1465         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
1466         /* Delay 1.5ms */
1467         udelay(1500);
1468         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
1469         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
1470
1471         /* Enable AFE Macro Block's Bandgap */
1472         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1473         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
1474         mdelay(1);
1475
1476         /* Enable AFE Mbias */
1477         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1478         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
1479         mdelay(1);
1480
1481         /* Enable LDOA15 block */
1482         tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
1483         rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
1484
1485         /* Set Digital Vdd to Retention isolation Path. */
1486         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
1487         rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
1488
1489
1490         /* For warm reboot NIC disappera bug. */
1491         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1492         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
1493
1494         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
1495
1496         /* Enable AFE PLL Macro Block */
1497         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
1498         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
1499         /* Enable MAC 80MHZ clock */
1500         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
1501         rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
1502         mdelay(1);
1503
1504         /* Release isolation AFE PLL & MD */
1505         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
1506
1507         /* Enable MAC clock */
1508         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1509         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
1510
1511         /* Enable Core digital and enable IOREG R/W */
1512         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1513         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
1514         /* enable REG_EN */
1515         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
1516
1517         /* Switch the control path. */
1518         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1519         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
1520
1521         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1522         tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
1523         if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1524                 rtlpriv->psc.pwrdomain_protect = false;
1525                 return;
1526         }
1527
1528         rtl_write_word(rtlpriv, CMDR, 0x37FC);
1529
1530         /* After MACIO reset,we must refresh LED state. */
1531         _rtl92se_gen_refreshledstate(hw);
1532
1533         rtlpriv->psc.pwrdomain_protect = false;
1534 }
1535
1536 void rtl92se_card_disable(struct ieee80211_hw *hw)
1537 {
1538         struct rtl_priv *rtlpriv = rtl_priv(hw);
1539         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1540         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1541         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1542         enum nl80211_iftype opmode;
1543         u8 wait = 30;
1544
1545         rtlpriv->intf_ops->enable_aspm(hw);
1546
1547         if (rtlpci->driver_is_goingto_unload ||
1548                 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1549                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1550
1551         /* we should chnge GPIO to input mode
1552          * this will drop away current about 25mA*/
1553         rtl8192se_gpiobit3_cfg_inputmode(hw);
1554
1555         /* this is very important for ips power save */
1556         while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) {
1557                 if (rtlpriv->psc.pwrdomain_protect)
1558                         mdelay(20);
1559                 else
1560                         break;
1561         }
1562
1563         mac->link_state = MAC80211_NOLINK;
1564         opmode = NL80211_IFTYPE_UNSPECIFIED;
1565         _rtl92se_set_media_status(hw, opmode);
1566
1567         _rtl92s_phy_set_rfhalt(hw);
1568         udelay(100);
1569 }
1570
1571 void rtl92se_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta,
1572                              u32 *p_intb)
1573 {
1574         struct rtl_priv *rtlpriv = rtl_priv(hw);
1575         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1576
1577         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1578         rtl_write_dword(rtlpriv, ISR, *p_inta);
1579
1580         *p_intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1];
1581         rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1582 }
1583
1584 void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw)
1585 {
1586         struct rtl_priv *rtlpriv = rtl_priv(hw);
1587         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1588         u16 bcntime_cfg = 0;
1589         u16 bcn_cw = 6, bcn_ifs = 0xf;
1590         u16 atim_window = 2;
1591
1592         /* ATIM Window (in unit of TU). */
1593         rtl_write_word(rtlpriv, ATIMWND, atim_window);
1594
1595         /* Beacon interval (in unit of TU). */
1596         rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval);
1597
1598         /* DrvErlyInt (in unit of TU). (Time to send
1599          * interrupt to notify driver to change
1600          * beacon content) */
1601         rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4);
1602
1603         /* BcnDMATIM(in unit of us). Indicates the
1604          * time before TBTT to perform beacon queue DMA  */
1605         rtl_write_word(rtlpriv, BCN_DMATIME, 256);
1606
1607         /* Force beacon frame transmission even
1608          * after receiving beacon frame from
1609          * other ad hoc STA */
1610         rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100);
1611
1612         /* Beacon Time Configuration */
1613         if (mac->opmode == NL80211_IFTYPE_ADHOC)
1614                 bcntime_cfg |= (bcn_cw << BCN_TCFG_CW_SHIFT);
1615
1616         /* TODO: bcn_ifs may required to be changed on ASIC */
1617         bcntime_cfg |= bcn_ifs << BCN_TCFG_IFS;
1618
1619         /*for beacon changed */
1620         rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval);
1621 }
1622
1623 void rtl92se_set_beacon_interval(struct ieee80211_hw *hw)
1624 {
1625         struct rtl_priv *rtlpriv = rtl_priv(hw);
1626         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1627         u16 bcn_interval = mac->beacon_interval;
1628
1629         /* Beacon interval (in unit of TU). */
1630         rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval);
1631         /* 2008.10.24 added by tynli for beacon changed. */
1632         rtl92s_phy_set_beacon_hwreg(hw, bcn_interval);
1633 }
1634
1635 void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw,
1636                 u32 add_msr, u32 rm_msr)
1637 {
1638         struct rtl_priv *rtlpriv = rtl_priv(hw);
1639         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1640
1641         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1642                  add_msr, rm_msr);
1643
1644         if (add_msr)
1645                 rtlpci->irq_mask[0] |= add_msr;
1646
1647         if (rm_msr)
1648                 rtlpci->irq_mask[0] &= (~rm_msr);
1649
1650         rtl92se_disable_interrupt(hw);
1651         rtl92se_enable_interrupt(hw);
1652 }
1653
1654 static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw *hw)
1655 {
1656         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1657         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1658         u8 efuse_id;
1659
1660         rtlhal->ic_class = IC_INFERIORITY_A;
1661
1662         /* Only retrieving while using EFUSE. */
1663         if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) &&
1664                 !rtlefuse->autoload_failflag) {
1665                 efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET);
1666
1667                 if (efuse_id == 0xfe)
1668                         rtlhal->ic_class = IC_INFERIORITY_B;
1669         }
1670 }
1671
1672 static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1673 {
1674         struct rtl_priv *rtlpriv = rtl_priv(hw);
1675         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1676         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1677         struct device *dev = &rtl_pcipriv(hw)->dev.pdev->dev;
1678         u16 i, usvalue;
1679         u16     eeprom_id;
1680         u8 tempval;
1681         u8 hwinfo[HWSET_MAX_SIZE_92S];
1682         u8 rf_path, index;
1683
1684         switch (rtlefuse->epromtype) {
1685         case EEPROM_BOOT_EFUSE:
1686                 rtl_efuse_shadow_map_update(hw);
1687                 break;
1688
1689         case EEPROM_93C46:
1690                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1691                          "RTL819X Not boot from eeprom, check it !!\n");
1692                 return;
1693
1694         default:
1695                 dev_warn(dev, "no efuse data\n");
1696                 return;
1697         }
1698
1699         memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1700                HWSET_MAX_SIZE_92S);
1701
1702         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
1703                       hwinfo, HWSET_MAX_SIZE_92S);
1704
1705         eeprom_id = *((u16 *)&hwinfo[0]);
1706         if (eeprom_id != RTL8190_EEPROM_ID) {
1707                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1708                          "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1709                 rtlefuse->autoload_failflag = true;
1710         } else {
1711                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1712                 rtlefuse->autoload_failflag = false;
1713         }
1714
1715         if (rtlefuse->autoload_failflag)
1716                 return;
1717
1718         _rtl8192se_get_IC_Inferiority(hw);
1719
1720         /* Read IC Version && Channel Plan */
1721         /* VID, DID      SE     0xA-D */
1722         rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1723         rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1724         rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1725         rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1726         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1727
1728         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1729                  "EEPROMId = 0x%4x\n", eeprom_id);
1730         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1731                  "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1732         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1733                  "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1734         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1735                  "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1736         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1737                  "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1738
1739         for (i = 0; i < 6; i += 2) {
1740                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1741                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1742         }
1743
1744         for (i = 0; i < 6; i++)
1745                 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1746
1747         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1748
1749         /* Get Tx Power Level by Channel */
1750         /* Read Tx power of Channel 1 ~ 14 from EEPROM. */
1751         /* 92S suupport RF A & B */
1752         for (rf_path = 0; rf_path < 2; rf_path++) {
1753                 for (i = 0; i < 3; i++) {
1754                         /* Read CCK RF A & B Tx power  */
1755                         rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1756                         hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i];
1757
1758                         /* Read OFDM RF A & B Tx power for 1T */
1759                         rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1760                         hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i];
1761
1762                         /* Read OFDM RF A & B Tx power for 2T */
1763                         rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path][i]
1764                                  = hwinfo[EEPROM_TXPOWERBASE + 12 +
1765                                    rf_path * 3 + i];
1766                 }
1767         }
1768
1769         for (rf_path = 0; rf_path < 2; rf_path++)
1770                 for (i = 0; i < 3; i++)
1771                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1772                                 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1773                                 rf_path, i,
1774                                 rtlefuse->eeprom_chnlarea_txpwr_cck
1775                                 [rf_path][i]);
1776         for (rf_path = 0; rf_path < 2; rf_path++)
1777                 for (i = 0; i < 3; i++)
1778                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1779                                 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1780                                 rf_path, i,
1781                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1782                                 [rf_path][i]);
1783         for (rf_path = 0; rf_path < 2; rf_path++)
1784                 for (i = 0; i < 3; i++)
1785                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1786                                 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1787                                 rf_path, i,
1788                                 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1789                                 [rf_path][i]);
1790
1791         for (rf_path = 0; rf_path < 2; rf_path++) {
1792
1793                 /* Assign dedicated channel tx power */
1794                 for (i = 0; i < 14; i++)        {
1795                         /* channel 1~3 use the same Tx Power Level. */
1796                         if (i < 3)
1797                                 index = 0;
1798                         /* Channel 4-8 */
1799                         else if (i < 8)
1800                                 index = 1;
1801                         /* Channel 9-14 */
1802                         else
1803                                 index = 2;
1804
1805                         /* Record A & B CCK /OFDM - 1T/2T Channel area
1806                          * tx power */
1807                         rtlefuse->txpwrlevel_cck[rf_path][i]  =
1808                                 rtlefuse->eeprom_chnlarea_txpwr_cck
1809                                                         [rf_path][index];
1810                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i]  =
1811                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1812                                                         [rf_path][index];
1813                         rtlefuse->txpwrlevel_ht40_2s[rf_path][i]  =
1814                                 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1815                                                         [rf_path][index];
1816                 }
1817
1818                 for (i = 0; i < 14; i++) {
1819                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1820                                 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1821                                 rf_path, i,
1822                                 rtlefuse->txpwrlevel_cck[rf_path][i],
1823                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1824                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1825                 }
1826         }
1827
1828         for (rf_path = 0; rf_path < 2; rf_path++) {
1829                 for (i = 0; i < 3; i++) {
1830                         /* Read Power diff limit. */
1831                         rtlefuse->eeprom_pwrgroup[rf_path][i] =
1832                                 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i];
1833                 }
1834         }
1835
1836         for (rf_path = 0; rf_path < 2; rf_path++) {
1837                 /* Fill Pwr group */
1838                 for (i = 0; i < 14; i++) {
1839                         /* Chanel 1-3 */
1840                         if (i < 3)
1841                                 index = 0;
1842                         /* Channel 4-8 */
1843                         else if (i < 8)
1844                                 index = 1;
1845                         /* Channel 9-13 */
1846                         else
1847                                 index = 2;
1848
1849                         rtlefuse->pwrgroup_ht20[rf_path][i] =
1850                                 (rtlefuse->eeprom_pwrgroup[rf_path][index] &
1851                                 0xf);
1852                         rtlefuse->pwrgroup_ht40[rf_path][i] =
1853                                 ((rtlefuse->eeprom_pwrgroup[rf_path][index] &
1854                                 0xf0) >> 4);
1855
1856                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1857                                 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1858                                 rf_path, i,
1859                                 rtlefuse->pwrgroup_ht20[rf_path][i]);
1860                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1861                                 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1862                                 rf_path, i,
1863                                 rtlefuse->pwrgroup_ht40[rf_path][i]);
1864                         }
1865         }
1866
1867         for (i = 0; i < 14; i++) {
1868                 /* Read tx power difference between HT OFDM 20/40 MHZ */
1869                 /* channel 1-3 */
1870                 if (i < 3)
1871                         index = 0;
1872                 /* Channel 4-8 */
1873                 else if (i < 8)
1874                         index = 1;
1875                 /* Channel 9-14 */
1876                 else
1877                         index = 2;
1878
1879                 tempval = hwinfo[EEPROM_TX_PWR_HT20_DIFF + index] & 0xff;
1880                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1881                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1882                                                  ((tempval >> 4) & 0xF);
1883
1884                 /* Read OFDM<->HT tx power diff */
1885                 /* Channel 1-3 */
1886                 if (i < 3)
1887                         index = 0;
1888                 /* Channel 4-8 */
1889                 else if (i < 8)
1890                         index = 0x11;
1891                 /* Channel 9-14 */
1892                 else
1893                         index = 1;
1894
1895                 tempval = hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index] & 0xff;
1896                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] =
1897                                  (tempval & 0xF);
1898                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1899                                  ((tempval >> 4) & 0xF);
1900
1901                 tempval = hwinfo[TX_PWR_SAFETY_CHK];
1902                 rtlefuse->txpwr_safetyflag = (tempval & 0x01);
1903         }
1904
1905         rtlefuse->eeprom_regulatory = 0;
1906         if (rtlefuse->eeprom_version >= 2) {
1907                 /* BIT(0)~2 */
1908                 if (rtlefuse->eeprom_version >= 4)
1909                         rtlefuse->eeprom_regulatory =
1910                                  (hwinfo[EEPROM_REGULATORY] & 0x7);
1911                 else /* BIT(0) */
1912                         rtlefuse->eeprom_regulatory =
1913                                  (hwinfo[EEPROM_REGULATORY] & 0x1);
1914         }
1915         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1916                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1917
1918         for (i = 0; i < 14; i++)
1919                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1920                         "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1921                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1922         for (i = 0; i < 14; i++)
1923                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1924                         "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1925                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1926         for (i = 0; i < 14; i++)
1927                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1928                         "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1929                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1930         for (i = 0; i < 14; i++)
1931                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1932                         "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1933                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1934
1935         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1936                 "TxPwrSafetyFlag = %d\n", rtlefuse->txpwr_safetyflag);
1937
1938         /* Read RF-indication and Tx Power gain
1939          * index diff of legacy to HT OFDM rate. */
1940         tempval = hwinfo[EEPROM_RFIND_POWERDIFF] & 0xff;
1941         rtlefuse->eeprom_txpowerdiff = tempval;
1942         rtlefuse->legacy_httxpowerdiff =
1943                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0];
1944
1945         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1946                 "TxPowerDiff = %#x\n", rtlefuse->eeprom_txpowerdiff);
1947
1948         /* Get TSSI value for each path. */
1949         usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A];
1950         rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8);
1951         usvalue = hwinfo[EEPROM_TSSI_B];
1952         rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff);
1953
1954         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1955                 rtlefuse->eeprom_tssi[RF90_PATH_A],
1956                 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1957
1958         /* Read antenna tx power offset of B/C/D to A  from EEPROM */
1959         /* and read ThermalMeter from EEPROM */
1960         tempval = hwinfo[EEPROM_THERMALMETER];
1961         rtlefuse->eeprom_thermalmeter = tempval;
1962         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1963                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1964
1965         /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */
1966         rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f);
1967         rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100;
1968
1969         /* Read CrystalCap from EEPROM */
1970         tempval = hwinfo[EEPROM_CRYSTALCAP] >> 4;
1971         rtlefuse->eeprom_crystalcap = tempval;
1972         /* CrystalCap, BIT(12)~15 */
1973         rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap;
1974
1975         /* Read IC Version && Channel Plan */
1976         /* Version ID, Channel plan */
1977         rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
1978         rtlefuse->txpwr_fromeprom = true;
1979         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1980                 "EEPROM ChannelPlan = 0x%4x\n", rtlefuse->eeprom_channelplan);
1981
1982         /* Read Customer ID or Board Type!!! */
1983         tempval = hwinfo[EEPROM_BOARDTYPE];
1984         /* Change RF type definition */
1985         if (tempval == 0)
1986                 rtlphy->rf_type = RF_2T2R;
1987         else if (tempval == 1)
1988                 rtlphy->rf_type = RF_1T2R;
1989         else if (tempval == 2)
1990                 rtlphy->rf_type = RF_1T2R;
1991         else if (tempval == 3)
1992                 rtlphy->rf_type = RF_1T1R;
1993
1994         /* 1T2R but 1SS (1x1 receive combining) */
1995         rtlefuse->b1x1_recvcombine = false;
1996         if (rtlphy->rf_type == RF_1T2R) {
1997                 tempval = rtl_read_byte(rtlpriv, 0x07);
1998                 if (!(tempval & BIT(0))) {
1999                         rtlefuse->b1x1_recvcombine = true;
2000                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2001                                  "RF_TYPE=1T2R but only 1SS\n");
2002                 }
2003         }
2004         rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine;
2005         rtlefuse->eeprom_oemid = *&hwinfo[EEPROM_CUSTOMID];
2006
2007         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n",
2008                  rtlefuse->eeprom_oemid);
2009
2010         /* set channel paln to world wide 13 */
2011         rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
2012 }
2013
2014 void rtl92se_read_eeprom_info(struct ieee80211_hw *hw)
2015 {
2016         struct rtl_priv *rtlpriv = rtl_priv(hw);
2017         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2018         u8 tmp_u1b = 0;
2019
2020         tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD);
2021
2022         if (tmp_u1b & BIT(4)) {
2023                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2024                 rtlefuse->epromtype = EEPROM_93C46;
2025         } else {
2026                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2027                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2028         }
2029
2030         if (tmp_u1b & BIT(5)) {
2031                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2032                 rtlefuse->autoload_failflag = false;
2033                 _rtl92se_read_adapter_info(hw);
2034         } else {
2035                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
2036                 rtlefuse->autoload_failflag = true;
2037         }
2038 }
2039
2040 static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw,
2041                                           struct ieee80211_sta *sta)
2042 {
2043         struct rtl_priv *rtlpriv = rtl_priv(hw);
2044         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2045         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2046         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2047         u32 ratr_value;
2048         u8 ratr_index = 0;
2049         u8 nmode = mac->ht_enable;
2050         u8 mimo_ps = IEEE80211_SMPS_OFF;
2051         u16 shortgi_rate = 0;
2052         u32 tmp_ratr_value = 0;
2053         u8 curtxbw_40mhz = mac->bw_40;
2054         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2055                                 1 : 0;
2056         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2057                                 1 : 0;
2058         enum wireless_mode wirelessmode = mac->mode;
2059
2060         if (rtlhal->current_bandtype == BAND_ON_5G)
2061                 ratr_value = sta->supp_rates[1] << 4;
2062         else
2063                 ratr_value = sta->supp_rates[0];
2064         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2065                 ratr_value = 0xfff;
2066         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2067                         sta->ht_cap.mcs.rx_mask[0] << 12);
2068         switch (wirelessmode) {
2069         case WIRELESS_MODE_B:
2070                 ratr_value &= 0x0000000D;
2071                 break;
2072         case WIRELESS_MODE_G:
2073                 ratr_value &= 0x00000FF5;
2074                 break;
2075         case WIRELESS_MODE_N_24G:
2076         case WIRELESS_MODE_N_5G:
2077                 nmode = 1;
2078                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2079                         ratr_value &= 0x0007F005;
2080                 } else {
2081                         u32 ratr_mask;
2082
2083                         if (get_rf_type(rtlphy) == RF_1T2R ||
2084                             get_rf_type(rtlphy) == RF_1T1R) {
2085                                 if (curtxbw_40mhz)
2086                                         ratr_mask = 0x000ff015;
2087                                 else
2088                                         ratr_mask = 0x000ff005;
2089                         } else {
2090                                 if (curtxbw_40mhz)
2091                                         ratr_mask = 0x0f0ff015;
2092                                 else
2093                                         ratr_mask = 0x0f0ff005;
2094                         }
2095
2096                         ratr_value &= ratr_mask;
2097                 }
2098                 break;
2099         default:
2100                 if (rtlphy->rf_type == RF_1T2R)
2101                         ratr_value &= 0x000ff0ff;
2102                 else
2103                         ratr_value &= 0x0f0ff0ff;
2104
2105                 break;
2106         }
2107
2108         if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2109                 ratr_value &= 0x0FFFFFFF;
2110         else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2111                 ratr_value &= 0x0FFFFFF0;
2112
2113         if (nmode && ((curtxbw_40mhz &&
2114                          curshortgi_40mhz) || (!curtxbw_40mhz &&
2115                                                  curshortgi_20mhz))) {
2116
2117                 ratr_value |= 0x10000000;
2118                 tmp_ratr_value = (ratr_value >> 12);
2119
2120                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2121                         if ((1 << shortgi_rate) & tmp_ratr_value)
2122                                 break;
2123                 }
2124
2125                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2126                     (shortgi_rate << 4) | (shortgi_rate);
2127
2128                 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2129         }
2130
2131         rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value);
2132         if (ratr_value & 0xfffff000)
2133                 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N);
2134         else
2135                 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG);
2136
2137         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2138                  rtl_read_dword(rtlpriv, ARFR0));
2139 }
2140
2141 static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw,
2142                                          struct ieee80211_sta *sta,
2143                                          u8 rssi_level)
2144 {
2145         struct rtl_priv *rtlpriv = rtl_priv(hw);
2146         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2147         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2148         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2149         struct rtl_sta_info *sta_entry = NULL;
2150         u32 ratr_bitmap;
2151         u8 ratr_index = 0;
2152         u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
2153         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2154                                 1 : 0;
2155         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2156                                 1 : 0;
2157         enum wireless_mode wirelessmode = 0;
2158         bool shortgi = false;
2159         u32 ratr_value = 0;
2160         u8 shortgi_rate = 0;
2161         u32 mask = 0;
2162         u32 band = 0;
2163         bool bmulticast = false;
2164         u8 macid = 0;
2165         u8 mimo_ps = IEEE80211_SMPS_OFF;
2166
2167         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2168         wirelessmode = sta_entry->wireless_mode;
2169         if (mac->opmode == NL80211_IFTYPE_STATION)
2170                 curtxbw_40mhz = mac->bw_40;
2171         else if (mac->opmode == NL80211_IFTYPE_AP ||
2172                 mac->opmode == NL80211_IFTYPE_ADHOC)
2173                 macid = sta->aid + 1;
2174
2175         if (rtlhal->current_bandtype == BAND_ON_5G)
2176                 ratr_bitmap = sta->supp_rates[1] << 4;
2177         else
2178                 ratr_bitmap = sta->supp_rates[0];
2179         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2180                 ratr_bitmap = 0xfff;
2181         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2182                         sta->ht_cap.mcs.rx_mask[0] << 12);
2183         switch (wirelessmode) {
2184         case WIRELESS_MODE_B:
2185                 band |= WIRELESS_11B;
2186                 ratr_index = RATR_INX_WIRELESS_B;
2187                 if (ratr_bitmap & 0x0000000c)
2188                         ratr_bitmap &= 0x0000000d;
2189                 else
2190                         ratr_bitmap &= 0x0000000f;
2191                 break;
2192         case WIRELESS_MODE_G:
2193                 band |= (WIRELESS_11G | WIRELESS_11B);
2194                 ratr_index = RATR_INX_WIRELESS_GB;
2195
2196                 if (rssi_level == 1)
2197                         ratr_bitmap &= 0x00000f00;
2198                 else if (rssi_level == 2)
2199                         ratr_bitmap &= 0x00000ff0;
2200                 else
2201                         ratr_bitmap &= 0x00000ff5;
2202                 break;
2203         case WIRELESS_MODE_A:
2204                 band |= WIRELESS_11A;
2205                 ratr_index = RATR_INX_WIRELESS_A;
2206                 ratr_bitmap &= 0x00000ff0;
2207                 break;
2208         case WIRELESS_MODE_N_24G:
2209         case WIRELESS_MODE_N_5G:
2210                 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2211                 ratr_index = RATR_INX_WIRELESS_NGB;
2212
2213                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2214                         if (rssi_level == 1)
2215                                 ratr_bitmap &= 0x00070000;
2216                         else if (rssi_level == 2)
2217                                 ratr_bitmap &= 0x0007f000;
2218                         else
2219                                 ratr_bitmap &= 0x0007f005;
2220                 } else {
2221                         if (rtlphy->rf_type == RF_1T2R ||
2222                                 rtlphy->rf_type == RF_1T1R) {
2223                                 if (rssi_level == 1) {
2224                                                 ratr_bitmap &= 0x000f0000;
2225                                 } else if (rssi_level == 3) {
2226                                         ratr_bitmap &= 0x000fc000;
2227                                 } else if (rssi_level == 5) {
2228                                                 ratr_bitmap &= 0x000ff000;
2229                                 } else {
2230                                         if (curtxbw_40mhz)
2231                                                 ratr_bitmap &= 0x000ff015;
2232                                         else
2233                                                 ratr_bitmap &= 0x000ff005;
2234                                 }
2235                         } else {
2236                                 if (rssi_level == 1) {
2237                                         ratr_bitmap &= 0x0f8f0000;
2238                                 } else if (rssi_level == 3) {
2239                                         ratr_bitmap &= 0x0f8fc000;
2240                                 } else if (rssi_level == 5) {
2241                                         ratr_bitmap &= 0x0f8ff000;
2242                                 } else {
2243                                         if (curtxbw_40mhz)
2244                                                 ratr_bitmap &= 0x0f8ff015;
2245                                         else
2246                                                 ratr_bitmap &= 0x0f8ff005;
2247                                 }
2248                         }
2249                 }
2250
2251                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2252                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2253                         if (macid == 0)
2254                                 shortgi = true;
2255                         else if (macid == 1)
2256                                 shortgi = false;
2257                 }
2258                 break;
2259         default:
2260                 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2261                 ratr_index = RATR_INX_WIRELESS_NGB;
2262
2263                 if (rtlphy->rf_type == RF_1T2R)
2264                         ratr_bitmap &= 0x000ff0ff;
2265                 else
2266                         ratr_bitmap &= 0x0f8ff0ff;
2267                 break;
2268         }
2269         sta_entry->ratr_index = ratr_index;
2270
2271         if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2272                 ratr_bitmap &= 0x0FFFFFFF;
2273         else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2274                 ratr_bitmap &= 0x0FFFFFF0;
2275
2276         if (shortgi) {
2277                 ratr_bitmap |= 0x10000000;
2278                 /* Get MAX MCS available. */
2279                 ratr_value = (ratr_bitmap >> 12);
2280                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2281                         if ((1 << shortgi_rate) & ratr_value)
2282                                 break;
2283                 }
2284
2285                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2286                         (shortgi_rate << 4) | (shortgi_rate);
2287                 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2288         }
2289
2290         mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf);
2291
2292         RT_TRACE(rtlpriv, COMP_RATR, DBG_TRACE, "mask = %x, bitmap = %x\n",
2293                  mask, ratr_bitmap);
2294         rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap);
2295         rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8)));
2296
2297         if (macid != 0)
2298                 sta_entry->ratr_index = ratr_index;
2299 }
2300
2301 void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw,
2302                 struct ieee80211_sta *sta, u8 rssi_level)
2303 {
2304         struct rtl_priv *rtlpriv = rtl_priv(hw);
2305
2306         if (rtlpriv->dm.useramask)
2307                 rtl92se_update_hal_rate_mask(hw, sta, rssi_level);
2308         else
2309                 rtl92se_update_hal_rate_table(hw, sta);
2310 }
2311
2312 void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw)
2313 {
2314         struct rtl_priv *rtlpriv = rtl_priv(hw);
2315         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2316         u16 sifs_timer;
2317
2318         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2319                                       &mac->slot_time);
2320         sifs_timer = 0x0e0e;
2321         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2322
2323 }
2324
2325 /* this ifunction is for RFKILL, it's different with windows,
2326  * because UI will disable wireless when GPIO Radio Off.
2327  * And here we not check or Disable/Enable ASPM like windows*/
2328 bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2329 {
2330         struct rtl_priv *rtlpriv = rtl_priv(hw);
2331         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2332         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2333         enum rf_pwrstate rfpwr_toset /*, cur_rfstate */;
2334         unsigned long flag = 0;
2335         bool actuallyset = false;
2336         bool turnonbypowerdomain = false;
2337
2338         /* just 8191se can check gpio before firstup, 92c/92d have fixed it */
2339         if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
2340                 return false;
2341
2342         if (ppsc->swrf_processing)
2343                 return false;
2344
2345         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2346         if (ppsc->rfchange_inprogress) {
2347                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2348                 return false;
2349         } else {
2350                 ppsc->rfchange_inprogress = true;
2351                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2352         }
2353
2354         /* cur_rfstate = ppsc->rfpwr_state;*/
2355
2356         /* because after _rtl92s_phy_set_rfhalt, all power
2357          * closed, so we must open some power for GPIO check,
2358          * or we will always check GPIO RFOFF here,
2359          * And we should close power after GPIO check */
2360         if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2361                 _rtl92se_power_domain_init(hw);
2362                 turnonbypowerdomain = true;
2363         }
2364
2365         rfpwr_toset = _rtl92se_rf_onoff_detect(hw);
2366
2367         if ((ppsc->hwradiooff) && (rfpwr_toset == ERFON)) {
2368                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2369                          "RFKILL-HW Radio ON, RF ON\n");
2370
2371                 rfpwr_toset = ERFON;
2372                 ppsc->hwradiooff = false;
2373                 actuallyset = true;
2374         } else if ((!ppsc->hwradiooff) && (rfpwr_toset == ERFOFF)) {
2375                 RT_TRACE(rtlpriv, COMP_RF,
2376                          DBG_DMESG, "RFKILL-HW Radio OFF, RF OFF\n");
2377
2378                 rfpwr_toset = ERFOFF;
2379                 ppsc->hwradiooff = true;
2380                 actuallyset = true;
2381         }
2382
2383         if (actuallyset) {
2384                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2385                 ppsc->rfchange_inprogress = false;
2386                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2387
2388         /* this not include ifconfig wlan0 down case */
2389         /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */
2390         } else {
2391                 /* because power_domain_init may be happen when
2392                  * _rtl92s_phy_set_rfhalt, this will open some powers
2393                  * and cause current increasing about 40 mA for ips,
2394                  * rfoff and ifconfig down, so we set
2395                  * _rtl92s_phy_set_rfhalt again here */
2396                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC &&
2397                         turnonbypowerdomain) {
2398                         _rtl92s_phy_set_rfhalt(hw);
2399                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2400                 }
2401
2402                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2403                 ppsc->rfchange_inprogress = false;
2404                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2405         }
2406
2407         *valid = 1;
2408         return !ppsc->hwradiooff;
2409
2410 }
2411
2412 /* Is_wepkey just used for WEP used as group & pairwise key
2413  * if pairwise is AES ang group is WEP Is_wepkey == false.*/
2414 void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
2415         bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all)
2416 {
2417         struct rtl_priv *rtlpriv = rtl_priv(hw);
2418         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2419         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2420         u8 *macaddr = p_macaddr;
2421
2422         u32 entry_id = 0;
2423         bool is_pairwise = false;
2424
2425         static u8 cam_const_addr[4][6] = {
2426                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2427                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2428                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2429                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2430         };
2431         static u8 cam_const_broad[] = {
2432                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2433         };
2434
2435         if (clear_all) {
2436                 u8 idx = 0;
2437                 u8 cam_offset = 0;
2438                 u8 clear_number = 5;
2439
2440                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2441
2442                 for (idx = 0; idx < clear_number; idx++) {
2443                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2444                         rtl_cam_empty_entry(hw, cam_offset + idx);
2445
2446                         if (idx < 5) {
2447                                 memset(rtlpriv->sec.key_buf[idx], 0,
2448                                        MAX_KEY_LEN);
2449                                 rtlpriv->sec.key_len[idx] = 0;
2450                         }
2451                 }
2452
2453         } else {
2454                 switch (enc_algo) {
2455                 case WEP40_ENCRYPTION:
2456                         enc_algo = CAM_WEP40;
2457                         break;
2458                 case WEP104_ENCRYPTION:
2459                         enc_algo = CAM_WEP104;
2460                         break;
2461                 case TKIP_ENCRYPTION:
2462                         enc_algo = CAM_TKIP;
2463                         break;
2464                 case AESCCMP_ENCRYPTION:
2465                         enc_algo = CAM_AES;
2466                         break;
2467                 default:
2468                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2469                                  "switch case %#x not processed\n", enc_algo);
2470                         enc_algo = CAM_TKIP;
2471                         break;
2472                 }
2473
2474                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2475                         macaddr = cam_const_addr[key_index];
2476                         entry_id = key_index;
2477                 } else {
2478                         if (is_group) {
2479                                 macaddr = cam_const_broad;
2480                                 entry_id = key_index;
2481                         } else {
2482                                 if (mac->opmode == NL80211_IFTYPE_AP) {
2483                                         entry_id = rtl_cam_get_free_entry(hw,
2484                                                                  p_macaddr);
2485                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2486                                                 RT_TRACE(rtlpriv,
2487                                                          COMP_SEC, DBG_EMERG,
2488                                                          "Can not find free hw security cam entry\n");
2489                                                 return;
2490                                         }
2491                                 } else {
2492                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2493                                 }
2494
2495                                 key_index = PAIRWISE_KEYIDX;
2496                                 is_pairwise = true;
2497                         }
2498                 }
2499
2500                 if (rtlpriv->sec.key_len[key_index] == 0) {
2501                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2502                                  "delete one entry, entry_id is %d\n",
2503                                  entry_id);
2504                         if (mac->opmode == NL80211_IFTYPE_AP)
2505                                 rtl_cam_del_entry(hw, p_macaddr);
2506                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2507                 } else {
2508                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2509                                  "add one entry\n");
2510                         if (is_pairwise) {
2511                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2512                                          "set Pairwise key\n");
2513
2514                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2515                                         entry_id, enc_algo,
2516                                         CAM_CONFIG_NO_USEDK,
2517                                         rtlpriv->sec.key_buf[key_index]);
2518                         } else {
2519                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2520                                          "set group key\n");
2521
2522                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2523                                         rtl_cam_add_one_entry(hw,
2524                                                 rtlefuse->dev_addr,
2525                                                 PAIRWISE_KEYIDX,
2526                                                 CAM_PAIRWISE_KEY_POSITION,
2527                                                 enc_algo, CAM_CONFIG_NO_USEDK,
2528                                                 rtlpriv->sec.key_buf[entry_id]);
2529                                 }
2530
2531                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2532                                               entry_id, enc_algo,
2533                                               CAM_CONFIG_NO_USEDK,
2534                                               rtlpriv->sec.key_buf[entry_id]);
2535                         }
2536
2537                 }
2538         }
2539 }
2540
2541 void rtl92se_suspend(struct ieee80211_hw *hw)
2542 {
2543         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2544
2545         rtlpci->up_first_time = true;
2546 }
2547
2548 void rtl92se_resume(struct ieee80211_hw *hw)
2549 {
2550         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2551         u32 val;
2552
2553         pci_read_config_dword(rtlpci->pdev, 0x40, &val);
2554         if ((val & 0x0000ff00) != 0)
2555                 pci_write_config_dword(rtlpci->pdev, 0x40,
2556                         val & 0xffff00ff);
2557 }