1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
45 void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
47 struct rtl_priv *rtlpriv = rtl_priv(hw);
48 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
53 *((u32 *) (val)) = rtlpci->receive_config;
56 case HW_VAR_RF_STATE: {
57 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
60 case HW_VAR_FW_PSMODE_STATUS: {
61 *((bool *) (val)) = ppsc->fw_current_inpsmode;
64 case HW_VAR_CORRECT_TSF: {
66 u32 *ptsf_low = (u32 *)&tsf;
67 u32 *ptsf_high = ((u32 *)&tsf) + 1;
69 *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4));
70 *ptsf_low = rtl_read_dword(rtlpriv, TSFR);
72 *((u64 *) (val)) = tsf;
77 *((bool *)(val)) = rtlpriv->dm.current_mrc_switch;
81 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
82 "switch case not processed\n");
88 void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
90 struct rtl_priv *rtlpriv = rtl_priv(hw);
91 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
92 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
93 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
94 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
95 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
98 case HW_VAR_ETHER_ADDR:{
99 rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]);
100 rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]);
103 case HW_VAR_BASIC_RATE:{
104 u16 rate_cfg = ((u16 *) val)[0];
107 if (rtlhal->version == VERSION_8192S_ACUT)
108 rate_cfg = rate_cfg & 0x150;
110 rate_cfg = rate_cfg & 0x15f;
114 rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff);
115 rtl_write_byte(rtlpriv, RRSR + 1,
116 (rate_cfg >> 8) & 0xff);
118 while (rate_cfg > 0x1) {
119 rate_cfg = (rate_cfg >> 1);
122 rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index);
127 rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]);
128 rtl_write_word(rtlpriv, BSSIDR + 4,
129 ((u16 *)(val + 4))[0]);
133 rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]);
134 rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]);
137 case HW_VAR_SLOT_TIME:{
140 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
141 "HW_VAR_SLOT_TIME %x\n", val[0]);
143 rtl_write_byte(rtlpriv, SLOT_TIME, val[0]);
145 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
146 rtlpriv->cfg->ops->set_hw_reg(hw,
152 case HW_VAR_ACK_PREAMBLE:{
154 u8 short_preamble = (bool) (*val);
155 reg_tmp = (mac->cur_40_prime_sc) << 5;
159 rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp);
162 case HW_VAR_AMPDU_MIN_SPACE:{
163 u8 min_spacing_to_set;
166 min_spacing_to_set = *val;
167 if (min_spacing_to_set <= 7) {
168 if (rtlpriv->sec.pairwise_enc_algorithm ==
174 if (min_spacing_to_set < sec_min_space)
175 min_spacing_to_set = sec_min_space;
176 if (min_spacing_to_set > 5)
177 min_spacing_to_set = 5;
180 ((mac->min_space_cfg & 0xf8) |
183 *val = min_spacing_to_set;
185 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
186 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
189 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
194 case HW_VAR_SHORTGI_DENSITY:{
197 density_to_set = *val;
198 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
199 mac->min_space_cfg |= (density_to_set << 3);
201 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
202 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
205 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
210 case HW_VAR_AMPDU_FACTOR:{
213 u8 factorlevel[18] = {
214 2, 4, 4, 7, 7, 13, 13,
220 if (factor_toset <= 3) {
221 factor_toset = (1 << (factor_toset + 2));
222 if (factor_toset > 0xf)
225 for (index = 0; index < 17; index++) {
226 if (factorlevel[index] > factor_toset)
231 for (index = 0; index < 8; index++) {
232 regtoset = ((factorlevel[index * 2]) |
235 rtl_write_byte(rtlpriv,
236 AGGLEN_LMT_L + index,
240 regtoset = ((factorlevel[16]) |
241 (factorlevel[17] << 4));
242 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset);
244 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
245 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
250 case HW_VAR_AC_PARAM:{
252 rtl92s_dm_init_edca_turbo(hw);
254 if (rtlpci->acm_method != EACMWAY2_SW)
255 rtlpriv->cfg->ops->set_hw_reg(hw,
260 case HW_VAR_ACM_CTRL:{
262 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&(
264 u8 acm = p_aci_aifsn->f.acm;
265 u8 acm_ctrl = rtl_read_byte(rtlpriv, AcmHwCtrl);
267 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?
273 acm_ctrl |= AcmHw_BeqEn;
276 acm_ctrl |= AcmHw_ViqEn;
279 acm_ctrl |= AcmHw_VoqEn;
282 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
283 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
290 acm_ctrl &= (~AcmHw_BeqEn);
293 acm_ctrl &= (~AcmHw_ViqEn);
296 acm_ctrl &= (~AcmHw_VoqEn);
299 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
300 "switch case not processed\n");
305 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
306 "HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl);
307 rtl_write_byte(rtlpriv, AcmHwCtrl, acm_ctrl);
311 rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]);
312 rtlpci->receive_config = ((u32 *) (val))[0];
315 case HW_VAR_RETRY_LIMIT:{
316 u8 retry_limit = val[0];
318 rtl_write_word(rtlpriv, RETRY_LIMIT,
319 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
320 retry_limit << RETRY_LIMIT_LONG_SHIFT);
323 case HW_VAR_DUAL_TSF_RST: {
326 case HW_VAR_EFUSE_BYTES: {
327 rtlefuse->efuse_usedbytes = *((u16 *) val);
330 case HW_VAR_EFUSE_USAGE: {
331 rtlefuse->efuse_usedpercentage = *val;
334 case HW_VAR_IO_CMD: {
337 case HW_VAR_WPA_CONFIG: {
338 rtl_write_byte(rtlpriv, REG_SECR, *val);
341 case HW_VAR_SET_RPWM:{
344 case HW_VAR_H2C_FW_PWRMODE:{
347 case HW_VAR_FW_PSMODE_STATUS: {
348 ppsc->fw_current_inpsmode = *((bool *) val);
351 case HW_VAR_H2C_FW_JOINBSSRPT:{
357 case HW_VAR_CORRECT_TSF:{
361 bool bmrc_toset = *((bool *)val);
365 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
367 u1bdata = (u8)rtl_get_bbreg(hw,
368 ROFDM1_TRXPATHENABLE,
370 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
372 ((u1bdata & 0xf0) | 0x03));
373 u1bdata = (u8)rtl_get_bbreg(hw,
374 ROFDM0_TRXPATHENABLE,
376 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
380 /* Update current settings. */
381 rtlpriv->dm.current_mrc_switch = bmrc_toset;
383 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
385 u1bdata = (u8)rtl_get_bbreg(hw,
386 ROFDM1_TRXPATHENABLE,
388 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
390 ((u1bdata & 0xf0) | 0x01));
391 u1bdata = (u8)rtl_get_bbreg(hw,
392 ROFDM0_TRXPATHENABLE,
394 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
395 MASKBYTE1, (u1bdata & 0xfb));
397 /* Update current settings. */
398 rtlpriv->dm.current_mrc_switch = bmrc_toset;
403 case HW_VAR_FW_LPS_ACTION: {
404 bool enter_fwlps = *((bool *)val);
405 u8 rpwm_val, fw_pwrmode;
406 bool fw_current_inps;
409 rpwm_val = 0x02; /* RF off */
410 fw_current_inps = true;
411 rtlpriv->cfg->ops->set_hw_reg(hw,
412 HW_VAR_FW_PSMODE_STATUS,
413 (u8 *)(&fw_current_inps));
414 rtlpriv->cfg->ops->set_hw_reg(hw,
415 HW_VAR_H2C_FW_PWRMODE,
416 &ppsc->fwctrl_psmode);
418 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
421 rpwm_val = 0x0C; /* RF on */
422 fw_pwrmode = FW_PS_ACTIVE_MODE;
423 fw_current_inps = false;
424 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
426 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
429 rtlpriv->cfg->ops->set_hw_reg(hw,
430 HW_VAR_FW_PSMODE_STATUS,
431 (u8 *)(&fw_current_inps));
435 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
436 "switch case not processed\n");
442 void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw)
444 struct rtl_priv *rtlpriv = rtl_priv(hw);
445 u8 sec_reg_value = 0x0;
447 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
448 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
449 rtlpriv->sec.pairwise_enc_algorithm,
450 rtlpriv->sec.group_enc_algorithm);
452 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
453 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
454 "not open hw encryption\n");
458 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
460 if (rtlpriv->sec.use_defaultkey) {
461 sec_reg_value |= SCR_TXUSEDK;
462 sec_reg_value |= SCR_RXUSEDK;
465 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
468 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
472 static u8 _rtl92se_halset_sysclk(struct ieee80211_hw *hw, u8 data)
474 struct rtl_priv *rtlpriv = rtl_priv(hw);
476 bool bresult = false;
479 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
481 /* Wait the MAC synchronized. */
484 /* Check if it is set ready. */
485 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
486 bresult = ((tmpvalue & BIT(7)) == (data & BIT(7)));
488 if ((data & (BIT(6) | BIT(7))) == false) {
495 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
496 if ((tmpvalue & BIT(6)))
499 pr_err("wait for BIT(6) return value %x\n", tmpvalue);
515 void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw)
517 struct rtl_priv *rtlpriv = rtl_priv(hw);
520 /* The following config GPIO function */
521 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
522 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
524 /* config GPIO3 to input */
525 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
526 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
530 static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw)
532 struct rtl_priv *rtlpriv = rtl_priv(hw);
536 /* The following config GPIO function */
537 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
538 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
540 /* config GPIO3 to input */
541 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
542 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
544 /* On some of the platform, driver cannot read correct
545 * value without delay between Write_GPIO_SEL and Read_GPIO_IN */
549 u1tmp = rtl_read_byte(rtlpriv, GPIO_IN_SE);
550 retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF;
555 static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw)
557 struct rtl_priv *rtlpriv = rtl_priv(hw);
558 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
559 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
566 if (rtlpci->first_init) {
567 /* Reset PCIE Digital */
568 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
570 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
572 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0));
575 /* Switch to SW IO control */
576 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
577 if (tmpu1b & BIT(7)) {
578 tmpu1b &= ~(BIT(6) | BIT(7));
580 /* Set failed, return to prevent hang. */
581 if (!_rtl92se_halset_sysclk(hw, tmpu1b))
585 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
587 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
590 /* Clear FW RPWM for FW control LPS.*/
591 rtl_write_byte(rtlpriv, RPWM, 0x0);
593 /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */
594 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
596 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
597 /* wait for BIT 10/11/15 to pull high automatically!! */
600 rtl_write_byte(rtlpriv, CMDR, 0);
601 rtl_write_byte(rtlpriv, TCR, 0);
603 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
604 tmpu1b = rtl_read_byte(rtlpriv, 0x562);
606 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
608 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
610 /* Enable AFE clock source */
611 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
612 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
615 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
616 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
618 /* Enable AFE Macro Block's Bandgap */
619 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
620 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
623 /* Enable AFE Mbias */
624 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
625 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
628 /* Enable LDOA15 block */
629 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
630 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
632 /* Set Digital Vdd to Retention isolation Path. */
633 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
634 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
636 /* For warm reboot NIC disappera bug. */
637 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
638 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
640 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
642 /* Enable AFE PLL Macro Block */
643 /* We need to delay 100u before enabling PLL. */
645 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
646 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
648 /* for divider reset */
650 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) |
653 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
656 /* Enable MAC 80MHZ clock */
657 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
658 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
661 /* Release isolation AFE PLL & MD */
662 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
664 /* Enable MAC clock */
665 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
666 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
668 /* Enable Core digital and enable IOREG R/W */
669 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
670 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
672 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
673 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7)));
676 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
678 /* Switch the control path. */
679 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
680 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
682 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
683 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
684 if (!_rtl92se_halset_sysclk(hw, tmpu1b))
685 return; /* Set failed, return to prevent hang. */
687 rtl_write_word(rtlpriv, CMDR, 0x07FC);
689 /* MH We must enable the section of code to prevent load IMEM fail. */
690 /* Load MAC register from WMAc temporarily We simulate macreg. */
691 /* txt HW will provide MAC txt later */
692 rtl_write_byte(rtlpriv, 0x6, 0x30);
693 rtl_write_byte(rtlpriv, 0x49, 0xf0);
695 rtl_write_byte(rtlpriv, 0x4b, 0x81);
697 rtl_write_byte(rtlpriv, 0xb5, 0x21);
699 rtl_write_byte(rtlpriv, 0xdc, 0xff);
700 rtl_write_byte(rtlpriv, 0xdd, 0xff);
701 rtl_write_byte(rtlpriv, 0xde, 0xff);
702 rtl_write_byte(rtlpriv, 0xdf, 0xff);
704 rtl_write_byte(rtlpriv, 0x11a, 0x00);
705 rtl_write_byte(rtlpriv, 0x11b, 0x00);
707 for (i = 0; i < 32; i++)
708 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b);
710 rtl_write_byte(rtlpriv, 0x236, 0xff);
712 rtl_write_byte(rtlpriv, 0x503, 0x22);
714 if (ppsc->support_aspm && !ppsc->support_backdoor)
715 rtl_write_byte(rtlpriv, 0x560, 0x40);
717 rtl_write_byte(rtlpriv, 0x560, 0x00);
719 rtl_write_byte(rtlpriv, DBG_PORT, 0x91);
721 /* Set RX Desc Address */
722 rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
723 rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma);
725 /* Set TX Desc Address */
726 rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma);
727 rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma);
728 rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma);
729 rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma);
730 rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma);
731 rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma);
732 rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma);
733 rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma);
734 rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma);
736 rtl_write_word(rtlpriv, CMDR, 0x37FC);
738 /* To make sure that TxDMA can ready to download FW. */
739 /* We should reset TxDMA if IMEM RPT was not ready. */
741 tmpu1b = rtl_read_byte(rtlpriv, TCR);
742 if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
746 } while (pollingcnt--);
748 if (pollingcnt <= 0) {
749 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
750 "Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n",
752 tmpu1b = rtl_read_byte(rtlpriv, CMDR);
753 rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN));
756 rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN);
759 /* After MACIO reset,we must refresh LED state. */
760 if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) ||
761 (ppsc->rfoff_reason == 0)) {
762 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
763 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
764 enum rf_pwrstate rfpwr_state_toset;
765 rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw);
767 if (rfpwr_state_toset == ERFON)
768 rtl92se_sw_led_on(hw, pLed0);
772 static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw)
774 struct rtl_priv *rtlpriv = rtl_priv(hw);
775 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
776 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
777 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
781 /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */
783 /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */
784 /* Turn on 0x40 Command register */
785 rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN |
786 SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN |
787 RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN));
789 /* Set TCR TX DMA pre 2 FULL enable bit */
790 rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) |
794 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
796 /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */
798 /* 4. Timing Control Register (Offset: 0x0080 - 0x009F) */
799 /* Set CCK/OFDM SIFS */
800 /* CCK SIFS shall always be 10us. */
801 rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a);
802 rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010);
805 rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40);
808 rtl_write_word(rtlpriv, BCN_INTERVAL, 100);
809 rtl_write_word(rtlpriv, ATIMWND, 2);
811 /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */
812 /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */
813 /* Firmware allocate now, associate with FW internal setting.!!! */
815 /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */
816 /* 5.3 Set driver info, we only accept PHY status now. */
817 /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO */
818 rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6));
820 /* 6. Adaptive Control Register (Offset: 0x0160 - 0x01CF) */
821 /* Set RRSR to all legacy rate and HT rate
822 * CCK rate is supported by default.
823 * CCK rate will be filtered out only when associated
824 * AP does not support it.
825 * Only enable ACK rate to OFDM 24M
826 * Disable RRSR for CCK rate in A-Cut */
828 if (rtlhal->version == VERSION_8192S_ACUT)
829 rtl_write_byte(rtlpriv, RRSR, 0xf0);
830 else if (rtlhal->version == VERSION_8192S_BCUT)
831 rtl_write_byte(rtlpriv, RRSR, 0xff);
832 rtl_write_byte(rtlpriv, RRSR + 1, 0x01);
833 rtl_write_byte(rtlpriv, RRSR + 2, 0x00);
835 /* A-Cut IC do not support CCK rate. We forbid ARFR to */
836 /* fallback to CCK rate */
837 for (i = 0; i < 8; i++) {
838 /*Disable RRSR for CCK rate in A-Cut */
839 if (rtlhal->version == VERSION_8192S_ACUT)
840 rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0);
843 /* Different rate use different AMPDU size */
844 /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */
845 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f);
846 /* MCS0/1/2/3 use max AMPDU size 4*2=8K */
847 rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442);
848 /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */
849 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7);
850 /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */
851 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772);
852 /* MCS12/13/14/15 use max AMPDU size 15*2=30K */
853 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd);
855 /* Set Data / Response auto rate fallack retry count */
856 rtl_write_dword(rtlpriv, DARFRC, 0x04010000);
857 rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605);
858 rtl_write_dword(rtlpriv, RARFRC, 0x04010000);
859 rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605);
861 /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */
862 /* Set all rate to support SG */
863 rtl_write_word(rtlpriv, SG_RATE, 0xFFFF);
865 /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */
866 /* Set NAV protection length */
867 rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080);
868 /* CF-END Threshold */
869 rtl_write_byte(rtlpriv, CFEND_TH, 0xFF);
870 /* Set AMPDU minimum space */
871 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07);
872 /* Set TXOP stall control for several queue/HI/BCN/MGT/ */
873 rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00);
875 /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */
876 /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */
877 /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */
878 /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */
879 /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */
881 /* 14. Set driver info, we only accept PHY status now. */
882 rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4);
884 /* 15. For EEPROM R/W Workaround */
885 /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */
886 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
887 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13));
888 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
889 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8)));
892 /* We may R/W EFUSE in EEPROM mode */
893 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
896 tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1);
898 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval);
900 /* Change Program timing */
901 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72);
902 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "EFUSE CONFIG OK\n");
905 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
909 static void _rtl92se_hw_configure(struct ieee80211_hw *hw)
911 struct rtl_priv *rtlpriv = rtl_priv(hw);
912 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
913 struct rtl_phy *rtlphy = &(rtlpriv->phy);
914 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
916 u8 reg_bw_opmode = 0;
920 reg_bw_opmode = BW_OPMODE_20MHZ;
921 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
923 regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL);
924 reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp;
925 rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr);
926 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
928 /* Set Retry Limit here */
929 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
930 (u8 *)(&rtlpci->shortretry_limit));
932 rtl_write_byte(rtlpriv, MLT, 0x8f);
934 /* For Min Spacing configuration. */
935 switch (rtlphy->rf_type) {
938 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
942 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
945 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg);
948 int rtl92se_hw_init(struct ieee80211_hw *hw)
950 struct rtl_priv *rtlpriv = rtl_priv(hw);
951 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
952 struct rtl_phy *rtlphy = &(rtlpriv->phy);
953 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
954 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
957 bool rtstatus = true;
961 int wdcapra_add[] = {
962 EDCAPARA_BE, EDCAPARA_BK,
963 EDCAPARA_VI, EDCAPARA_VO};
966 rtlpci->being_init_adapter = true;
968 /* As this function can take a very long time (up to 350 ms)
969 * and can be called with irqs disabled, reenable the irqs
970 * to let the other devices continue being serviced.
972 * It is safe doing so since our own interrupts will only be enabled
973 * in a subsequent step.
975 local_save_flags(flags);
978 rtlpriv->intf_ops->disable_aspm(hw);
980 /* 1. MAC Initialize */
981 /* Before FW download, we have to set some MAC register */
982 _rtl92se_macconfig_before_fwdownload(hw);
984 rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv,
985 PMC_FSM) >> 16) & 0xF);
987 rtl8192se_gpiobit3_cfg_inputmode(hw);
989 /* 2. download firmware */
990 rtstatus = rtl92s_download_fw(hw);
992 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
993 "Failed to download FW. Init HW without FW now... "
994 "Please copy FW into /lib/firmware/rtlwifi\n");
999 /* After FW download, we have to reset MAC register */
1000 _rtl92se_macconfig_after_fwdownload(hw);
1002 /*Retrieve default FW Cmd IO map. */
1003 rtlhal->fwcmd_iomap = rtl_read_word(rtlpriv, LBUS_MON_ADDR);
1004 rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK);
1006 /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */
1007 if (!rtl92s_phy_mac_config(hw)) {
1008 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "MAC Config failed\n");
1013 /* because last function modify RCR, so we update
1014 * rcr var here, or TP will unstable for receive_config
1015 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1016 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1018 rtlpci->receive_config = rtl_read_dword(rtlpriv, RCR);
1019 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1020 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
1022 /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */
1023 /* We must set flag avoid BB/RF config period later!! */
1024 rtl_write_dword(rtlpriv, CMDR, 0x37FC);
1026 /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */
1027 if (!rtl92s_phy_bb_config(hw)) {
1028 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "BB Config failed\n");
1033 /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */
1034 /* Before initalizing RF. We can not use FW to do RF-R/W. */
1036 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1038 /* Before RF-R/W we must execute the IO from Scott's suggestion. */
1039 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB);
1040 if (rtlhal->version == VERSION_8192S_ACUT)
1041 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07);
1043 rtl_write_byte(rtlpriv, RF_CTRL, 0x07);
1045 if (!rtl92s_phy_rf_config(hw)) {
1046 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RF Config failed\n");
1051 /* After read predefined TXT, we must set BB/MAC/RF
1052 * register as our requirement */
1054 rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw,
1058 rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw,
1063 /*---- Set CCK and OFDM Block "ON"----*/
1064 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1065 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1067 /*3 Set Hardware(Do nothing now) */
1068 _rtl92se_hw_configure(hw);
1070 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1071 /* TX power index for different rate set. */
1072 /* Get original hw reg values */
1073 rtl92s_phy_get_hw_reg_originalvalue(hw);
1074 /* Write correct tx power index */
1075 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1077 /* We must set MAC address after firmware download. */
1078 for (i = 0; i < 6; i++)
1079 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1081 /* EEPROM R/W workaround */
1082 tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG);
1083 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3)));
1085 rtl_write_byte(rtlpriv, 0x4d, 0x0);
1087 if (hal_get_firmwareversion(rtlpriv) >= 0x49) {
1088 tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4));
1089 tmp_byte = tmp_byte | BIT(5);
1090 rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte);
1091 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF);
1094 /* We enable high power and RA related mechanism after NIC
1096 if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
1097 /* Fw v.53 and later. */
1098 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT);
1099 } else if (hal_get_firmwareversion(rtlpriv) == 0x34) {
1101 rtl_write_dword(rtlpriv, WFM5, FW_RA_INIT);
1102 rtl92s_phy_chk_fwcmd_iodone(hw);
1104 /* Compatible earlier FW version. */
1105 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
1106 rtl92s_phy_chk_fwcmd_iodone(hw);
1107 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
1108 rtl92s_phy_chk_fwcmd_iodone(hw);
1109 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
1110 rtl92s_phy_chk_fwcmd_iodone(hw);
1113 /* Add to prevent ASPM bug. */
1114 /* Always enable hst and NIC clock request. */
1115 rtl92s_phy_switch_ephy_parameter(hw);
1118 * 1. Clear all H/W keys.
1119 * 2. Enable H/W encryption/decryption. */
1120 rtl_cam_reset_all_entry(hw);
1121 secr_value |= SCR_TXENCENABLE;
1122 secr_value |= SCR_RXENCENABLE;
1123 secr_value |= SCR_NOSKMC;
1124 rtl_write_byte(rtlpriv, REG_SECR, secr_value);
1126 for (i = 0; i < 4; i++)
1127 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322);
1129 if (rtlphy->rf_type == RF_1T2R) {
1130 bool mrc2set = true;
1131 /* Turn on B-Path */
1132 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set);
1135 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON);
1138 local_irq_restore(flags);
1139 rtlpci->being_init_adapter = false;
1143 void rtl92se_set_mac_addr(struct rtl_io *io, const u8 *addr)
1145 /* This is a stub. */
1148 void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1150 struct rtl_priv *rtlpriv = rtl_priv(hw);
1153 if (rtlpriv->psc.rfpwr_state != ERFON)
1156 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1159 reg_rcr |= (RCR_CBSSID);
1160 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1161 } else if (!check_bssid) {
1162 reg_rcr &= (~RCR_CBSSID);
1163 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1168 static int _rtl92se_set_media_status(struct ieee80211_hw *hw,
1169 enum nl80211_iftype type)
1171 struct rtl_priv *rtlpriv = rtl_priv(hw);
1172 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1174 bt_msr &= ~MSR_LINK_MASK;
1177 case NL80211_IFTYPE_UNSPECIFIED:
1178 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
1179 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1180 "Set Network type to NO LINK!\n");
1182 case NL80211_IFTYPE_ADHOC:
1183 bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
1184 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1185 "Set Network type to Ad Hoc!\n");
1187 case NL80211_IFTYPE_STATION:
1188 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
1189 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1190 "Set Network type to STA!\n");
1192 case NL80211_IFTYPE_AP:
1193 bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
1194 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1195 "Set Network type to AP!\n");
1198 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1199 "Network type %d not supported!\n", type);
1204 if (type != NL80211_IFTYPE_AP &&
1205 rtlpriv->mac80211.link_state < MAC80211_LINKED)
1206 bt_msr = rtl_read_byte(rtlpriv, MSR) & ~MSR_LINK_MASK;
1207 rtl_write_byte(rtlpriv, MSR, bt_msr);
1209 temp = rtl_read_dword(rtlpriv, TCR);
1210 rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8)));
1211 rtl_write_dword(rtlpriv, TCR, temp | BIT(8));
1217 /* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */
1218 int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1220 struct rtl_priv *rtlpriv = rtl_priv(hw);
1222 if (_rtl92se_set_media_status(hw, type))
1225 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1226 if (type != NL80211_IFTYPE_AP)
1227 rtl92se_set_check_bssid(hw, true);
1229 rtl92se_set_check_bssid(hw, false);
1235 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1236 void rtl92se_set_qos(struct ieee80211_hw *hw, int aci)
1238 struct rtl_priv *rtlpriv = rtl_priv(hw);
1239 rtl92s_dm_init_edca_turbo(hw);
1243 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f);
1246 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */
1249 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322);
1252 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222);
1255 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1260 void rtl92se_enable_interrupt(struct ieee80211_hw *hw)
1262 struct rtl_priv *rtlpriv = rtl_priv(hw);
1263 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1265 rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]);
1266 /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */
1267 rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F);
1268 rtlpci->irq_enabled = true;
1271 void rtl92se_disable_interrupt(struct ieee80211_hw *hw)
1273 struct rtl_priv *rtlpriv;
1274 struct rtl_pci *rtlpci;
1276 rtlpriv = rtl_priv(hw);
1277 /* if firmware not available, no interrupts */
1278 if (!rtlpriv || !rtlpriv->max_fw_size)
1280 rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1281 rtl_write_dword(rtlpriv, INTA_MASK, 0);
1282 rtl_write_dword(rtlpriv, INTA_MASK + 4, 0);
1283 rtlpci->irq_enabled = false;
1286 static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data)
1288 struct rtl_priv *rtlpriv = rtl_priv(hw);
1290 bool result = false;
1293 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
1295 /* Wait the MAC synchronized. */
1298 /* Check if it is set ready. */
1299 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1300 result = ((tmp & BIT(7)) == (data & BIT(7)));
1302 if ((data & (BIT(6) | BIT(7))) == false) {
1308 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1313 pr_err("wait for BIT(6) return value %x\n", tmp);
1329 static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
1331 struct rtl_priv *rtlpriv = rtl_priv(hw);
1332 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1333 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1336 if (rtlhal->driver_going2unload)
1337 rtl_write_byte(rtlpriv, 0x560, 0x0);
1339 /* Power save for BB/RF */
1340 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
1342 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
1343 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
1344 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
1345 rtl_write_word(rtlpriv, CMDR, 0x57FC);
1347 rtl_write_word(rtlpriv, CMDR, 0x77FC);
1348 rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
1350 rtl_write_word(rtlpriv, CMDR, 0x37FC);
1352 rtl_write_word(rtlpriv, CMDR, 0x77FC);
1354 rtl_write_word(rtlpriv, CMDR, 0x57FC);
1355 rtl_write_word(rtlpriv, CMDR, 0x0000);
1357 if (rtlhal->driver_going2unload) {
1358 u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1));
1359 u1btmp &= ~(BIT(0));
1360 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp);
1363 u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1365 /* Add description. After switch control path. register
1366 * after page1 will be invisible. We can not do any IO
1367 * for register>0x40. After resume&MACIO reset, we need
1368 * to remember previous reg content. */
1369 if (u1btmp & BIT(7)) {
1370 u1btmp &= ~(BIT(6) | BIT(7));
1371 if (!_rtl92s_set_sysclk(hw, u1btmp)) {
1372 pr_err("Switch ctrl path fail\n");
1377 /* Power save for MAC */
1378 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS &&
1379 !rtlhal->driver_going2unload) {
1380 /* enable LED function */
1381 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1382 /* SW/HW radio off or halt adapter!! For example S3/S4 */
1384 /* LED function disable. Power range is about 8mA now. */
1385 /* if write 0xF1 disconnet_pci power
1386 * ifconfig wlan0 down power are both high 35:70 */
1387 /* if write oxF9 disconnet_pci power
1388 * ifconfig wlan0 down power are both low 12:45*/
1389 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1392 rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70);
1393 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68);
1394 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x00);
1395 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1396 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E);
1397 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1401 static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw)
1403 struct rtl_priv *rtlpriv = rtl_priv(hw);
1404 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1405 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1406 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
1408 if (rtlpci->up_first_time == 1)
1411 if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS)
1412 rtl92se_sw_led_on(hw, pLed0);
1414 rtl92se_sw_led_off(hw, pLed0);
1418 static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
1420 struct rtl_priv *rtlpriv = rtl_priv(hw);
1424 rtlpriv->psc.pwrdomain_protect = true;
1426 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1427 if (tmpu1b & BIT(7)) {
1428 tmpu1b &= ~(BIT(6) | BIT(7));
1429 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1430 rtlpriv->psc.pwrdomain_protect = false;
1435 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
1436 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1438 /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */
1439 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1441 /* If IPS we need to turn LED on. So we not
1442 * not disable BIT 3/7 of reg3. */
1443 if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW))
1448 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
1449 /* wait for BIT 10/11/15 to pull high automatically!! */
1452 rtl_write_byte(rtlpriv, CMDR, 0);
1453 rtl_write_byte(rtlpriv, TCR, 0);
1455 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
1456 tmpu1b = rtl_read_byte(rtlpriv, 0x562);
1458 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1459 tmpu1b &= ~(BIT(3));
1460 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1462 /* Enable AFE clock source */
1463 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
1464 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
1467 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
1468 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
1470 /* Enable AFE Macro Block's Bandgap */
1471 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1472 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
1475 /* Enable AFE Mbias */
1476 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1477 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
1480 /* Enable LDOA15 block */
1481 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
1482 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
1484 /* Set Digital Vdd to Retention isolation Path. */
1485 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
1486 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
1489 /* For warm reboot NIC disappera bug. */
1490 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1491 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
1493 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
1495 /* Enable AFE PLL Macro Block */
1496 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
1497 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
1498 /* Enable MAC 80MHZ clock */
1499 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
1500 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
1503 /* Release isolation AFE PLL & MD */
1504 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
1506 /* Enable MAC clock */
1507 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1508 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
1510 /* Enable Core digital and enable IOREG R/W */
1511 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1512 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
1514 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
1516 /* Switch the control path. */
1517 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1518 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
1520 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1521 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
1522 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1523 rtlpriv->psc.pwrdomain_protect = false;
1527 rtl_write_word(rtlpriv, CMDR, 0x37FC);
1529 /* After MACIO reset,we must refresh LED state. */
1530 _rtl92se_gen_refreshledstate(hw);
1532 rtlpriv->psc.pwrdomain_protect = false;
1535 void rtl92se_card_disable(struct ieee80211_hw *hw)
1537 struct rtl_priv *rtlpriv = rtl_priv(hw);
1538 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1539 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1540 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1541 enum nl80211_iftype opmode;
1544 rtlpriv->intf_ops->enable_aspm(hw);
1546 if (rtlpci->driver_is_goingto_unload ||
1547 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1548 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1550 /* we should chnge GPIO to input mode
1551 * this will drop away current about 25mA*/
1552 rtl8192se_gpiobit3_cfg_inputmode(hw);
1554 /* this is very important for ips power save */
1555 while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) {
1556 if (rtlpriv->psc.pwrdomain_protect)
1562 mac->link_state = MAC80211_NOLINK;
1563 opmode = NL80211_IFTYPE_UNSPECIFIED;
1564 _rtl92se_set_media_status(hw, opmode);
1566 _rtl92s_phy_set_rfhalt(hw);
1570 void rtl92se_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta,
1573 struct rtl_priv *rtlpriv = rtl_priv(hw);
1574 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1576 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1577 rtl_write_dword(rtlpriv, ISR, *p_inta);
1579 *p_intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1];
1580 rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1583 void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw)
1585 struct rtl_priv *rtlpriv = rtl_priv(hw);
1586 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1587 u16 bcntime_cfg = 0;
1588 u16 bcn_cw = 6, bcn_ifs = 0xf;
1589 u16 atim_window = 2;
1591 /* ATIM Window (in unit of TU). */
1592 rtl_write_word(rtlpriv, ATIMWND, atim_window);
1594 /* Beacon interval (in unit of TU). */
1595 rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval);
1597 /* DrvErlyInt (in unit of TU). (Time to send
1598 * interrupt to notify driver to change
1599 * beacon content) */
1600 rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4);
1602 /* BcnDMATIM(in unit of us). Indicates the
1603 * time before TBTT to perform beacon queue DMA */
1604 rtl_write_word(rtlpriv, BCN_DMATIME, 256);
1606 /* Force beacon frame transmission even
1607 * after receiving beacon frame from
1608 * other ad hoc STA */
1609 rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100);
1611 /* Beacon Time Configuration */
1612 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1613 bcntime_cfg |= (bcn_cw << BCN_TCFG_CW_SHIFT);
1615 /* TODO: bcn_ifs may required to be changed on ASIC */
1616 bcntime_cfg |= bcn_ifs << BCN_TCFG_IFS;
1618 /*for beacon changed */
1619 rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval);
1622 void rtl92se_set_beacon_interval(struct ieee80211_hw *hw)
1624 struct rtl_priv *rtlpriv = rtl_priv(hw);
1625 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1626 u16 bcn_interval = mac->beacon_interval;
1628 /* Beacon interval (in unit of TU). */
1629 rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval);
1630 /* 2008.10.24 added by tynli for beacon changed. */
1631 rtl92s_phy_set_beacon_hwreg(hw, bcn_interval);
1634 void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw,
1635 u32 add_msr, u32 rm_msr)
1637 struct rtl_priv *rtlpriv = rtl_priv(hw);
1638 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1640 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1644 rtlpci->irq_mask[0] |= add_msr;
1647 rtlpci->irq_mask[0] &= (~rm_msr);
1649 rtl92se_disable_interrupt(hw);
1650 rtl92se_enable_interrupt(hw);
1653 static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw *hw)
1655 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1656 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1659 rtlhal->ic_class = IC_INFERIORITY_A;
1661 /* Only retrieving while using EFUSE. */
1662 if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) &&
1663 !rtlefuse->autoload_failflag) {
1664 efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET);
1666 if (efuse_id == 0xfe)
1667 rtlhal->ic_class = IC_INFERIORITY_B;
1671 static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1673 struct rtl_priv *rtlpriv = rtl_priv(hw);
1674 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1675 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1676 struct device *dev = &rtl_pcipriv(hw)->dev.pdev->dev;
1680 u8 hwinfo[HWSET_MAX_SIZE_92S];
1683 switch (rtlefuse->epromtype) {
1684 case EEPROM_BOOT_EFUSE:
1685 rtl_efuse_shadow_map_update(hw);
1689 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1690 "RTL819X Not boot from eeprom, check it !!\n");
1694 dev_warn(dev, "no efuse data\n");
1698 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1699 HWSET_MAX_SIZE_92S);
1701 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
1702 hwinfo, HWSET_MAX_SIZE_92S);
1704 eeprom_id = *((u16 *)&hwinfo[0]);
1705 if (eeprom_id != RTL8190_EEPROM_ID) {
1706 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1707 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1708 rtlefuse->autoload_failflag = true;
1710 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1711 rtlefuse->autoload_failflag = false;
1714 if (rtlefuse->autoload_failflag)
1717 _rtl8192se_get_IC_Inferiority(hw);
1719 /* Read IC Version && Channel Plan */
1720 /* VID, DID SE 0xA-D */
1721 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1722 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1723 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1724 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1725 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1727 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1728 "EEPROMId = 0x%4x\n", eeprom_id);
1729 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1730 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1731 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1732 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1733 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1734 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1735 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1736 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1738 for (i = 0; i < 6; i += 2) {
1739 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1740 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1743 for (i = 0; i < 6; i++)
1744 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1746 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1748 /* Get Tx Power Level by Channel */
1749 /* Read Tx power of Channel 1 ~ 14 from EEPROM. */
1750 /* 92S suupport RF A & B */
1751 for (rf_path = 0; rf_path < 2; rf_path++) {
1752 for (i = 0; i < 3; i++) {
1753 /* Read CCK RF A & B Tx power */
1754 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1755 hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i];
1757 /* Read OFDM RF A & B Tx power for 1T */
1758 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1759 hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i];
1761 /* Read OFDM RF A & B Tx power for 2T */
1762 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path][i]
1763 = hwinfo[EEPROM_TXPOWERBASE + 12 +
1768 for (rf_path = 0; rf_path < 2; rf_path++)
1769 for (i = 0; i < 3; i++)
1770 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1771 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1773 rtlefuse->eeprom_chnlarea_txpwr_cck
1775 for (rf_path = 0; rf_path < 2; rf_path++)
1776 for (i = 0; i < 3; i++)
1777 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1778 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1780 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1782 for (rf_path = 0; rf_path < 2; rf_path++)
1783 for (i = 0; i < 3; i++)
1784 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1785 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1787 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1790 for (rf_path = 0; rf_path < 2; rf_path++) {
1792 /* Assign dedicated channel tx power */
1793 for (i = 0; i < 14; i++) {
1794 /* channel 1~3 use the same Tx Power Level. */
1804 /* Record A & B CCK /OFDM - 1T/2T Channel area
1806 rtlefuse->txpwrlevel_cck[rf_path][i] =
1807 rtlefuse->eeprom_chnlarea_txpwr_cck
1809 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1810 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1812 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1813 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1817 for (i = 0; i < 14; i++) {
1818 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1819 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1821 rtlefuse->txpwrlevel_cck[rf_path][i],
1822 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1823 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1827 for (rf_path = 0; rf_path < 2; rf_path++) {
1828 for (i = 0; i < 3; i++) {
1829 /* Read Power diff limit. */
1830 rtlefuse->eeprom_pwrgroup[rf_path][i] =
1831 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i];
1835 for (rf_path = 0; rf_path < 2; rf_path++) {
1836 /* Fill Pwr group */
1837 for (i = 0; i < 14; i++) {
1848 rtlefuse->pwrgroup_ht20[rf_path][i] =
1849 (rtlefuse->eeprom_pwrgroup[rf_path][index] &
1851 rtlefuse->pwrgroup_ht40[rf_path][i] =
1852 ((rtlefuse->eeprom_pwrgroup[rf_path][index] &
1855 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1856 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1858 rtlefuse->pwrgroup_ht20[rf_path][i]);
1859 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1860 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1862 rtlefuse->pwrgroup_ht40[rf_path][i]);
1866 for (i = 0; i < 14; i++) {
1867 /* Read tx power difference between HT OFDM 20/40 MHZ */
1878 tempval = hwinfo[EEPROM_TX_PWR_HT20_DIFF + index] & 0xff;
1879 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1880 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1881 ((tempval >> 4) & 0xF);
1883 /* Read OFDM<->HT tx power diff */
1894 tempval = hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index] & 0xff;
1895 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] =
1897 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1898 ((tempval >> 4) & 0xF);
1900 tempval = hwinfo[TX_PWR_SAFETY_CHK];
1901 rtlefuse->txpwr_safetyflag = (tempval & 0x01);
1904 rtlefuse->eeprom_regulatory = 0;
1905 if (rtlefuse->eeprom_version >= 2) {
1907 if (rtlefuse->eeprom_version >= 4)
1908 rtlefuse->eeprom_regulatory =
1909 (hwinfo[EEPROM_REGULATORY] & 0x7);
1911 rtlefuse->eeprom_regulatory =
1912 (hwinfo[EEPROM_REGULATORY] & 0x1);
1914 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1915 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1917 for (i = 0; i < 14; i++)
1918 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1919 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1920 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1921 for (i = 0; i < 14; i++)
1922 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1923 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1924 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1925 for (i = 0; i < 14; i++)
1926 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1927 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1928 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1929 for (i = 0; i < 14; i++)
1930 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1931 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1932 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1934 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1935 "TxPwrSafetyFlag = %d\n", rtlefuse->txpwr_safetyflag);
1937 /* Read RF-indication and Tx Power gain
1938 * index diff of legacy to HT OFDM rate. */
1939 tempval = hwinfo[EEPROM_RFIND_POWERDIFF] & 0xff;
1940 rtlefuse->eeprom_txpowerdiff = tempval;
1941 rtlefuse->legacy_httxpowerdiff =
1942 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0];
1944 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1945 "TxPowerDiff = %#x\n", rtlefuse->eeprom_txpowerdiff);
1947 /* Get TSSI value for each path. */
1948 usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A];
1949 rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8);
1950 usvalue = hwinfo[EEPROM_TSSI_B];
1951 rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff);
1953 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1954 rtlefuse->eeprom_tssi[RF90_PATH_A],
1955 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1957 /* Read antenna tx power offset of B/C/D to A from EEPROM */
1958 /* and read ThermalMeter from EEPROM */
1959 tempval = hwinfo[EEPROM_THERMALMETER];
1960 rtlefuse->eeprom_thermalmeter = tempval;
1961 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1962 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1964 /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */
1965 rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f);
1966 rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100;
1968 /* Read CrystalCap from EEPROM */
1969 tempval = hwinfo[EEPROM_CRYSTALCAP] >> 4;
1970 rtlefuse->eeprom_crystalcap = tempval;
1971 /* CrystalCap, BIT(12)~15 */
1972 rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap;
1974 /* Read IC Version && Channel Plan */
1975 /* Version ID, Channel plan */
1976 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
1977 rtlefuse->txpwr_fromeprom = true;
1978 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1979 "EEPROM ChannelPlan = 0x%4x\n", rtlefuse->eeprom_channelplan);
1981 /* Read Customer ID or Board Type!!! */
1982 tempval = hwinfo[EEPROM_BOARDTYPE];
1983 /* Change RF type definition */
1985 rtlphy->rf_type = RF_2T2R;
1986 else if (tempval == 1)
1987 rtlphy->rf_type = RF_1T2R;
1988 else if (tempval == 2)
1989 rtlphy->rf_type = RF_1T2R;
1990 else if (tempval == 3)
1991 rtlphy->rf_type = RF_1T1R;
1993 /* 1T2R but 1SS (1x1 receive combining) */
1994 rtlefuse->b1x1_recvcombine = false;
1995 if (rtlphy->rf_type == RF_1T2R) {
1996 tempval = rtl_read_byte(rtlpriv, 0x07);
1997 if (!(tempval & BIT(0))) {
1998 rtlefuse->b1x1_recvcombine = true;
1999 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2000 "RF_TYPE=1T2R but only 1SS\n");
2003 rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine;
2004 rtlefuse->eeprom_oemid = *&hwinfo[EEPROM_CUSTOMID];
2006 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n",
2007 rtlefuse->eeprom_oemid);
2009 /* set channel paln to world wide 13 */
2010 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
2013 void rtl92se_read_eeprom_info(struct ieee80211_hw *hw)
2015 struct rtl_priv *rtlpriv = rtl_priv(hw);
2016 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2019 tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD);
2021 if (tmp_u1b & BIT(4)) {
2022 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2023 rtlefuse->epromtype = EEPROM_93C46;
2025 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2026 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2029 if (tmp_u1b & BIT(5)) {
2030 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2031 rtlefuse->autoload_failflag = false;
2032 _rtl92se_read_adapter_info(hw);
2034 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
2035 rtlefuse->autoload_failflag = true;
2039 static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw,
2040 struct ieee80211_sta *sta)
2042 struct rtl_priv *rtlpriv = rtl_priv(hw);
2043 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2044 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2045 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2048 u8 nmode = mac->ht_enable;
2049 u8 mimo_ps = IEEE80211_SMPS_OFF;
2050 u16 shortgi_rate = 0;
2051 u32 tmp_ratr_value = 0;
2052 u8 curtxbw_40mhz = mac->bw_40;
2053 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2055 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2057 enum wireless_mode wirelessmode = mac->mode;
2059 if (rtlhal->current_bandtype == BAND_ON_5G)
2060 ratr_value = sta->supp_rates[1] << 4;
2062 ratr_value = sta->supp_rates[0];
2063 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2065 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2066 sta->ht_cap.mcs.rx_mask[0] << 12);
2067 switch (wirelessmode) {
2068 case WIRELESS_MODE_B:
2069 ratr_value &= 0x0000000D;
2071 case WIRELESS_MODE_G:
2072 ratr_value &= 0x00000FF5;
2074 case WIRELESS_MODE_N_24G:
2075 case WIRELESS_MODE_N_5G:
2077 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2078 ratr_value &= 0x0007F005;
2082 if (get_rf_type(rtlphy) == RF_1T2R ||
2083 get_rf_type(rtlphy) == RF_1T1R) {
2085 ratr_mask = 0x000ff015;
2087 ratr_mask = 0x000ff005;
2090 ratr_mask = 0x0f0ff015;
2092 ratr_mask = 0x0f0ff005;
2095 ratr_value &= ratr_mask;
2099 if (rtlphy->rf_type == RF_1T2R)
2100 ratr_value &= 0x000ff0ff;
2102 ratr_value &= 0x0f0ff0ff;
2107 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2108 ratr_value &= 0x0FFFFFFF;
2109 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2110 ratr_value &= 0x0FFFFFF0;
2112 if (nmode && ((curtxbw_40mhz &&
2113 curshortgi_40mhz) || (!curtxbw_40mhz &&
2114 curshortgi_20mhz))) {
2116 ratr_value |= 0x10000000;
2117 tmp_ratr_value = (ratr_value >> 12);
2119 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2120 if ((1 << shortgi_rate) & tmp_ratr_value)
2124 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2125 (shortgi_rate << 4) | (shortgi_rate);
2127 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2130 rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value);
2131 if (ratr_value & 0xfffff000)
2132 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N);
2134 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG);
2136 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2137 rtl_read_dword(rtlpriv, ARFR0));
2140 static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw,
2141 struct ieee80211_sta *sta,
2144 struct rtl_priv *rtlpriv = rtl_priv(hw);
2145 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2146 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2147 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2148 struct rtl_sta_info *sta_entry = NULL;
2151 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
2152 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2154 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2156 enum wireless_mode wirelessmode = 0;
2157 bool shortgi = false;
2159 u8 shortgi_rate = 0;
2162 bool bmulticast = false;
2164 u8 mimo_ps = IEEE80211_SMPS_OFF;
2166 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2167 wirelessmode = sta_entry->wireless_mode;
2168 if (mac->opmode == NL80211_IFTYPE_STATION)
2169 curtxbw_40mhz = mac->bw_40;
2170 else if (mac->opmode == NL80211_IFTYPE_AP ||
2171 mac->opmode == NL80211_IFTYPE_ADHOC)
2172 macid = sta->aid + 1;
2174 if (rtlhal->current_bandtype == BAND_ON_5G)
2175 ratr_bitmap = sta->supp_rates[1] << 4;
2177 ratr_bitmap = sta->supp_rates[0];
2178 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2179 ratr_bitmap = 0xfff;
2180 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2181 sta->ht_cap.mcs.rx_mask[0] << 12);
2182 switch (wirelessmode) {
2183 case WIRELESS_MODE_B:
2184 band |= WIRELESS_11B;
2185 ratr_index = RATR_INX_WIRELESS_B;
2186 if (ratr_bitmap & 0x0000000c)
2187 ratr_bitmap &= 0x0000000d;
2189 ratr_bitmap &= 0x0000000f;
2191 case WIRELESS_MODE_G:
2192 band |= (WIRELESS_11G | WIRELESS_11B);
2193 ratr_index = RATR_INX_WIRELESS_GB;
2195 if (rssi_level == 1)
2196 ratr_bitmap &= 0x00000f00;
2197 else if (rssi_level == 2)
2198 ratr_bitmap &= 0x00000ff0;
2200 ratr_bitmap &= 0x00000ff5;
2202 case WIRELESS_MODE_A:
2203 band |= WIRELESS_11A;
2204 ratr_index = RATR_INX_WIRELESS_A;
2205 ratr_bitmap &= 0x00000ff0;
2207 case WIRELESS_MODE_N_24G:
2208 case WIRELESS_MODE_N_5G:
2209 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2210 ratr_index = RATR_INX_WIRELESS_NGB;
2212 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2213 if (rssi_level == 1)
2214 ratr_bitmap &= 0x00070000;
2215 else if (rssi_level == 2)
2216 ratr_bitmap &= 0x0007f000;
2218 ratr_bitmap &= 0x0007f005;
2220 if (rtlphy->rf_type == RF_1T2R ||
2221 rtlphy->rf_type == RF_1T1R) {
2222 if (rssi_level == 1) {
2223 ratr_bitmap &= 0x000f0000;
2224 } else if (rssi_level == 3) {
2225 ratr_bitmap &= 0x000fc000;
2226 } else if (rssi_level == 5) {
2227 ratr_bitmap &= 0x000ff000;
2230 ratr_bitmap &= 0x000ff015;
2232 ratr_bitmap &= 0x000ff005;
2235 if (rssi_level == 1) {
2236 ratr_bitmap &= 0x0f8f0000;
2237 } else if (rssi_level == 3) {
2238 ratr_bitmap &= 0x0f8fc000;
2239 } else if (rssi_level == 5) {
2240 ratr_bitmap &= 0x0f8ff000;
2243 ratr_bitmap &= 0x0f8ff015;
2245 ratr_bitmap &= 0x0f8ff005;
2250 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2251 (!curtxbw_40mhz && curshortgi_20mhz)) {
2254 else if (macid == 1)
2259 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2260 ratr_index = RATR_INX_WIRELESS_NGB;
2262 if (rtlphy->rf_type == RF_1T2R)
2263 ratr_bitmap &= 0x000ff0ff;
2265 ratr_bitmap &= 0x0f8ff0ff;
2268 sta_entry->ratr_index = ratr_index;
2270 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2271 ratr_bitmap &= 0x0FFFFFFF;
2272 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2273 ratr_bitmap &= 0x0FFFFFF0;
2276 ratr_bitmap |= 0x10000000;
2277 /* Get MAX MCS available. */
2278 ratr_value = (ratr_bitmap >> 12);
2279 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2280 if ((1 << shortgi_rate) & ratr_value)
2284 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2285 (shortgi_rate << 4) | (shortgi_rate);
2286 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2289 mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf);
2291 RT_TRACE(rtlpriv, COMP_RATR, DBG_TRACE, "mask = %x, bitmap = %x\n",
2293 rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap);
2294 rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8)));
2297 sta_entry->ratr_index = ratr_index;
2300 void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw,
2301 struct ieee80211_sta *sta, u8 rssi_level)
2303 struct rtl_priv *rtlpriv = rtl_priv(hw);
2305 if (rtlpriv->dm.useramask)
2306 rtl92se_update_hal_rate_mask(hw, sta, rssi_level);
2308 rtl92se_update_hal_rate_table(hw, sta);
2311 void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw)
2313 struct rtl_priv *rtlpriv = rtl_priv(hw);
2314 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2317 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2319 sifs_timer = 0x0e0e;
2320 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2324 /* this ifunction is for RFKILL, it's different with windows,
2325 * because UI will disable wireless when GPIO Radio Off.
2326 * And here we not check or Disable/Enable ASPM like windows*/
2327 bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2329 struct rtl_priv *rtlpriv = rtl_priv(hw);
2330 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2331 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2332 enum rf_pwrstate rfpwr_toset /*, cur_rfstate */;
2333 unsigned long flag = 0;
2334 bool actuallyset = false;
2335 bool turnonbypowerdomain = false;
2337 /* just 8191se can check gpio before firstup, 92c/92d have fixed it */
2338 if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
2341 if (ppsc->swrf_processing)
2344 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2345 if (ppsc->rfchange_inprogress) {
2346 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2349 ppsc->rfchange_inprogress = true;
2350 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2353 /* cur_rfstate = ppsc->rfpwr_state;*/
2355 /* because after _rtl92s_phy_set_rfhalt, all power
2356 * closed, so we must open some power for GPIO check,
2357 * or we will always check GPIO RFOFF here,
2358 * And we should close power after GPIO check */
2359 if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2360 _rtl92se_power_domain_init(hw);
2361 turnonbypowerdomain = true;
2364 rfpwr_toset = _rtl92se_rf_onoff_detect(hw);
2366 if ((ppsc->hwradiooff) && (rfpwr_toset == ERFON)) {
2367 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2368 "RFKILL-HW Radio ON, RF ON\n");
2370 rfpwr_toset = ERFON;
2371 ppsc->hwradiooff = false;
2373 } else if ((!ppsc->hwradiooff) && (rfpwr_toset == ERFOFF)) {
2374 RT_TRACE(rtlpriv, COMP_RF,
2375 DBG_DMESG, "RFKILL-HW Radio OFF, RF OFF\n");
2377 rfpwr_toset = ERFOFF;
2378 ppsc->hwradiooff = true;
2383 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2384 ppsc->rfchange_inprogress = false;
2385 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2387 /* this not include ifconfig wlan0 down case */
2388 /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */
2390 /* because power_domain_init may be happen when
2391 * _rtl92s_phy_set_rfhalt, this will open some powers
2392 * and cause current increasing about 40 mA for ips,
2393 * rfoff and ifconfig down, so we set
2394 * _rtl92s_phy_set_rfhalt again here */
2395 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC &&
2396 turnonbypowerdomain) {
2397 _rtl92s_phy_set_rfhalt(hw);
2398 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2401 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2402 ppsc->rfchange_inprogress = false;
2403 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2407 return !ppsc->hwradiooff;
2411 /* Is_wepkey just used for WEP used as group & pairwise key
2412 * if pairwise is AES ang group is WEP Is_wepkey == false.*/
2413 void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
2414 bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all)
2416 struct rtl_priv *rtlpriv = rtl_priv(hw);
2417 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2418 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2419 u8 *macaddr = p_macaddr;
2422 bool is_pairwise = false;
2424 static u8 cam_const_addr[4][6] = {
2425 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2426 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2427 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2428 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2430 static u8 cam_const_broad[] = {
2431 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2437 u8 clear_number = 5;
2439 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2441 for (idx = 0; idx < clear_number; idx++) {
2442 rtl_cam_mark_invalid(hw, cam_offset + idx);
2443 rtl_cam_empty_entry(hw, cam_offset + idx);
2446 memset(rtlpriv->sec.key_buf[idx], 0,
2448 rtlpriv->sec.key_len[idx] = 0;
2454 case WEP40_ENCRYPTION:
2455 enc_algo = CAM_WEP40;
2457 case WEP104_ENCRYPTION:
2458 enc_algo = CAM_WEP104;
2460 case TKIP_ENCRYPTION:
2461 enc_algo = CAM_TKIP;
2463 case AESCCMP_ENCRYPTION:
2467 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2468 "switch case not processed\n");
2469 enc_algo = CAM_TKIP;
2473 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2474 macaddr = cam_const_addr[key_index];
2475 entry_id = key_index;
2478 macaddr = cam_const_broad;
2479 entry_id = key_index;
2481 if (mac->opmode == NL80211_IFTYPE_AP) {
2482 entry_id = rtl_cam_get_free_entry(hw,
2484 if (entry_id >= TOTAL_CAM_ENTRY) {
2486 COMP_SEC, DBG_EMERG,
2487 "Can not find free hw security cam entry\n");
2491 entry_id = CAM_PAIRWISE_KEY_POSITION;
2494 key_index = PAIRWISE_KEYIDX;
2499 if (rtlpriv->sec.key_len[key_index] == 0) {
2500 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2501 "delete one entry, entry_id is %d\n",
2503 if (mac->opmode == NL80211_IFTYPE_AP)
2504 rtl_cam_del_entry(hw, p_macaddr);
2505 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2507 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2510 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2511 "set Pairwise key\n");
2513 rtl_cam_add_one_entry(hw, macaddr, key_index,
2515 CAM_CONFIG_NO_USEDK,
2516 rtlpriv->sec.key_buf[key_index]);
2518 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2521 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2522 rtl_cam_add_one_entry(hw,
2525 CAM_PAIRWISE_KEY_POSITION,
2526 enc_algo, CAM_CONFIG_NO_USEDK,
2527 rtlpriv->sec.key_buf[entry_id]);
2530 rtl_cam_add_one_entry(hw, macaddr, key_index,
2532 CAM_CONFIG_NO_USEDK,
2533 rtlpriv->sec.key_buf[entry_id]);
2540 void rtl92se_suspend(struct ieee80211_hw *hw)
2542 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2544 rtlpci->up_first_time = true;
2547 void rtl92se_resume(struct ieee80211_hw *hw)
2549 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2552 pci_read_config_dword(rtlpci->pdev, 0x40, &val);
2553 if ((val & 0x0000ff00) != 0)
2554 pci_write_config_dword(rtlpci->pdev, 0x40,