drivers/net/wireless/rt2x00/rt2500pci.c

   1 /*
   2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500pci
  23         Abstract: rt2500pci device specific routines.
  24         Supported chipsets: RT2560.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34 #include <linux/slab.h>
  35
  36 #include "rt2x00.h"
  37 #include "rt2x00mmio.h"
  38 #include "rt2x00pci.h"
  39 #include "rt2500pci.h"
  40
  41 /*
  42  * Register access.
  43  * All access to the CSR registers will go through the methods
  44  * rt2x00mmio_register_read and rt2x00mmio_register_write.
  45  * BBP and RF register require indirect register access,
  46  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  47  * These indirect registers work with busy bits,
  48  * and we will try maximal REGISTER_BUSY_COUNT times to access
  49  * the register while taking a REGISTER_BUSY_DELAY us delay
  50  * between each attampt. When the busy bit is still set at that time,
  51  * the access attempt is considered to have failed,
  52  * and we will print an error.
  53  */
  54 #define WAIT_FOR_BBP(__dev, __reg) \
  55         rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
  56 #define WAIT_FOR_RF(__dev, __reg) \
  57         rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
  58
  59 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  60                                 const unsigned int word, const u8 value)
  61 {
  62         u32 reg;
  63
  64         mutex_lock(&rt2x00dev->csr_mutex);
  65
  66         /*
  67          * Wait until the BBP becomes available, afterwards we
  68          * can safely write the new data into the register.
  69          */
  70         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  71                 reg = 0;
  72                 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  73                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  74                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  75                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  76
  77                 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
  78         }
  79
  80         mutex_unlock(&rt2x00dev->csr_mutex);
  81 }
  82
  83 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  84                                const unsigned int word, u8 *value)
  85 {
  86         u32 reg;
  87
  88         mutex_lock(&rt2x00dev->csr_mutex);
  89
  90         /*
  91          * Wait until the BBP becomes available, afterwards we
  92          * can safely write the read request into the register.
  93          * After the data has been written, we wait until hardware
  94          * returns the correct value, if at any time the register
  95          * doesn't become available in time, reg will be 0xffffffff
  96          * which means we return 0xff to the caller.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 101                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 102                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 103
 104                 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
 105
 106                 WAIT_FOR_BBP(rt2x00dev, &reg);
 107         }
 108
 109         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 110
 111         mutex_unlock(&rt2x00dev->csr_mutex);
 112 }
 113
 114 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
 115                                const unsigned int word, const u32 value)
 116 {
 117         u32 reg;
 118
 119         mutex_lock(&rt2x00dev->csr_mutex);
 120
 121         /*
 122          * Wait until the RF becomes available, afterwards we
 123          * can safely write the new data into the register.
 124          */
 125         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 126                 reg = 0;
 127                 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 128                 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 129                 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 130                 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 131
 132                 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg);
 133                 rt2x00_rf_write(rt2x00dev, word, value);
 134         }
 135
 136         mutex_unlock(&rt2x00dev->csr_mutex);
 137 }
 138
 139 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 140 {
 141         struct rt2x00_dev *rt2x00dev = eeprom->data;
 142         u32 reg;
 143
 144         rt2x00mmio_register_read(rt2x00dev, CSR21, &reg);
 145
 146         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 147         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 148         eeprom->reg_data_clock =
 149             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 150         eeprom->reg_chip_select =
 151             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 152 }
 153
 154 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 155 {
 156         struct rt2x00_dev *rt2x00dev = eeprom->data;
 157         u32 reg = 0;
 158
 159         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 160         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 161         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 162                            !!eeprom->reg_data_clock);
 163         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 164                            !!eeprom->reg_chip_select);
 165
 166         rt2x00mmio_register_write(rt2x00dev, CSR21, reg);
 167 }
 168
 169 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 170 static const struct rt2x00debug rt2500pci_rt2x00debug = {
 171         .owner  = THIS_MODULE,
 172         .csr    = {
 173                 .read           = rt2x00mmio_register_read,
 174                 .write          = rt2x00mmio_register_write,
 175                 .flags          = RT2X00DEBUGFS_OFFSET,
 176                 .word_base      = CSR_REG_BASE,
 177                 .word_size      = sizeof(u32),
 178                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 179         },
 180         .eeprom = {
 181                 .read           = rt2x00_eeprom_read,
 182                 .write          = rt2x00_eeprom_write,
 183                 .word_base      = EEPROM_BASE,
 184                 .word_size      = sizeof(u16),
 185                 .word_count     = EEPROM_SIZE / sizeof(u16),
 186         },
 187         .bbp    = {
 188                 .read           = rt2500pci_bbp_read,
 189                 .write          = rt2500pci_bbp_write,
 190                 .word_base      = BBP_BASE,
 191                 .word_size      = sizeof(u8),
 192                 .word_count     = BBP_SIZE / sizeof(u8),
 193         },
 194         .rf     = {
 195                 .read           = rt2x00_rf_read,
 196                 .write          = rt2500pci_rf_write,
 197                 .word_base      = RF_BASE,
 198                 .word_size      = sizeof(u32),
 199                 .word_count     = RF_SIZE / sizeof(u32),
 200         },
 201 };
 202 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 203
 204 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 205 {
 206         u32 reg;
 207
 208         rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg);
 209         return rt2x00_get_field32(reg, GPIOCSR_VAL0);
 210 }
 211
 212 #ifdef CONFIG_RT2X00_LIB_LEDS
 213 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
 214                                      enum led_brightness brightness)
 215 {
 216         struct rt2x00_led *led =
 217             container_of(led_cdev, struct rt2x00_led, led_dev);
 218         unsigned int enabled = brightness != LED_OFF;
 219         u32 reg;
 220
 221         rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg);
 222
 223         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 224                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 225         else if (led->type == LED_TYPE_ACTIVITY)
 226                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 227
 228         rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
 229 }
 230
 231 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
 232                                unsigned long *delay_on,
 233                                unsigned long *delay_off)
 234 {
 235         struct rt2x00_led *led =
 236             container_of(led_cdev, struct rt2x00_led, led_dev);
 237         u32 reg;
 238
 239         rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg);
 240         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 241         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 242         rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
 243
 244         return 0;
 245 }
 246
 247 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
 248                                struct rt2x00_led *led,
 249                                enum led_type type)
 250 {
 251         led->rt2x00dev = rt2x00dev;
 252         led->type = type;
 253         led->led_dev.brightness_set = rt2500pci_brightness_set;
 254         led->led_dev.blink_set = rt2500pci_blink_set;
 255         led->flags = LED_INITIALIZED;
 256 }
 257 #endif /* CONFIG_RT2X00_LIB_LEDS */
 258
 259 /*
 260  * Configuration handlers.
 261  */
 262 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
 263                                     const unsigned int filter_flags)
 264 {
 265         u32 reg;
 266
 267         /*
 268          * Start configuration steps.
 269          * Note that the version error will always be dropped
 270          * and broadcast frames will always be accepted since
 271          * there is no filter for it at this time.
 272          */
 273         rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
 274         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 275                            !(filter_flags & FIF_FCSFAIL));
 276         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 277                            !(filter_flags & FIF_PLCPFAIL));
 278         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 279                            !(filter_flags & FIF_CONTROL));
 280         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 281                            !(filter_flags & FIF_PROMISC_IN_BSS));
 282         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 283                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 284                            !rt2x00dev->intf_ap_count);
 285         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 286         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
 287                            !(filter_flags & FIF_ALLMULTI));
 288         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
 289         rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
 290 }
 291
 292 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
 293                                   struct rt2x00_intf *intf,
 294                                   struct rt2x00intf_conf *conf,
 295                                   const unsigned int flags)
 296 {
 297         struct data_queue *queue = rt2x00dev->bcn;
 298         unsigned int bcn_preload;
 299         u32 reg;
 300
 301         if (flags & CONFIG_UPDATE_TYPE) {
 302                 /*
 303                  * Enable beacon config
 304                  */
 305                 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
 306                 rt2x00mmio_register_read(rt2x00dev, BCNCSR1, &reg);
 307                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 308                 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
 309                 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg);
 310
 311                 /*
 312                  * Enable synchronisation.
 313                  */
 314                 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
 315                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 316                 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
 317         }
 318
 319         if (flags & CONFIG_UPDATE_MAC)
 320                 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
 321                                               conf->mac, sizeof(conf->mac));
 322
 323         if (flags & CONFIG_UPDATE_BSSID)
 324                 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5,
 325                                               conf->bssid, sizeof(conf->bssid));
 326 }
 327
 328 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
 329                                  struct rt2x00lib_erp *erp,
 330                                  u32 changed)
 331 {
 332         int preamble_mask;
 333         u32 reg;
 334
 335         /*
 336          * When short preamble is enabled, we should set bit 0x08
 337          */
 338         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
 339                 preamble_mask = erp->short_preamble << 3;
 340
 341                 rt2x00mmio_register_read(rt2x00dev, TXCSR1, &reg);
 342                 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162);
 343                 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2);
 344                 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 345                 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 346                 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg);
 347
 348                 rt2x00mmio_register_read(rt2x00dev, ARCSR2, &reg);
 349                 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 350                 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 351                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 352                                    GET_DURATION(ACK_SIZE, 10));
 353                 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg);
 354
 355                 rt2x00mmio_register_read(rt2x00dev, ARCSR3, &reg);
 356                 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 357                 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 358                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 359                                    GET_DURATION(ACK_SIZE, 20));
 360                 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg);
 361
 362                 rt2x00mmio_register_read(rt2x00dev, ARCSR4, &reg);
 363                 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 364                 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 365                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 366                                    GET_DURATION(ACK_SIZE, 55));
 367                 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg);
 368
 369                 rt2x00mmio_register_read(rt2x00dev, ARCSR5, &reg);
 370                 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 371                 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 372                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 373                                    GET_DURATION(ACK_SIZE, 110));
 374                 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg);
 375         }
 376
 377         if (changed & BSS_CHANGED_BASIC_RATES)
 378                 rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
 379
 380         if (changed & BSS_CHANGED_ERP_SLOT) {
 381                 rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
 382                 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
 383                 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
 384
 385                 rt2x00mmio_register_read(rt2x00dev, CSR18, &reg);
 386                 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
 387                 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
 388                 rt2x00mmio_register_write(rt2x00dev, CSR18, reg);
 389
 390                 rt2x00mmio_register_read(rt2x00dev, CSR19, &reg);
 391                 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
 392                 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
 393                 rt2x00mmio_register_write(rt2x00dev, CSR19, reg);
 394         }
 395
 396         if (changed & BSS_CHANGED_BEACON_INT) {
 397                 rt2x00mmio_register_read(rt2x00dev, CSR12, &reg);
 398                 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 399                                    erp->beacon_int * 16);
 400                 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 401                                    erp->beacon_int * 16);
 402                 rt2x00mmio_register_write(rt2x00dev, CSR12, reg);
 403         }
 404
 405 }
 406
 407 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
 408                                  struct antenna_setup *ant)
 409 {
 410         u32 reg;
 411         u8 r14;
 412         u8 r2;
 413
 414         /*
 415          * We should never come here because rt2x00lib is supposed
 416          * to catch this and send us the correct antenna explicitely.
 417          */
 418         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 419                ant->tx == ANTENNA_SW_DIVERSITY);
 420
 421         rt2x00mmio_register_read(rt2x00dev, BBPCSR1, &reg);
 422         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
 423         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
 424
 425         /*
 426          * Configure the TX antenna.
 427          */
 428         switch (ant->tx) {
 429         case ANTENNA_A:
 430                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
 431                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
 432                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
 433                 break;
 434         case ANTENNA_B:
 435         default:
 436                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 437                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 438                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 439                 break;
 440         }
 441
 442         /*
 443          * Configure the RX antenna.
 444          */
 445         switch (ant->rx) {
 446         case ANTENNA_A:
 447                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
 448                 break;
 449         case ANTENNA_B:
 450         default:
 451                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 452                 break;
 453         }
 454
 455         /*
 456          * RT2525E and RT5222 need to flip TX I/Q
 457          */
 458         if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) {
 459                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
 460                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
 461                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
 462
 463                 /*
 464                  * RT2525E does not need RX I/Q Flip.
 465                  */
 466                 if (rt2x00_rf(rt2x00dev, RF2525E))
 467                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
 468         } else {
 469                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
 470                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
 471         }
 472
 473         rt2x00mmio_register_write(rt2x00dev, BBPCSR1, reg);
 474         rt2500pci_bbp_write(rt2x00dev, 14, r14);
 475         rt2500pci_bbp_write(rt2x00dev, 2, r2);
 476 }
 477
 478 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
 479                                      struct rf_channel *rf, const int txpower)
 480 {
 481         u8 r70;
 482
 483         /*
 484          * Set TXpower.
 485          */
 486         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 487
 488         /*
 489          * Switch on tuning bits.
 490          * For RT2523 devices we do not need to update the R1 register.
 491          */
 492         if (!rt2x00_rf(rt2x00dev, RF2523))
 493                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 494         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 495
 496         /*
 497          * For RT2525 we should first set the channel to half band higher.
 498          */
 499         if (rt2x00_rf(rt2x00dev, RF2525)) {
 500                 static const u32 vals[] = {
 501                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
 502                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
 503                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
 504                         0x00080d2e, 0x00080d3a
 505                 };
 506
 507                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 508                 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
 509                 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 510                 if (rf->rf4)
 511                         rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 512         }
 513
 514         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 515         rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
 516         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 517         if (rf->rf4)
 518                 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 519
 520         /*
 521          * Channel 14 requires the Japan filter bit to be set.
 522          */
 523         r70 = 0x46;
 524         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
 525         rt2500pci_bbp_write(rt2x00dev, 70, r70);
 526
 527         msleep(1);
 528
 529         /*
 530          * Switch off tuning bits.
 531          * For RT2523 devices we do not need to update the R1 register.
 532          */
 533         if (!rt2x00_rf(rt2x00dev, RF2523)) {
 534                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 535                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 536         }
 537
 538         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 539         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 540
 541         /*
 542          * Clear false CRC during channel switch.
 543          */
 544         rt2x00mmio_register_read(rt2x00dev, CNT0, &rf->rf1);
 545 }
 546
 547 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 548                                      const int txpower)
 549 {
 550         u32 rf3;
 551
 552         rt2x00_rf_read(rt2x00dev, 3, &rf3);
 553         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 554         rt2500pci_rf_write(rt2x00dev, 3, rf3);
 555 }
 556
 557 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 558                                          struct rt2x00lib_conf *libconf)
 559 {
 560         u32 reg;
 561
 562         rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
 563         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
 564                            libconf->conf->long_frame_max_tx_count);
 565         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
 566                            libconf->conf->short_frame_max_tx_count);
 567         rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
 568 }
 569
 570 static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
 571                                 struct rt2x00lib_conf *libconf)
 572 {
 573         enum dev_state state =
 574             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 575                 STATE_SLEEP : STATE_AWAKE;
 576         u32 reg;
 577
 578         if (state == STATE_SLEEP) {
 579                 rt2x00mmio_register_read(rt2x00dev, CSR20, &reg);
 580                 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
 581                                    (rt2x00dev->beacon_int - 20) * 16);
 582                 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
 583                                    libconf->conf->listen_interval - 1);
 584
 585                 /* We must first disable autowake before it can be enabled */
 586                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
 587                 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
 588
 589                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
 590                 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
 591         } else {
 592                 rt2x00mmio_register_read(rt2x00dev, CSR20, &reg);
 593                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
 594                 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
 595         }
 596
 597         rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 598 }
 599
 600 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
 601                              struct rt2x00lib_conf *libconf,
 602                              const unsigned int flags)
 603 {
 604         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 605                 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
 606                                          libconf->conf->power_level);
 607         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
 608             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
 609                 rt2500pci_config_txpower(rt2x00dev,
 610                                          libconf->conf->power_level);
 611         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 612                 rt2500pci_config_retry_limit(rt2x00dev, libconf);
 613         if (flags & IEEE80211_CONF_CHANGE_PS)
 614                 rt2500pci_config_ps(rt2x00dev, libconf);
 615 }
 616
 617 /*
 618  * Link tuning
 619  */
 620 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
 621                                  struct link_qual *qual)
 622 {
 623         u32 reg;
 624
 625         /*
 626          * Update FCS error count from register.
 627          */
 628         rt2x00mmio_register_read(rt2x00dev, CNT0, &reg);
 629         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 630
 631         /*
 632          * Update False CCA count from register.
 633          */
 634         rt2x00mmio_register_read(rt2x00dev, CNT3, &reg);
 635         qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
 636 }
 637
 638 static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev,
 639                                      struct link_qual *qual, u8 vgc_level)
 640 {
 641         if (qual->vgc_level_reg != vgc_level) {
 642                 rt2500pci_bbp_write(rt2x00dev, 17, vgc_level);
 643                 qual->vgc_level = vgc_level;
 644                 qual->vgc_level_reg = vgc_level;
 645         }
 646 }
 647
 648 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
 649                                   struct link_qual *qual)
 650 {
 651         rt2500pci_set_vgc(rt2x00dev, qual, 0x48);
 652 }
 653
 654 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev,
 655                                  struct link_qual *qual, const u32 count)
 656 {
 657         /*
 658          * To prevent collisions with MAC ASIC on chipsets
 659          * up to version C the link tuning should halt after 20
 660          * seconds while being associated.
 661          */
 662         if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D &&
 663             rt2x00dev->intf_associated && count > 20)
 664                 return;
 665
 666         /*
 667          * Chipset versions C and lower should directly continue
 668          * to the dynamic CCA tuning. Chipset version D and higher
 669          * should go straight to dynamic CCA tuning when they
 670          * are not associated.
 671          */
 672         if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D ||
 673             !rt2x00dev->intf_associated)
 674                 goto dynamic_cca_tune;
 675
 676         /*
 677          * A too low RSSI will cause too much false CCA which will
 678          * then corrupt the R17 tuning. To remidy this the tuning should
 679          * be stopped (While making sure the R17 value will not exceed limits)
 680          */
 681         if (qual->rssi < -80 && count > 20) {
 682                 if (qual->vgc_level_reg >= 0x41)
 683                         rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
 684                 return;
 685         }
 686
 687         /*
 688          * Special big-R17 for short distance
 689          */
 690         if (qual->rssi >= -58) {
 691                 rt2500pci_set_vgc(rt2x00dev, qual, 0x50);
 692                 return;
 693         }
 694
 695         /*
 696          * Special mid-R17 for middle distance
 697          */
 698         if (qual->rssi >= -74) {
 699                 rt2500pci_set_vgc(rt2x00dev, qual, 0x41);
 700                 return;
 701         }
 702
 703         /*
 704          * Leave short or middle distance condition, restore r17
 705          * to the dynamic tuning range.
 706          */
 707         if (qual->vgc_level_reg >= 0x41) {
 708                 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
 709                 return;
 710         }
 711
 712 dynamic_cca_tune:
 713
 714         /*
 715          * R17 is inside the dynamic tuning range,
 716          * start tuning the link based on the false cca counter.
 717          */
 718         if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40)
 719                 rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg);
 720         else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32)
 721                 rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg);
 722 }
 723
 724 /*
 725  * Queue handlers.
 726  */
 727 static void rt2500pci_start_queue(struct data_queue *queue)
 728 {
 729         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 730         u32 reg;
 731
 732         switch (queue->qid) {
 733         case QID_RX:
 734                 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
 735                 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
 736                 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
 737                 break;
 738         case QID_BEACON:
 739                 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
 740                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 741                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 742                 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
 743                 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
 744                 break;
 745         default:
 746                 break;
 747         }
 748 }
 749
 750 static void rt2500pci_kick_queue(struct data_queue *queue)
 751 {
 752         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 753         u32 reg;
 754
 755         switch (queue->qid) {
 756         case QID_AC_VO:
 757                 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
 758                 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
 759                 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
 760                 break;
 761         case QID_AC_VI:
 762                 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
 763                 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
 764                 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
 765                 break;
 766         case QID_ATIM:
 767                 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
 768                 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
 769                 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
 770                 break;
 771         default:
 772                 break;
 773         }
 774 }
 775
 776 static void rt2500pci_stop_queue(struct data_queue *queue)
 777 {
 778         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 779         u32 reg;
 780
 781         switch (queue->qid) {
 782         case QID_AC_VO:
 783         case QID_AC_VI:
 784         case QID_ATIM:
 785                 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
 786                 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 787                 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
 788                 break;
 789         case QID_RX:
 790                 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
 791                 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
 792                 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
 793                 break;
 794         case QID_BEACON:
 795                 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
 796                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 797                 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 798                 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 799                 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
 800
 801                 /*
 802                  * Wait for possibly running tbtt tasklets.
 803                  */
 804                 tasklet_kill(&rt2x00dev->tbtt_tasklet);
 805                 break;
 806         default:
 807                 break;
 808         }
 809 }
 810
 811 /*
 812  * Initialization functions.
 813  */
 814 static bool rt2500pci_get_entry_state(struct queue_entry *entry)
 815 {
 816         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
 817         u32 word;
 818
 819         if (entry->queue->qid == QID_RX) {
 820                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 821
 822                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
 823         } else {
 824                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 825
 826                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
 827                         rt2x00_get_field32(word, TXD_W0_VALID));
 828         }
 829 }
 830
 831 static void rt2500pci_clear_entry(struct queue_entry *entry)
 832 {
 833         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
 834         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 835         u32 word;
 836
 837         if (entry->queue->qid == QID_RX) {
 838                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 839                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
 840                 rt2x00_desc_write(entry_priv->desc, 1, word);
 841
 842                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 843                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 844                 rt2x00_desc_write(entry_priv->desc, 0, word);
 845         } else {
 846                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 847                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 848                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 849                 rt2x00_desc_write(entry_priv->desc, 0, word);
 850         }
 851 }
 852
 853 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
 854 {
 855         struct queue_entry_priv_mmio *entry_priv;
 856         u32 reg;
 857
 858         /*
 859          * Initialize registers.
 860          */
 861         rt2x00mmio_register_read(rt2x00dev, TXCSR2, &reg);
 862         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 863         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 864         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
 865         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 866         rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg);
 867
 868         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 869         rt2x00mmio_register_read(rt2x00dev, TXCSR3, &reg);
 870         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 871                            entry_priv->desc_dma);
 872         rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg);
 873
 874         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 875         rt2x00mmio_register_read(rt2x00dev, TXCSR5, &reg);
 876         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 877                            entry_priv->desc_dma);
 878         rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg);
 879
 880         entry_priv = rt2x00dev->atim->entries[0].priv_data;
 881         rt2x00mmio_register_read(rt2x00dev, TXCSR4, &reg);
 882         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 883                            entry_priv->desc_dma);
 884         rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg);
 885
 886         entry_priv = rt2x00dev->bcn->entries[0].priv_data;
 887         rt2x00mmio_register_read(rt2x00dev, TXCSR6, &reg);
 888         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 889                            entry_priv->desc_dma);
 890         rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg);
 891
 892         rt2x00mmio_register_read(rt2x00dev, RXCSR1, &reg);
 893         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 894         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 895         rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg);
 896
 897         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 898         rt2x00mmio_register_read(rt2x00dev, RXCSR2, &reg);
 899         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 900                            entry_priv->desc_dma);
 901         rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg);
 902
 903         return 0;
 904 }
 905
 906 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
 907 {
 908         u32 reg;
 909
 910         rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002);
 911         rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002);
 912         rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00020002);
 913         rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002);
 914
 915         rt2x00mmio_register_read(rt2x00dev, TIMECSR, &reg);
 916         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 917         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 918         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 919         rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg);
 920
 921         rt2x00mmio_register_read(rt2x00dev, CSR9, &reg);
 922         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 923                            rt2x00dev->rx->data_size / 128);
 924         rt2x00mmio_register_write(rt2x00dev, CSR9, reg);
 925
 926         /*
 927          * Always use CWmin and CWmax set in descriptor.
 928          */
 929         rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
 930         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
 931         rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
 932
 933         rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
 934         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 935         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 936         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 937         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
 938         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
 939         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 940         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
 941         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
 942         rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
 943
 944         rt2x00mmio_register_write(rt2x00dev, CNT3, 0);
 945
 946         rt2x00mmio_register_read(rt2x00dev, TXCSR8, &reg);
 947         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
 948         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
 949         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
 950         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
 951         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
 952         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
 953         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
 954         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
 955         rt2x00mmio_register_write(rt2x00dev, TXCSR8, reg);
 956
 957         rt2x00mmio_register_read(rt2x00dev, ARTCSR0, &reg);
 958         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
 959         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
 960         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
 961         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
 962         rt2x00mmio_register_write(rt2x00dev, ARTCSR0, reg);
 963
 964         rt2x00mmio_register_read(rt2x00dev, ARTCSR1, &reg);
 965         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
 966         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
 967         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
 968         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
 969         rt2x00mmio_register_write(rt2x00dev, ARTCSR1, reg);
 970
 971         rt2x00mmio_register_read(rt2x00dev, ARTCSR2, &reg);
 972         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
 973         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
 974         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
 975         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
 976         rt2x00mmio_register_write(rt2x00dev, ARTCSR2, reg);
 977
 978         rt2x00mmio_register_read(rt2x00dev, RXCSR3, &reg);
 979         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
 980         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 981         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
 982         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 983         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
 984         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 985         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
 986         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
 987         rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg);
 988
 989         rt2x00mmio_register_read(rt2x00dev, PCICSR, &reg);
 990         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
 991         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
 992         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
 993         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
 994         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
 995         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
 996         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
 997         rt2x00mmio_register_write(rt2x00dev, PCICSR, reg);
 998
 999         rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
1000
1001         rt2x00mmio_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
1002         rt2x00mmio_register_write(rt2x00dev, TESTCSR, 0x000000f0);
1003
1004         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1005                 return -EBUSY;
1006
1007         rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00213223);
1008         rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518);
1009
1010         rt2x00mmio_register_read(rt2x00dev, MACCSR2, &reg);
1011         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
1012         rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg);
1013
1014         rt2x00mmio_register_read(rt2x00dev, RALINKCSR, &reg);
1015         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
1016         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
1017         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
1018         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
1019         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
1020         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
1021         rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg);
1022
1023         rt2x00mmio_register_write(rt2x00dev, BBPCSR1, 0x82188200);
1024
1025         rt2x00mmio_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
1026
1027         rt2x00mmio_register_read(rt2x00dev, CSR1, &reg);
1028         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
1029         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
1030         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
1031         rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
1032
1033         rt2x00mmio_register_read(rt2x00dev, CSR1, &reg);
1034         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
1035         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
1036         rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
1037
1038         /*
1039          * We must clear the FCS and FIFO error count.
1040          * These registers are cleared on read,
1041          * so we may pass a useless variable to store the value.
1042          */
1043         rt2x00mmio_register_read(rt2x00dev, CNT0, &reg);
1044         rt2x00mmio_register_read(rt2x00dev, CNT4, &reg);
1045
1046         return 0;
1047 }
1048
1049 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1050 {
1051         unsigned int i;
1052         u8 value;
1053
1054         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1055                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
1056                 if ((value != 0xff) && (value != 0x00))
1057                         return 0;
1058                 udelay(REGISTER_BUSY_DELAY);
1059         }
1060
1061         rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
1062         return -EACCES;
1063 }
1064
1065 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1066 {
1067         unsigned int i;
1068         u16 eeprom;
1069         u8 reg_id;
1070         u8 value;
1071
1072         if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
1073                 return -EACCES;
1074
1075         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
1076         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
1077         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
1078         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
1079         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
1080         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
1081         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
1082         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
1083         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
1084         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
1085         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
1086         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
1087         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
1088         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
1089         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
1090         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
1091         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
1092         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
1093         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
1094         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
1095         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
1096         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
1097         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
1098         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1099         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1100         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1101         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1102         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1103         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1104         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1105
1106         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1107                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1108
1109                 if (eeprom != 0xffff && eeprom != 0x0000) {
1110                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1111                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1112                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1113                 }
1114         }
1115
1116         return 0;
1117 }
1118
1119 /*
1120  * Device state switch handlers.
1121  */
1122 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1123                                  enum dev_state state)
1124 {
1125         int mask = (state == STATE_RADIO_IRQ_OFF);
1126         u32 reg;
1127         unsigned long flags;
1128
1129         /*
1130          * When interrupts are being enabled, the interrupt registers
1131          * should clear the register to assure a clean state.
1132          */
1133         if (state == STATE_RADIO_IRQ_ON) {
1134                 rt2x00mmio_register_read(rt2x00dev, CSR7, &reg);
1135                 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
1136         }
1137
1138         /*
1139          * Only toggle the interrupts bits we are going to use.
1140          * Non-checked interrupt bits are disabled by default.
1141          */
1142         spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1143
1144         rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
1145         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1146         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1147         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1148         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1149         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1150         rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1151
1152         spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1153
1154         if (state == STATE_RADIO_IRQ_OFF) {
1155                 /*
1156                  * Ensure that all tasklets are finished.
1157                  */
1158                 tasklet_kill(&rt2x00dev->txstatus_tasklet);
1159                 tasklet_kill(&rt2x00dev->rxdone_tasklet);
1160                 tasklet_kill(&rt2x00dev->tbtt_tasklet);
1161         }
1162 }
1163
1164 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1165 {
1166         /*
1167          * Initialize all registers.
1168          */
1169         if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1170                      rt2500pci_init_registers(rt2x00dev) ||
1171                      rt2500pci_init_bbp(rt2x00dev)))
1172                 return -EIO;
1173
1174         return 0;
1175 }
1176
1177 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1178 {
1179         /*
1180          * Disable power
1181          */
1182         rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0);
1183 }
1184
1185 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1186                                enum dev_state state)
1187 {
1188         u32 reg, reg2;
1189         unsigned int i;
1190         char put_to_sleep;
1191         char bbp_state;
1192         char rf_state;
1193
1194         put_to_sleep = (state != STATE_AWAKE);
1195
1196         rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg);
1197         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1198         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1199         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1200         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1201         rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1202
1203         /*
1204          * Device is not guaranteed to be in the requested state yet.
1205          * We must wait until the register indicates that the
1206          * device has entered the correct state.
1207          */
1208         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1209                 rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg2);
1210                 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1211                 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
1212                 if (bbp_state == state && rf_state == state)
1213                         return 0;
1214                 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1215                 msleep(10);
1216         }
1217
1218         return -EBUSY;
1219 }
1220
1221 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1222                                       enum dev_state state)
1223 {
1224         int retval = 0;
1225
1226         switch (state) {
1227         case STATE_RADIO_ON:
1228                 retval = rt2500pci_enable_radio(rt2x00dev);
1229                 break;
1230         case STATE_RADIO_OFF:
1231                 rt2500pci_disable_radio(rt2x00dev);
1232                 break;
1233         case STATE_RADIO_IRQ_ON:
1234         case STATE_RADIO_IRQ_OFF:
1235                 rt2500pci_toggle_irq(rt2x00dev, state);
1236                 break;
1237         case STATE_DEEP_SLEEP:
1238         case STATE_SLEEP:
1239         case STATE_STANDBY:
1240         case STATE_AWAKE:
1241                 retval = rt2500pci_set_state(rt2x00dev, state);
1242                 break;
1243         default:
1244                 retval = -ENOTSUPP;
1245                 break;
1246         }
1247
1248         if (unlikely(retval))
1249                 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1250                            state, retval);
1251
1252         return retval;
1253 }
1254
1255 /*
1256  * TX descriptor initialization
1257  */
1258 static void rt2500pci_write_tx_desc(struct queue_entry *entry,
1259                                     struct txentry_desc *txdesc)
1260 {
1261         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1262         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1263         __le32 *txd = entry_priv->desc;
1264         u32 word;
1265
1266         /*
1267          * Start writing the descriptor words.
1268          */
1269         rt2x00_desc_read(txd, 1, &word);
1270         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1271         rt2x00_desc_write(txd, 1, word);
1272
1273         rt2x00_desc_read(txd, 2, &word);
1274         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1275         rt2x00_set_field32(&word, TXD_W2_AIFS, entry->queue->aifs);
1276         rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->queue->cw_min);
1277         rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->queue->cw_max);
1278         rt2x00_desc_write(txd, 2, word);
1279
1280         rt2x00_desc_read(txd, 3, &word);
1281         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
1282         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
1283         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW,
1284                            txdesc->u.plcp.length_low);
1285         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH,
1286                            txdesc->u.plcp.length_high);
1287         rt2x00_desc_write(txd, 3, word);
1288
1289         rt2x00_desc_read(txd, 10, &word);
1290         rt2x00_set_field32(&word, TXD_W10_RTS,
1291                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1292         rt2x00_desc_write(txd, 10, word);
1293
1294         /*
1295          * Writing TXD word 0 must the last to prevent a race condition with
1296          * the device, whereby the device may take hold of the TXD before we
1297          * finished updating it.
1298          */
1299         rt2x00_desc_read(txd, 0, &word);
1300         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1301         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1302         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1303                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1304         rt2x00_set_field32(&word, TXD_W0_ACK,
1305                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1306         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1307                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1308         rt2x00_set_field32(&word, TXD_W0_OFDM,
1309                            (txdesc->rate_mode == RATE_MODE_OFDM));
1310         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1311         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1312         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1313                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1314         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1315         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1316         rt2x00_desc_write(txd, 0, word);
1317
1318         /*
1319          * Register descriptor details in skb frame descriptor.
1320          */
1321         skbdesc->desc = txd;
1322         skbdesc->desc_len = TXD_DESC_SIZE;
1323 }
1324
1325 /*
1326  * TX data initialization
1327  */
1328 static void rt2500pci_write_beacon(struct queue_entry *entry,
1329                                    struct txentry_desc *txdesc)
1330 {
1331         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1332         u32 reg;
1333
1334         /*
1335          * Disable beaconing while we are reloading the beacon data,
1336          * otherwise we might be sending out invalid data.
1337          */
1338         rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
1339         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1340         rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1341
1342         if (rt2x00queue_map_txskb(entry)) {
1343                 rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n");
1344                 goto out;
1345         }
1346
1347         /*
1348          * Write the TX descriptor for the beacon.
1349          */
1350         rt2500pci_write_tx_desc(entry, txdesc);
1351
1352         /*
1353          * Dump beacon to userspace through debugfs.
1354          */
1355         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1356 out:
1357         /*
1358          * Enable beaconing again.
1359          */
1360         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1361         rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1362 }
1363
1364 /*
1365  * RX control handlers
1366  */
1367 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1368                                   struct rxdone_entry_desc *rxdesc)
1369 {
1370         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1371         u32 word0;
1372         u32 word2;
1373
1374         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1375         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1376
1377         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1378                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1379         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1380                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1381
1382         /*
1383          * Obtain the status about this packet.
1384          * When frame was received with an OFDM bitrate,
1385          * the signal is the PLCP value. If it was received with
1386          * a CCK bitrate the signal is the rate in 100kbit/s.
1387          */
1388         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1389         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1390             entry->queue->rt2x00dev->rssi_offset;
1391         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1392
1393         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1394                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1395         else
1396                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1397         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1398                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1399 }
1400
1401 /*
1402  * Interrupt functions.
1403  */
1404 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1405                              const enum data_queue_qid queue_idx)
1406 {
1407         struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
1408         struct queue_entry_priv_mmio *entry_priv;
1409         struct queue_entry *entry;
1410         struct txdone_entry_desc txdesc;
1411         u32 word;
1412
1413         while (!rt2x00queue_empty(queue)) {
1414                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1415                 entry_priv = entry->priv_data;
1416                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1417
1418                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1419                     !rt2x00_get_field32(word, TXD_W0_VALID))
1420                         break;
1421
1422                 /*
1423                  * Obtain the status about this packet.
1424                  */
1425                 txdesc.flags = 0;
1426                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1427                 case 0: /* Success */
1428                 case 1: /* Success with retry */
1429                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1430                         break;
1431                 case 2: /* Failure, excessive retries */
1432                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1433                         /* Don't break, this is a failed frame! */
1434                 default: /* Failure */
1435                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1436                 }
1437                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1438
1439                 rt2x00lib_txdone(entry, &txdesc);
1440         }
1441 }
1442
1443 static inline void rt2500pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1444                                               struct rt2x00_field32 irq_field)
1445 {
1446         u32 reg;
1447
1448         /*
1449          * Enable a single interrupt. The interrupt mask register
1450          * access needs locking.
1451          */
1452         spin_lock_irq(&rt2x00dev->irqmask_lock);
1453
1454         rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
1455         rt2x00_set_field32(&reg, irq_field, 0);
1456         rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1457
1458         spin_unlock_irq(&rt2x00dev->irqmask_lock);
1459 }
1460
1461 static void rt2500pci_txstatus_tasklet(unsigned long data)
1462 {
1463         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1464         u32 reg;
1465
1466         /*
1467          * Handle all tx queues.
1468          */
1469         rt2500pci_txdone(rt2x00dev, QID_ATIM);
1470         rt2500pci_txdone(rt2x00dev, QID_AC_VO);
1471         rt2500pci_txdone(rt2x00dev, QID_AC_VI);
1472
1473         /*
1474          * Enable all TXDONE interrupts again.
1475          */
1476         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
1477                 spin_lock_irq(&rt2x00dev->irqmask_lock);
1478
1479                 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
1480                 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1481                 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1482                 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
1483                 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1484
1485                 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1486         }
1487 }
1488
1489 static void rt2500pci_tbtt_tasklet(unsigned long data)
1490 {
1491         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1492         rt2x00lib_beacondone(rt2x00dev);
1493         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1494                 rt2500pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
1495 }
1496
1497 static void rt2500pci_rxdone_tasklet(unsigned long data)
1498 {
1499         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1500         if (rt2x00mmio_rxdone(rt2x00dev))
1501                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1502         else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1503                 rt2500pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
1504 }
1505
1506 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1507 {
1508         struct rt2x00_dev *rt2x00dev = dev_instance;
1509         u32 reg, mask;
1510
1511         /*
1512          * Get the interrupt sources & saved to local variable.
1513          * Write register value back to clear pending interrupts.
1514          */
1515         rt2x00mmio_register_read(rt2x00dev, CSR7, &reg);
1516         rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
1517
1518         if (!reg)
1519                 return IRQ_NONE;
1520
1521         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1522                 return IRQ_HANDLED;
1523
1524         mask = reg;
1525
1526         /*
1527          * Schedule tasklets for interrupt handling.
1528          */
1529         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1530                 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1531
1532         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1533                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1534
1535         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1536             rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1537             rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1538                 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1539                 /*
1540                  * Mask out all txdone interrupts.
1541                  */
1542                 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1543                 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1544                 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1545         }
1546
1547         /*
1548          * Disable all interrupts for which a tasklet was scheduled right now,
1549          * the tasklet will reenable the appropriate interrupts.
1550          */
1551         spin_lock(&rt2x00dev->irqmask_lock);
1552
1553         rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
1554         reg |= mask;
1555         rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1556
1557         spin_unlock(&rt2x00dev->irqmask_lock);
1558
1559         return IRQ_HANDLED;
1560 }
1561
1562 /*
1563  * Device probe functions.
1564  */
1565 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1566 {
1567         struct eeprom_93cx6 eeprom;
1568         u32 reg;
1569         u16 word;
1570         u8 *mac;
1571
1572         rt2x00mmio_register_read(rt2x00dev, CSR21, &reg);
1573
1574         eeprom.data = rt2x00dev;
1575         eeprom.register_read = rt2500pci_eepromregister_read;
1576         eeprom.register_write = rt2500pci_eepromregister_write;
1577         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1578             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1579         eeprom.reg_data_in = 0;
1580         eeprom.reg_data_out = 0;
1581         eeprom.reg_data_clock = 0;
1582         eeprom.reg_chip_select = 0;
1583
1584         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1585                                EEPROM_SIZE / sizeof(u16));
1586
1587         /*
1588          * Start validation of the data that has been read.
1589          */
1590         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1591         if (!is_valid_ether_addr(mac)) {
1592                 eth_random_addr(mac);
1593                 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
1594         }
1595
1596         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1597         if (word == 0xffff) {
1598                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1599                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1600                                    ANTENNA_SW_DIVERSITY);
1601                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1602                                    ANTENNA_SW_DIVERSITY);
1603                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1604                                    LED_MODE_DEFAULT);
1605                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1606                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1607                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1608                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1609                 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
1610         }
1611
1612         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1613         if (word == 0xffff) {
1614                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1615                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1616                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1617                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1618                 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
1619         }
1620
1621         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1622         if (word == 0xffff) {
1623                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1624                                    DEFAULT_RSSI_OFFSET);
1625                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1626                 rt2x00_eeprom_dbg(rt2x00dev, "Calibrate offset: 0x%04x\n",
1627                                   word);
1628         }
1629
1630         return 0;
1631 }
1632
1633 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1634 {
1635         u32 reg;
1636         u16 value;
1637         u16 eeprom;
1638
1639         /*
1640          * Read EEPROM word for configuration.
1641          */
1642         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1643
1644         /*
1645          * Identify RF chipset.
1646          */
1647         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1648         rt2x00mmio_register_read(rt2x00dev, CSR0, &reg);
1649         rt2x00_set_chip(rt2x00dev, RT2560, value,
1650                         rt2x00_get_field32(reg, CSR0_REVISION));
1651
1652         if (!rt2x00_rf(rt2x00dev, RF2522) &&
1653             !rt2x00_rf(rt2x00dev, RF2523) &&
1654             !rt2x00_rf(rt2x00dev, RF2524) &&
1655             !rt2x00_rf(rt2x00dev, RF2525) &&
1656             !rt2x00_rf(rt2x00dev, RF2525E) &&
1657             !rt2x00_rf(rt2x00dev, RF5222)) {
1658                 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
1659                 return -ENODEV;
1660         }
1661
1662         /*
1663          * Identify default antenna configuration.
1664          */
1665         rt2x00dev->default_ant.tx =
1666             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1667         rt2x00dev->default_ant.rx =
1668             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1669
1670         /*
1671          * Store led mode, for correct led behaviour.
1672          */
1673 #ifdef CONFIG_RT2X00_LIB_LEDS
1674         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1675
1676         rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1677         if (value == LED_MODE_TXRX_ACTIVITY ||
1678             value == LED_MODE_DEFAULT ||
1679             value == LED_MODE_ASUS)
1680                 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1681                                    LED_TYPE_ACTIVITY);
1682 #endif /* CONFIG_RT2X00_LIB_LEDS */
1683
1684         /*
1685          * Detect if this device has an hardware controlled radio.
1686          */
1687         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1688                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1689
1690         /*
1691          * Check if the BBP tuning should be enabled.
1692          */
1693         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1694         if (!rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1695                 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1696
1697         /*
1698          * Read the RSSI <-> dBm offset information.
1699          */
1700         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1701         rt2x00dev->rssi_offset =
1702             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1703
1704         return 0;
1705 }
1706
1707 /*
1708  * RF value list for RF2522
1709  * Supports: 2.4 GHz
1710  */
1711 static const struct rf_channel rf_vals_bg_2522[] = {
1712         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1713         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1714         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1715         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1716         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1717         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1718         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1719         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1720         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1721         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1722         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1723         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1724         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1725         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1726 };
1727
1728 /*
1729  * RF value list for RF2523
1730  * Supports: 2.4 GHz
1731  */
1732 static const struct rf_channel rf_vals_bg_2523[] = {
1733         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1734         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1735         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1736         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1737         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1738         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1739         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1740         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1741         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1742         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1743         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1744         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1745         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1746         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1747 };
1748
1749 /*
1750  * RF value list for RF2524
1751  * Supports: 2.4 GHz
1752  */
1753 static const struct rf_channel rf_vals_bg_2524[] = {
1754         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1755         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1756         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1757         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1758         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1759         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1760         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1761         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1762         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1763         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1764         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1765         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1766         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1767         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1768 };
1769
1770 /*
1771  * RF value list for RF2525
1772  * Supports: 2.4 GHz
1773  */
1774 static const struct rf_channel rf_vals_bg_2525[] = {
1775         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1776         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1777         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1778         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1779         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1780         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1781         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1782         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1783         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1784         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1785         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1786         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1787         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1788         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1789 };
1790
1791 /*
1792  * RF value list for RF2525e
1793  * Supports: 2.4 GHz
1794  */
1795 static const struct rf_channel rf_vals_bg_2525e[] = {
1796         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1797         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1798         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1799         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1800         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1801         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1802         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1803         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1804         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1805         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1806         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1807         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1808         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1809         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1810 };
1811
1812 /*
1813  * RF value list for RF5222
1814  * Supports: 2.4 GHz & 5.2 GHz
1815  */
1816 static const struct rf_channel rf_vals_5222[] = {
1817         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1818         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1819         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1820         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1821         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1822         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1823         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1824         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1825         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1826         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1827         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1828         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1829         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1830         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1831
1832         /* 802.11 UNI / HyperLan 2 */
1833         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1834         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1835         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1836         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1837         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1838         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1839         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1840         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1841
1842         /* 802.11 HyperLan 2 */
1843         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1844         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1845         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1846         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1847         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1848         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1849         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1850         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1851         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1852         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1853
1854         /* 802.11 UNII */
1855         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1856         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1857         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1858         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1859         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1860 };
1861
1862 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1863 {
1864         struct hw_mode_spec *spec = &rt2x00dev->spec;
1865         struct channel_info *info;
1866         char *tx_power;
1867         unsigned int i;
1868
1869         /*
1870          * Initialize all hw fields.
1871          */
1872         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1873                                IEEE80211_HW_SIGNAL_DBM |
1874                                IEEE80211_HW_SUPPORTS_PS |
1875                                IEEE80211_HW_PS_NULLFUNC_STACK;
1876
1877         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1878         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1879                                 rt2x00_eeprom_addr(rt2x00dev,
1880                                                    EEPROM_MAC_ADDR_0));
1881
1882         /*
1883          * Initialize hw_mode information.
1884          */
1885         spec->supported_bands = SUPPORT_BAND_2GHZ;
1886         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1887
1888         if (rt2x00_rf(rt2x00dev, RF2522)) {
1889                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1890                 spec->channels = rf_vals_bg_2522;
1891         } else if (rt2x00_rf(rt2x00dev, RF2523)) {
1892                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1893                 spec->channels = rf_vals_bg_2523;
1894         } else if (rt2x00_rf(rt2x00dev, RF2524)) {
1895                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1896                 spec->channels = rf_vals_bg_2524;
1897         } else if (rt2x00_rf(rt2x00dev, RF2525)) {
1898                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1899                 spec->channels = rf_vals_bg_2525;
1900         } else if (rt2x00_rf(rt2x00dev, RF2525E)) {
1901                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1902                 spec->channels = rf_vals_bg_2525e;
1903         } else if (rt2x00_rf(rt2x00dev, RF5222)) {
1904                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1905                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1906                 spec->channels = rf_vals_5222;
1907         }
1908
1909         /*
1910          * Create channel information array
1911          */
1912         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
1913         if (!info)
1914                 return -ENOMEM;
1915
1916         spec->channels_info = info;
1917
1918         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1919         for (i = 0; i < 14; i++) {
1920                 info[i].max_power = MAX_TXPOWER;
1921                 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1922         }
1923
1924         if (spec->num_channels > 14) {
1925                 for (i = 14; i < spec->num_channels; i++) {
1926                         info[i].max_power = MAX_TXPOWER;
1927                         info[i].default_power1 = DEFAULT_TXPOWER;
1928                 }
1929         }
1930
1931         return 0;
1932 }
1933
1934 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1935 {
1936         int retval;
1937         u32 reg;
1938
1939         /*
1940          * Allocate eeprom data.
1941          */
1942         retval = rt2500pci_validate_eeprom(rt2x00dev);
1943         if (retval)
1944                 return retval;
1945
1946         retval = rt2500pci_init_eeprom(rt2x00dev);
1947         if (retval)
1948                 return retval;
1949
1950         /*
1951          * Enable rfkill polling by setting GPIO direction of the
1952          * rfkill switch GPIO pin correctly.
1953          */
1954         rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg);
1955         rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1);
1956         rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg);
1957
1958         /*
1959          * Initialize hw specifications.
1960          */
1961         retval = rt2500pci_probe_hw_mode(rt2x00dev);
1962         if (retval)
1963                 return retval;
1964
1965         /*
1966          * This device requires the atim queue and DMA-mapped skbs.
1967          */
1968         __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1969         __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1970         __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
1971
1972         /*
1973          * Set the rssi offset.
1974          */
1975         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1976
1977         return 0;
1978 }
1979
1980 /*
1981  * IEEE80211 stack callback functions.
1982  */
1983 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw,
1984                              struct ieee80211_vif *vif)
1985 {
1986         struct rt2x00_dev *rt2x00dev = hw->priv;
1987         u64 tsf;
1988         u32 reg;
1989
1990         rt2x00mmio_register_read(rt2x00dev, CSR17, &reg);
1991         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1992         rt2x00mmio_register_read(rt2x00dev, CSR16, &reg);
1993         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1994
1995         return tsf;
1996 }
1997
1998 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1999 {
2000         struct rt2x00_dev *rt2x00dev = hw->priv;
2001         u32 reg;
2002
2003         rt2x00mmio_register_read(rt2x00dev, CSR15, &reg);
2004         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
2005 }
2006
2007 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
2008         .tx                     = rt2x00mac_tx,
2009         .start                  = rt2x00mac_start,
2010         .stop                   = rt2x00mac_stop,
2011         .add_interface          = rt2x00mac_add_interface,
2012         .remove_interface       = rt2x00mac_remove_interface,
2013         .config                 = rt2x00mac_config,
2014         .configure_filter       = rt2x00mac_configure_filter,
2015         .sw_scan_start          = rt2x00mac_sw_scan_start,
2016         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
2017         .get_stats              = rt2x00mac_get_stats,
2018         .bss_info_changed       = rt2x00mac_bss_info_changed,
2019         .conf_tx                = rt2x00mac_conf_tx,
2020         .get_tsf                = rt2500pci_get_tsf,
2021         .tx_last_beacon         = rt2500pci_tx_last_beacon,
2022         .rfkill_poll            = rt2x00mac_rfkill_poll,
2023         .flush                  = rt2x00mac_flush,
2024         .set_antenna            = rt2x00mac_set_antenna,
2025         .get_antenna            = rt2x00mac_get_antenna,
2026         .get_ringparam          = rt2x00mac_get_ringparam,
2027         .tx_frames_pending      = rt2x00mac_tx_frames_pending,
2028 };
2029
2030 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
2031         .irq_handler            = rt2500pci_interrupt,
2032         .txstatus_tasklet       = rt2500pci_txstatus_tasklet,
2033         .tbtt_tasklet           = rt2500pci_tbtt_tasklet,
2034         .rxdone_tasklet         = rt2500pci_rxdone_tasklet,
2035         .probe_hw               = rt2500pci_probe_hw,
2036         .initialize             = rt2x00mmio_initialize,
2037         .uninitialize           = rt2x00mmio_uninitialize,
2038         .get_entry_state        = rt2500pci_get_entry_state,
2039         .clear_entry            = rt2500pci_clear_entry,
2040         .set_device_state       = rt2500pci_set_device_state,
2041         .rfkill_poll            = rt2500pci_rfkill_poll,
2042         .link_stats             = rt2500pci_link_stats,
2043         .reset_tuner            = rt2500pci_reset_tuner,
2044         .link_tuner             = rt2500pci_link_tuner,
2045         .start_queue            = rt2500pci_start_queue,
2046         .kick_queue             = rt2500pci_kick_queue,
2047         .stop_queue             = rt2500pci_stop_queue,
2048         .flush_queue            = rt2x00mmio_flush_queue,
2049         .write_tx_desc          = rt2500pci_write_tx_desc,
2050         .write_beacon           = rt2500pci_write_beacon,
2051         .fill_rxdone            = rt2500pci_fill_rxdone,
2052         .config_filter          = rt2500pci_config_filter,
2053         .config_intf            = rt2500pci_config_intf,
2054         .config_erp             = rt2500pci_config_erp,
2055         .config_ant             = rt2500pci_config_ant,
2056         .config                 = rt2500pci_config,
2057 };
2058
2059 static const struct data_queue_desc rt2500pci_queue_rx = {
2060         .entry_num              = 32,
2061         .data_size              = DATA_FRAME_SIZE,
2062         .desc_size              = RXD_DESC_SIZE,
2063         .priv_size              = sizeof(struct queue_entry_priv_mmio),
2064 };
2065
2066 static const struct data_queue_desc rt2500pci_queue_tx = {
2067         .entry_num              = 32,
2068         .data_size              = DATA_FRAME_SIZE,
2069         .desc_size              = TXD_DESC_SIZE,
2070         .priv_size              = sizeof(struct queue_entry_priv_mmio),
2071 };
2072
2073 static const struct data_queue_desc rt2500pci_queue_bcn = {
2074         .entry_num              = 1,
2075         .data_size              = MGMT_FRAME_SIZE,
2076         .desc_size              = TXD_DESC_SIZE,
2077         .priv_size              = sizeof(struct queue_entry_priv_mmio),
2078 };
2079
2080 static const struct data_queue_desc rt2500pci_queue_atim = {
2081         .entry_num              = 8,
2082         .data_size              = DATA_FRAME_SIZE,
2083         .desc_size              = TXD_DESC_SIZE,
2084         .priv_size              = sizeof(struct queue_entry_priv_mmio),
2085 };
2086
2087 static const struct rt2x00_ops rt2500pci_ops = {
2088         .name                   = KBUILD_MODNAME,
2089         .max_ap_intf            = 1,
2090         .eeprom_size            = EEPROM_SIZE,
2091         .rf_size                = RF_SIZE,
2092         .tx_queues              = NUM_TX_QUEUES,
2093         .extra_tx_headroom      = 0,
2094         .rx                     = &rt2500pci_queue_rx,
2095         .tx                     = &rt2500pci_queue_tx,
2096         .bcn                    = &rt2500pci_queue_bcn,
2097         .atim                   = &rt2500pci_queue_atim,
2098         .lib                    = &rt2500pci_rt2x00_ops,
2099         .hw                     = &rt2500pci_mac80211_ops,
2100 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2101         .debugfs                = &rt2500pci_rt2x00debug,
2102 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2103 };
2104
2105 /*
2106  * RT2500pci module information.
2107  */
2108 static DEFINE_PCI_DEVICE_TABLE(rt2500pci_device_table) = {
2109         { PCI_DEVICE(0x1814, 0x0201) },
2110         { 0, }
2111 };
2112
2113 MODULE_AUTHOR(DRV_PROJECT);
2114 MODULE_VERSION(DRV_VERSION);
2115 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
2116 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
2117 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
2118 MODULE_LICENSE("GPL");
2119
2120 static int rt2500pci_probe(struct pci_dev *pci_dev,
2121                            const struct pci_device_id *id)
2122 {
2123         return rt2x00pci_probe(pci_dev, &rt2500pci_ops);
2124 }
2125
2126 static struct pci_driver rt2500pci_driver = {
2127         .name           = KBUILD_MODNAME,
2128         .id_table       = rt2500pci_device_table,
2129         .probe          = rt2500pci_probe,
2130         .remove         = rt2x00pci_remove,
2131         .suspend        = rt2x00pci_suspend,
2132         .resume         = rt2x00pci_resume,
2133 };
2134
2135 module_pci_driver(rt2500pci_driver);