drivers/net/wireless/rtlwifi/rtl8192ce/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../regd.h"
  34 #include "../cam.h"
  35 #include "../ps.h"
  36 #include "../pci.h"
  37 #include "reg.h"
  38 #include "def.h"
  39 #include "phy.h"
  40 #include "../rtl8192c/dm_common.h"
  41 #include "../rtl8192c/fw_common.h"
  42 #include "../rtl8192c/phy_common.h"
  43 #include "dm.h"
  44 #include "led.h"
  45 #include "hw.h"
  46
  47 #define LLT_CONFIG      5
  48
  49 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  50                                       u8 set_bits, u8 clear_bits)
  51 {
  52         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  53         struct rtl_priv *rtlpriv = rtl_priv(hw);
  54
  55         rtlpci->reg_bcn_ctrl_val |= set_bits;
  56         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  57
  58         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
  59 }
  60
  61 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
  62 {
  63         struct rtl_priv *rtlpriv = rtl_priv(hw);
  64         u8 tmp1byte;
  65
  66         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  67         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  68         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  69         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  70         tmp1byte &= ~(BIT(0));
  71         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  72 }
  73
  74 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
  75 {
  76         struct rtl_priv *rtlpriv = rtl_priv(hw);
  77         u8 tmp1byte;
  78
  79         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  80         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
  81         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  82         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  83         tmp1byte |= BIT(0);
  84         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  85 }
  86
  87 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
  88 {
  89         _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
  90 }
  91
  92 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
  93 {
  94         _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
  95 }
  96
  97 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  98 {
  99         struct rtl_priv *rtlpriv = rtl_priv(hw);
 100         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 101         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 102
 103         switch (variable) {
 104         case HW_VAR_RCR:
 105                 *((u32 *) (val)) = rtlpci->receive_config;
 106                 break;
 107         case HW_VAR_RF_STATE:
 108                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 109                 break;
 110         case HW_VAR_FWLPS_RF_ON:{
 111                         enum rf_pwrstate rfState;
 112                         u32 val_rcr;
 113
 114                         rtlpriv->cfg->ops->get_hw_reg(hw,
 115                                                       HW_VAR_RF_STATE,
 116                                                       (u8 *) (&rfState));
 117                         if (rfState == ERFOFF) {
 118                                 *((bool *) (val)) = true;
 119                         } else {
 120                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 121                                 val_rcr &= 0x00070000;
 122                                 if (val_rcr)
 123                                         *((bool *) (val)) = false;
 124                                 else
 125                                         *((bool *) (val)) = true;
 126                         }
 127                         break;
 128                 }
 129         case HW_VAR_FW_PSMODE_STATUS:
 130                 *((bool *) (val)) = ppsc->fw_current_inpsmode;
 131                 break;
 132         case HW_VAR_CORRECT_TSF:{
 133                 u64 tsf;
 134                 u32 *ptsf_low = (u32 *)&tsf;
 135                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 136
 137                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 138                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 139
 140                 *((u64 *) (val)) = tsf;
 141
 142                 break;
 143                 }
 144         default:
 145                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 146                          "switch case not processed\n");
 147                 break;
 148         }
 149 }
 150
 151 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 152 {
 153         struct rtl_priv *rtlpriv = rtl_priv(hw);
 154         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 155         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 156         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 157         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 158         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 159         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 160         u8 idx;
 161
 162         switch (variable) {
 163         case HW_VAR_ETHER_ADDR:{
 164                         for (idx = 0; idx < ETH_ALEN; idx++) {
 165                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
 166                                                val[idx]);
 167                         }
 168                         break;
 169                 }
 170         case HW_VAR_BASIC_RATE:{
 171                         u16 rate_cfg = ((u16 *) val)[0];
 172                         u8 rate_index = 0;
 173                         rate_cfg &= 0x15f;
 174                         rate_cfg |= 0x01;
 175                         rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
 176                         rtl_write_byte(rtlpriv, REG_RRSR + 1,
 177                                        (rate_cfg >> 8) & 0xff);
 178                         while (rate_cfg > 0x1) {
 179                                 rate_cfg = (rate_cfg >> 1);
 180                                 rate_index++;
 181                         }
 182                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
 183                                        rate_index);
 184                         break;
 185                 }
 186         case HW_VAR_BSSID:{
 187                         for (idx = 0; idx < ETH_ALEN; idx++) {
 188                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 189                                                val[idx]);
 190                         }
 191                         break;
 192                 }
 193         case HW_VAR_SIFS:{
 194                         rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 195                         rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 196
 197                         rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 198                         rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 199
 200                         if (!mac->ht_enable)
 201                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 202                                                0x0e0e);
 203                         else
 204                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 205                                                *((u16 *) val));
 206                         break;
 207                 }
 208         case HW_VAR_SLOT_TIME:{
 209                         u8 e_aci;
 210
 211                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 212                                  "HW_VAR_SLOT_TIME %x\n", val[0]);
 213
 214                         rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 215
 216                         for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 217                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 218                                                               HW_VAR_AC_PARAM,
 219                                                               &e_aci);
 220                         }
 221                         break;
 222                 }
 223         case HW_VAR_ACK_PREAMBLE:{
 224                         u8 reg_tmp;
 225                         u8 short_preamble = (bool)*val;
 226                         reg_tmp = (mac->cur_40_prime_sc) << 5;
 227                         if (short_preamble)
 228                                 reg_tmp |= 0x80;
 229
 230                         rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
 231                         break;
 232                 }
 233         case HW_VAR_AMPDU_MIN_SPACE:{
 234                         u8 min_spacing_to_set;
 235                         u8 sec_min_space;
 236
 237                         min_spacing_to_set = *val;
 238                         if (min_spacing_to_set <= 7) {
 239                                 sec_min_space = 0;
 240
 241                                 if (min_spacing_to_set < sec_min_space)
 242                                         min_spacing_to_set = sec_min_space;
 243
 244                                 mac->min_space_cfg = ((mac->min_space_cfg &
 245                                                        0xf8) |
 246                                                       min_spacing_to_set);
 247
 248                                 *val = min_spacing_to_set;
 249
 250                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 251                                          "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 252                                          mac->min_space_cfg);
 253
 254                                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 255                                                mac->min_space_cfg);
 256                         }
 257                         break;
 258                 }
 259         case HW_VAR_SHORTGI_DENSITY:{
 260                         u8 density_to_set;
 261
 262                         density_to_set = *val;
 263                         mac->min_space_cfg |= (density_to_set << 3);
 264
 265                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 266                                  "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 267                                  mac->min_space_cfg);
 268
 269                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 270                                        mac->min_space_cfg);
 271
 272                         break;
 273                 }
 274         case HW_VAR_AMPDU_FACTOR:{
 275                         u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
 276                         u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
 277
 278                         u8 factor_toset;
 279                         u8 *p_regtoset = NULL;
 280                         u8 index = 0;
 281
 282                         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 283                             (rtlpcipriv->bt_coexist.bt_coexist_type ==
 284                             BT_CSR_BC4))
 285                                 p_regtoset = regtoset_bt;
 286                         else
 287                                 p_regtoset = regtoset_normal;
 288
 289                         factor_toset = *(val);
 290                         if (factor_toset <= 3) {
 291                                 factor_toset = (1 << (factor_toset + 2));
 292                                 if (factor_toset > 0xf)
 293                                         factor_toset = 0xf;
 294
 295                                 for (index = 0; index < 4; index++) {
 296                                         if ((p_regtoset[index] & 0xf0) >
 297                                             (factor_toset << 4))
 298                                                 p_regtoset[index] =
 299                                                     (p_regtoset[index] & 0x0f) |
 300                                                     (factor_toset << 4);
 301
 302                                         if ((p_regtoset[index] & 0x0f) >
 303                                             factor_toset)
 304                                                 p_regtoset[index] =
 305                                                     (p_regtoset[index] & 0xf0) |
 306                                                     (factor_toset);
 307
 308                                         rtl_write_byte(rtlpriv,
 309                                                        (REG_AGGLEN_LMT + index),
 310                                                        p_regtoset[index]);
 311
 312                                 }
 313
 314                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 315                                          "Set HW_VAR_AMPDU_FACTOR: %#x\n",
 316                                          factor_toset);
 317                         }
 318                         break;
 319                 }
 320         case HW_VAR_AC_PARAM:{
 321                         u8 e_aci = *(val);
 322                         rtl92c_dm_init_edca_turbo(hw);
 323
 324                         if (rtlpci->acm_method != EACMWAY2_SW)
 325                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 326                                                               HW_VAR_ACM_CTRL,
 327                                                               (&e_aci));
 328                         break;
 329                 }
 330         case HW_VAR_ACM_CTRL:{
 331                         u8 e_aci = *(val);
 332                         union aci_aifsn *p_aci_aifsn =
 333                             (union aci_aifsn *)(&(mac->ac[0].aifs));
 334                         u8 acm = p_aci_aifsn->f.acm;
 335                         u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 336
 337                         acm_ctrl =
 338                             acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 339
 340                         if (acm) {
 341                                 switch (e_aci) {
 342                                 case AC0_BE:
 343                                         acm_ctrl |= AcmHw_BeqEn;
 344                                         break;
 345                                 case AC2_VI:
 346                                         acm_ctrl |= AcmHw_ViqEn;
 347                                         break;
 348                                 case AC3_VO:
 349                                         acm_ctrl |= AcmHw_VoqEn;
 350                                         break;
 351                                 default:
 352                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 353                                                  "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 354                                                  acm);
 355                                         break;
 356                                 }
 357                         } else {
 358                                 switch (e_aci) {
 359                                 case AC0_BE:
 360                                         acm_ctrl &= (~AcmHw_BeqEn);
 361                                         break;
 362                                 case AC2_VI:
 363                                         acm_ctrl &= (~AcmHw_ViqEn);
 364                                         break;
 365                                 case AC3_VO:
 366                                         acm_ctrl &= (~AcmHw_BeqEn);
 367                                         break;
 368                                 default:
 369                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 370                                                  "switch case not processed\n");
 371                                         break;
 372                                 }
 373                         }
 374
 375                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 376                                  "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 377                                  acm_ctrl);
 378                         rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 379                         break;
 380                 }
 381         case HW_VAR_RCR:{
 382                         rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
 383                         rtlpci->receive_config = ((u32 *) (val))[0];
 384                         break;
 385                 }
 386         case HW_VAR_RETRY_LIMIT:{
 387                         u8 retry_limit = val[0];
 388
 389                         rtl_write_word(rtlpriv, REG_RL,
 390                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 391                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
 392                         break;
 393                 }
 394         case HW_VAR_DUAL_TSF_RST:
 395                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 396                 break;
 397         case HW_VAR_EFUSE_BYTES:
 398                 rtlefuse->efuse_usedbytes = *((u16 *) val);
 399                 break;
 400         case HW_VAR_EFUSE_USAGE:
 401                 rtlefuse->efuse_usedpercentage = *val;
 402                 break;
 403         case HW_VAR_IO_CMD:
 404                 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
 405                 break;
 406         case HW_VAR_WPA_CONFIG:
 407                 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
 408                 break;
 409         case HW_VAR_SET_RPWM:{
 410                         u8 rpwm_val;
 411
 412                         rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 413                         udelay(1);
 414
 415                         if (rpwm_val & BIT(7)) {
 416                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
 417                         } else {
 418                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 419                                                *val | BIT(7));
 420                         }
 421
 422                         break;
 423                 }
 424         case HW_VAR_H2C_FW_PWRMODE:{
 425                         u8 psmode = *val;
 426
 427                         if ((psmode != FW_PS_ACTIVE_MODE) &&
 428                             (!IS_92C_SERIAL(rtlhal->version))) {
 429                                 rtl92c_dm_rf_saving(hw, true);
 430                         }
 431
 432                         rtl92c_set_fw_pwrmode_cmd(hw, *val);
 433                         break;
 434                 }
 435         case HW_VAR_FW_PSMODE_STATUS:
 436                 ppsc->fw_current_inpsmode = *((bool *) val);
 437                 break;
 438         case HW_VAR_H2C_FW_JOINBSSRPT:{
 439                         u8 mstatus = *val;
 440                         u8 tmp_regcr, tmp_reg422;
 441                         bool recover = false;
 442
 443                         if (mstatus == RT_MEDIA_CONNECT) {
 444                                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 445                                                               NULL);
 446
 447                                 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 448                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 449                                                (tmp_regcr | BIT(0)));
 450
 451                                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
 452                                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
 453
 454                                 tmp_reg422 =
 455                                     rtl_read_byte(rtlpriv,
 456                                                   REG_FWHW_TXQ_CTRL + 2);
 457                                 if (tmp_reg422 & BIT(6))
 458                                         recover = true;
 459                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 460                                                tmp_reg422 & (~BIT(6)));
 461
 462                                 rtl92c_set_fw_rsvdpagepkt(hw, NULL);
 463
 464                                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
 465                                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
 466
 467                                 if (recover) {
 468                                         rtl_write_byte(rtlpriv,
 469                                                        REG_FWHW_TXQ_CTRL + 2,
 470                                                        tmp_reg422);
 471                                 }
 472
 473                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 474                                                (tmp_regcr & ~(BIT(0))));
 475                         }
 476                         rtl92c_set_fw_joinbss_report_cmd(hw, *val);
 477
 478                         break;
 479                 }
 480         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 481                 rtl92c_set_p2p_ps_offload_cmd(hw, *val);
 482                 break;
 483         case HW_VAR_AID:{
 484                         u16 u2btmp;
 485                         u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 486                         u2btmp &= 0xC000;
 487                         rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 488                                                 mac->assoc_id));
 489
 490                         break;
 491                 }
 492         case HW_VAR_CORRECT_TSF:{
 493                         u8 btype_ibss = val[0];
 494
 495                         if (btype_ibss)
 496                                 _rtl92ce_stop_tx_beacon(hw);
 497
 498                         _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
 499
 500                         rtl_write_dword(rtlpriv, REG_TSFTR,
 501                                         (u32) (mac->tsf & 0xffffffff));
 502                         rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 503                                         (u32) ((mac->tsf >> 32) & 0xffffffff));
 504
 505                         _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
 506
 507                         if (btype_ibss)
 508                                 _rtl92ce_resume_tx_beacon(hw);
 509
 510                         break;
 511
 512                 }
 513         case HW_VAR_FW_LPS_ACTION: {
 514                         bool enter_fwlps = *((bool *)val);
 515                         u8 rpwm_val, fw_pwrmode;
 516                         bool fw_current_inps;
 517
 518                         if (enter_fwlps) {
 519                                 rpwm_val = 0x02;        /* RF off */
 520                                 fw_current_inps = true;
 521                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 522                                                 HW_VAR_FW_PSMODE_STATUS,
 523                                                 (u8 *)(&fw_current_inps));
 524                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 525                                                 HW_VAR_H2C_FW_PWRMODE,
 526                                                 &ppsc->fwctrl_psmode);
 527
 528                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 529                                                               HW_VAR_SET_RPWM,
 530                                                               &rpwm_val);
 531                         } else {
 532                                 rpwm_val = 0x0C;        /* RF on */
 533                                 fw_pwrmode = FW_PS_ACTIVE_MODE;
 534                                 fw_current_inps = false;
 535                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 536                                                               HW_VAR_SET_RPWM,
 537                                                               &rpwm_val);
 538                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 539                                                 HW_VAR_H2C_FW_PWRMODE,
 540                                                 &fw_pwrmode);
 541
 542                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 543                                                 HW_VAR_FW_PSMODE_STATUS,
 544                                                 (u8 *)(&fw_current_inps));
 545                         }
 546                 break; }
 547         case HW_VAR_KEEP_ALIVE:
 548                 break;
 549         default:
 550                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 551                          "switch case %d not processed\n", variable);
 552                 break;
 553         }
 554 }
 555
 556 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 557 {
 558         struct rtl_priv *rtlpriv = rtl_priv(hw);
 559         bool status = true;
 560         long count = 0;
 561         u32 value = _LLT_INIT_ADDR(address) |
 562             _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
 563
 564         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 565
 566         do {
 567                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 568                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 569                         break;
 570
 571                 if (count > POLLING_LLT_THRESHOLD) {
 572                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 573                                  "Failed to polling write LLT done at address %d!\n",
 574                                  address);
 575                         status = false;
 576                         break;
 577                 }
 578         } while (++count);
 579
 580         return status;
 581 }
 582
 583 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
 584 {
 585         struct rtl_priv *rtlpriv = rtl_priv(hw);
 586         unsigned short i;
 587         u8 txpktbuf_bndy;
 588         u8 maxPage;
 589         bool status;
 590
 591 #if LLT_CONFIG == 1
 592         maxPage = 255;
 593         txpktbuf_bndy = 252;
 594 #elif LLT_CONFIG == 2
 595         maxPage = 127;
 596         txpktbuf_bndy = 124;
 597 #elif LLT_CONFIG == 3
 598         maxPage = 255;
 599         txpktbuf_bndy = 174;
 600 #elif LLT_CONFIG == 4
 601         maxPage = 255;
 602         txpktbuf_bndy = 246;
 603 #elif LLT_CONFIG == 5
 604         maxPage = 255;
 605         txpktbuf_bndy = 246;
 606 #endif
 607
 608 #if LLT_CONFIG == 1
 609         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
 610         rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
 611 #elif LLT_CONFIG == 2
 612         rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
 613 #elif LLT_CONFIG == 3
 614         rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
 615 #elif LLT_CONFIG == 4
 616         rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
 617 #elif LLT_CONFIG == 5
 618         rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
 619
 620         rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
 621 #endif
 622
 623         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
 624         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 625
 626         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 627         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 628
 629         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 630         rtl_write_byte(rtlpriv, REG_PBP, 0x11);
 631         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 632
 633         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 634                 status = _rtl92ce_llt_write(hw, i, i + 1);
 635                 if (true != status)
 636                         return status;
 637         }
 638
 639         status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 640         if (true != status)
 641                 return status;
 642
 643         for (i = txpktbuf_bndy; i < maxPage; i++) {
 644                 status = _rtl92ce_llt_write(hw, i, (i + 1));
 645                 if (true != status)
 646                         return status;
 647         }
 648
 649         status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy);
 650         if (true != status)
 651                 return status;
 652
 653         return true;
 654 }
 655
 656 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
 657 {
 658         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 659         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 660         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 661         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 662
 663         if (rtlpci->up_first_time)
 664                 return;
 665
 666         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 667                 rtl92ce_sw_led_on(hw, pLed0);
 668         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 669                 rtl92ce_sw_led_on(hw, pLed0);
 670         else
 671                 rtl92ce_sw_led_off(hw, pLed0);
 672 }
 673
 674 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
 675 {
 676         struct rtl_priv *rtlpriv = rtl_priv(hw);
 677         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 678         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 679         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 680
 681         unsigned char bytetmp;
 682         unsigned short wordtmp;
 683         u16 retry;
 684
 685         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 686         if (rtlpcipriv->bt_coexist.bt_coexistence) {
 687                 u32 value32;
 688                 value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO);
 689                 value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK);
 690                 rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32);
 691         }
 692         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
 693         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
 694
 695         if (rtlpcipriv->bt_coexist.bt_coexistence) {
 696                 u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
 697
 698                 u4b_tmp &= (~0x00024800);
 699                 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
 700         }
 701
 702         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
 703         udelay(2);
 704
 705         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 706         udelay(2);
 707
 708         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 709         udelay(2);
 710
 711         retry = 0;
 712         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
 713                  rtl_read_dword(rtlpriv, 0xEC), bytetmp);
 714
 715         while ((bytetmp & BIT(0)) && retry < 1000) {
 716                 retry++;
 717                 udelay(50);
 718                 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 719                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
 720                          rtl_read_dword(rtlpriv, 0xEC), bytetmp);
 721                 udelay(50);
 722         }
 723
 724         rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
 725
 726         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
 727         udelay(2);
 728
 729         if (rtlpcipriv->bt_coexist.bt_coexistence) {
 730                 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd;
 731                 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp);
 732         }
 733
 734         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 735
 736         if (!_rtl92ce_llt_table_init(hw))
 737                 return false;
 738
 739         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 740         rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
 741
 742         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
 743
 744         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 745         wordtmp &= 0xf;
 746         wordtmp |= 0xF771;
 747         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 748
 749         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 750         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 751         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 752
 753         rtl_write_byte(rtlpriv, 0x4d0, 0x0);
 754
 755         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 756                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 757                         DMA_BIT_MASK(32));
 758         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 759                         (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 760                         DMA_BIT_MASK(32));
 761         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 762                         (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 763         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 764                         (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 765         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 766                         (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 767         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 768                         (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 769         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 770                         (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 771                         DMA_BIT_MASK(32));
 772         rtl_write_dword(rtlpriv, REG_RX_DESA,
 773                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 774                         DMA_BIT_MASK(32));
 775
 776         if (IS_92C_SERIAL(rtlhal->version))
 777                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
 778         else
 779                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
 780
 781         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 782
 783         bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 784         rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
 785         do {
 786                 retry++;
 787                 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 788         } while ((retry < 200) && (bytetmp & BIT(7)));
 789
 790         _rtl92ce_gen_refresh_led_state(hw);
 791
 792         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 793
 794         return true;
 795 }
 796
 797 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
 798 {
 799         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 800         struct rtl_priv *rtlpriv = rtl_priv(hw);
 801         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 802         u8 reg_bw_opmode;
 803         u32 reg_prsr;
 804
 805         reg_bw_opmode = BW_OPMODE_20MHZ;
 806         reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 807
 808         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
 809
 810         rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 811
 812         rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
 813
 814         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
 815
 816         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
 817
 818         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
 819
 820         rtl_write_word(rtlpriv, REG_RL, 0x0707);
 821
 822         rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
 823
 824         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 825
 826         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
 827         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
 828         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
 829         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
 830
 831         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 832             (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
 833                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
 834         else
 835                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
 836
 837         rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
 838
 839         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
 840
 841         rtlpci->reg_bcn_ctrl_val = 0x1f;
 842         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
 843
 844         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 845
 846         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 847
 848         rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
 849         rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
 850
 851         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 852             (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
 853                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 854                 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
 855         } else {
 856                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 857                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 858         }
 859
 860         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 861              (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
 862                 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
 863         else
 864                 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
 865
 866         rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
 867
 868         rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
 869         rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
 870
 871         rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
 872
 873         rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
 874
 875         rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
 876         rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
 877
 878 }
 879
 880 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
 881 {
 882         struct rtl_priv *rtlpriv = rtl_priv(hw);
 883         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 884
 885         rtl_write_byte(rtlpriv, 0x34b, 0x93);
 886         rtl_write_word(rtlpriv, 0x350, 0x870c);
 887         rtl_write_byte(rtlpriv, 0x352, 0x1);
 888
 889         if (ppsc->support_backdoor)
 890                 rtl_write_byte(rtlpriv, 0x349, 0x1b);
 891         else
 892                 rtl_write_byte(rtlpriv, 0x349, 0x03);
 893
 894         rtl_write_word(rtlpriv, 0x350, 0x2718);
 895         rtl_write_byte(rtlpriv, 0x352, 0x1);
 896 }
 897
 898 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
 899 {
 900         struct rtl_priv *rtlpriv = rtl_priv(hw);
 901         u8 sec_reg_value;
 902
 903         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 904                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 905                  rtlpriv->sec.pairwise_enc_algorithm,
 906                  rtlpriv->sec.group_enc_algorithm);
 907
 908         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 909                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 910                          "not open hw encryption\n");
 911                 return;
 912         }
 913
 914         sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
 915
 916         if (rtlpriv->sec.use_defaultkey) {
 917                 sec_reg_value |= SCR_TxUseDK;
 918                 sec_reg_value |= SCR_RxUseDK;
 919         }
 920
 921         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
 922
 923         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
 924
 925         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
 926                  "The SECR-value %x\n", sec_reg_value);
 927
 928         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 929
 930 }
 931
 932 int rtl92ce_hw_init(struct ieee80211_hw *hw)
 933 {
 934         struct rtl_priv *rtlpriv = rtl_priv(hw);
 935         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 936         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 937         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 938         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 939         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 940         bool rtstatus = true;
 941         bool is92c;
 942         int err;
 943         u8 tmp_u1b;
 944         unsigned long flags;
 945
 946         rtlpci->being_init_adapter = true;
 947
 948         /* Since this function can take a very long time (up to 350 ms)
 949          * and can be called with irqs disabled, reenable the irqs
 950          * to let the other devices continue being serviced.
 951          *
 952          * It is safe doing so since our own interrupts will only be enabled
 953          * in a subsequent step.
 954          */
 955         local_save_flags(flags);
 956         local_irq_enable();
 957
 958         rtlpriv->intf_ops->disable_aspm(hw);
 959         rtstatus = _rtl92ce_init_mac(hw);
 960         if (!rtstatus) {
 961                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
 962                 err = 1;
 963                 goto exit;
 964         }
 965
 966         err = rtl92c_download_fw(hw);
 967         if (err) {
 968                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 969                          "Failed to download FW. Init HW without FW now..\n");
 970                 err = 1;
 971                 goto exit;
 972         }
 973
 974         rtlhal->last_hmeboxnum = 0;
 975         rtl92c_phy_mac_config(hw);
 976         /* because last function modify RCR, so we update
 977          * rcr var here, or TP will unstable for receive_config
 978          * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
 979          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
 980         rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
 981         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
 982         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 983         rtl92c_phy_bb_config(hw);
 984         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
 985         rtl92c_phy_rf_config(hw);
 986         if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
 987             !IS_92C_SERIAL(rtlhal->version)) {
 988                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
 989                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
 990         } else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) {
 991                 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE);
 992                 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31);
 993                 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425);
 994                 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200);
 995                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053);
 996                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201);
 997         }
 998         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
 999                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1000         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1001                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1002         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1003         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1004         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
1005         _rtl92ce_hw_configure(hw);
1006         rtl_cam_reset_all_entry(hw);
1007         rtl92ce_enable_hw_security_config(hw);
1008
1009         ppsc->rfpwr_state = ERFON;
1010
1011         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1012         _rtl92ce_enable_aspm_back_door(hw);
1013         rtlpriv->intf_ops->enable_aspm(hw);
1014
1015         rtl8192ce_bt_hw_init(hw);
1016
1017         if (ppsc->rfpwr_state == ERFON) {
1018                 rtl92c_phy_set_rfpath_switch(hw, 1);
1019                 if (rtlphy->iqk_initialized) {
1020                         rtl92c_phy_iq_calibrate(hw, true);
1021                 } else {
1022                         rtl92c_phy_iq_calibrate(hw, false);
1023                         rtlphy->iqk_initialized = true;
1024                 }
1025
1026                 rtl92c_dm_check_txpower_tracking(hw);
1027                 rtl92c_phy_lc_calibrate(hw);
1028         }
1029
1030         is92c = IS_92C_SERIAL(rtlhal->version);
1031         tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1032         if (!(tmp_u1b & BIT(0))) {
1033                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1034                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
1035         }
1036
1037         if (!(tmp_u1b & BIT(1)) && is92c) {
1038                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
1039                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path B\n");
1040         }
1041
1042         if (!(tmp_u1b & BIT(4))) {
1043                 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1044                 tmp_u1b &= 0x0F;
1045                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1046                 udelay(10);
1047                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1048                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
1049         }
1050         rtl92c_dm_init(hw);
1051 exit:
1052         local_irq_restore(flags);
1053         rtlpci->being_init_adapter = false;
1054         return err;
1055 }
1056
1057 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
1058 {
1059         struct rtl_priv *rtlpriv = rtl_priv(hw);
1060         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1061         enum version_8192c version = VERSION_UNKNOWN;
1062         u32 value32;
1063         const char *versionid;
1064
1065         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1066         if (value32 & TRP_VAUX_EN) {
1067                 version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
1068                            VERSION_A_CHIP_88C;
1069         } else {
1070                 version = (enum version_8192c) (CHIP_VER_B |
1071                                 ((value32 & TYPE_ID) ? CHIP_92C_BITMASK : 0) |
1072                                 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1073                 if ((!IS_CHIP_VENDOR_UMC(version)) && (value32 &
1074                      CHIP_VER_RTL_MASK)) {
1075                         version = (enum version_8192c)(version |
1076                                    ((((value32 & CHIP_VER_RTL_MASK) == BIT(12))
1077                                    ? CHIP_VENDOR_UMC_B_CUT : CHIP_UNKNOWN) |
1078                                    CHIP_VENDOR_UMC));
1079                 }
1080                 if (IS_92C_SERIAL(version)) {
1081                         value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM);
1082                         version = (enum version_8192c)(version |
1083                                    ((CHIP_BONDING_IDENTIFIER(value32)
1084                                    == CHIP_BONDING_92C_1T2R) ?
1085                                    RF_TYPE_1T2R : 0));
1086                 }
1087         }
1088
1089         switch (version) {
1090         case VERSION_B_CHIP_92C:
1091                 versionid = "B_CHIP_92C";
1092                 break;
1093         case VERSION_B_CHIP_88C:
1094                 versionid = "B_CHIP_88C";
1095                 break;
1096         case VERSION_A_CHIP_92C:
1097                 versionid = "A_CHIP_92C";
1098                 break;
1099         case VERSION_A_CHIP_88C:
1100                 versionid = "A_CHIP_88C";
1101                 break;
1102         case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
1103                 versionid = "A_CUT_92C_1T2R";
1104                 break;
1105         case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
1106                 versionid = "A_CUT_92C";
1107                 break;
1108         case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
1109                 versionid = "A_CUT_88C";
1110                 break;
1111         case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
1112                 versionid = "B_CUT_92C_1T2R";
1113                 break;
1114         case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
1115                 versionid = "B_CUT_92C";
1116                 break;
1117         case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
1118                 versionid = "B_CUT_88C";
1119                 break;
1120         default:
1121                 versionid = "Unknown. Bug?";
1122                 break;
1123         }
1124
1125         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1126                  "Chip Version ID: %s\n", versionid);
1127
1128         switch (version & 0x3) {
1129         case CHIP_88C:
1130                 rtlphy->rf_type = RF_1T1R;
1131                 break;
1132         case CHIP_92C:
1133                 rtlphy->rf_type = RF_2T2R;
1134                 break;
1135         case CHIP_92C_1T2R:
1136                 rtlphy->rf_type = RF_1T2R;
1137                 break;
1138         default:
1139                 rtlphy->rf_type = RF_1T1R;
1140                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1141                          "ERROR RF_Type is set!!\n");
1142                 break;
1143         }
1144
1145         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1146                  rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R");
1147
1148         return version;
1149 }
1150
1151 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
1152                                      enum nl80211_iftype type)
1153 {
1154         struct rtl_priv *rtlpriv = rtl_priv(hw);
1155         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1156         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1157         bt_msr &= 0xfc;
1158
1159         if (type == NL80211_IFTYPE_UNSPECIFIED ||
1160             type == NL80211_IFTYPE_STATION) {
1161                 _rtl92ce_stop_tx_beacon(hw);
1162                 _rtl92ce_enable_bcn_sub_func(hw);
1163         } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP ||
1164                    type == NL80211_IFTYPE_MESH_POINT) {
1165                 _rtl92ce_resume_tx_beacon(hw);
1166                 _rtl92ce_disable_bcn_sub_func(hw);
1167         } else {
1168                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1169                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",
1170                          type);
1171         }
1172
1173         switch (type) {
1174         case NL80211_IFTYPE_UNSPECIFIED:
1175                 bt_msr |= MSR_NOLINK;
1176                 ledaction = LED_CTL_LINK;
1177                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1178                          "Set Network type to NO LINK!\n");
1179                 break;
1180         case NL80211_IFTYPE_ADHOC:
1181                 bt_msr |= MSR_ADHOC;
1182                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1183                          "Set Network type to Ad Hoc!\n");
1184                 break;
1185         case NL80211_IFTYPE_STATION:
1186                 bt_msr |= MSR_INFRA;
1187                 ledaction = LED_CTL_LINK;
1188                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1189                          "Set Network type to STA!\n");
1190                 break;
1191         case NL80211_IFTYPE_AP:
1192                 bt_msr |= MSR_AP;
1193                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1194                          "Set Network type to AP!\n");
1195                 break;
1196         case NL80211_IFTYPE_MESH_POINT:
1197                 bt_msr |= MSR_ADHOC;
1198                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1199                          "Set Network type to Mesh Point!\n");
1200                 break;
1201         default:
1202                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1203                          "Network type %d not supported!\n", type);
1204                 return 1;
1205
1206         }
1207
1208         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1209         rtlpriv->cfg->ops->led_control(hw, ledaction);
1210         if ((bt_msr & MSR_MASK) == MSR_AP)
1211                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1212         else
1213                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1214         return 0;
1215 }
1216
1217 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1218 {
1219         struct rtl_priv *rtlpriv = rtl_priv(hw);
1220         u32 reg_rcr;
1221
1222         if (rtlpriv->psc.rfpwr_state != ERFON)
1223                 return;
1224
1225         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1226
1227         if (check_bssid) {
1228                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1229                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1230                                               (u8 *) (&reg_rcr));
1231                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
1232         } else if (!check_bssid) {
1233                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1234                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
1235                 rtlpriv->cfg->ops->set_hw_reg(hw,
1236                                               HW_VAR_RCR, (u8 *) (&reg_rcr));
1237         }
1238
1239 }
1240
1241 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1242 {
1243         struct rtl_priv *rtlpriv = rtl_priv(hw);
1244
1245         if (_rtl92ce_set_media_status(hw, type))
1246                 return -EOPNOTSUPP;
1247
1248         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1249                 if (type != NL80211_IFTYPE_AP &&
1250                     type != NL80211_IFTYPE_MESH_POINT)
1251                         rtl92ce_set_check_bssid(hw, true);
1252         } else {
1253                 rtl92ce_set_check_bssid(hw, false);
1254         }
1255
1256         return 0;
1257 }
1258
1259 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1260 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1261 {
1262         struct rtl_priv *rtlpriv = rtl_priv(hw);
1263         rtl92c_dm_init_edca_turbo(hw);
1264         switch (aci) {
1265         case AC1_BK:
1266                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1267                 break;
1268         case AC0_BE:
1269                 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1270                 break;
1271         case AC2_VI:
1272                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1273                 break;
1274         case AC3_VO:
1275                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1276                 break;
1277         default:
1278                 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1279                 break;
1280         }
1281 }
1282
1283 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1284 {
1285         struct rtl_priv *rtlpriv = rtl_priv(hw);
1286         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1287
1288         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1289         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1290 }
1291
1292 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1293 {
1294         struct rtl_priv *rtlpriv = rtl_priv(hw);
1295         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1296
1297         rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1298         rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1299         synchronize_irq(rtlpci->pdev->irq);
1300 }
1301
1302 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1303 {
1304         struct rtl_priv *rtlpriv = rtl_priv(hw);
1305         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1306         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1307         u8 u1b_tmp;
1308         u32 u4b_tmp;
1309
1310         rtlpriv->intf_ops->enable_aspm(hw);
1311         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1312         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1313         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1314         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1315         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1316         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1317         if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7))
1318                 rtl92c_firmware_selfreset(hw);
1319         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1320         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1321         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1322         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1323         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1324              ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
1325              (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8))) {
1326                 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 |
1327                                 (u1b_tmp << 8));
1328         } else {
1329                 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
1330                                 (u1b_tmp << 8));
1331         }
1332         rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1333         rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1334         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1335         if (!IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version))
1336                 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1337         if (rtlpcipriv->bt_coexist.bt_coexistence) {
1338                 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
1339                 u4b_tmp |= 0x03824800;
1340                 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
1341         } else {
1342                 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1343         }
1344
1345         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1346         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1347 }
1348
1349 void rtl92ce_card_disable(struct ieee80211_hw *hw)
1350 {
1351         struct rtl_priv *rtlpriv = rtl_priv(hw);
1352         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1353         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1354         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1355         enum nl80211_iftype opmode;
1356
1357         mac->link_state = MAC80211_NOLINK;
1358         opmode = NL80211_IFTYPE_UNSPECIFIED;
1359         _rtl92ce_set_media_status(hw, opmode);
1360         if (rtlpci->driver_is_goingto_unload ||
1361             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1362                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1363         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1364         _rtl92ce_poweroff_adapter(hw);
1365
1366         /* after power off we should do iqk again */
1367         rtlpriv->phy.iqk_initialized = false;
1368 }
1369
1370 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
1371                                   u32 *p_inta, u32 *p_intb)
1372 {
1373         struct rtl_priv *rtlpriv = rtl_priv(hw);
1374         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1375
1376         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1377         rtl_write_dword(rtlpriv, ISR, *p_inta);
1378
1379         /*
1380          * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1381          * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1382          */
1383 }
1384
1385 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
1386 {
1387
1388         struct rtl_priv *rtlpriv = rtl_priv(hw);
1389         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1390         u16 bcn_interval, atim_window;
1391
1392         bcn_interval = mac->beacon_interval;
1393         atim_window = 2;        /*FIX MERGE */
1394         rtl92ce_disable_interrupt(hw);
1395         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1396         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1397         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1398         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1399         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1400         rtl_write_byte(rtlpriv, 0x606, 0x30);
1401         rtl92ce_enable_interrupt(hw);
1402 }
1403
1404 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
1405 {
1406         struct rtl_priv *rtlpriv = rtl_priv(hw);
1407         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1408         u16 bcn_interval = mac->beacon_interval;
1409
1410         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1411                  "beacon_interval:%d\n", bcn_interval);
1412         rtl92ce_disable_interrupt(hw);
1413         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1414         rtl92ce_enable_interrupt(hw);
1415 }
1416
1417 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1418                                    u32 add_msr, u32 rm_msr)
1419 {
1420         struct rtl_priv *rtlpriv = rtl_priv(hw);
1421         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1422
1423         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1424                  add_msr, rm_msr);
1425
1426         if (add_msr)
1427                 rtlpci->irq_mask[0] |= add_msr;
1428         if (rm_msr)
1429                 rtlpci->irq_mask[0] &= (~rm_msr);
1430         rtl92ce_disable_interrupt(hw);
1431         rtl92ce_enable_interrupt(hw);
1432 }
1433
1434 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1435                                                  bool autoload_fail,
1436                                                  u8 *hwinfo)
1437 {
1438         struct rtl_priv *rtlpriv = rtl_priv(hw);
1439         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1440         u8 rf_path, index, tempval;
1441         u16 i;
1442
1443         for (rf_path = 0; rf_path < 2; rf_path++) {
1444                 for (i = 0; i < 3; i++) {
1445                         if (!autoload_fail) {
1446                                 rtlefuse->
1447                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
1448                                     hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1449                                 rtlefuse->
1450                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1451                                     hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
1452                                            i];
1453                         } else {
1454                                 rtlefuse->
1455                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
1456                                     EEPROM_DEFAULT_TXPOWERLEVEL;
1457                                 rtlefuse->
1458                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1459                                     EEPROM_DEFAULT_TXPOWERLEVEL;
1460                         }
1461                 }
1462         }
1463
1464         for (i = 0; i < 3; i++) {
1465                 if (!autoload_fail)
1466                         tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1467                 else
1468                         tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1469                 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
1470                     (tempval & 0xf);
1471                 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
1472                     ((tempval & 0xf0) >> 4);
1473         }
1474
1475         for (rf_path = 0; rf_path < 2; rf_path++)
1476                 for (i = 0; i < 3; i++)
1477                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1478                                 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1479                                 rf_path, i,
1480                                 rtlefuse->
1481                                 eeprom_chnlarea_txpwr_cck[rf_path][i]);
1482         for (rf_path = 0; rf_path < 2; rf_path++)
1483                 for (i = 0; i < 3; i++)
1484                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1485                                 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1486                                 rf_path, i,
1487                                 rtlefuse->
1488                                 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
1489         for (rf_path = 0; rf_path < 2; rf_path++)
1490                 for (i = 0; i < 3; i++)
1491                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1492                                 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1493                                 rf_path, i,
1494                                 rtlefuse->
1495                                 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]);
1496
1497         for (rf_path = 0; rf_path < 2; rf_path++) {
1498                 for (i = 0; i < 14; i++) {
1499                         index = rtl92c_get_chnl_group((u8)i);
1500
1501                         rtlefuse->txpwrlevel_cck[rf_path][i] =
1502                             rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
1503                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1504                             rtlefuse->
1505                             eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
1506
1507                         if ((rtlefuse->
1508                              eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1509                              rtlefuse->
1510                              eprom_chnl_txpwr_ht40_2sdf[rf_path][index])
1511                             > 0) {
1512                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1513                                     rtlefuse->
1514                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path]
1515                                     [index] -
1516                                     rtlefuse->
1517                                     eprom_chnl_txpwr_ht40_2sdf[rf_path]
1518                                     [index];
1519                         } else {
1520                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1521                         }
1522                 }
1523
1524                 for (i = 0; i < 14; i++) {
1525                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1526                                 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1527                                 rf_path, i,
1528                                 rtlefuse->txpwrlevel_cck[rf_path][i],
1529                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1530                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1531                 }
1532         }
1533
1534         for (i = 0; i < 3; i++) {
1535                 if (!autoload_fail) {
1536                         rtlefuse->eeprom_pwrlimit_ht40[i] =
1537                             hwinfo[EEPROM_TXPWR_GROUP + i];
1538                         rtlefuse->eeprom_pwrlimit_ht20[i] =
1539                             hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1540                 } else {
1541                         rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1542                         rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1543                 }
1544         }
1545
1546         for (rf_path = 0; rf_path < 2; rf_path++) {
1547                 for (i = 0; i < 14; i++) {
1548                         index = rtl92c_get_chnl_group((u8)i);
1549
1550                         if (rf_path == RF90_PATH_A) {
1551                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1552                                     (rtlefuse->eeprom_pwrlimit_ht20[index]
1553                                      & 0xf);
1554                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1555                                     (rtlefuse->eeprom_pwrlimit_ht40[index]
1556                                      & 0xf);
1557                         } else if (rf_path == RF90_PATH_B) {
1558                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1559                                     ((rtlefuse->eeprom_pwrlimit_ht20[index]
1560                                       & 0xf0) >> 4);
1561                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1562                                     ((rtlefuse->eeprom_pwrlimit_ht40[index]
1563                                       & 0xf0) >> 4);
1564                         }
1565
1566                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1567                                 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1568                                 rf_path, i,
1569                                 rtlefuse->pwrgroup_ht20[rf_path][i]);
1570                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1571                                 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1572                                 rf_path, i,
1573                                 rtlefuse->pwrgroup_ht40[rf_path][i]);
1574                 }
1575         }
1576
1577         for (i = 0; i < 14; i++) {
1578                 index = rtl92c_get_chnl_group((u8)i);
1579
1580                 if (!autoload_fail)
1581                         tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1582                 else
1583                         tempval = EEPROM_DEFAULT_HT20_DIFF;
1584
1585                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1586                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1587                     ((tempval >> 4) & 0xF);
1588
1589                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1590                         rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1591
1592                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1593                         rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1594
1595                 index = rtl92c_get_chnl_group((u8)i);
1596
1597                 if (!autoload_fail)
1598                         tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1599                 else
1600                         tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1601
1602                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1603                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1604                     ((tempval >> 4) & 0xF);
1605         }
1606
1607         rtlefuse->legacy_ht_txpowerdiff =
1608             rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1609
1610         for (i = 0; i < 14; i++)
1611                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1612                         "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1613                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1614         for (i = 0; i < 14; i++)
1615                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1616                         "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1617                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1618         for (i = 0; i < 14; i++)
1619                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1620                         "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1621                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1622         for (i = 0; i < 14; i++)
1623                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1624                         "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1625                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1626
1627         if (!autoload_fail)
1628                 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1629         else
1630                 rtlefuse->eeprom_regulatory = 0;
1631         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1632                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1633
1634         if (!autoload_fail) {
1635                 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1636                 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
1637         } else {
1638                 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1639                 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1640         }
1641         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1642                 rtlefuse->eeprom_tssi[RF90_PATH_A],
1643                 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1644
1645         if (!autoload_fail)
1646                 tempval = hwinfo[EEPROM_THERMAL_METER];
1647         else
1648                 tempval = EEPROM_DEFAULT_THERMALMETER;
1649         rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1650
1651         if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1652                 rtlefuse->apk_thermalmeterignore = true;
1653
1654         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1655         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1656                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1657 }
1658
1659 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1660 {
1661         struct rtl_priv *rtlpriv = rtl_priv(hw);
1662         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1663         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1664         u16 i, usvalue;
1665         u8 hwinfo[HWSET_MAX_SIZE];
1666         u16 eeprom_id;
1667
1668         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1669                 rtl_efuse_shadow_map_update(hw);
1670
1671                 memcpy((void *)hwinfo,
1672                        (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1673                        HWSET_MAX_SIZE);
1674         } else if (rtlefuse->epromtype == EEPROM_93C46) {
1675                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1676                          "RTL819X Not boot from eeprom, check it !!");
1677         }
1678
1679         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
1680                       hwinfo, HWSET_MAX_SIZE);
1681
1682         eeprom_id = *((u16 *)&hwinfo[0]);
1683         if (eeprom_id != RTL8190_EEPROM_ID) {
1684                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1685                          "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1686                 rtlefuse->autoload_failflag = true;
1687         } else {
1688                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1689                 rtlefuse->autoload_failflag = false;
1690         }
1691
1692         if (rtlefuse->autoload_failflag)
1693                 return;
1694
1695         rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1696         rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1697         rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1698         rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1699         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1700                  "EEPROMId = 0x%4x\n", eeprom_id);
1701         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1702                  "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1703         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1704                  "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1705         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1706                  "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1707         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1708                  "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1709
1710         for (i = 0; i < 6; i += 2) {
1711                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1712                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1713         }
1714
1715         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1716
1717         _rtl92ce_read_txpower_info_from_hwpg(hw,
1718                                              rtlefuse->autoload_failflag,
1719                                              hwinfo);
1720
1721         rtl8192ce_read_bt_coexist_info_from_hwpg(hw,
1722                                                  rtlefuse->autoload_failflag,
1723                                                  hwinfo);
1724
1725         rtlefuse->eeprom_channelplan = *&hwinfo[EEPROM_CHANNELPLAN];
1726         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1727         rtlefuse->txpwr_fromeprom = true;
1728         rtlefuse->eeprom_oemid = *&hwinfo[EEPROM_CUSTOMER_ID];
1729
1730         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1731                  "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1732
1733         /* set channel paln to world wide 13 */
1734         rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1735
1736         if (rtlhal->oem_id == RT_CID_DEFAULT) {
1737                 switch (rtlefuse->eeprom_oemid) {
1738                 case EEPROM_CID_DEFAULT:
1739                         if (rtlefuse->eeprom_did == 0x8176) {
1740                                 if ((rtlefuse->eeprom_svid == 0x103C &&
1741                                      rtlefuse->eeprom_smid == 0x1629))
1742                                         rtlhal->oem_id = RT_CID_819X_HP;
1743                                 else
1744                                         rtlhal->oem_id = RT_CID_DEFAULT;
1745                         } else {
1746                                 rtlhal->oem_id = RT_CID_DEFAULT;
1747                         }
1748                         break;
1749                 case EEPROM_CID_TOSHIBA:
1750                         rtlhal->oem_id = RT_CID_TOSHIBA;
1751                         break;
1752                 case EEPROM_CID_QMI:
1753                         rtlhal->oem_id = RT_CID_819X_QMI;
1754                         break;
1755                 case EEPROM_CID_WHQL:
1756                 default:
1757                         rtlhal->oem_id = RT_CID_DEFAULT;
1758                         break;
1759
1760                 }
1761         }
1762
1763 }
1764
1765 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1766 {
1767         struct rtl_priv *rtlpriv = rtl_priv(hw);
1768         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1769         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1770
1771         switch (rtlhal->oem_id) {
1772         case RT_CID_819X_HP:
1773                 pcipriv->ledctl.led_opendrain = true;
1774                 break;
1775         case RT_CID_819X_LENOVO:
1776         case RT_CID_DEFAULT:
1777         case RT_CID_TOSHIBA:
1778         case RT_CID_CCX:
1779         case RT_CID_819X_ACER:
1780         case RT_CID_WHQL:
1781         default:
1782                 break;
1783         }
1784         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1785                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1786 }
1787
1788 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1789 {
1790         struct rtl_priv *rtlpriv = rtl_priv(hw);
1791         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1792         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1793         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1794         u8 tmp_u1b;
1795
1796         rtlhal->version = _rtl92ce_read_chip_version(hw);
1797         if (get_rf_type(rtlphy) == RF_1T1R)
1798                 rtlpriv->dm.rfpath_rxenable[0] = true;
1799         else
1800                 rtlpriv->dm.rfpath_rxenable[0] =
1801                     rtlpriv->dm.rfpath_rxenable[1] = true;
1802         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1803                  rtlhal->version);
1804         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1805         if (tmp_u1b & BIT(4)) {
1806                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1807                 rtlefuse->epromtype = EEPROM_93C46;
1808         } else {
1809                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1810                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1811         }
1812         if (tmp_u1b & BIT(5)) {
1813                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1814                 rtlefuse->autoload_failflag = false;
1815                 _rtl92ce_read_adapter_info(hw);
1816         } else {
1817                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1818         }
1819         _rtl92ce_hal_customized_behavior(hw);
1820 }
1821
1822 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw,
1823                 struct ieee80211_sta *sta)
1824 {
1825         struct rtl_priv *rtlpriv = rtl_priv(hw);
1826         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1827         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1828         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1829         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1830         u32 ratr_value;
1831         u8 ratr_index = 0;
1832         u8 nmode = mac->ht_enable;
1833         u8 mimo_ps = IEEE80211_SMPS_OFF;
1834         u16 shortgi_rate;
1835         u32 tmp_ratr_value;
1836         u8 curtxbw_40mhz = mac->bw_40;
1837         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1838                                1 : 0;
1839         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1840                                1 : 0;
1841         enum wireless_mode wirelessmode = mac->mode;
1842
1843         if (rtlhal->current_bandtype == BAND_ON_5G)
1844                 ratr_value = sta->supp_rates[1] << 4;
1845         else
1846                 ratr_value = sta->supp_rates[0];
1847         if (mac->opmode == NL80211_IFTYPE_ADHOC)
1848                 ratr_value = 0xfff;
1849
1850         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1851                         sta->ht_cap.mcs.rx_mask[0] << 12);
1852         switch (wirelessmode) {
1853         case WIRELESS_MODE_B:
1854                 if (ratr_value & 0x0000000c)
1855                         ratr_value &= 0x0000000d;
1856                 else
1857                         ratr_value &= 0x0000000f;
1858                 break;
1859         case WIRELESS_MODE_G:
1860                 ratr_value &= 0x00000FF5;
1861                 break;
1862         case WIRELESS_MODE_N_24G:
1863         case WIRELESS_MODE_N_5G:
1864                 nmode = 1;
1865                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1866                         ratr_value &= 0x0007F005;
1867                 } else {
1868                         u32 ratr_mask;
1869
1870                         if (get_rf_type(rtlphy) == RF_1T2R ||
1871                             get_rf_type(rtlphy) == RF_1T1R)
1872                                 ratr_mask = 0x000ff005;
1873                         else
1874                                 ratr_mask = 0x0f0ff005;
1875
1876                         ratr_value &= ratr_mask;
1877                 }
1878                 break;
1879         default:
1880                 if (rtlphy->rf_type == RF_1T2R)
1881                         ratr_value &= 0x000ff0ff;
1882                 else
1883                         ratr_value &= 0x0f0ff0ff;
1884
1885                 break;
1886         }
1887
1888         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1889             (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) &&
1890             (rtlpcipriv->bt_coexist.bt_cur_state) &&
1891             (rtlpcipriv->bt_coexist.bt_ant_isolation) &&
1892             ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ||
1893             (rtlpcipriv->bt_coexist.bt_service == BT_BUSY)))
1894                 ratr_value &= 0x0fffcfc0;
1895         else
1896                 ratr_value &= 0x0FFFFFFF;
1897
1898         if (nmode && ((curtxbw_40mhz &&
1899                          curshortgi_40mhz) || (!curtxbw_40mhz &&
1900                                                curshortgi_20mhz))) {
1901
1902                 ratr_value |= 0x10000000;
1903                 tmp_ratr_value = (ratr_value >> 12);
1904
1905                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1906                         if ((1 << shortgi_rate) & tmp_ratr_value)
1907                                 break;
1908                 }
1909
1910                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1911                     (shortgi_rate << 4) | (shortgi_rate);
1912         }
1913
1914         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1915
1916         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1917                  rtl_read_dword(rtlpriv, REG_ARFR0));
1918 }
1919
1920 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw,
1921                 struct ieee80211_sta *sta, u8 rssi_level)
1922 {
1923         struct rtl_priv *rtlpriv = rtl_priv(hw);
1924         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1925         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1926         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1927         struct rtl_sta_info *sta_entry = NULL;
1928         u32 ratr_bitmap;
1929         u8 ratr_index;
1930         u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
1931         u8 curshortgi_40mhz = curtxbw_40mhz &&
1932                               (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1933                                 1 : 0;
1934         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1935                                 1 : 0;
1936         enum wireless_mode wirelessmode = 0;
1937         bool shortgi = false;
1938         u8 rate_mask[5];
1939         u8 macid = 0;
1940         u8 mimo_ps = IEEE80211_SMPS_OFF;
1941
1942         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1943         wirelessmode = sta_entry->wireless_mode;
1944         if (mac->opmode == NL80211_IFTYPE_STATION ||
1945             mac->opmode == NL80211_IFTYPE_MESH_POINT)
1946                 curtxbw_40mhz = mac->bw_40;
1947         else if (mac->opmode == NL80211_IFTYPE_AP ||
1948                 mac->opmode == NL80211_IFTYPE_ADHOC)
1949                 macid = sta->aid + 1;
1950
1951         if (rtlhal->current_bandtype == BAND_ON_5G)
1952                 ratr_bitmap = sta->supp_rates[1] << 4;
1953         else
1954                 ratr_bitmap = sta->supp_rates[0];
1955         if (mac->opmode == NL80211_IFTYPE_ADHOC)
1956                 ratr_bitmap = 0xfff;
1957         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1958                         sta->ht_cap.mcs.rx_mask[0] << 12);
1959         switch (wirelessmode) {
1960         case WIRELESS_MODE_B:
1961                 ratr_index = RATR_INX_WIRELESS_B;
1962                 if (ratr_bitmap & 0x0000000c)
1963                         ratr_bitmap &= 0x0000000d;
1964                 else
1965                         ratr_bitmap &= 0x0000000f;
1966                 break;
1967         case WIRELESS_MODE_G:
1968                 ratr_index = RATR_INX_WIRELESS_GB;
1969
1970                 if (rssi_level == 1)
1971                         ratr_bitmap &= 0x00000f00;
1972                 else if (rssi_level == 2)
1973                         ratr_bitmap &= 0x00000ff0;
1974                 else
1975                         ratr_bitmap &= 0x00000ff5;
1976                 break;
1977         case WIRELESS_MODE_A:
1978                 ratr_index = RATR_INX_WIRELESS_A;
1979                 ratr_bitmap &= 0x00000ff0;
1980                 break;
1981         case WIRELESS_MODE_N_24G:
1982         case WIRELESS_MODE_N_5G:
1983                 ratr_index = RATR_INX_WIRELESS_NGB;
1984
1985                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1986                         if (rssi_level == 1)
1987                                 ratr_bitmap &= 0x00070000;
1988                         else if (rssi_level == 2)
1989                                 ratr_bitmap &= 0x0007f000;
1990                         else
1991                                 ratr_bitmap &= 0x0007f005;
1992                 } else {
1993                         if (rtlphy->rf_type == RF_1T2R ||
1994                             rtlphy->rf_type == RF_1T1R) {
1995                                 if (curtxbw_40mhz) {
1996                                         if (rssi_level == 1)
1997                                                 ratr_bitmap &= 0x000f0000;
1998                                         else if (rssi_level == 2)
1999                                                 ratr_bitmap &= 0x000ff000;
2000                                         else
2001                                                 ratr_bitmap &= 0x000ff015;
2002                                 } else {
2003                                         if (rssi_level == 1)
2004                                                 ratr_bitmap &= 0x000f0000;
2005                                         else if (rssi_level == 2)
2006                                                 ratr_bitmap &= 0x000ff000;
2007                                         else
2008                                                 ratr_bitmap &= 0x000ff005;
2009                                 }
2010                         } else {
2011                                 if (curtxbw_40mhz) {
2012                                         if (rssi_level == 1)
2013                                                 ratr_bitmap &= 0x0f0f0000;
2014                                         else if (rssi_level == 2)
2015                                                 ratr_bitmap &= 0x0f0ff000;
2016                                         else
2017                                                 ratr_bitmap &= 0x0f0ff015;
2018                                 } else {
2019                                         if (rssi_level == 1)
2020                                                 ratr_bitmap &= 0x0f0f0000;
2021                                         else if (rssi_level == 2)
2022                                                 ratr_bitmap &= 0x0f0ff000;
2023                                         else
2024                                                 ratr_bitmap &= 0x0f0ff005;
2025                                 }
2026                         }
2027                 }
2028
2029                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2030                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2031
2032                         if (macid == 0)
2033                                 shortgi = true;
2034                         else if (macid == 1)
2035                                 shortgi = false;
2036                 }
2037                 break;
2038         default:
2039                 ratr_index = RATR_INX_WIRELESS_NGB;
2040
2041                 if (rtlphy->rf_type == RF_1T2R)
2042                         ratr_bitmap &= 0x000ff0ff;
2043                 else
2044                         ratr_bitmap &= 0x0f0ff0ff;
2045                 break;
2046         }
2047         sta_entry->ratr_index = ratr_index;
2048
2049         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2050                  "ratr_bitmap :%x\n", ratr_bitmap);
2051         *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2052                                      (ratr_index << 28);
2053         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2054         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2055                  "Rate_index:%x, ratr_val:%x, %5phC\n",
2056                  ratr_index, ratr_bitmap, rate_mask);
2057         rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2058
2059         if (macid != 0)
2060                 sta_entry->ratr_index = ratr_index;
2061 }
2062
2063 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw,
2064                 struct ieee80211_sta *sta, u8 rssi_level)
2065 {
2066         struct rtl_priv *rtlpriv = rtl_priv(hw);
2067
2068         if (rtlpriv->dm.useramask)
2069                 rtl92ce_update_hal_rate_mask(hw, sta, rssi_level);
2070         else
2071                 rtl92ce_update_hal_rate_table(hw, sta);
2072 }
2073
2074 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
2075 {
2076         struct rtl_priv *rtlpriv = rtl_priv(hw);
2077         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2078         u16 sifs_timer;
2079
2080         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2081                                       &mac->slot_time);
2082         if (!mac->ht_enable)
2083                 sifs_timer = 0x0a0a;
2084         else
2085                 sifs_timer = 0x1010;
2086         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2087 }
2088
2089 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2090 {
2091         struct rtl_priv *rtlpriv = rtl_priv(hw);
2092         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2093         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2094         enum rf_pwrstate e_rfpowerstate_toset;
2095         u8 u1tmp;
2096         bool actuallyset = false;
2097         unsigned long flag;
2098
2099         if (rtlpci->being_init_adapter)
2100                 return false;
2101
2102         if (ppsc->swrf_processing)
2103                 return false;
2104
2105         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2106         if (ppsc->rfchange_inprogress) {
2107                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2108                 return false;
2109         } else {
2110                 ppsc->rfchange_inprogress = true;
2111                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2112         }
2113
2114         rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2115                        REG_MAC_PINMUX_CFG)&~(BIT(3)));
2116
2117         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2118         e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2119
2120         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2121                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2122                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
2123
2124                 e_rfpowerstate_toset = ERFON;
2125                 ppsc->hwradiooff = false;
2126                 actuallyset = true;
2127         } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2128                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2129                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2130
2131                 e_rfpowerstate_toset = ERFOFF;
2132                 ppsc->hwradiooff = true;
2133                 actuallyset = true;
2134         }
2135
2136         if (actuallyset) {
2137                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2138                 ppsc->rfchange_inprogress = false;
2139                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2140         } else {
2141                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2142                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2143
2144                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2145                 ppsc->rfchange_inprogress = false;
2146                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2147         }
2148
2149         *valid = 1;
2150         return !ppsc->hwradiooff;
2151
2152 }
2153
2154 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
2155                      u8 *p_macaddr, bool is_group, u8 enc_algo,
2156                      bool is_wepkey, bool clear_all)
2157 {
2158         struct rtl_priv *rtlpriv = rtl_priv(hw);
2159         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2160         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2161         u8 *macaddr = p_macaddr;
2162         u32 entry_id = 0;
2163         bool is_pairwise = false;
2164
2165         static u8 cam_const_addr[4][6] = {
2166                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2167                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2168                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2169                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2170         };
2171         static u8 cam_const_broad[] = {
2172                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2173         };
2174
2175         if (clear_all) {
2176                 u8 idx = 0;
2177                 u8 cam_offset = 0;
2178                 u8 clear_number = 5;
2179
2180                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2181
2182                 for (idx = 0; idx < clear_number; idx++) {
2183                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2184                         rtl_cam_empty_entry(hw, cam_offset + idx);
2185
2186                         if (idx < 5) {
2187                                 memset(rtlpriv->sec.key_buf[idx], 0,
2188                                        MAX_KEY_LEN);
2189                                 rtlpriv->sec.key_len[idx] = 0;
2190                         }
2191                 }
2192
2193         } else {
2194                 switch (enc_algo) {
2195                 case WEP40_ENCRYPTION:
2196                         enc_algo = CAM_WEP40;
2197                         break;
2198                 case WEP104_ENCRYPTION:
2199                         enc_algo = CAM_WEP104;
2200                         break;
2201                 case TKIP_ENCRYPTION:
2202                         enc_algo = CAM_TKIP;
2203                         break;
2204                 case AESCCMP_ENCRYPTION:
2205                         enc_algo = CAM_AES;
2206                         break;
2207                 default:
2208                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2209                                  "switch case not processed\n");
2210                         enc_algo = CAM_TKIP;
2211                         break;
2212                 }
2213
2214                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2215                         macaddr = cam_const_addr[key_index];
2216                         entry_id = key_index;
2217                 } else {
2218                         if (is_group) {
2219                                 macaddr = cam_const_broad;
2220                                 entry_id = key_index;
2221                         } else {
2222                                 if (mac->opmode == NL80211_IFTYPE_AP ||
2223                                     mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2224                                         entry_id = rtl_cam_get_free_entry(hw,
2225                                                                  p_macaddr);
2226                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2227                                                 RT_TRACE(rtlpriv, COMP_SEC,
2228                                                          DBG_EMERG,
2229                                                          "Can not find free hw security cam entry\n");
2230                                                 return;
2231                                         }
2232                                 } else {
2233                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2234                                 }
2235
2236                                 key_index = PAIRWISE_KEYIDX;
2237                                 is_pairwise = true;
2238                         }
2239                 }
2240
2241                 if (rtlpriv->sec.key_len[key_index] == 0) {
2242                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2243                                  "delete one entry, entry_id is %d\n",
2244                                  entry_id);
2245                         if (mac->opmode == NL80211_IFTYPE_AP ||
2246                             mac->opmode == NL80211_IFTYPE_MESH_POINT)
2247                                 rtl_cam_del_entry(hw, p_macaddr);
2248                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2249                 } else {
2250                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2251                                  "The insert KEY length is %d\n",
2252                                  rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2253                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2254                                  "The insert KEY is %x %x\n",
2255                                  rtlpriv->sec.key_buf[0][0],
2256                                  rtlpriv->sec.key_buf[0][1]);
2257
2258                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2259                                  "add one entry\n");
2260                         if (is_pairwise) {
2261                                 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2262                                               "Pairwise Key content",
2263                                               rtlpriv->sec.pairwise_key,
2264                                               rtlpriv->sec.
2265                                               key_len[PAIRWISE_KEYIDX]);
2266
2267                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2268                                          "set Pairwise key\n");
2269
2270                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2271                                                       entry_id, enc_algo,
2272                                                       CAM_CONFIG_NO_USEDK,
2273                                                       rtlpriv->sec.
2274                                                       key_buf[key_index]);
2275                         } else {
2276                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2277                                          "set group key\n");
2278
2279                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2280                                         rtl_cam_add_one_entry(hw,
2281                                                 rtlefuse->dev_addr,
2282                                                 PAIRWISE_KEYIDX,
2283                                                 CAM_PAIRWISE_KEY_POSITION,
2284                                                 enc_algo,
2285                                                 CAM_CONFIG_NO_USEDK,
2286                                                 rtlpriv->sec.key_buf
2287                                                 [entry_id]);
2288                                 }
2289
2290                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2291                                                 entry_id, enc_algo,
2292                                                 CAM_CONFIG_NO_USEDK,
2293                                                 rtlpriv->sec.key_buf[entry_id]);
2294                         }
2295
2296                 }
2297         }
2298 }
2299
2300 static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw)
2301 {
2302         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2303
2304         rtlpcipriv->bt_coexist.bt_coexistence =
2305                         rtlpcipriv->bt_coexist.eeprom_bt_coexist;
2306         rtlpcipriv->bt_coexist.bt_ant_num =
2307                         rtlpcipriv->bt_coexist.eeprom_bt_ant_num;
2308         rtlpcipriv->bt_coexist.bt_coexist_type =
2309                         rtlpcipriv->bt_coexist.eeprom_bt_type;
2310
2311         if (rtlpcipriv->bt_coexist.reg_bt_iso == 2)
2312                 rtlpcipriv->bt_coexist.bt_ant_isolation =
2313                         rtlpcipriv->bt_coexist.eeprom_bt_ant_isol;
2314         else
2315                 rtlpcipriv->bt_coexist.bt_ant_isolation =
2316                         rtlpcipriv->bt_coexist.reg_bt_iso;
2317
2318         rtlpcipriv->bt_coexist.bt_radio_shared_type =
2319                         rtlpcipriv->bt_coexist.eeprom_bt_radio_shared;
2320
2321         if (rtlpcipriv->bt_coexist.bt_coexistence) {
2322
2323                 if (rtlpcipriv->bt_coexist.reg_bt_sco == 1)
2324                         rtlpcipriv->bt_coexist.bt_service = BT_OTHER_ACTION;
2325                 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 2)
2326                         rtlpcipriv->bt_coexist.bt_service = BT_SCO;
2327                 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 4)
2328                         rtlpcipriv->bt_coexist.bt_service = BT_BUSY;
2329                 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 5)
2330                         rtlpcipriv->bt_coexist.bt_service = BT_OTHERBUSY;
2331                 else
2332                         rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
2333
2334                 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
2335                 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
2336                 rtlpcipriv->bt_coexist.bt_rssi_state = 0xff;
2337         }
2338 }
2339
2340 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2341                                               bool auto_load_fail, u8 *hwinfo)
2342 {
2343         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2344         u8 val;
2345
2346         if (!auto_load_fail) {
2347                 rtlpcipriv->bt_coexist.eeprom_bt_coexist =
2348                                         ((hwinfo[RF_OPTION1] & 0xe0) >> 5);
2349                 val = hwinfo[RF_OPTION4];
2350                 rtlpcipriv->bt_coexist.eeprom_bt_type = ((val & 0xe) >> 1);
2351                 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = (val & 0x1);
2352                 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol = ((val & 0x10) >> 4);
2353                 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared =
2354                                                          ((val & 0x20) >> 5);
2355         } else {
2356                 rtlpcipriv->bt_coexist.eeprom_bt_coexist = 0;
2357                 rtlpcipriv->bt_coexist.eeprom_bt_type = BT_2WIRE;
2358                 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2;
2359                 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol = 0;
2360                 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2361         }
2362
2363         rtl8192ce_bt_var_init(hw);
2364 }
2365
2366 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw)
2367 {
2368         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2369
2370         /* 0:Low, 1:High, 2:From Efuse. */
2371         rtlpcipriv->bt_coexist.reg_bt_iso = 2;
2372         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2373         rtlpcipriv->bt_coexist.reg_bt_sco = 3;
2374         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2375         rtlpcipriv->bt_coexist.reg_bt_sco = 0;
2376 }
2377
2378
2379 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw)
2380 {
2381         struct rtl_priv *rtlpriv = rtl_priv(hw);
2382         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2383         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2384
2385         u8 u1_tmp;
2386
2387         if (rtlpcipriv->bt_coexist.bt_coexistence &&
2388             ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
2389               rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8)) {
2390
2391                 if (rtlpcipriv->bt_coexist.bt_ant_isolation)
2392                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2393
2394                 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2395                          BIT_OFFSET_LEN_MASK_32(0, 1);
2396                 u1_tmp = u1_tmp |
2397                          ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
2398                          0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2399                          ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ?
2400                          0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2401                 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2402
2403                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2404                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2405                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2406
2407                 /* Config to 1T1R. */
2408                 if (rtlphy->rf_type == RF_1T1R) {
2409                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2410                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2411                         rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2412
2413                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2414                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2415                         rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2416                 }
2417         }
2418 }
2419
2420 void rtl92ce_suspend(struct ieee80211_hw *hw)
2421 {
2422 }
2423
2424 void rtl92ce_resume(struct ieee80211_hw *hw)
2425 {
2426 }