1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
40 #include "../rtl8192c/dm_common.h"
41 #include "../rtl8192c/fw_common.h"
42 #include "../rtl8192c/phy_common.h"
49 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
50 u8 set_bits, u8 clear_bits)
52 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
53 struct rtl_priv *rtlpriv = rtl_priv(hw);
55 rtlpci->reg_bcn_ctrl_val |= set_bits;
56 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
58 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
61 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
63 struct rtl_priv *rtlpriv = rtl_priv(hw);
66 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
67 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
68 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
69 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
70 tmp1byte &= ~(BIT(0));
71 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
74 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
76 struct rtl_priv *rtlpriv = rtl_priv(hw);
79 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
80 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
81 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
82 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
84 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
87 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
89 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
92 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
94 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
97 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
99 struct rtl_priv *rtlpriv = rtl_priv(hw);
100 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
101 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
105 *((u32 *) (val)) = rtlpci->receive_config;
107 case HW_VAR_RF_STATE:
108 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
110 case HW_VAR_FWLPS_RF_ON:{
111 enum rf_pwrstate rfState;
114 rtlpriv->cfg->ops->get_hw_reg(hw,
117 if (rfState == ERFOFF) {
118 *((bool *) (val)) = true;
120 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
121 val_rcr &= 0x00070000;
123 *((bool *) (val)) = false;
125 *((bool *) (val)) = true;
129 case HW_VAR_FW_PSMODE_STATUS:
130 *((bool *) (val)) = ppsc->fw_current_inpsmode;
132 case HW_VAR_CORRECT_TSF:{
134 u32 *ptsf_low = (u32 *)&tsf;
135 u32 *ptsf_high = ((u32 *)&tsf) + 1;
137 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
138 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
140 *((u64 *) (val)) = tsf;
145 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
146 "switch case not processed\n");
151 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
153 struct rtl_priv *rtlpriv = rtl_priv(hw);
154 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
155 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
156 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
157 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
158 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
159 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
163 case HW_VAR_ETHER_ADDR:{
164 for (idx = 0; idx < ETH_ALEN; idx++) {
165 rtl_write_byte(rtlpriv, (REG_MACID + idx),
170 case HW_VAR_BASIC_RATE:{
171 u16 rate_cfg = ((u16 *) val)[0];
175 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
176 rtl_write_byte(rtlpriv, REG_RRSR + 1,
177 (rate_cfg >> 8) & 0xff);
178 while (rate_cfg > 0x1) {
179 rate_cfg = (rate_cfg >> 1);
182 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
187 for (idx = 0; idx < ETH_ALEN; idx++) {
188 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
194 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
195 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
197 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
198 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
201 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
204 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
208 case HW_VAR_SLOT_TIME:{
211 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
212 "HW_VAR_SLOT_TIME %x\n", val[0]);
214 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
216 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
217 rtlpriv->cfg->ops->set_hw_reg(hw,
223 case HW_VAR_ACK_PREAMBLE:{
225 u8 short_preamble = (bool)*val;
226 reg_tmp = (mac->cur_40_prime_sc) << 5;
230 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
233 case HW_VAR_AMPDU_MIN_SPACE:{
234 u8 min_spacing_to_set;
237 min_spacing_to_set = *val;
238 if (min_spacing_to_set <= 7) {
241 if (min_spacing_to_set < sec_min_space)
242 min_spacing_to_set = sec_min_space;
244 mac->min_space_cfg = ((mac->min_space_cfg &
248 *val = min_spacing_to_set;
250 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
251 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
254 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
259 case HW_VAR_SHORTGI_DENSITY:{
262 density_to_set = *val;
263 mac->min_space_cfg |= (density_to_set << 3);
265 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
266 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
269 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
274 case HW_VAR_AMPDU_FACTOR:{
275 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
276 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
279 u8 *p_regtoset = NULL;
282 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
283 (rtlpcipriv->bt_coexist.bt_coexist_type ==
285 p_regtoset = regtoset_bt;
287 p_regtoset = regtoset_normal;
289 factor_toset = *(val);
290 if (factor_toset <= 3) {
291 factor_toset = (1 << (factor_toset + 2));
292 if (factor_toset > 0xf)
295 for (index = 0; index < 4; index++) {
296 if ((p_regtoset[index] & 0xf0) >
299 (p_regtoset[index] & 0x0f) |
302 if ((p_regtoset[index] & 0x0f) >
305 (p_regtoset[index] & 0xf0) |
308 rtl_write_byte(rtlpriv,
309 (REG_AGGLEN_LMT + index),
314 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
315 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
320 case HW_VAR_AC_PARAM:{
322 rtl92c_dm_init_edca_turbo(hw);
324 if (rtlpci->acm_method != EACMWAY2_SW)
325 rtlpriv->cfg->ops->set_hw_reg(hw,
330 case HW_VAR_ACM_CTRL:{
332 union aci_aifsn *p_aci_aifsn =
333 (union aci_aifsn *)(&(mac->ac[0].aifs));
334 u8 acm = p_aci_aifsn->f.acm;
335 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
338 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
343 acm_ctrl |= AcmHw_BeqEn;
346 acm_ctrl |= AcmHw_ViqEn;
349 acm_ctrl |= AcmHw_VoqEn;
352 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
353 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
360 acm_ctrl &= (~AcmHw_BeqEn);
363 acm_ctrl &= (~AcmHw_ViqEn);
366 acm_ctrl &= (~AcmHw_BeqEn);
369 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
370 "switch case not processed\n");
375 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
376 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
378 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
382 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
383 rtlpci->receive_config = ((u32 *) (val))[0];
386 case HW_VAR_RETRY_LIMIT:{
387 u8 retry_limit = val[0];
389 rtl_write_word(rtlpriv, REG_RL,
390 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
391 retry_limit << RETRY_LIMIT_LONG_SHIFT);
394 case HW_VAR_DUAL_TSF_RST:
395 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
397 case HW_VAR_EFUSE_BYTES:
398 rtlefuse->efuse_usedbytes = *((u16 *) val);
400 case HW_VAR_EFUSE_USAGE:
401 rtlefuse->efuse_usedpercentage = *val;
404 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
406 case HW_VAR_WPA_CONFIG:
407 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
409 case HW_VAR_SET_RPWM:{
412 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
415 if (rpwm_val & BIT(7)) {
416 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
418 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
424 case HW_VAR_H2C_FW_PWRMODE:{
427 if ((psmode != FW_PS_ACTIVE_MODE) &&
428 (!IS_92C_SERIAL(rtlhal->version))) {
429 rtl92c_dm_rf_saving(hw, true);
432 rtl92c_set_fw_pwrmode_cmd(hw, *val);
435 case HW_VAR_FW_PSMODE_STATUS:
436 ppsc->fw_current_inpsmode = *((bool *) val);
438 case HW_VAR_H2C_FW_JOINBSSRPT:{
440 u8 tmp_regcr, tmp_reg422;
441 bool recover = false;
443 if (mstatus == RT_MEDIA_CONNECT) {
444 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
447 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
448 rtl_write_byte(rtlpriv, REG_CR + 1,
449 (tmp_regcr | BIT(0)));
451 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
452 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
455 rtl_read_byte(rtlpriv,
456 REG_FWHW_TXQ_CTRL + 2);
457 if (tmp_reg422 & BIT(6))
459 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
460 tmp_reg422 & (~BIT(6)));
462 rtl92c_set_fw_rsvdpagepkt(hw, NULL);
464 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
465 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
468 rtl_write_byte(rtlpriv,
469 REG_FWHW_TXQ_CTRL + 2,
473 rtl_write_byte(rtlpriv, REG_CR + 1,
474 (tmp_regcr & ~(BIT(0))));
476 rtl92c_set_fw_joinbss_report_cmd(hw, *val);
480 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
481 rtl92c_set_p2p_ps_offload_cmd(hw, *val);
485 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
487 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
492 case HW_VAR_CORRECT_TSF:{
493 u8 btype_ibss = val[0];
496 _rtl92ce_stop_tx_beacon(hw);
498 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
500 rtl_write_dword(rtlpriv, REG_TSFTR,
501 (u32) (mac->tsf & 0xffffffff));
502 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
503 (u32) ((mac->tsf >> 32) & 0xffffffff));
505 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
508 _rtl92ce_resume_tx_beacon(hw);
513 case HW_VAR_FW_LPS_ACTION: {
514 bool enter_fwlps = *((bool *)val);
515 u8 rpwm_val, fw_pwrmode;
516 bool fw_current_inps;
519 rpwm_val = 0x02; /* RF off */
520 fw_current_inps = true;
521 rtlpriv->cfg->ops->set_hw_reg(hw,
522 HW_VAR_FW_PSMODE_STATUS,
523 (u8 *)(&fw_current_inps));
524 rtlpriv->cfg->ops->set_hw_reg(hw,
525 HW_VAR_H2C_FW_PWRMODE,
526 &ppsc->fwctrl_psmode);
528 rtlpriv->cfg->ops->set_hw_reg(hw,
532 rpwm_val = 0x0C; /* RF on */
533 fw_pwrmode = FW_PS_ACTIVE_MODE;
534 fw_current_inps = false;
535 rtlpriv->cfg->ops->set_hw_reg(hw,
538 rtlpriv->cfg->ops->set_hw_reg(hw,
539 HW_VAR_H2C_FW_PWRMODE,
542 rtlpriv->cfg->ops->set_hw_reg(hw,
543 HW_VAR_FW_PSMODE_STATUS,
544 (u8 *)(&fw_current_inps));
547 case HW_VAR_KEEP_ALIVE:
550 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
551 "switch case %d not processed\n", variable);
556 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
558 struct rtl_priv *rtlpriv = rtl_priv(hw);
561 u32 value = _LLT_INIT_ADDR(address) |
562 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
564 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
567 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
568 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
571 if (count > POLLING_LLT_THRESHOLD) {
572 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
573 "Failed to polling write LLT done at address %d!\n",
583 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
585 struct rtl_priv *rtlpriv = rtl_priv(hw);
594 #elif LLT_CONFIG == 2
597 #elif LLT_CONFIG == 3
600 #elif LLT_CONFIG == 4
603 #elif LLT_CONFIG == 5
609 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
610 rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
611 #elif LLT_CONFIG == 2
612 rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
613 #elif LLT_CONFIG == 3
614 rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
615 #elif LLT_CONFIG == 4
616 rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
617 #elif LLT_CONFIG == 5
618 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
620 rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
623 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
624 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
626 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
627 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
629 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
630 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
631 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
633 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
634 status = _rtl92ce_llt_write(hw, i, i + 1);
639 status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
643 for (i = txpktbuf_bndy; i < maxPage; i++) {
644 status = _rtl92ce_llt_write(hw, i, (i + 1));
649 status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy);
656 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
658 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
659 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
660 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
661 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
663 if (rtlpci->up_first_time)
666 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
667 rtl92ce_sw_led_on(hw, pLed0);
668 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
669 rtl92ce_sw_led_on(hw, pLed0);
671 rtl92ce_sw_led_off(hw, pLed0);
674 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
676 struct rtl_priv *rtlpriv = rtl_priv(hw);
677 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
678 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
679 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
681 unsigned char bytetmp;
682 unsigned short wordtmp;
685 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
686 if (rtlpcipriv->bt_coexist.bt_coexistence) {
688 value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO);
689 value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK);
690 rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32);
692 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
693 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
695 if (rtlpcipriv->bt_coexist.bt_coexistence) {
696 u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
698 u4b_tmp &= (~0x00024800);
699 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
702 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
705 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
708 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
712 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
713 rtl_read_dword(rtlpriv, 0xEC), bytetmp);
715 while ((bytetmp & BIT(0)) && retry < 1000) {
718 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
719 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
720 rtl_read_dword(rtlpriv, 0xEC), bytetmp);
724 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
726 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
729 if (rtlpcipriv->bt_coexist.bt_coexistence) {
730 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd;
731 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp);
734 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
736 if (!_rtl92ce_llt_table_init(hw))
739 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
740 rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
742 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
744 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
747 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
749 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
750 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
751 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
753 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
755 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
756 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
758 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
759 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
761 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
762 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
763 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
764 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
765 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
766 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
767 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
768 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
769 rtl_write_dword(rtlpriv, REG_HQ_DESA,
770 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
772 rtl_write_dword(rtlpriv, REG_RX_DESA,
773 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
776 if (IS_92C_SERIAL(rtlhal->version))
777 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
779 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
781 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
783 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
784 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
787 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
788 } while ((retry < 200) && (bytetmp & BIT(7)));
790 _rtl92ce_gen_refresh_led_state(hw);
792 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
797 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
799 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
800 struct rtl_priv *rtlpriv = rtl_priv(hw);
801 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
805 reg_bw_opmode = BW_OPMODE_20MHZ;
806 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
808 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
810 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
812 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
814 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
816 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
818 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
820 rtl_write_word(rtlpriv, REG_RL, 0x0707);
822 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
824 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
826 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
827 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
828 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
829 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
831 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
832 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
833 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
835 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
837 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
839 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
841 rtlpci->reg_bcn_ctrl_val = 0x1f;
842 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
844 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
846 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
848 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
849 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
851 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
852 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
853 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
854 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
856 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
857 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
860 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
861 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
862 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
864 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
866 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
868 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
869 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
871 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
873 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
875 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
876 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
880 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
882 struct rtl_priv *rtlpriv = rtl_priv(hw);
883 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
885 rtl_write_byte(rtlpriv, 0x34b, 0x93);
886 rtl_write_word(rtlpriv, 0x350, 0x870c);
887 rtl_write_byte(rtlpriv, 0x352, 0x1);
889 if (ppsc->support_backdoor)
890 rtl_write_byte(rtlpriv, 0x349, 0x1b);
892 rtl_write_byte(rtlpriv, 0x349, 0x03);
894 rtl_write_word(rtlpriv, 0x350, 0x2718);
895 rtl_write_byte(rtlpriv, 0x352, 0x1);
898 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
900 struct rtl_priv *rtlpriv = rtl_priv(hw);
903 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
904 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
905 rtlpriv->sec.pairwise_enc_algorithm,
906 rtlpriv->sec.group_enc_algorithm);
908 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
909 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
910 "not open hw encryption\n");
914 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
916 if (rtlpriv->sec.use_defaultkey) {
917 sec_reg_value |= SCR_TxUseDK;
918 sec_reg_value |= SCR_RxUseDK;
921 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
923 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
925 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
926 "The SECR-value %x\n", sec_reg_value);
928 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
932 int rtl92ce_hw_init(struct ieee80211_hw *hw)
934 struct rtl_priv *rtlpriv = rtl_priv(hw);
935 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
936 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
937 struct rtl_phy *rtlphy = &(rtlpriv->phy);
938 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
939 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
940 bool rtstatus = true;
946 rtlpci->being_init_adapter = true;
948 /* Since this function can take a very long time (up to 350 ms)
949 * and can be called with irqs disabled, reenable the irqs
950 * to let the other devices continue being serviced.
952 * It is safe doing so since our own interrupts will only be enabled
953 * in a subsequent step.
955 local_save_flags(flags);
958 rtlpriv->intf_ops->disable_aspm(hw);
959 rtstatus = _rtl92ce_init_mac(hw);
961 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
966 err = rtl92c_download_fw(hw);
968 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
969 "Failed to download FW. Init HW without FW now..\n");
974 rtlhal->last_hmeboxnum = 0;
975 rtl92c_phy_mac_config(hw);
976 /* because last function modify RCR, so we update
977 * rcr var here, or TP will unstable for receive_config
978 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
979 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
980 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
981 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
982 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
983 rtl92c_phy_bb_config(hw);
984 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
985 rtl92c_phy_rf_config(hw);
986 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
987 !IS_92C_SERIAL(rtlhal->version)) {
988 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
989 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
990 } else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) {
991 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE);
992 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31);
993 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425);
994 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200);
995 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053);
996 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201);
998 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
999 RF_CHNLBW, RFREG_OFFSET_MASK);
1000 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1001 RF_CHNLBW, RFREG_OFFSET_MASK);
1002 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1003 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1004 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
1005 _rtl92ce_hw_configure(hw);
1006 rtl_cam_reset_all_entry(hw);
1007 rtl92ce_enable_hw_security_config(hw);
1009 ppsc->rfpwr_state = ERFON;
1011 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1012 _rtl92ce_enable_aspm_back_door(hw);
1013 rtlpriv->intf_ops->enable_aspm(hw);
1015 rtl8192ce_bt_hw_init(hw);
1017 if (ppsc->rfpwr_state == ERFON) {
1018 rtl92c_phy_set_rfpath_switch(hw, 1);
1019 if (rtlphy->iqk_initialized) {
1020 rtl92c_phy_iq_calibrate(hw, true);
1022 rtl92c_phy_iq_calibrate(hw, false);
1023 rtlphy->iqk_initialized = true;
1026 rtl92c_dm_check_txpower_tracking(hw);
1027 rtl92c_phy_lc_calibrate(hw);
1030 is92c = IS_92C_SERIAL(rtlhal->version);
1031 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1032 if (!(tmp_u1b & BIT(0))) {
1033 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1034 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
1037 if (!(tmp_u1b & BIT(1)) && is92c) {
1038 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
1039 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path B\n");
1042 if (!(tmp_u1b & BIT(4))) {
1043 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1045 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1047 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1048 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
1052 local_irq_restore(flags);
1053 rtlpci->being_init_adapter = false;
1057 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
1059 struct rtl_priv *rtlpriv = rtl_priv(hw);
1060 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1061 enum version_8192c version = VERSION_UNKNOWN;
1063 const char *versionid;
1065 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1066 if (value32 & TRP_VAUX_EN) {
1067 version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
1070 version = (enum version_8192c) (CHIP_VER_B |
1071 ((value32 & TYPE_ID) ? CHIP_92C_BITMASK : 0) |
1072 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1073 if ((!IS_CHIP_VENDOR_UMC(version)) && (value32 &
1074 CHIP_VER_RTL_MASK)) {
1075 version = (enum version_8192c)(version |
1076 ((((value32 & CHIP_VER_RTL_MASK) == BIT(12))
1077 ? CHIP_VENDOR_UMC_B_CUT : CHIP_UNKNOWN) |
1080 if (IS_92C_SERIAL(version)) {
1081 value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM);
1082 version = (enum version_8192c)(version |
1083 ((CHIP_BONDING_IDENTIFIER(value32)
1084 == CHIP_BONDING_92C_1T2R) ?
1090 case VERSION_B_CHIP_92C:
1091 versionid = "B_CHIP_92C";
1093 case VERSION_B_CHIP_88C:
1094 versionid = "B_CHIP_88C";
1096 case VERSION_A_CHIP_92C:
1097 versionid = "A_CHIP_92C";
1099 case VERSION_A_CHIP_88C:
1100 versionid = "A_CHIP_88C";
1102 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
1103 versionid = "A_CUT_92C_1T2R";
1105 case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
1106 versionid = "A_CUT_92C";
1108 case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
1109 versionid = "A_CUT_88C";
1111 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
1112 versionid = "B_CUT_92C_1T2R";
1114 case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
1115 versionid = "B_CUT_92C";
1117 case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
1118 versionid = "B_CUT_88C";
1121 versionid = "Unknown. Bug?";
1125 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1126 "Chip Version ID: %s\n", versionid);
1128 switch (version & 0x3) {
1130 rtlphy->rf_type = RF_1T1R;
1133 rtlphy->rf_type = RF_2T2R;
1136 rtlphy->rf_type = RF_1T2R;
1139 rtlphy->rf_type = RF_1T1R;
1140 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1141 "ERROR RF_Type is set!!\n");
1145 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1146 rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R");
1151 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
1152 enum nl80211_iftype type)
1154 struct rtl_priv *rtlpriv = rtl_priv(hw);
1155 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1156 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1159 if (type == NL80211_IFTYPE_UNSPECIFIED ||
1160 type == NL80211_IFTYPE_STATION) {
1161 _rtl92ce_stop_tx_beacon(hw);
1162 _rtl92ce_enable_bcn_sub_func(hw);
1163 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP ||
1164 type == NL80211_IFTYPE_MESH_POINT) {
1165 _rtl92ce_resume_tx_beacon(hw);
1166 _rtl92ce_disable_bcn_sub_func(hw);
1168 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1169 "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",
1174 case NL80211_IFTYPE_UNSPECIFIED:
1175 bt_msr |= MSR_NOLINK;
1176 ledaction = LED_CTL_LINK;
1177 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1178 "Set Network type to NO LINK!\n");
1180 case NL80211_IFTYPE_ADHOC:
1181 bt_msr |= MSR_ADHOC;
1182 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1183 "Set Network type to Ad Hoc!\n");
1185 case NL80211_IFTYPE_STATION:
1186 bt_msr |= MSR_INFRA;
1187 ledaction = LED_CTL_LINK;
1188 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1189 "Set Network type to STA!\n");
1191 case NL80211_IFTYPE_AP:
1193 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1194 "Set Network type to AP!\n");
1196 case NL80211_IFTYPE_MESH_POINT:
1197 bt_msr |= MSR_ADHOC;
1198 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1199 "Set Network type to Mesh Point!\n");
1202 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1203 "Network type %d not supported!\n", type);
1208 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1209 rtlpriv->cfg->ops->led_control(hw, ledaction);
1210 if ((bt_msr & MSR_MASK) == MSR_AP)
1211 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1213 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1217 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1219 struct rtl_priv *rtlpriv = rtl_priv(hw);
1222 if (rtlpriv->psc.rfpwr_state != ERFON)
1225 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1228 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1229 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1231 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
1232 } else if (!check_bssid) {
1233 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1234 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
1235 rtlpriv->cfg->ops->set_hw_reg(hw,
1236 HW_VAR_RCR, (u8 *) (®_rcr));
1241 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1243 struct rtl_priv *rtlpriv = rtl_priv(hw);
1245 if (_rtl92ce_set_media_status(hw, type))
1248 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1249 if (type != NL80211_IFTYPE_AP &&
1250 type != NL80211_IFTYPE_MESH_POINT)
1251 rtl92ce_set_check_bssid(hw, true);
1253 rtl92ce_set_check_bssid(hw, false);
1259 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1260 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1262 struct rtl_priv *rtlpriv = rtl_priv(hw);
1263 rtl92c_dm_init_edca_turbo(hw);
1266 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1269 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1272 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1275 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1278 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1283 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1285 struct rtl_priv *rtlpriv = rtl_priv(hw);
1286 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1288 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1289 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1290 rtlpci->irq_enabled = true;
1293 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1295 struct rtl_priv *rtlpriv = rtl_priv(hw);
1296 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1298 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1299 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1300 rtlpci->irq_enabled = false;
1303 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1305 struct rtl_priv *rtlpriv = rtl_priv(hw);
1306 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1307 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1311 rtlpriv->intf_ops->enable_aspm(hw);
1312 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1313 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1314 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1315 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1316 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1317 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1318 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7))
1319 rtl92c_firmware_selfreset(hw);
1320 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1321 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1322 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1323 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1324 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1325 ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
1326 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8))) {
1327 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 |
1330 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
1333 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1334 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1335 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1336 if (!IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version))
1337 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1338 if (rtlpcipriv->bt_coexist.bt_coexistence) {
1339 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
1340 u4b_tmp |= 0x03824800;
1341 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
1343 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1346 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1347 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1350 void rtl92ce_card_disable(struct ieee80211_hw *hw)
1352 struct rtl_priv *rtlpriv = rtl_priv(hw);
1353 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1354 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1355 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1356 enum nl80211_iftype opmode;
1358 mac->link_state = MAC80211_NOLINK;
1359 opmode = NL80211_IFTYPE_UNSPECIFIED;
1360 _rtl92ce_set_media_status(hw, opmode);
1361 if (rtlpci->driver_is_goingto_unload ||
1362 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1363 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1364 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1365 _rtl92ce_poweroff_adapter(hw);
1367 /* after power off we should do iqk again */
1368 rtlpriv->phy.iqk_initialized = false;
1371 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
1372 u32 *p_inta, u32 *p_intb)
1374 struct rtl_priv *rtlpriv = rtl_priv(hw);
1375 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1377 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1378 rtl_write_dword(rtlpriv, ISR, *p_inta);
1381 * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1382 * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1386 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
1389 struct rtl_priv *rtlpriv = rtl_priv(hw);
1390 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1391 u16 bcn_interval, atim_window;
1393 bcn_interval = mac->beacon_interval;
1394 atim_window = 2; /*FIX MERGE */
1395 rtl92ce_disable_interrupt(hw);
1396 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1397 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1398 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1399 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1400 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1401 rtl_write_byte(rtlpriv, 0x606, 0x30);
1402 rtl92ce_enable_interrupt(hw);
1405 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
1407 struct rtl_priv *rtlpriv = rtl_priv(hw);
1408 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1409 u16 bcn_interval = mac->beacon_interval;
1411 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1412 "beacon_interval:%d\n", bcn_interval);
1413 rtl92ce_disable_interrupt(hw);
1414 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1415 rtl92ce_enable_interrupt(hw);
1418 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1419 u32 add_msr, u32 rm_msr)
1421 struct rtl_priv *rtlpriv = rtl_priv(hw);
1422 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1424 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1428 rtlpci->irq_mask[0] |= add_msr;
1430 rtlpci->irq_mask[0] &= (~rm_msr);
1431 rtl92ce_disable_interrupt(hw);
1432 rtl92ce_enable_interrupt(hw);
1435 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1439 struct rtl_priv *rtlpriv = rtl_priv(hw);
1440 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1441 u8 rf_path, index, tempval;
1444 for (rf_path = 0; rf_path < 2; rf_path++) {
1445 for (i = 0; i < 3; i++) {
1446 if (!autoload_fail) {
1448 eeprom_chnlarea_txpwr_cck[rf_path][i] =
1449 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1451 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1452 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
1456 eeprom_chnlarea_txpwr_cck[rf_path][i] =
1457 EEPROM_DEFAULT_TXPOWERLEVEL;
1459 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1460 EEPROM_DEFAULT_TXPOWERLEVEL;
1465 for (i = 0; i < 3; i++) {
1467 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1469 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1470 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
1472 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
1473 ((tempval & 0xf0) >> 4);
1476 for (rf_path = 0; rf_path < 2; rf_path++)
1477 for (i = 0; i < 3; i++)
1478 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1479 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1482 eeprom_chnlarea_txpwr_cck[rf_path][i]);
1483 for (rf_path = 0; rf_path < 2; rf_path++)
1484 for (i = 0; i < 3; i++)
1485 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1486 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1489 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
1490 for (rf_path = 0; rf_path < 2; rf_path++)
1491 for (i = 0; i < 3; i++)
1492 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1493 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1496 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]);
1498 for (rf_path = 0; rf_path < 2; rf_path++) {
1499 for (i = 0; i < 14; i++) {
1500 index = rtl92c_get_chnl_group((u8)i);
1502 rtlefuse->txpwrlevel_cck[rf_path][i] =
1503 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
1504 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1506 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
1509 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1511 eprom_chnl_txpwr_ht40_2sdf[rf_path][index])
1513 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1515 eeprom_chnlarea_txpwr_ht40_1s[rf_path]
1518 eprom_chnl_txpwr_ht40_2sdf[rf_path]
1521 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1525 for (i = 0; i < 14; i++) {
1526 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1527 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1529 rtlefuse->txpwrlevel_cck[rf_path][i],
1530 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1531 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1535 for (i = 0; i < 3; i++) {
1536 if (!autoload_fail) {
1537 rtlefuse->eeprom_pwrlimit_ht40[i] =
1538 hwinfo[EEPROM_TXPWR_GROUP + i];
1539 rtlefuse->eeprom_pwrlimit_ht20[i] =
1540 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1542 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1543 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1547 for (rf_path = 0; rf_path < 2; rf_path++) {
1548 for (i = 0; i < 14; i++) {
1549 index = rtl92c_get_chnl_group((u8)i);
1551 if (rf_path == RF90_PATH_A) {
1552 rtlefuse->pwrgroup_ht20[rf_path][i] =
1553 (rtlefuse->eeprom_pwrlimit_ht20[index]
1555 rtlefuse->pwrgroup_ht40[rf_path][i] =
1556 (rtlefuse->eeprom_pwrlimit_ht40[index]
1558 } else if (rf_path == RF90_PATH_B) {
1559 rtlefuse->pwrgroup_ht20[rf_path][i] =
1560 ((rtlefuse->eeprom_pwrlimit_ht20[index]
1562 rtlefuse->pwrgroup_ht40[rf_path][i] =
1563 ((rtlefuse->eeprom_pwrlimit_ht40[index]
1567 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1568 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1570 rtlefuse->pwrgroup_ht20[rf_path][i]);
1571 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1572 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1574 rtlefuse->pwrgroup_ht40[rf_path][i]);
1578 for (i = 0; i < 14; i++) {
1579 index = rtl92c_get_chnl_group((u8)i);
1582 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1584 tempval = EEPROM_DEFAULT_HT20_DIFF;
1586 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1587 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1588 ((tempval >> 4) & 0xF);
1590 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1591 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1593 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1594 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1596 index = rtl92c_get_chnl_group((u8)i);
1599 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1601 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1603 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1604 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1605 ((tempval >> 4) & 0xF);
1608 rtlefuse->legacy_ht_txpowerdiff =
1609 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1611 for (i = 0; i < 14; i++)
1612 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1613 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1614 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1615 for (i = 0; i < 14; i++)
1616 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1617 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1618 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1619 for (i = 0; i < 14; i++)
1620 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1621 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1622 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1623 for (i = 0; i < 14; i++)
1624 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1625 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1626 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1629 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1631 rtlefuse->eeprom_regulatory = 0;
1632 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1633 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1635 if (!autoload_fail) {
1636 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1637 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
1639 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1640 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1642 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1643 rtlefuse->eeprom_tssi[RF90_PATH_A],
1644 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1647 tempval = hwinfo[EEPROM_THERMAL_METER];
1649 tempval = EEPROM_DEFAULT_THERMALMETER;
1650 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1652 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1653 rtlefuse->apk_thermalmeterignore = true;
1655 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1656 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1657 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1660 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1662 struct rtl_priv *rtlpriv = rtl_priv(hw);
1663 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1664 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1666 u8 hwinfo[HWSET_MAX_SIZE];
1669 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1670 rtl_efuse_shadow_map_update(hw);
1672 memcpy((void *)hwinfo,
1673 (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1675 } else if (rtlefuse->epromtype == EEPROM_93C46) {
1676 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1677 "RTL819X Not boot from eeprom, check it !!");
1680 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
1681 hwinfo, HWSET_MAX_SIZE);
1683 eeprom_id = *((u16 *)&hwinfo[0]);
1684 if (eeprom_id != RTL8190_EEPROM_ID) {
1685 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1686 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1687 rtlefuse->autoload_failflag = true;
1689 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1690 rtlefuse->autoload_failflag = false;
1693 if (rtlefuse->autoload_failflag)
1696 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1697 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1698 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1699 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1700 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1701 "EEPROMId = 0x%4x\n", eeprom_id);
1702 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1703 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1704 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1705 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1706 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1707 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1708 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1709 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1711 for (i = 0; i < 6; i += 2) {
1712 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1713 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1716 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1718 _rtl92ce_read_txpower_info_from_hwpg(hw,
1719 rtlefuse->autoload_failflag,
1722 rtl8192ce_read_bt_coexist_info_from_hwpg(hw,
1723 rtlefuse->autoload_failflag,
1726 rtlefuse->eeprom_channelplan = *&hwinfo[EEPROM_CHANNELPLAN];
1727 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1728 rtlefuse->txpwr_fromeprom = true;
1729 rtlefuse->eeprom_oemid = *&hwinfo[EEPROM_CUSTOMER_ID];
1731 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1732 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1734 /* set channel paln to world wide 13 */
1735 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1737 if (rtlhal->oem_id == RT_CID_DEFAULT) {
1738 switch (rtlefuse->eeprom_oemid) {
1739 case EEPROM_CID_DEFAULT:
1740 if (rtlefuse->eeprom_did == 0x8176) {
1741 if ((rtlefuse->eeprom_svid == 0x103C &&
1742 rtlefuse->eeprom_smid == 0x1629))
1743 rtlhal->oem_id = RT_CID_819X_HP;
1745 rtlhal->oem_id = RT_CID_DEFAULT;
1747 rtlhal->oem_id = RT_CID_DEFAULT;
1750 case EEPROM_CID_TOSHIBA:
1751 rtlhal->oem_id = RT_CID_TOSHIBA;
1753 case EEPROM_CID_QMI:
1754 rtlhal->oem_id = RT_CID_819X_QMI;
1756 case EEPROM_CID_WHQL:
1758 rtlhal->oem_id = RT_CID_DEFAULT;
1766 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1768 struct rtl_priv *rtlpriv = rtl_priv(hw);
1769 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1770 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1772 switch (rtlhal->oem_id) {
1773 case RT_CID_819X_HP:
1774 pcipriv->ledctl.led_opendrain = true;
1776 case RT_CID_819X_LENOVO:
1777 case RT_CID_DEFAULT:
1778 case RT_CID_TOSHIBA:
1780 case RT_CID_819X_ACER:
1785 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1786 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1789 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1791 struct rtl_priv *rtlpriv = rtl_priv(hw);
1792 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1793 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1794 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1797 rtlhal->version = _rtl92ce_read_chip_version(hw);
1798 if (get_rf_type(rtlphy) == RF_1T1R)
1799 rtlpriv->dm.rfpath_rxenable[0] = true;
1801 rtlpriv->dm.rfpath_rxenable[0] =
1802 rtlpriv->dm.rfpath_rxenable[1] = true;
1803 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1805 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1806 if (tmp_u1b & BIT(4)) {
1807 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1808 rtlefuse->epromtype = EEPROM_93C46;
1810 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1811 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1813 if (tmp_u1b & BIT(5)) {
1814 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1815 rtlefuse->autoload_failflag = false;
1816 _rtl92ce_read_adapter_info(hw);
1818 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1820 _rtl92ce_hal_customized_behavior(hw);
1823 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw,
1824 struct ieee80211_sta *sta)
1826 struct rtl_priv *rtlpriv = rtl_priv(hw);
1827 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1828 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1829 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1830 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1833 u8 nmode = mac->ht_enable;
1834 u8 mimo_ps = IEEE80211_SMPS_OFF;
1837 u8 curtxbw_40mhz = mac->bw_40;
1838 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1840 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1842 enum wireless_mode wirelessmode = mac->mode;
1844 if (rtlhal->current_bandtype == BAND_ON_5G)
1845 ratr_value = sta->supp_rates[1] << 4;
1847 ratr_value = sta->supp_rates[0];
1848 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1851 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1852 sta->ht_cap.mcs.rx_mask[0] << 12);
1853 switch (wirelessmode) {
1854 case WIRELESS_MODE_B:
1855 if (ratr_value & 0x0000000c)
1856 ratr_value &= 0x0000000d;
1858 ratr_value &= 0x0000000f;
1860 case WIRELESS_MODE_G:
1861 ratr_value &= 0x00000FF5;
1863 case WIRELESS_MODE_N_24G:
1864 case WIRELESS_MODE_N_5G:
1866 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1867 ratr_value &= 0x0007F005;
1871 if (get_rf_type(rtlphy) == RF_1T2R ||
1872 get_rf_type(rtlphy) == RF_1T1R)
1873 ratr_mask = 0x000ff005;
1875 ratr_mask = 0x0f0ff005;
1877 ratr_value &= ratr_mask;
1881 if (rtlphy->rf_type == RF_1T2R)
1882 ratr_value &= 0x000ff0ff;
1884 ratr_value &= 0x0f0ff0ff;
1889 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1890 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) &&
1891 (rtlpcipriv->bt_coexist.bt_cur_state) &&
1892 (rtlpcipriv->bt_coexist.bt_ant_isolation) &&
1893 ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ||
1894 (rtlpcipriv->bt_coexist.bt_service == BT_BUSY)))
1895 ratr_value &= 0x0fffcfc0;
1897 ratr_value &= 0x0FFFFFFF;
1899 if (nmode && ((curtxbw_40mhz &&
1900 curshortgi_40mhz) || (!curtxbw_40mhz &&
1901 curshortgi_20mhz))) {
1903 ratr_value |= 0x10000000;
1904 tmp_ratr_value = (ratr_value >> 12);
1906 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1907 if ((1 << shortgi_rate) & tmp_ratr_value)
1911 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1912 (shortgi_rate << 4) | (shortgi_rate);
1915 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1917 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1918 rtl_read_dword(rtlpriv, REG_ARFR0));
1921 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw,
1922 struct ieee80211_sta *sta, u8 rssi_level)
1924 struct rtl_priv *rtlpriv = rtl_priv(hw);
1925 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1926 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1927 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1928 struct rtl_sta_info *sta_entry = NULL;
1931 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
1932 u8 curshortgi_40mhz = curtxbw_40mhz &&
1933 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1935 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1937 enum wireless_mode wirelessmode = 0;
1938 bool shortgi = false;
1941 u8 mimo_ps = IEEE80211_SMPS_OFF;
1943 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1944 wirelessmode = sta_entry->wireless_mode;
1945 if (mac->opmode == NL80211_IFTYPE_STATION ||
1946 mac->opmode == NL80211_IFTYPE_MESH_POINT)
1947 curtxbw_40mhz = mac->bw_40;
1948 else if (mac->opmode == NL80211_IFTYPE_AP ||
1949 mac->opmode == NL80211_IFTYPE_ADHOC)
1950 macid = sta->aid + 1;
1952 if (rtlhal->current_bandtype == BAND_ON_5G)
1953 ratr_bitmap = sta->supp_rates[1] << 4;
1955 ratr_bitmap = sta->supp_rates[0];
1956 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1957 ratr_bitmap = 0xfff;
1958 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1959 sta->ht_cap.mcs.rx_mask[0] << 12);
1960 switch (wirelessmode) {
1961 case WIRELESS_MODE_B:
1962 ratr_index = RATR_INX_WIRELESS_B;
1963 if (ratr_bitmap & 0x0000000c)
1964 ratr_bitmap &= 0x0000000d;
1966 ratr_bitmap &= 0x0000000f;
1968 case WIRELESS_MODE_G:
1969 ratr_index = RATR_INX_WIRELESS_GB;
1971 if (rssi_level == 1)
1972 ratr_bitmap &= 0x00000f00;
1973 else if (rssi_level == 2)
1974 ratr_bitmap &= 0x00000ff0;
1976 ratr_bitmap &= 0x00000ff5;
1978 case WIRELESS_MODE_A:
1979 ratr_index = RATR_INX_WIRELESS_A;
1980 ratr_bitmap &= 0x00000ff0;
1982 case WIRELESS_MODE_N_24G:
1983 case WIRELESS_MODE_N_5G:
1984 ratr_index = RATR_INX_WIRELESS_NGB;
1986 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1987 if (rssi_level == 1)
1988 ratr_bitmap &= 0x00070000;
1989 else if (rssi_level == 2)
1990 ratr_bitmap &= 0x0007f000;
1992 ratr_bitmap &= 0x0007f005;
1994 if (rtlphy->rf_type == RF_1T2R ||
1995 rtlphy->rf_type == RF_1T1R) {
1996 if (curtxbw_40mhz) {
1997 if (rssi_level == 1)
1998 ratr_bitmap &= 0x000f0000;
1999 else if (rssi_level == 2)
2000 ratr_bitmap &= 0x000ff000;
2002 ratr_bitmap &= 0x000ff015;
2004 if (rssi_level == 1)
2005 ratr_bitmap &= 0x000f0000;
2006 else if (rssi_level == 2)
2007 ratr_bitmap &= 0x000ff000;
2009 ratr_bitmap &= 0x000ff005;
2012 if (curtxbw_40mhz) {
2013 if (rssi_level == 1)
2014 ratr_bitmap &= 0x0f0f0000;
2015 else if (rssi_level == 2)
2016 ratr_bitmap &= 0x0f0ff000;
2018 ratr_bitmap &= 0x0f0ff015;
2020 if (rssi_level == 1)
2021 ratr_bitmap &= 0x0f0f0000;
2022 else if (rssi_level == 2)
2023 ratr_bitmap &= 0x0f0ff000;
2025 ratr_bitmap &= 0x0f0ff005;
2030 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2031 (!curtxbw_40mhz && curshortgi_20mhz)) {
2035 else if (macid == 1)
2040 ratr_index = RATR_INX_WIRELESS_NGB;
2042 if (rtlphy->rf_type == RF_1T2R)
2043 ratr_bitmap &= 0x000ff0ff;
2045 ratr_bitmap &= 0x0f0ff0ff;
2048 sta_entry->ratr_index = ratr_index;
2050 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2051 "ratr_bitmap :%x\n", ratr_bitmap);
2052 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2054 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2055 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2056 "Rate_index:%x, ratr_val:%x, %5phC\n",
2057 ratr_index, ratr_bitmap, rate_mask);
2058 rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2061 sta_entry->ratr_index = ratr_index;
2064 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw,
2065 struct ieee80211_sta *sta, u8 rssi_level)
2067 struct rtl_priv *rtlpriv = rtl_priv(hw);
2069 if (rtlpriv->dm.useramask)
2070 rtl92ce_update_hal_rate_mask(hw, sta, rssi_level);
2072 rtl92ce_update_hal_rate_table(hw, sta);
2075 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
2077 struct rtl_priv *rtlpriv = rtl_priv(hw);
2078 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2081 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2083 if (!mac->ht_enable)
2084 sifs_timer = 0x0a0a;
2086 sifs_timer = 0x1010;
2087 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2090 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2092 struct rtl_priv *rtlpriv = rtl_priv(hw);
2093 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2094 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2095 enum rf_pwrstate e_rfpowerstate_toset;
2097 bool actuallyset = false;
2100 if (rtlpci->being_init_adapter)
2103 if (ppsc->swrf_processing)
2106 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2107 if (ppsc->rfchange_inprogress) {
2108 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2111 ppsc->rfchange_inprogress = true;
2112 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2115 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2116 REG_MAC_PINMUX_CFG)&~(BIT(3)));
2118 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2119 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2121 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2122 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2123 "GPIOChangeRF - HW Radio ON, RF ON\n");
2125 e_rfpowerstate_toset = ERFON;
2126 ppsc->hwradiooff = false;
2128 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2129 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2130 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2132 e_rfpowerstate_toset = ERFOFF;
2133 ppsc->hwradiooff = true;
2138 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2139 ppsc->rfchange_inprogress = false;
2140 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2142 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2143 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2145 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2146 ppsc->rfchange_inprogress = false;
2147 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2151 return !ppsc->hwradiooff;
2155 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
2156 u8 *p_macaddr, bool is_group, u8 enc_algo,
2157 bool is_wepkey, bool clear_all)
2159 struct rtl_priv *rtlpriv = rtl_priv(hw);
2160 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2161 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2162 u8 *macaddr = p_macaddr;
2164 bool is_pairwise = false;
2166 static u8 cam_const_addr[4][6] = {
2167 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2168 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2169 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2170 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2172 static u8 cam_const_broad[] = {
2173 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2179 u8 clear_number = 5;
2181 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2183 for (idx = 0; idx < clear_number; idx++) {
2184 rtl_cam_mark_invalid(hw, cam_offset + idx);
2185 rtl_cam_empty_entry(hw, cam_offset + idx);
2188 memset(rtlpriv->sec.key_buf[idx], 0,
2190 rtlpriv->sec.key_len[idx] = 0;
2196 case WEP40_ENCRYPTION:
2197 enc_algo = CAM_WEP40;
2199 case WEP104_ENCRYPTION:
2200 enc_algo = CAM_WEP104;
2202 case TKIP_ENCRYPTION:
2203 enc_algo = CAM_TKIP;
2205 case AESCCMP_ENCRYPTION:
2209 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2210 "switch case not processed\n");
2211 enc_algo = CAM_TKIP;
2215 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2216 macaddr = cam_const_addr[key_index];
2217 entry_id = key_index;
2220 macaddr = cam_const_broad;
2221 entry_id = key_index;
2223 if (mac->opmode == NL80211_IFTYPE_AP ||
2224 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2225 entry_id = rtl_cam_get_free_entry(hw,
2227 if (entry_id >= TOTAL_CAM_ENTRY) {
2228 RT_TRACE(rtlpriv, COMP_SEC,
2230 "Can not find free hw security cam entry\n");
2234 entry_id = CAM_PAIRWISE_KEY_POSITION;
2237 key_index = PAIRWISE_KEYIDX;
2242 if (rtlpriv->sec.key_len[key_index] == 0) {
2243 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2244 "delete one entry, entry_id is %d\n",
2246 if (mac->opmode == NL80211_IFTYPE_AP ||
2247 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2248 rtl_cam_del_entry(hw, p_macaddr);
2249 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2251 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2252 "The insert KEY length is %d\n",
2253 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2254 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2255 "The insert KEY is %x %x\n",
2256 rtlpriv->sec.key_buf[0][0],
2257 rtlpriv->sec.key_buf[0][1]);
2259 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2262 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2263 "Pairwise Key content",
2264 rtlpriv->sec.pairwise_key,
2266 key_len[PAIRWISE_KEYIDX]);
2268 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2269 "set Pairwise key\n");
2271 rtl_cam_add_one_entry(hw, macaddr, key_index,
2273 CAM_CONFIG_NO_USEDK,
2275 key_buf[key_index]);
2277 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2280 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2281 rtl_cam_add_one_entry(hw,
2284 CAM_PAIRWISE_KEY_POSITION,
2286 CAM_CONFIG_NO_USEDK,
2287 rtlpriv->sec.key_buf
2291 rtl_cam_add_one_entry(hw, macaddr, key_index,
2293 CAM_CONFIG_NO_USEDK,
2294 rtlpriv->sec.key_buf[entry_id]);
2301 static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw)
2303 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2305 rtlpcipriv->bt_coexist.bt_coexistence =
2306 rtlpcipriv->bt_coexist.eeprom_bt_coexist;
2307 rtlpcipriv->bt_coexist.bt_ant_num =
2308 rtlpcipriv->bt_coexist.eeprom_bt_ant_num;
2309 rtlpcipriv->bt_coexist.bt_coexist_type =
2310 rtlpcipriv->bt_coexist.eeprom_bt_type;
2312 if (rtlpcipriv->bt_coexist.reg_bt_iso == 2)
2313 rtlpcipriv->bt_coexist.bt_ant_isolation =
2314 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol;
2316 rtlpcipriv->bt_coexist.bt_ant_isolation =
2317 rtlpcipriv->bt_coexist.reg_bt_iso;
2319 rtlpcipriv->bt_coexist.bt_radio_shared_type =
2320 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared;
2322 if (rtlpcipriv->bt_coexist.bt_coexistence) {
2324 if (rtlpcipriv->bt_coexist.reg_bt_sco == 1)
2325 rtlpcipriv->bt_coexist.bt_service = BT_OTHER_ACTION;
2326 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 2)
2327 rtlpcipriv->bt_coexist.bt_service = BT_SCO;
2328 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 4)
2329 rtlpcipriv->bt_coexist.bt_service = BT_BUSY;
2330 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 5)
2331 rtlpcipriv->bt_coexist.bt_service = BT_OTHERBUSY;
2333 rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
2335 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
2336 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
2337 rtlpcipriv->bt_coexist.bt_rssi_state = 0xff;
2341 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2342 bool auto_load_fail, u8 *hwinfo)
2344 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2347 if (!auto_load_fail) {
2348 rtlpcipriv->bt_coexist.eeprom_bt_coexist =
2349 ((hwinfo[RF_OPTION1] & 0xe0) >> 5);
2350 val = hwinfo[RF_OPTION4];
2351 rtlpcipriv->bt_coexist.eeprom_bt_type = ((val & 0xe) >> 1);
2352 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = (val & 0x1);
2353 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol = ((val & 0x10) >> 4);
2354 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared =
2355 ((val & 0x20) >> 5);
2357 rtlpcipriv->bt_coexist.eeprom_bt_coexist = 0;
2358 rtlpcipriv->bt_coexist.eeprom_bt_type = BT_2WIRE;
2359 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2;
2360 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol = 0;
2361 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2364 rtl8192ce_bt_var_init(hw);
2367 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw)
2369 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2371 /* 0:Low, 1:High, 2:From Efuse. */
2372 rtlpcipriv->bt_coexist.reg_bt_iso = 2;
2373 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2374 rtlpcipriv->bt_coexist.reg_bt_sco = 3;
2375 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2376 rtlpcipriv->bt_coexist.reg_bt_sco = 0;
2380 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw)
2382 struct rtl_priv *rtlpriv = rtl_priv(hw);
2383 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2384 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2388 if (rtlpcipriv->bt_coexist.bt_coexistence &&
2389 ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
2390 rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8)) {
2392 if (rtlpcipriv->bt_coexist.bt_ant_isolation)
2393 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2395 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2396 BIT_OFFSET_LEN_MASK_32(0, 1);
2398 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
2399 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2400 ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ?
2401 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2402 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2404 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2405 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2406 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2408 /* Config to 1T1R. */
2409 if (rtlphy->rf_type == RF_1T1R) {
2410 u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2411 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2412 rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2414 u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2415 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2416 rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2421 void rtl92ce_suspend(struct ieee80211_hw *hw)
2425 void rtl92ce_resume(struct ieee80211_hw *hw)