drivers/net/wireless/rtlwifi/rtl8192de/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../regd.h"
  34 #include "../cam.h"
  35 #include "../ps.h"
  36 #include "../pci.h"
  37 #include "reg.h"
  38 #include "def.h"
  39 #include "phy.h"
  40 #include "dm.h"
  41 #include "fw.h"
  42 #include "led.h"
  43 #include "sw.h"
  44 #include "hw.h"
  45
  46 u32 rtl92de_read_dword_dbi(struct ieee80211_hw *hw, u16 offset, u8 direct)
  47 {
  48         struct rtl_priv *rtlpriv = rtl_priv(hw);
  49         u32 value;
  50
  51         rtl_write_word(rtlpriv, REG_DBI_CTRL, (offset & 0xFFC));
  52         rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(1) | direct);
  53         udelay(10);
  54         value = rtl_read_dword(rtlpriv, REG_DBI_RDATA);
  55         return value;
  56 }
  57
  58 void rtl92de_write_dword_dbi(struct ieee80211_hw *hw,
  59                              u16 offset, u32 value, u8 direct)
  60 {
  61         struct rtl_priv *rtlpriv = rtl_priv(hw);
  62
  63         rtl_write_word(rtlpriv, REG_DBI_CTRL, ((offset & 0xFFC) | 0xF000));
  64         rtl_write_dword(rtlpriv, REG_DBI_WDATA, value);
  65         rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct);
  66 }
  67
  68 static void _rtl92de_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  69                                       u8 set_bits, u8 clear_bits)
  70 {
  71         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  72         struct rtl_priv *rtlpriv = rtl_priv(hw);
  73
  74         rtlpci->reg_bcn_ctrl_val |= set_bits;
  75         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  76         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  77 }
  78
  79 static void _rtl92de_stop_tx_beacon(struct ieee80211_hw *hw)
  80 {
  81         struct rtl_priv *rtlpriv = rtl_priv(hw);
  82         u8 tmp1byte;
  83
  84         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  85         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  86         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
  87         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  88         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  89         tmp1byte &= ~(BIT(0));
  90         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  91 }
  92
  93 static void _rtl92de_resume_tx_beacon(struct ieee80211_hw *hw)
  94 {
  95         struct rtl_priv *rtlpriv = rtl_priv(hw);
  96         u8 tmp1byte;
  97
  98         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  99         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
 100         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
 101         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 102         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
 103         tmp1byte |= BIT(0);
 104         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
 105 }
 106
 107 static void _rtl92de_enable_bcn_sub_func(struct ieee80211_hw *hw)
 108 {
 109         _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1));
 110 }
 111
 112 static void _rtl92de_disable_bcn_sub_func(struct ieee80211_hw *hw)
 113 {
 114         _rtl92de_set_bcn_ctrl_reg(hw, BIT(1), 0);
 115 }
 116
 117 void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 118 {
 119         struct rtl_priv *rtlpriv = rtl_priv(hw);
 120         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 121         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 122
 123         switch (variable) {
 124         case HW_VAR_RCR:
 125                 *((u32 *) (val)) = rtlpci->receive_config;
 126                 break;
 127         case HW_VAR_RF_STATE:
 128                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 129                 break;
 130         case HW_VAR_FWLPS_RF_ON:{
 131                 enum rf_pwrstate rfState;
 132                 u32 val_rcr;
 133
 134                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
 135                                               (u8 *) (&rfState));
 136                 if (rfState == ERFOFF) {
 137                         *((bool *) (val)) = true;
 138                 } else {
 139                         val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 140                         val_rcr &= 0x00070000;
 141                         if (val_rcr)
 142                                 *((bool *) (val)) = false;
 143                         else
 144                                 *((bool *) (val)) = true;
 145                 }
 146                 break;
 147         }
 148         case HW_VAR_FW_PSMODE_STATUS:
 149                 *((bool *) (val)) = ppsc->fw_current_inpsmode;
 150                 break;
 151         case HW_VAR_CORRECT_TSF:{
 152                 u64 tsf;
 153                 u32 *ptsf_low = (u32 *)&tsf;
 154                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 155
 156                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 157                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 158                 *((u64 *) (val)) = tsf;
 159                 break;
 160         }
 161         case HW_VAR_INT_MIGRATION:
 162                 *((bool *)(val)) = rtlpriv->dm.interrupt_migration;
 163                 break;
 164         case HW_VAR_INT_AC:
 165                 *((bool *)(val)) = rtlpriv->dm.disable_tx_int;
 166                 break;
 167         default:
 168                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 169                          "switch case not processed\n");
 170                 break;
 171         }
 172 }
 173
 174 void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 175 {
 176         struct rtl_priv *rtlpriv = rtl_priv(hw);
 177         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 178         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 179         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 180         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 181         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 182         u8 idx;
 183
 184         switch (variable) {
 185         case HW_VAR_ETHER_ADDR:
 186                 for (idx = 0; idx < ETH_ALEN; idx++) {
 187                         rtl_write_byte(rtlpriv, (REG_MACID + idx),
 188                                        val[idx]);
 189                 }
 190                 break;
 191         case HW_VAR_BASIC_RATE: {
 192                 u16 rate_cfg = ((u16 *) val)[0];
 193                 u8 rate_index = 0;
 194
 195                 rate_cfg = rate_cfg & 0x15f;
 196                 if (mac->vendor == PEER_CISCO &&
 197                     ((rate_cfg & 0x150) == 0))
 198                         rate_cfg |= 0x01;
 199                 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
 200                 rtl_write_byte(rtlpriv, REG_RRSR + 1,
 201                                (rate_cfg >> 8) & 0xff);
 202                 while (rate_cfg > 0x1) {
 203                         rate_cfg = (rate_cfg >> 1);
 204                         rate_index++;
 205                 }
 206                 if (rtlhal->fw_version > 0xe)
 207                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
 208                                        rate_index);
 209                 break;
 210         }
 211         case HW_VAR_BSSID:
 212                 for (idx = 0; idx < ETH_ALEN; idx++) {
 213                         rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 214                                        val[idx]);
 215                 }
 216                 break;
 217         case HW_VAR_SIFS:
 218                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 219                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 220                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 221                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 222                 if (!mac->ht_enable)
 223                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 224                                        0x0e0e);
 225                 else
 226                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 227                                        *((u16 *) val));
 228                 break;
 229         case HW_VAR_SLOT_TIME: {
 230                 u8 e_aci;
 231
 232                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 233                          "HW_VAR_SLOT_TIME %x\n", val[0]);
 234                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 235                 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
 236                         rtlpriv->cfg->ops->set_hw_reg(hw,
 237                                                       HW_VAR_AC_PARAM,
 238                                                       (&e_aci));
 239                 break;
 240         }
 241         case HW_VAR_ACK_PREAMBLE: {
 242                 u8 reg_tmp;
 243                 u8 short_preamble = (bool) (*val);
 244
 245                 reg_tmp = (mac->cur_40_prime_sc) << 5;
 246                 if (short_preamble)
 247                         reg_tmp |= 0x80;
 248                 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
 249                 break;
 250         }
 251         case HW_VAR_AMPDU_MIN_SPACE: {
 252                 u8 min_spacing_to_set;
 253                 u8 sec_min_space;
 254
 255                 min_spacing_to_set = *val;
 256                 if (min_spacing_to_set <= 7) {
 257                         sec_min_space = 0;
 258                         if (min_spacing_to_set < sec_min_space)
 259                                 min_spacing_to_set = sec_min_space;
 260                         mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
 261                                               min_spacing_to_set);
 262                         *val = min_spacing_to_set;
 263                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 264                                  "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 265                                  mac->min_space_cfg);
 266                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 267                                        mac->min_space_cfg);
 268                 }
 269                 break;
 270         }
 271         case HW_VAR_SHORTGI_DENSITY: {
 272                 u8 density_to_set;
 273
 274                 density_to_set = *val;
 275                 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
 276                 mac->min_space_cfg |= (density_to_set << 3);
 277                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 278                          "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 279                          mac->min_space_cfg);
 280                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 281                                mac->min_space_cfg);
 282                 break;
 283         }
 284         case HW_VAR_AMPDU_FACTOR: {
 285                 u8 factor_toset;
 286                 u32 regtoSet;
 287                 u8 *ptmp_byte = NULL;
 288                 u8 index;
 289
 290                 if (rtlhal->macphymode == DUALMAC_DUALPHY)
 291                         regtoSet = 0xb9726641;
 292                 else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
 293                         regtoSet = 0x66626641;
 294                 else
 295                         regtoSet = 0xb972a841;
 296                 factor_toset = *val;
 297                 if (factor_toset <= 3) {
 298                         factor_toset = (1 << (factor_toset + 2));
 299                         if (factor_toset > 0xf)
 300                                 factor_toset = 0xf;
 301                         for (index = 0; index < 4; index++) {
 302                                 ptmp_byte = (u8 *) (&regtoSet) + index;
 303                                 if ((*ptmp_byte & 0xf0) >
 304                                     (factor_toset << 4))
 305                                         *ptmp_byte = (*ptmp_byte & 0x0f)
 306                                                  | (factor_toset << 4);
 307                                 if ((*ptmp_byte & 0x0f) > factor_toset)
 308                                         *ptmp_byte = (*ptmp_byte & 0xf0)
 309                                                      | (factor_toset);
 310                         }
 311                         rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoSet);
 312                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 313                                  "Set HW_VAR_AMPDU_FACTOR: %#x\n",
 314                                  factor_toset);
 315                 }
 316                 break;
 317         }
 318         case HW_VAR_AC_PARAM: {
 319                 u8 e_aci = *val;
 320                 rtl92d_dm_init_edca_turbo(hw);
 321                 if (rtlpci->acm_method != eAcmWay2_SW)
 322                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
 323                                                       &e_aci);
 324                 break;
 325         }
 326         case HW_VAR_ACM_CTRL: {
 327                 u8 e_aci = *val;
 328                 union aci_aifsn *p_aci_aifsn =
 329                     (union aci_aifsn *)(&(mac->ac[0].aifs));
 330                 u8 acm = p_aci_aifsn->f.acm;
 331                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 332
 333                 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?  0x0 : 0x1);
 334                 if (acm) {
 335                         switch (e_aci) {
 336                         case AC0_BE:
 337                                 acm_ctrl |= ACMHW_BEQEN;
 338                                 break;
 339                         case AC2_VI:
 340                                 acm_ctrl |= ACMHW_VIQEN;
 341                                 break;
 342                         case AC3_VO:
 343                                 acm_ctrl |= ACMHW_VOQEN;
 344                                 break;
 345                         default:
 346                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 347                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 348                                          acm);
 349                                 break;
 350                         }
 351                 } else {
 352                         switch (e_aci) {
 353                         case AC0_BE:
 354                                 acm_ctrl &= (~ACMHW_BEQEN);
 355                                 break;
 356                         case AC2_VI:
 357                                 acm_ctrl &= (~ACMHW_VIQEN);
 358                                 break;
 359                         case AC3_VO:
 360                                 acm_ctrl &= (~ACMHW_VOQEN);
 361                                 break;
 362                         default:
 363                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 364                                          "switch case not processed\n");
 365                                 break;
 366                         }
 367                 }
 368                 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 369                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 370                          acm_ctrl);
 371                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 372                 break;
 373         }
 374         case HW_VAR_RCR:
 375                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
 376                 rtlpci->receive_config = ((u32 *) (val))[0];
 377                 break;
 378         case HW_VAR_RETRY_LIMIT: {
 379                 u8 retry_limit = val[0];
 380
 381                 rtl_write_word(rtlpriv, REG_RL,
 382                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 383                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 384                 break;
 385         }
 386         case HW_VAR_DUAL_TSF_RST:
 387                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 388                 break;
 389         case HW_VAR_EFUSE_BYTES:
 390                 rtlefuse->efuse_usedbytes = *((u16 *) val);
 391                 break;
 392         case HW_VAR_EFUSE_USAGE:
 393                 rtlefuse->efuse_usedpercentage = *val;
 394                 break;
 395         case HW_VAR_IO_CMD:
 396                 rtl92d_phy_set_io_cmd(hw, (*(enum io_type *)val));
 397                 break;
 398         case HW_VAR_WPA_CONFIG:
 399                 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
 400                 break;
 401         case HW_VAR_SET_RPWM:
 402                 rtl92d_fill_h2c_cmd(hw, H2C_PWRM, 1, (val));
 403                 break;
 404         case HW_VAR_H2C_FW_PWRMODE:
 405                 break;
 406         case HW_VAR_FW_PSMODE_STATUS:
 407                 ppsc->fw_current_inpsmode = *((bool *) val);
 408                 break;
 409         case HW_VAR_H2C_FW_JOINBSSRPT: {
 410                 u8 mstatus = (*val);
 411                 u8 tmp_regcr, tmp_reg422;
 412                 bool recover = false;
 413
 414                 if (mstatus == RT_MEDIA_CONNECT) {
 415                         rtlpriv->cfg->ops->set_hw_reg(hw,
 416                                                       HW_VAR_AID, NULL);
 417                         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 418                         rtl_write_byte(rtlpriv, REG_CR + 1,
 419                                        (tmp_regcr | BIT(0)));
 420                         _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
 421                         _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
 422                         tmp_reg422 = rtl_read_byte(rtlpriv,
 423                                                  REG_FWHW_TXQ_CTRL + 2);
 424                         if (tmp_reg422 & BIT(6))
 425                                 recover = true;
 426                         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 427                                        tmp_reg422 & (~BIT(6)));
 428                         rtl92d_set_fw_rsvdpagepkt(hw, 0);
 429                         _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
 430                         _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
 431                         if (recover)
 432                                 rtl_write_byte(rtlpriv,
 433                                                REG_FWHW_TXQ_CTRL + 2,
 434                                                tmp_reg422);
 435                         rtl_write_byte(rtlpriv, REG_CR + 1,
 436                                        (tmp_regcr & ~(BIT(0))));
 437                 }
 438                 rtl92d_set_fw_joinbss_report_cmd(hw, (*val));
 439                 break;
 440         }
 441         case HW_VAR_AID: {
 442                 u16 u2btmp;
 443                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 444                 u2btmp &= 0xC000;
 445                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 446                                mac->assoc_id));
 447                 break;
 448         }
 449         case HW_VAR_CORRECT_TSF: {
 450                 u8 btype_ibss = val[0];
 451
 452                 if (btype_ibss)
 453                         _rtl92de_stop_tx_beacon(hw);
 454                 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
 455                 rtl_write_dword(rtlpriv, REG_TSFTR,
 456                                 (u32) (mac->tsf & 0xffffffff));
 457                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 458                                 (u32) ((mac->tsf >> 32) & 0xffffffff));
 459                 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
 460                 if (btype_ibss)
 461                         _rtl92de_resume_tx_beacon(hw);
 462
 463                 break;
 464         }
 465         case HW_VAR_INT_MIGRATION: {
 466                 bool int_migration = *(bool *) (val);
 467
 468                 if (int_migration) {
 469                         /* Set interrupt migration timer and
 470                          * corresponding Tx/Rx counter.
 471                          * timer 25ns*0xfa0=100us for 0xf packets.
 472                          * 0x306:Rx, 0x307:Tx */
 473                         rtl_write_dword(rtlpriv, REG_INT_MIG, 0xfe000fa0);
 474                         rtlpriv->dm.interrupt_migration = int_migration;
 475                 } else {
 476                         /* Reset all interrupt migration settings. */
 477                         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 478                         rtlpriv->dm.interrupt_migration = int_migration;
 479                 }
 480                 break;
 481         }
 482         case HW_VAR_INT_AC: {
 483                 bool disable_ac_int = *((bool *) val);
 484
 485                 /* Disable four ACs interrupts. */
 486                 if (disable_ac_int) {
 487                         /* Disable VO, VI, BE and BK four AC interrupts
 488                          * to gain more efficient CPU utilization.
 489                          * When extremely highly Rx OK occurs,
 490                          * we will disable Tx interrupts.
 491                          */
 492                         rtlpriv->cfg->ops->update_interrupt_mask(hw, 0,
 493                                                  RT_AC_INT_MASKS);
 494                         rtlpriv->dm.disable_tx_int = disable_ac_int;
 495                 /* Enable four ACs interrupts. */
 496                 } else {
 497                         rtlpriv->cfg->ops->update_interrupt_mask(hw,
 498                                                  RT_AC_INT_MASKS, 0);
 499                         rtlpriv->dm.disable_tx_int = disable_ac_int;
 500                 }
 501                 break;
 502         }
 503         default:
 504                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 505                          "switch case not processed\n");
 506                 break;
 507         }
 508 }
 509
 510 static bool _rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 511 {
 512         struct rtl_priv *rtlpriv = rtl_priv(hw);
 513         bool status = true;
 514         long count = 0;
 515         u32 value = _LLT_INIT_ADDR(address) |
 516             _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
 517
 518         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 519         do {
 520                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 521                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 522                         break;
 523                 if (count > POLLING_LLT_THRESHOLD) {
 524                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 525                                  "Failed to polling write LLT done at address %d!\n",
 526                                  address);
 527                         status = false;
 528                         break;
 529                 }
 530         } while (++count);
 531         return status;
 532 }
 533
 534 static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw)
 535 {
 536         struct rtl_priv *rtlpriv = rtl_priv(hw);
 537         unsigned short i;
 538         u8 txpktbuf_bndy;
 539         u8 maxPage;
 540         bool status;
 541         u32 value32; /* High+low page number */
 542         u8 value8;       /* normal page number */
 543
 544         if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
 545                 maxPage = 255;
 546                 txpktbuf_bndy = 246;
 547                 value8 = 0;
 548                 value32 = 0x80bf0d29;
 549         } else if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
 550                 maxPage = 127;
 551                 txpktbuf_bndy = 123;
 552                 value8 = 0;
 553                 value32 = 0x80750005;
 554         }
 555
 556         /* Set reserved page for each queue */
 557         /* 11.  RQPN 0x200[31:0] = 0x80BD1C1C */
 558         /* load RQPN */
 559         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
 560         rtl_write_dword(rtlpriv, REG_RQPN, value32);
 561
 562         /* 12.  TXRKTBUG_PG_BNDY 0x114[31:0] = 0x27FF00F6 */
 563         /* TXRKTBUG_PG_BNDY */
 564         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
 565                         (rtl_read_word(rtlpriv, REG_TRXFF_BNDY + 2) << 16 |
 566                         txpktbuf_bndy));
 567
 568         /* 13.  TDECTRL[15:8] 0x209[7:0] = 0xF6 */
 569         /* Beacon Head for TXDMA */
 570         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 571
 572         /* 14.  BCNQ_PGBNDY 0x424[7:0] =  0xF6 */
 573         /* BCNQ_PGBNDY */
 574         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 575         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 576
 577         /* 15.  WMAC_LBK_BF_HD 0x45D[7:0] =  0xF6 */
 578         /* WMAC_LBK_BF_HD */
 579         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 580
 581         /* Set Tx/Rx page size (Tx must be 128 Bytes, */
 582         /* Rx can be 64,128,256,512,1024 bytes) */
 583         /* 16.  PBP [7:0] = 0x11 */
 584         /* TRX page size */
 585         rtl_write_byte(rtlpriv, REG_PBP, 0x11);
 586
 587         /* 17.  DRV_INFO_SZ = 0x04 */
 588         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 589
 590         /* 18.  LLT_table_init(Adapter);  */
 591         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 592                 status = _rtl92de_llt_write(hw, i, i + 1);
 593                 if (true != status)
 594                         return status;
 595         }
 596
 597         /* end of list */
 598         status = _rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 599         if (true != status)
 600                 return status;
 601
 602         /* Make the other pages as ring buffer */
 603         /* This ring buffer is used as beacon buffer if we */
 604         /* config this MAC as two MAC transfer. */
 605         /* Otherwise used as local loopback buffer.  */
 606         for (i = txpktbuf_bndy; i < maxPage; i++) {
 607                 status = _rtl92de_llt_write(hw, i, (i + 1));
 608                 if (true != status)
 609                         return status;
 610         }
 611
 612         /* Let last entry point to the start entry of ring buffer */
 613         status = _rtl92de_llt_write(hw, maxPage, txpktbuf_bndy);
 614         if (true != status)
 615                 return status;
 616
 617         return true;
 618 }
 619
 620 static void _rtl92de_gen_refresh_led_state(struct ieee80211_hw *hw)
 621 {
 622         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 623         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 624         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 625         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 626
 627         if (rtlpci->up_first_time)
 628                 return;
 629         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 630                 rtl92de_sw_led_on(hw, pLed0);
 631         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 632                 rtl92de_sw_led_on(hw, pLed0);
 633         else
 634                 rtl92de_sw_led_off(hw, pLed0);
 635 }
 636
 637 static bool _rtl92de_init_mac(struct ieee80211_hw *hw)
 638 {
 639         struct rtl_priv *rtlpriv = rtl_priv(hw);
 640         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 641         unsigned char bytetmp;
 642         unsigned short wordtmp;
 643         u16 retry;
 644
 645         rtl92d_phy_set_poweron(hw);
 646         /* Add for resume sequence of power domain according
 647          * to power document V11. Chapter V.11....  */
 648         /* 0.   RSV_CTRL 0x1C[7:0] = 0x00  */
 649         /* unlock ISO/CLK/Power control register */
 650         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 651         rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x05);
 652
 653         /* 1.   AFE_XTAL_CTRL [7:0] = 0x0F  enable XTAL */
 654         /* 2.   SPS0_CTRL 0x11[7:0] = 0x2b  enable SPS into PWM mode  */
 655         /* 3.   delay (1ms) this is not necessary when initially power on */
 656
 657         /* C.   Resume Sequence */
 658         /* a.   SPS0_CTRL 0x11[7:0] = 0x2b */
 659         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
 660
 661         /* b.   AFE_XTAL_CTRL [7:0] = 0x0F */
 662         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
 663
 664         /* c.   DRV runs power on init flow */
 665
 666         /* auto enable WLAN */
 667         /* 4.   APS_FSMCO 0x04[8] = 1; wait till 0x04[8] = 0   */
 668         /* Power On Reset for MAC Block */
 669         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
 670         udelay(2);
 671         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 672         udelay(2);
 673
 674         /* 5.   Wait while 0x04[8] == 0 goto 2, otherwise goto 1 */
 675         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 676         udelay(50);
 677         retry = 0;
 678         while ((bytetmp & BIT(0)) && retry < 1000) {
 679                 retry++;
 680                 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 681                 udelay(50);
 682         }
 683
 684         /* Enable Radio off, GPIO, and LED function */
 685         /* 6.   APS_FSMCO 0x04[15:0] = 0x0012  when enable HWPDN */
 686         rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
 687
 688         /* release RF digital isolation  */
 689         /* 7.  SYS_ISO_CTRL 0x01[1]    = 0x0;  */
 690         /*Set REG_SYS_ISO_CTRL 0x1=0x82 to prevent wake# problem. */
 691         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
 692         udelay(2);
 693
 694         /* make sure that BB reset OK. */
 695         /* rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); */
 696
 697         /* Disable REG_CR before enable it to assure reset */
 698         rtl_write_word(rtlpriv, REG_CR, 0x0);
 699
 700         /* Release MAC IO register reset */
 701         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 702
 703         /* clear stopping tx/rx dma   */
 704         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x0);
 705
 706         /* rtl_write_word(rtlpriv,REG_CR+2, 0x2); */
 707
 708         /* System init */
 709         /* 18.  LLT_table_init(Adapter);  */
 710         if (!_rtl92de_llt_table_init(hw))
 711                 return false;
 712
 713         /* Clear interrupt and enable interrupt */
 714         /* 19.  HISR 0x124[31:0] = 0xffffffff;  */
 715         /*      HISRE 0x12C[7:0] = 0xFF */
 716         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 717         rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
 718
 719         /* 20.  HIMR 0x120[31:0] |= [enable INT mask bit map];  */
 720         /* 21.  HIMRE 0x128[7:0] = [enable INT mask bit map] */
 721         /* The IMR should be enabled later after all init sequence
 722          * is finished. */
 723
 724         /* 22.  PCIE configuration space configuration */
 725         /* 23.  Ensure PCIe Device 0x80[15:0] = 0x0143 (ASPM+CLKREQ),  */
 726         /*      and PCIe gated clock function is enabled.    */
 727         /* PCIE configuration space will be written after
 728          * all init sequence.(Or by BIOS) */
 729
 730         rtl92d_phy_config_maccoexist_rfpage(hw);
 731
 732         /* THe below section is not related to power document Vxx . */
 733         /* This is only useful for driver and OS setting. */
 734         /* -------------------Software Relative Setting---------------------- */
 735         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 736         wordtmp &= 0xf;
 737         wordtmp |= 0xF771;
 738         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 739
 740         /* Reported Tx status from HW for rate adaptive. */
 741         /* This should be realtive to power on step 14. But in document V11  */
 742         /* still not contain the description.!!! */
 743         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 744
 745         /* Set Tx/Rx page size (Tx must be 128 Bytes,
 746          * Rx can be 64,128,256,512,1024 bytes) */
 747         /* rtl_write_byte(rtlpriv,REG_PBP, 0x11); */
 748
 749         /* Set RCR register */
 750         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 751         /* rtl_write_byte(rtlpriv,REG_RX_DRVINFO_SZ, 4); */
 752
 753         /*  Set TCR register */
 754         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 755
 756         /* disable earlymode */
 757         rtl_write_byte(rtlpriv, 0x4d0, 0x0);
 758
 759         /* Set TX/RX descriptor physical address(from OS API). */
 760         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 761                         rtlpci->tx_ring[BEACON_QUEUE].dma);
 762         rtl_write_dword(rtlpriv, REG_MGQ_DESA, rtlpci->tx_ring[MGNT_QUEUE].dma);
 763         rtl_write_dword(rtlpriv, REG_VOQ_DESA, rtlpci->tx_ring[VO_QUEUE].dma);
 764         rtl_write_dword(rtlpriv, REG_VIQ_DESA, rtlpci->tx_ring[VI_QUEUE].dma);
 765         rtl_write_dword(rtlpriv, REG_BEQ_DESA, rtlpci->tx_ring[BE_QUEUE].dma);
 766         rtl_write_dword(rtlpriv, REG_BKQ_DESA, rtlpci->tx_ring[BK_QUEUE].dma);
 767         rtl_write_dword(rtlpriv, REG_HQ_DESA, rtlpci->tx_ring[HIGH_QUEUE].dma);
 768         /* Set RX Desc Address */
 769         rtl_write_dword(rtlpriv, REG_RX_DESA,
 770                         rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
 771
 772         /* if we want to support 64 bit DMA, we should set it here,
 773          * but now we do not support 64 bit DMA*/
 774
 775         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x33);
 776
 777         /* Reset interrupt migration setting when initialization */
 778         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 779
 780         /* Reconsider when to do this operation after asking HWSD. */
 781         bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 782         rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
 783         do {
 784                 retry++;
 785                 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 786         } while ((retry < 200) && !(bytetmp & BIT(7)));
 787
 788         /* After MACIO reset,we must refresh LED state. */
 789         _rtl92de_gen_refresh_led_state(hw);
 790
 791         /* Reset H2C protection register */
 792         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 793
 794         return true;
 795 }
 796
 797 static void _rtl92de_hw_configure(struct ieee80211_hw *hw)
 798 {
 799         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 800         struct rtl_priv *rtlpriv = rtl_priv(hw);
 801         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 802         u8 reg_bw_opmode = BW_OPMODE_20MHZ;
 803         u32 reg_rrsr;
 804
 805         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 806         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
 807         rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 808         rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
 809         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
 810         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
 811         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
 812         rtl_write_word(rtlpriv, REG_RL, 0x0707);
 813         rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
 814         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 815         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
 816         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
 817         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
 818         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
 819         /* Aggregation threshold */
 820         if (rtlhal->macphymode == DUALMAC_DUALPHY)
 821                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb9726641);
 822         else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
 823                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66626641);
 824         else
 825                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
 826         rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
 827         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
 828         rtlpci->reg_bcn_ctrl_val = 0x1f;
 829         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
 830         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 831         rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
 832         rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
 833         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 834         /* For throughput */
 835         rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x6666);
 836         /* ACKTO for IOT issue. */
 837         rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
 838         /* Set Spec SIFS (used in NAV) */
 839         rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
 840         rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
 841         /* Set SIFS for CCK */
 842         rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
 843         /* Set SIFS for OFDM */
 844         rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
 845         /* Set Multicast Address. */
 846         rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
 847         rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
 848         switch (rtlpriv->phy.rf_type) {
 849         case RF_1T2R:
 850         case RF_1T1R:
 851                 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
 852                 break;
 853         case RF_2T2R:
 854         case RF_2T2R_GREEN:
 855                 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
 856                 break;
 857         }
 858 }
 859
 860 static void _rtl92de_enable_aspm_back_door(struct ieee80211_hw *hw)
 861 {
 862         struct rtl_priv *rtlpriv = rtl_priv(hw);
 863         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 864
 865         rtl_write_byte(rtlpriv, 0x34b, 0x93);
 866         rtl_write_word(rtlpriv, 0x350, 0x870c);
 867         rtl_write_byte(rtlpriv, 0x352, 0x1);
 868         if (ppsc->support_backdoor)
 869                 rtl_write_byte(rtlpriv, 0x349, 0x1b);
 870         else
 871                 rtl_write_byte(rtlpriv, 0x349, 0x03);
 872         rtl_write_word(rtlpriv, 0x350, 0x2718);
 873         rtl_write_byte(rtlpriv, 0x352, 0x1);
 874 }
 875
 876 void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw)
 877 {
 878         struct rtl_priv *rtlpriv = rtl_priv(hw);
 879         u8 sec_reg_value;
 880
 881         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 882                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 883                  rtlpriv->sec.pairwise_enc_algorithm,
 884                  rtlpriv->sec.group_enc_algorithm);
 885         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 886                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 887                          "not open hw encryption\n");
 888                 return;
 889         }
 890         sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
 891         if (rtlpriv->sec.use_defaultkey) {
 892                 sec_reg_value |= SCR_TXUSEDK;
 893                 sec_reg_value |= SCR_RXUSEDK;
 894         }
 895         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
 896         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
 897         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
 898                  "The SECR-value %x\n", sec_reg_value);
 899         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 900 }
 901
 902 int rtl92de_hw_init(struct ieee80211_hw *hw)
 903 {
 904         struct rtl_priv *rtlpriv = rtl_priv(hw);
 905         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 906         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 907         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 908         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 909         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 910         bool rtstatus = true;
 911         u8 tmp_u1b;
 912         int i;
 913         int err;
 914         unsigned long flags;
 915
 916         rtlpci->being_init_adapter = true;
 917         rtlpci->init_ready = false;
 918         spin_lock_irqsave(&globalmutex_for_power_and_efuse, flags);
 919         /* we should do iqk after disable/enable */
 920         rtl92d_phy_reset_iqk_result(hw);
 921         /* rtlpriv->intf_ops->disable_aspm(hw); */
 922         rtstatus = _rtl92de_init_mac(hw);
 923         if (!rtstatus) {
 924                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
 925                 err = 1;
 926                 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
 927                 return err;
 928         }
 929         err = rtl92d_download_fw(hw);
 930         spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
 931         if (err) {
 932                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 933                          "Failed to download FW. Init HW without FW..\n");
 934                 return 1;
 935         }
 936         rtlhal->last_hmeboxnum = 0;
 937         rtlpriv->psc.fw_current_inpsmode = false;
 938
 939         tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
 940         tmp_u1b = tmp_u1b | 0x30;
 941         rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
 942
 943         if (rtlhal->earlymode_enable) {
 944                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 945                          "EarlyMode Enabled!!!\n");
 946
 947                 tmp_u1b = rtl_read_byte(rtlpriv, 0x4d0);
 948                 tmp_u1b = tmp_u1b | 0x1f;
 949                 rtl_write_byte(rtlpriv, 0x4d0, tmp_u1b);
 950
 951                 rtl_write_byte(rtlpriv, 0x4d3, 0x80);
 952
 953                 tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
 954                 tmp_u1b = tmp_u1b | 0x40;
 955                 rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
 956         }
 957
 958         if (mac->rdg_en) {
 959                 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xff);
 960                 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200);
 961                 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05);
 962         }
 963
 964         rtl92d_phy_mac_config(hw);
 965         /* because last function modify RCR, so we update
 966          * rcr var here, or TP will unstable for receive_config
 967          * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
 968          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
 969         rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
 970         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
 971
 972         rtl92d_phy_bb_config(hw);
 973
 974         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
 975         /* set before initialize RF */
 976         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
 977
 978         /* config RF */
 979         rtl92d_phy_rf_config(hw);
 980
 981         /* After read predefined TXT, we must set BB/MAC/RF
 982          * register as our requirement */
 983         /* After load BB,RF params,we need do more for 92D. */
 984         rtl92d_update_bbrf_configuration(hw);
 985         /* set default value after initialize RF,  */
 986         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
 987         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
 988                         RF_CHNLBW, BRFREGOFFSETMASK);
 989         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
 990                         RF_CHNLBW, BRFREGOFFSETMASK);
 991
 992         /*---- Set CCK and OFDM Block "ON"----*/
 993         if (rtlhal->current_bandtype == BAND_ON_2_4G)
 994                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
 995         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
 996         if (rtlhal->interfaceindex == 0) {
 997                 /* RFPGA0_ANALOGPARAMETER2: cck clock select,
 998                  *  set to 20MHz by default */
 999                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1000                               BIT(11), 3);
1001         } else {
1002                 /* Mac1 */
1003                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(11) |
1004                               BIT(10), 3);
1005         }
1006
1007         _rtl92de_hw_configure(hw);
1008
1009         /* reset hw sec */
1010         rtl_cam_reset_all_entry(hw);
1011         rtl92de_enable_hw_security_config(hw);
1012
1013         /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1014         /* TX power index for different rate set. */
1015         rtl92d_phy_get_hw_reg_originalvalue(hw);
1016         rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
1017
1018         ppsc->rfpwr_state = ERFON;
1019
1020         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1021
1022         _rtl92de_enable_aspm_back_door(hw);
1023         /* rtlpriv->intf_ops->enable_aspm(hw); */
1024
1025         rtl92d_dm_init(hw);
1026         rtlpci->being_init_adapter = false;
1027
1028         if (ppsc->rfpwr_state == ERFON) {
1029                 rtl92d_phy_lc_calibrate(hw);
1030                 /* 5G and 2.4G must wait sometime to let RF LO ready */
1031                 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1032                         u32 tmp_rega;
1033                         for (i = 0; i < 10000; i++) {
1034                                 udelay(MAX_STALL_TIME);
1035
1036                                 tmp_rega = rtl_get_rfreg(hw,
1037                                                   (enum radio_path)RF90_PATH_A,
1038                                                   0x2a, BMASKDWORD);
1039
1040                                 if (((tmp_rega & BIT(11)) == BIT(11)))
1041                                         break;
1042                         }
1043                         /* check that loop was successful. If not, exit now */
1044                         if (i == 10000) {
1045                                 rtlpci->init_ready = false;
1046                                 return 1;
1047                         }
1048                 }
1049         }
1050         rtlpci->init_ready = true;
1051         return err;
1052 }
1053
1054 static enum version_8192d _rtl92de_read_chip_version(struct ieee80211_hw *hw)
1055 {
1056         struct rtl_priv *rtlpriv = rtl_priv(hw);
1057         enum version_8192d version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1058         u32 value32;
1059
1060         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1061         if (!(value32 & 0x000f0000)) {
1062                 version = VERSION_TEST_CHIP_92D_SINGLEPHY;
1063                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "TEST CHIP!!!\n");
1064         } else {
1065                 version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1066                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Normal CHIP!!!\n");
1067         }
1068         return version;
1069 }
1070
1071 static int _rtl92de_set_media_status(struct ieee80211_hw *hw,
1072                                      enum nl80211_iftype type)
1073 {
1074         struct rtl_priv *rtlpriv = rtl_priv(hw);
1075         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1076         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1077         u8 bcnfunc_enable;
1078
1079         bt_msr &= 0xfc;
1080
1081         if (type == NL80211_IFTYPE_UNSPECIFIED ||
1082             type == NL80211_IFTYPE_STATION) {
1083                 _rtl92de_stop_tx_beacon(hw);
1084                 _rtl92de_enable_bcn_sub_func(hw);
1085         } else if (type == NL80211_IFTYPE_ADHOC ||
1086                 type == NL80211_IFTYPE_AP) {
1087                 _rtl92de_resume_tx_beacon(hw);
1088                 _rtl92de_disable_bcn_sub_func(hw);
1089         } else {
1090                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1091                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",
1092                          type);
1093         }
1094         bcnfunc_enable = rtl_read_byte(rtlpriv, REG_BCN_CTRL);
1095         switch (type) {
1096         case NL80211_IFTYPE_UNSPECIFIED:
1097                 bt_msr |= MSR_NOLINK;
1098                 ledaction = LED_CTL_LINK;
1099                 bcnfunc_enable &= 0xF7;
1100                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1101                          "Set Network type to NO LINK!\n");
1102                 break;
1103         case NL80211_IFTYPE_ADHOC:
1104                 bt_msr |= MSR_ADHOC;
1105                 bcnfunc_enable |= 0x08;
1106                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1107                          "Set Network type to Ad Hoc!\n");
1108                 break;
1109         case NL80211_IFTYPE_STATION:
1110                 bt_msr |= MSR_INFRA;
1111                 ledaction = LED_CTL_LINK;
1112                 bcnfunc_enable &= 0xF7;
1113                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1114                          "Set Network type to STA!\n");
1115                 break;
1116         case NL80211_IFTYPE_AP:
1117                 bt_msr |= MSR_AP;
1118                 bcnfunc_enable |= 0x08;
1119                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1120                          "Set Network type to AP!\n");
1121                 break;
1122         default:
1123                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1124                          "Network type %d not supported!\n", type);
1125                 return 1;
1126                 break;
1127
1128         }
1129         rtl_write_byte(rtlpriv, REG_CR + 2, bt_msr);
1130         rtlpriv->cfg->ops->led_control(hw, ledaction);
1131         if ((bt_msr & 0xfc) == MSR_AP)
1132                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1133         else
1134                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1135         return 0;
1136 }
1137
1138 void rtl92de_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1139 {
1140         struct rtl_priv *rtlpriv = rtl_priv(hw);
1141         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1142         u32 reg_rcr = rtlpci->receive_config;
1143
1144         if (rtlpriv->psc.rfpwr_state != ERFON)
1145                 return;
1146         if (check_bssid) {
1147                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1148                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1149                 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
1150         } else if (!check_bssid) {
1151                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1152                 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
1153                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1154         }
1155 }
1156
1157 int rtl92de_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1158 {
1159         struct rtl_priv *rtlpriv = rtl_priv(hw);
1160
1161         if (_rtl92de_set_media_status(hw, type))
1162                 return -EOPNOTSUPP;
1163
1164         /* check bssid */
1165         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1166                 if (type != NL80211_IFTYPE_AP)
1167                         rtl92de_set_check_bssid(hw, true);
1168         } else {
1169                 rtl92de_set_check_bssid(hw, false);
1170         }
1171         return 0;
1172 }
1173
1174 /* do iqk or reload iqk */
1175 /* windows just rtl92d_phy_reload_iqk_setting in set channel,
1176  * but it's very strict for time sequence so we add
1177  * rtl92d_phy_reload_iqk_setting here */
1178 void rtl92d_linked_set_reg(struct ieee80211_hw *hw)
1179 {
1180         struct rtl_priv *rtlpriv = rtl_priv(hw);
1181         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1182         u8 indexforchannel;
1183         u8 channel = rtlphy->current_channel;
1184
1185         indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
1186         if (!rtlphy->iqk_matrix[indexforchannel].iqk_done) {
1187                 RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_DMESG,
1188                          "Do IQK for channel:%d\n", channel);
1189                 rtl92d_phy_iq_calibrate(hw);
1190         }
1191 }
1192
1193 /* don't set REG_EDCA_BE_PARAM here because
1194  * mac80211 will send pkt when scan */
1195 void rtl92de_set_qos(struct ieee80211_hw *hw, int aci)
1196 {
1197         rtl92d_dm_init_edca_turbo(hw);
1198 }
1199
1200 void rtl92de_enable_interrupt(struct ieee80211_hw *hw)
1201 {
1202         struct rtl_priv *rtlpriv = rtl_priv(hw);
1203         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1204
1205         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1206         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1207 }
1208
1209 void rtl92de_disable_interrupt(struct ieee80211_hw *hw)
1210 {
1211         struct rtl_priv *rtlpriv = rtl_priv(hw);
1212         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1213
1214         rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1215         rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1216         synchronize_irq(rtlpci->pdev->irq);
1217 }
1218
1219 static void _rtl92de_poweroff_adapter(struct ieee80211_hw *hw)
1220 {
1221         struct rtl_priv *rtlpriv = rtl_priv(hw);
1222         u8 u1b_tmp;
1223         unsigned long flags;
1224
1225         rtlpriv->intf_ops->enable_aspm(hw);
1226         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1227         rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(3), 0);
1228         rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(15), 0);
1229
1230         /* 0x20:value 05-->04 */
1231         rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1232
1233         /*  ==== Reset digital sequence   ====== */
1234         rtl92d_firmware_selfreset(hw);
1235
1236         /* f.   SYS_FUNC_EN 0x03[7:0]=0x51 reset MCU, MAC register, DCORE */
1237         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1238
1239         /* g.   MCUFWDL 0x80[1:0]=0 reset MCU ready status */
1240         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1241
1242         /*  ==== Pull GPIO PIN to balance level and LED control ====== */
1243
1244         /* h.     GPIO_PIN_CTRL 0x44[31:0]=0x000  */
1245         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1246
1247         /* i.    Value = GPIO_PIN_CTRL[7:0] */
1248         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1249
1250         /* j.    GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); */
1251         /* write external PIN level  */
1252         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL,
1253                         0x00FF0000 | (u1b_tmp << 8));
1254
1255         /* k.   GPIO_MUXCFG 0x42 [15:0] = 0x0780 */
1256         rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1257
1258         /* l.   LEDCFG 0x4C[15:0] = 0x8080 */
1259         rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1260
1261         /*  ==== Disable analog sequence === */
1262
1263         /* m.   AFE_PLL_CTRL[7:0] = 0x80  disable PLL */
1264         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1265
1266         /* n.   SPS0_CTRL 0x11[7:0] = 0x22  enter PFM mode */
1267         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1268
1269         /* o.   AFE_XTAL_CTRL 0x24[7:0] = 0x0E  disable XTAL, if No BT COEX */
1270         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1271
1272         /* p.   RSV_CTRL 0x1C[7:0] = 0x0E lock ISO/CLK/Power control register */
1273         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1274
1275         /*  ==== interface into suspend === */
1276
1277         /* q.   APS_FSMCO[15:8] = 0x58 PCIe suspend mode */
1278         /* According to power document V11, we need to set this */
1279         /* value as 0x18. Otherwise, we may not L0s sometimes. */
1280         /* This indluences power consumption. Bases on SD1's test, */
1281         /* set as 0x00 do not affect power current. And if it */
1282         /* is set as 0x18, they had ever met auto load fail problem. */
1283         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1284
1285         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1286                  "In PowerOff,reg0x%x=%X\n",
1287                  REG_SPS0_CTRL, rtl_read_byte(rtlpriv, REG_SPS0_CTRL));
1288         /* r.   Note: for PCIe interface, PON will not turn */
1289         /* off m-bias and BandGap in PCIe suspend mode.  */
1290
1291         /* 0x17[7] 1b': power off in process  0b' : power off over */
1292         if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
1293                 spin_lock_irqsave(&globalmutex_power, flags);
1294                 u1b_tmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
1295                 u1b_tmp &= (~BIT(7));
1296                 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1b_tmp);
1297                 spin_unlock_irqrestore(&globalmutex_power, flags);
1298         }
1299
1300         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<=======\n");
1301 }
1302
1303 void rtl92de_card_disable(struct ieee80211_hw *hw)
1304 {
1305         struct rtl_priv *rtlpriv = rtl_priv(hw);
1306         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1307         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1308         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1309         enum nl80211_iftype opmode;
1310
1311         mac->link_state = MAC80211_NOLINK;
1312         opmode = NL80211_IFTYPE_UNSPECIFIED;
1313         _rtl92de_set_media_status(hw, opmode);
1314
1315         if (rtlpci->driver_is_goingto_unload ||
1316             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1317                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1318         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1319         /* Power sequence for each MAC. */
1320         /* a. stop tx DMA  */
1321         /* b. close RF */
1322         /* c. clear rx buf */
1323         /* d. stop rx DMA */
1324         /* e.  reset MAC */
1325
1326         /* a. stop tx DMA */
1327         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1328         udelay(50);
1329
1330         /* b. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
1331
1332         /* c. ========RF OFF sequence==========  */
1333         /* 0x88c[23:20] = 0xf. */
1334         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1335         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00);
1336
1337         /* APSD_CTRL 0x600[7:0] = 0x40 */
1338         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1339
1340         /* Close antenna 0,0xc04,0xd04 */
1341         rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0);
1342         rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0);
1343
1344         /*  SYS_FUNC_EN 0x02[7:0] = 0xE2   reset BB state machine */
1345         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1346
1347         /* Mac0 can not do Global reset. Mac1 can do. */
1348         /* SYS_FUNC_EN 0x02[7:0] = 0xE0  reset BB state machine  */
1349         if (rtlpriv->rtlhal.interfaceindex == 1)
1350                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1351         udelay(50);
1352
1353         /* d.  stop tx/rx dma before disable REG_CR (0x100) to fix */
1354         /* dma hang issue when disable/enable device.  */
1355         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
1356         udelay(50);
1357         rtl_write_byte(rtlpriv, REG_CR, 0x0);
1358         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==> Do power off.......\n");
1359         if (rtl92d_phy_check_poweroff(hw))
1360                 _rtl92de_poweroff_adapter(hw);
1361         return;
1362 }
1363
1364 void rtl92de_interrupt_recognized(struct ieee80211_hw *hw,
1365                                   u32 *p_inta, u32 *p_intb)
1366 {
1367         struct rtl_priv *rtlpriv = rtl_priv(hw);
1368         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1369
1370         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1371         rtl_write_dword(rtlpriv, ISR, *p_inta);
1372
1373         /*
1374          * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1375          * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1376          */
1377 }
1378
1379 void rtl92de_set_beacon_related_registers(struct ieee80211_hw *hw)
1380 {
1381         struct rtl_priv *rtlpriv = rtl_priv(hw);
1382         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1383         u16 bcn_interval, atim_window;
1384
1385         bcn_interval = mac->beacon_interval;
1386         atim_window = 2;
1387         /*rtl92de_disable_interrupt(hw);  */
1388         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1389         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1390         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1391         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x20);
1392         if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)
1393                 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30);
1394         else
1395                 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x20);
1396         rtl_write_byte(rtlpriv, 0x606, 0x30);
1397 }
1398
1399 void rtl92de_set_beacon_interval(struct ieee80211_hw *hw)
1400 {
1401         struct rtl_priv *rtlpriv = rtl_priv(hw);
1402         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1403         u16 bcn_interval = mac->beacon_interval;
1404
1405         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1406                  "beacon_interval:%d\n", bcn_interval);
1407         /* rtl92de_disable_interrupt(hw); */
1408         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1409         /* rtl92de_enable_interrupt(hw); */
1410 }
1411
1412 void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw,
1413                                    u32 add_msr, u32 rm_msr)
1414 {
1415         struct rtl_priv *rtlpriv = rtl_priv(hw);
1416         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1417
1418         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1419                  add_msr, rm_msr);
1420         if (add_msr)
1421                 rtlpci->irq_mask[0] |= add_msr;
1422         if (rm_msr)
1423                 rtlpci->irq_mask[0] &= (~rm_msr);
1424         rtl92de_disable_interrupt(hw);
1425         rtl92de_enable_interrupt(hw);
1426 }
1427
1428 static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo,
1429                                  u8 *rom_content, bool autoLoadfail)
1430 {
1431         u32 rfpath, eeaddr, group, offset1, offset2;
1432         u8 i;
1433
1434         memset(pwrinfo, 0, sizeof(struct txpower_info));
1435         if (autoLoadfail) {
1436                 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1437                         for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1438                                 if (group < CHANNEL_GROUP_MAX_2G) {
1439                                         pwrinfo->cck_index[rfpath][group] =
1440                                             EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1441                                         pwrinfo->ht40_1sindex[rfpath][group] =
1442                                             EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1443                                 } else {
1444                                         pwrinfo->ht40_1sindex[rfpath][group] =
1445                                             EEPROM_DEFAULT_TXPOWERLEVEL_5G;
1446                                 }
1447                                 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1448                                     EEPROM_DEFAULT_HT40_2SDIFF;
1449                                 pwrinfo->ht20indexdiff[rfpath][group] =
1450                                     EEPROM_DEFAULT_HT20_DIFF;
1451                                 pwrinfo->ofdmindexdiff[rfpath][group] =
1452                                     EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1453                                 pwrinfo->ht40maxoffset[rfpath][group] =
1454                                     EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1455                                 pwrinfo->ht20maxoffset[rfpath][group] =
1456                                     EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1457                         }
1458                 }
1459                 for (i = 0; i < 3; i++) {
1460                         pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1461                         pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1462                 }
1463                 return;
1464         }
1465
1466         /* Maybe autoload OK,buf the tx power index value is not filled.
1467          * If we find it, we set it to default value. */
1468         for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1469                 for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) {
1470                         eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3)
1471                                  + group;
1472                         pwrinfo->cck_index[rfpath][group] =
1473                                         (rom_content[eeaddr] == 0xFF) ?
1474                                              (eeaddr > 0x7B ?
1475                                              EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1476                                              EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1477                                              rom_content[eeaddr];
1478                 }
1479         }
1480         for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1481                 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1482                         offset1 = group / 3;
1483                         offset2 = group % 3;
1484                         eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3) +
1485                             offset2 + offset1 * 21;
1486                         pwrinfo->ht40_1sindex[rfpath][group] =
1487                             (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ?
1488                                              EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1489                                              EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1490                                                  rom_content[eeaddr];
1491                 }
1492         }
1493         /* These just for 92D efuse offset. */
1494         for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1495                 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1496                         int base1 = EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G;
1497
1498                         offset1 = group / 3;
1499                         offset2 = group % 3;
1500
1501                         if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF)
1502                                 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1503                                     (rom_content[base1 +
1504                                      offset2 + offset1 * 21] >> (rfpath * 4))
1505                                      & 0xF;
1506                         else
1507                                 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1508                                     EEPROM_DEFAULT_HT40_2SDIFF;
1509                         if (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2
1510                             + offset1 * 21] != 0xFF)
1511                                 pwrinfo->ht20indexdiff[rfpath][group] =
1512                                     (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G
1513                                     + offset2 + offset1 * 21] >> (rfpath * 4))
1514                                     & 0xF;
1515                         else
1516                                 pwrinfo->ht20indexdiff[rfpath][group] =
1517                                     EEPROM_DEFAULT_HT20_DIFF;
1518                         if (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset2
1519                             + offset1 * 21] != 0xFF)
1520                                 pwrinfo->ofdmindexdiff[rfpath][group] =
1521                                     (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G
1522                                      + offset2 + offset1 * 21] >> (rfpath * 4))
1523                                      & 0xF;
1524                         else
1525                                 pwrinfo->ofdmindexdiff[rfpath][group] =
1526                                     EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1527                         if (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset2
1528                             + offset1 * 21] != 0xFF)
1529                                 pwrinfo->ht40maxoffset[rfpath][group] =
1530                                     (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G
1531                                     + offset2 + offset1 * 21] >> (rfpath * 4))
1532                                     & 0xF;
1533                         else
1534                                 pwrinfo->ht40maxoffset[rfpath][group] =
1535                                     EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1536                         if (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset2
1537                             + offset1 * 21] != 0xFF)
1538                                 pwrinfo->ht20maxoffset[rfpath][group] =
1539                                     (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G +
1540                                      offset2 + offset1 * 21] >> (rfpath * 4)) &
1541                                      0xF;
1542                         else
1543                                 pwrinfo->ht20maxoffset[rfpath][group] =
1544                                     EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1545                 }
1546         }
1547         if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) {
1548                 /* 5GL */
1549                 pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F;
1550                 pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F;
1551                 /* 5GM */
1552                 pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F;
1553                 pwrinfo->tssi_b[1] =
1554                     (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 |
1555                     (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2;
1556                 /* 5GH */
1557                 pwrinfo->tssi_a[2] = (rom_content[EEPROM_TSSI_AB_5G + 1] &
1558                                       0xF0) >> 4 |
1559                     (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4;
1560                 pwrinfo->tssi_b[2] = (rom_content[EEPROM_TSSI_AB_5G + 2] &
1561                                       0xFC) >> 2;
1562         } else {
1563                 for (i = 0; i < 3; i++) {
1564                         pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1565                         pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1566                 }
1567         }
1568 }
1569
1570 static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw,
1571                                        bool autoload_fail, u8 *hwinfo)
1572 {
1573         struct rtl_priv *rtlpriv = rtl_priv(hw);
1574         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1575         struct txpower_info pwrinfo;
1576         u8 tempval[2], i, pwr, diff;
1577         u32 ch, rfPath, group;
1578
1579         _rtl92de_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail);
1580         if (!autoload_fail) {
1581                 /* bit0~2 */
1582                 rtlefuse->eeprom_regulatory = (hwinfo[EEPROM_RF_OPT1] & 0x7);
1583                 rtlefuse->eeprom_thermalmeter =
1584                          hwinfo[EEPROM_THERMAL_METER] & 0x1f;
1585                 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_K];
1586                 tempval[0] = hwinfo[EEPROM_IQK_DELTA] & 0x03;
1587                 tempval[1] = (hwinfo[EEPROM_LCK_DELTA] & 0x0C) >> 2;
1588                 rtlefuse->txpwr_fromeprom = true;
1589                 if (IS_92D_D_CUT(rtlpriv->rtlhal.version) ||
1590                     IS_92D_E_CUT(rtlpriv->rtlhal.version)) {
1591                         rtlefuse->internal_pa_5g[0] =
1592                                 !((hwinfo[EEPROM_TSSI_A_5G] & BIT(6)) >> 6);
1593                         rtlefuse->internal_pa_5g[1] =
1594                                 !((hwinfo[EEPROM_TSSI_B_5G] & BIT(6)) >> 6);
1595                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1596                                  "Is D cut,Internal PA0 %d Internal PA1 %d\n",
1597                                  rtlefuse->internal_pa_5g[0],
1598                                  rtlefuse->internal_pa_5g[1]);
1599                 }
1600                 rtlefuse->eeprom_c9 = hwinfo[EEPROM_RF_OPT6];
1601                 rtlefuse->eeprom_cc = hwinfo[EEPROM_RF_OPT7];
1602         } else {
1603                 rtlefuse->eeprom_regulatory = 0;
1604                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1605                 rtlefuse->crystalcap = EEPROM_DEFAULT_CRYSTALCAP;
1606                 tempval[0] = tempval[1] = 3;
1607         }
1608
1609         /* Use default value to fill parameters if
1610          * efuse is not filled on some place. */
1611
1612         /* ThermalMeter from EEPROM */
1613         if (rtlefuse->eeprom_thermalmeter < 0x06 ||
1614             rtlefuse->eeprom_thermalmeter > 0x1c)
1615                 rtlefuse->eeprom_thermalmeter = 0x12;
1616         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1617
1618         /* check XTAL_K */
1619         if (rtlefuse->crystalcap == 0xFF)
1620                 rtlefuse->crystalcap = 0;
1621         if (rtlefuse->eeprom_regulatory > 3)
1622                 rtlefuse->eeprom_regulatory = 0;
1623
1624         for (i = 0; i < 2; i++) {
1625                 switch (tempval[i]) {
1626                 case 0:
1627                         tempval[i] = 5;
1628                         break;
1629                 case 1:
1630                         tempval[i] = 4;
1631                         break;
1632                 case 2:
1633                         tempval[i] = 3;
1634                         break;
1635                 case 3:
1636                 default:
1637                         tempval[i] = 0;
1638                         break;
1639                 }
1640         }
1641
1642         rtlefuse->delta_iqk = tempval[0];
1643         if (tempval[1] > 0)
1644                 rtlefuse->delta_lck = tempval[1] - 1;
1645         if (rtlefuse->eeprom_c9 == 0xFF)
1646                 rtlefuse->eeprom_c9 = 0x00;
1647         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1648                  "EEPROMRegulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1649         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1650                  "ThermalMeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1651         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1652                  "CrystalCap = 0x%x\n", rtlefuse->crystalcap);
1653         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1654                  "Delta_IQK = 0x%x Delta_LCK = 0x%x\n",
1655                  rtlefuse->delta_iqk, rtlefuse->delta_lck);
1656
1657         for (rfPath = 0; rfPath < RF6052_MAX_PATH; rfPath++) {
1658                 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1659                         group = rtl92d_get_chnlgroup_fromarray((u8) ch);
1660                         if (ch < CHANNEL_MAX_NUMBER_2G)
1661                                 rtlefuse->txpwrlevel_cck[rfPath][ch] =
1662                                     pwrinfo.cck_index[rfPath][group];
1663                         rtlefuse->txpwrlevel_ht40_1s[rfPath][ch] =
1664                                     pwrinfo.ht40_1sindex[rfPath][group];
1665                         rtlefuse->txpwr_ht20diff[rfPath][ch] =
1666                                     pwrinfo.ht20indexdiff[rfPath][group];
1667                         rtlefuse->txpwr_legacyhtdiff[rfPath][ch] =
1668                                     pwrinfo.ofdmindexdiff[rfPath][group];
1669                         rtlefuse->pwrgroup_ht20[rfPath][ch] =
1670                                     pwrinfo.ht20maxoffset[rfPath][group];
1671                         rtlefuse->pwrgroup_ht40[rfPath][ch] =
1672                                     pwrinfo.ht40maxoffset[rfPath][group];
1673                         pwr = pwrinfo.ht40_1sindex[rfPath][group];
1674                         diff = pwrinfo.ht40_2sindexdiff[rfPath][group];
1675                         rtlefuse->txpwrlevel_ht40_2s[rfPath][ch] =
1676                                     (pwr > diff) ? (pwr - diff) : 0;
1677                 }
1678         }
1679 }
1680
1681 static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw,
1682                                                u8 *content)
1683 {
1684         struct rtl_priv *rtlpriv = rtl_priv(hw);
1685         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1686         u8 macphy_crvalue = content[EEPROM_MAC_FUNCTION];
1687
1688         if (macphy_crvalue & BIT(3)) {
1689                 rtlhal->macphymode = SINGLEMAC_SINGLEPHY;
1690                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1691                          "MacPhyMode SINGLEMAC_SINGLEPHY\n");
1692         } else {
1693                 rtlhal->macphymode = DUALMAC_DUALPHY;
1694                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1695                          "MacPhyMode DUALMAC_DUALPHY\n");
1696         }
1697 }
1698
1699 static void _rtl92de_read_macphymode_and_bandtype(struct ieee80211_hw *hw,
1700                                                   u8 *content)
1701 {
1702         _rtl92de_read_macphymode_from_prom(hw, content);
1703         rtl92d_phy_config_macphymode(hw);
1704         rtl92d_phy_config_macphymode_info(hw);
1705 }
1706
1707 static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw)
1708 {
1709         struct rtl_priv *rtlpriv = rtl_priv(hw);
1710         enum version_8192d chipver = rtlpriv->rtlhal.version;
1711         u8 cutvalue[2];
1712         u16 chipvalue;
1713
1714         rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_H,
1715                                            &cutvalue[1]);
1716         rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_L,
1717                                            &cutvalue[0]);
1718         chipvalue = (cutvalue[1] << 8) | cutvalue[0];
1719         switch (chipvalue) {
1720         case 0xAA55:
1721                 chipver |= CHIP_92D_C_CUT;
1722                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "C-CUT!!!\n");
1723                 break;
1724         case 0x9966:
1725                 chipver |= CHIP_92D_D_CUT;
1726                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n");
1727                 break;
1728         case 0xCC33:
1729                 chipver |= CHIP_92D_E_CUT;
1730                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n");
1731                 break;
1732         default:
1733                 chipver |= CHIP_92D_D_CUT;
1734                 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Unknown CUT!\n");
1735                 break;
1736         }
1737         rtlpriv->rtlhal.version = chipver;
1738 }
1739
1740 static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw)
1741 {
1742         struct rtl_priv *rtlpriv = rtl_priv(hw);
1743         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1744         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1745         u16 i, usvalue;
1746         u8 hwinfo[HWSET_MAX_SIZE];
1747         u16 eeprom_id;
1748         unsigned long flags;
1749
1750         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1751                 spin_lock_irqsave(&globalmutex_for_power_and_efuse, flags);
1752                 rtl_efuse_shadow_map_update(hw);
1753                 _rtl92de_efuse_update_chip_version(hw);
1754                 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
1755                 memcpy((void *)hwinfo, (void *)&rtlefuse->efuse_map
1756                        [EFUSE_INIT_MAP][0],
1757                        HWSET_MAX_SIZE);
1758         } else if (rtlefuse->epromtype == EEPROM_93C46) {
1759                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1760                          "RTL819X Not boot from eeprom, check it !!\n");
1761         }
1762         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
1763                       hwinfo, HWSET_MAX_SIZE);
1764
1765         eeprom_id = *((u16 *)&hwinfo[0]);
1766         if (eeprom_id != RTL8190_EEPROM_ID) {
1767                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1768                          "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1769                 rtlefuse->autoload_failflag = true;
1770         } else {
1771                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1772                 rtlefuse->autoload_failflag = false;
1773         }
1774         if (rtlefuse->autoload_failflag) {
1775                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1776                          "RTL819X Not boot from eeprom, check it !!\n");
1777                 return;
1778         }
1779         rtlefuse->eeprom_oemid = hwinfo[EEPROM_CUSTOMER_ID];
1780         _rtl92de_read_macphymode_and_bandtype(hw, hwinfo);
1781
1782         /* VID, DID  SE     0xA-D */
1783         rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1784         rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1785         rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1786         rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1787         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROMId = 0x%4x\n", eeprom_id);
1788         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1789                  "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1790         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1791                  "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1792         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1793                  "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1794         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1795                  "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1796
1797         /* Read Permanent MAC address */
1798         if (rtlhal->interfaceindex == 0) {
1799                 for (i = 0; i < 6; i += 2) {
1800                         usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC0_92D + i];
1801                         *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1802                 }
1803         } else {
1804                 for (i = 0; i < 6; i += 2) {
1805                         usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC1_92D + i];
1806                         *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1807                 }
1808         }
1809         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR,
1810                                       rtlefuse->dev_addr);
1811         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1812         _rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo);
1813
1814         /* Read Channel Plan */
1815         switch (rtlhal->bandset) {
1816         case BAND_ON_2_4G:
1817                 rtlefuse->channel_plan = COUNTRY_CODE_TELEC;
1818                 break;
1819         case BAND_ON_5G:
1820                 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1821                 break;
1822         case BAND_ON_BOTH:
1823                 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1824                 break;
1825         default:
1826                 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1827                 break;
1828         }
1829         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1830         rtlefuse->txpwr_fromeprom = true;
1831         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1832                  "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1833 }
1834
1835 void rtl92de_read_eeprom_info(struct ieee80211_hw *hw)
1836 {
1837         struct rtl_priv *rtlpriv = rtl_priv(hw);
1838         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1839         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1840         u8 tmp_u1b;
1841
1842         rtlhal->version = _rtl92de_read_chip_version(hw);
1843         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1844         rtlefuse->autoload_status = tmp_u1b;
1845         if (tmp_u1b & BIT(4)) {
1846                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1847                 rtlefuse->epromtype = EEPROM_93C46;
1848         } else {
1849                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1850                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1851         }
1852         if (tmp_u1b & BIT(5)) {
1853                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1854
1855                 rtlefuse->autoload_failflag = false;
1856                 _rtl92de_read_adapter_info(hw);
1857         } else {
1858                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1859         }
1860         return;
1861 }
1862
1863 static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw,
1864                                           struct ieee80211_sta *sta)
1865 {
1866         struct rtl_priv *rtlpriv = rtl_priv(hw);
1867         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1868         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1869         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1870         u32 ratr_value;
1871         u8 ratr_index = 0;
1872         u8 nmode = mac->ht_enable;
1873         u8 mimo_ps = IEEE80211_SMPS_OFF;
1874         u16 shortgi_rate;
1875         u32 tmp_ratr_value;
1876         u8 curtxbw_40mhz = mac->bw_40;
1877         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1878                                                         1 : 0;
1879         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1880                                                         1 : 0;
1881         enum wireless_mode wirelessmode = mac->mode;
1882
1883         if (rtlhal->current_bandtype == BAND_ON_5G)
1884                 ratr_value = sta->supp_rates[1] << 4;
1885         else
1886                 ratr_value = sta->supp_rates[0];
1887         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1888                        sta->ht_cap.mcs.rx_mask[0] << 12);
1889         switch (wirelessmode) {
1890         case WIRELESS_MODE_A:
1891                 ratr_value &= 0x00000FF0;
1892                 break;
1893         case WIRELESS_MODE_B:
1894                 if (ratr_value & 0x0000000c)
1895                         ratr_value &= 0x0000000d;
1896                 else
1897                         ratr_value &= 0x0000000f;
1898                 break;
1899         case WIRELESS_MODE_G:
1900                 ratr_value &= 0x00000FF5;
1901                 break;
1902         case WIRELESS_MODE_N_24G:
1903         case WIRELESS_MODE_N_5G:
1904                 nmode = 1;
1905                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1906                         ratr_value &= 0x0007F005;
1907                 } else {
1908                         u32 ratr_mask;
1909
1910                         if (get_rf_type(rtlphy) == RF_1T2R ||
1911                             get_rf_type(rtlphy) == RF_1T1R) {
1912                                 ratr_mask = 0x000ff005;
1913                         } else {
1914                                 ratr_mask = 0x0f0ff005;
1915                         }
1916
1917                         ratr_value &= ratr_mask;
1918                 }
1919                 break;
1920         default:
1921                 if (rtlphy->rf_type == RF_1T2R)
1922                         ratr_value &= 0x000ff0ff;
1923                 else
1924                         ratr_value &= 0x0f0ff0ff;
1925
1926                 break;
1927         }
1928         ratr_value &= 0x0FFFFFFF;
1929         if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
1930             (!curtxbw_40mhz && curshortgi_20mhz))) {
1931                 ratr_value |= 0x10000000;
1932                 tmp_ratr_value = (ratr_value >> 12);
1933                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1934                         if ((1 << shortgi_rate) & tmp_ratr_value)
1935                                 break;
1936                 }
1937                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1938                     (shortgi_rate << 4) | (shortgi_rate);
1939         }
1940         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1941         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1942                  rtl_read_dword(rtlpriv, REG_ARFR0));
1943 }
1944
1945 static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw,
1946                 struct ieee80211_sta *sta, u8 rssi_level)
1947 {
1948         struct rtl_priv *rtlpriv = rtl_priv(hw);
1949         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1950         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1951         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1952         struct rtl_sta_info *sta_entry = NULL;
1953         u32 ratr_bitmap;
1954         u8 ratr_index;
1955         u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
1956         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1957                                                         1 : 0;
1958         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1959                                                         1 : 0;
1960         enum wireless_mode wirelessmode = 0;
1961         bool shortgi = false;
1962         u32 value[2];
1963         u8 macid = 0;
1964         u8 mimo_ps = IEEE80211_SMPS_OFF;
1965
1966         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1967         mimo_ps = sta_entry->mimo_ps;
1968         wirelessmode = sta_entry->wireless_mode;
1969         if (mac->opmode == NL80211_IFTYPE_STATION)
1970                 curtxbw_40mhz = mac->bw_40;
1971         else if (mac->opmode == NL80211_IFTYPE_AP ||
1972                 mac->opmode == NL80211_IFTYPE_ADHOC)
1973                 macid = sta->aid + 1;
1974
1975         if (rtlhal->current_bandtype == BAND_ON_5G)
1976                 ratr_bitmap = sta->supp_rates[1] << 4;
1977         else
1978                 ratr_bitmap = sta->supp_rates[0];
1979         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1980                         sta->ht_cap.mcs.rx_mask[0] << 12);
1981         switch (wirelessmode) {
1982         case WIRELESS_MODE_B:
1983                 ratr_index = RATR_INX_WIRELESS_B;
1984                 if (ratr_bitmap & 0x0000000c)
1985                         ratr_bitmap &= 0x0000000d;
1986                 else
1987                         ratr_bitmap &= 0x0000000f;
1988                 break;
1989         case WIRELESS_MODE_G:
1990                 ratr_index = RATR_INX_WIRELESS_GB;
1991
1992                 if (rssi_level == 1)
1993                         ratr_bitmap &= 0x00000f00;
1994                 else if (rssi_level == 2)
1995                         ratr_bitmap &= 0x00000ff0;
1996                 else
1997                         ratr_bitmap &= 0x00000ff5;
1998                 break;
1999         case WIRELESS_MODE_A:
2000                 ratr_index = RATR_INX_WIRELESS_G;
2001                 ratr_bitmap &= 0x00000ff0;
2002                 break;
2003         case WIRELESS_MODE_N_24G:
2004         case WIRELESS_MODE_N_5G:
2005                 if (wirelessmode == WIRELESS_MODE_N_24G)
2006                         ratr_index = RATR_INX_WIRELESS_NGB;
2007                 else
2008                         ratr_index = RATR_INX_WIRELESS_NG;
2009                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2010                         if (rssi_level == 1)
2011                                 ratr_bitmap &= 0x00070000;
2012                         else if (rssi_level == 2)
2013                                 ratr_bitmap &= 0x0007f000;
2014                         else
2015                                 ratr_bitmap &= 0x0007f005;
2016                 } else {
2017                         if (rtlphy->rf_type == RF_1T2R ||
2018                             rtlphy->rf_type == RF_1T1R) {
2019                                 if (curtxbw_40mhz) {
2020                                         if (rssi_level == 1)
2021                                                 ratr_bitmap &= 0x000f0000;
2022                                         else if (rssi_level == 2)
2023                                                 ratr_bitmap &= 0x000ff000;
2024                                         else
2025                                                 ratr_bitmap &= 0x000ff015;
2026                                 } else {
2027                                         if (rssi_level == 1)
2028                                                 ratr_bitmap &= 0x000f0000;
2029                                         else if (rssi_level == 2)
2030                                                 ratr_bitmap &= 0x000ff000;
2031                                         else
2032                                                 ratr_bitmap &= 0x000ff005;
2033                                 }
2034                         } else {
2035                                 if (curtxbw_40mhz) {
2036                                         if (rssi_level == 1)
2037                                                 ratr_bitmap &= 0x0f0f0000;
2038                                         else if (rssi_level == 2)
2039                                                 ratr_bitmap &= 0x0f0ff000;
2040                                         else
2041                                                 ratr_bitmap &= 0x0f0ff015;
2042                                 } else {
2043                                         if (rssi_level == 1)
2044                                                 ratr_bitmap &= 0x0f0f0000;
2045                                         else if (rssi_level == 2)
2046                                                 ratr_bitmap &= 0x0f0ff000;
2047                                         else
2048                                                 ratr_bitmap &= 0x0f0ff005;
2049                                 }
2050                         }
2051                 }
2052                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2053                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2054
2055                         if (macid == 0)
2056                                 shortgi = true;
2057                         else if (macid == 1)
2058                                 shortgi = false;
2059                 }
2060                 break;
2061         default:
2062                 ratr_index = RATR_INX_WIRELESS_NGB;
2063
2064                 if (rtlphy->rf_type == RF_1T2R)
2065                         ratr_bitmap &= 0x000ff0ff;
2066                 else
2067                         ratr_bitmap &= 0x0f0ff0ff;
2068                 break;
2069         }
2070
2071         value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28);
2072         value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2073         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2074                  "ratr_bitmap :%x value0:%x value1:%x\n",
2075                  ratr_bitmap, value[0], value[1]);
2076         rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *) value);
2077         if (macid != 0)
2078                 sta_entry->ratr_index = ratr_index;
2079 }
2080
2081 void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw,
2082                 struct ieee80211_sta *sta, u8 rssi_level)
2083 {
2084         struct rtl_priv *rtlpriv = rtl_priv(hw);
2085
2086         if (rtlpriv->dm.useramask)
2087                 rtl92de_update_hal_rate_mask(hw, sta, rssi_level);
2088         else
2089                 rtl92de_update_hal_rate_table(hw, sta);
2090 }
2091
2092 void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw)
2093 {
2094         struct rtl_priv *rtlpriv = rtl_priv(hw);
2095         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2096         u16 sifs_timer;
2097
2098         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2099                                       &mac->slot_time);
2100         if (!mac->ht_enable)
2101                 sifs_timer = 0x0a0a;
2102         else
2103                 sifs_timer = 0x1010;
2104         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2105 }
2106
2107 bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2108 {
2109         struct rtl_priv *rtlpriv = rtl_priv(hw);
2110         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2111         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2112         enum rf_pwrstate e_rfpowerstate_toset;
2113         u8 u1tmp;
2114         bool actuallyset = false;
2115         unsigned long flag;
2116
2117         if (rtlpci->being_init_adapter)
2118                 return false;
2119         if (ppsc->swrf_processing)
2120                 return false;
2121         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2122         if (ppsc->rfchange_inprogress) {
2123                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2124                 return false;
2125         } else {
2126                 ppsc->rfchange_inprogress = true;
2127                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2128         }
2129         rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2130                           REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2131         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2132         e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2133         if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2134                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2135                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
2136                 e_rfpowerstate_toset = ERFON;
2137                 ppsc->hwradiooff = false;
2138                 actuallyset = true;
2139         } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2140                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2141                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2142                 e_rfpowerstate_toset = ERFOFF;
2143                 ppsc->hwradiooff = true;
2144                 actuallyset = true;
2145         }
2146         if (actuallyset) {
2147                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2148                 ppsc->rfchange_inprogress = false;
2149                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2150         } else {
2151                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2152                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2153                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2154                 ppsc->rfchange_inprogress = false;
2155                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2156         }
2157         *valid = 1;
2158         return !ppsc->hwradiooff;
2159 }
2160
2161 void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index,
2162                      u8 *p_macaddr, bool is_group, u8 enc_algo,
2163                      bool is_wepkey, bool clear_all)
2164 {
2165         struct rtl_priv *rtlpriv = rtl_priv(hw);
2166         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2167         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2168         u8 *macaddr = p_macaddr;
2169         u32 entry_id;
2170         bool is_pairwise = false;
2171         static u8 cam_const_addr[4][6] = {
2172                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2173                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2174                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2175                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2176         };
2177         static u8 cam_const_broad[] = {
2178                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2179         };
2180
2181         if (clear_all) {
2182                 u8 idx;
2183                 u8 cam_offset = 0;
2184                 u8 clear_number = 5;
2185                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2186                 for (idx = 0; idx < clear_number; idx++) {
2187                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2188                         rtl_cam_empty_entry(hw, cam_offset + idx);
2189
2190                         if (idx < 5) {
2191                                 memset(rtlpriv->sec.key_buf[idx], 0,
2192                                        MAX_KEY_LEN);
2193                                 rtlpriv->sec.key_len[idx] = 0;
2194                         }
2195                 }
2196         } else {
2197                 switch (enc_algo) {
2198                 case WEP40_ENCRYPTION:
2199                         enc_algo = CAM_WEP40;
2200                         break;
2201                 case WEP104_ENCRYPTION:
2202                         enc_algo = CAM_WEP104;
2203                         break;
2204                 case TKIP_ENCRYPTION:
2205                         enc_algo = CAM_TKIP;
2206                         break;
2207                 case AESCCMP_ENCRYPTION:
2208                         enc_algo = CAM_AES;
2209                         break;
2210                 default:
2211                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2212                                  "switch case not processed\n");
2213                         enc_algo = CAM_TKIP;
2214                         break;
2215                 }
2216                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2217                         macaddr = cam_const_addr[key_index];
2218                         entry_id = key_index;
2219                 } else {
2220                         if (is_group) {
2221                                 macaddr = cam_const_broad;
2222                                 entry_id = key_index;
2223                         } else {
2224                                 if (mac->opmode == NL80211_IFTYPE_AP) {
2225                                         entry_id = rtl_cam_get_free_entry(hw,
2226                                                                  p_macaddr);
2227                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2228                                                 RT_TRACE(rtlpriv, COMP_SEC,
2229                                                          DBG_EMERG,
2230                                                          "Can not find free hw security cam entry\n");
2231                                                 return;
2232                                         }
2233                                 } else {
2234                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2235                                 }
2236                                 key_index = PAIRWISE_KEYIDX;
2237                                 is_pairwise = true;
2238                         }
2239                 }
2240                 if (rtlpriv->sec.key_len[key_index] == 0) {
2241                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2242                                  "delete one entry, entry_id is %d\n",
2243                                  entry_id);
2244                         if (mac->opmode == NL80211_IFTYPE_AP)
2245                                 rtl_cam_del_entry(hw, p_macaddr);
2246                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2247                 } else {
2248                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2249                                  "The insert KEY length is %d\n",
2250                                  rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2251                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2252                                  "The insert KEY is %x %x\n",
2253                                  rtlpriv->sec.key_buf[0][0],
2254                                  rtlpriv->sec.key_buf[0][1]);
2255                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2256                                  "add one entry\n");
2257                         if (is_pairwise) {
2258                                 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2259                                               "Pairwise Key content",
2260                                               rtlpriv->sec.pairwise_key,
2261                                               rtlpriv->
2262                                               sec.key_len[PAIRWISE_KEYIDX]);
2263                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2264                                          "set Pairwise key\n");
2265                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2266                                                       entry_id, enc_algo,
2267                                                       CAM_CONFIG_NO_USEDK,
2268                                                       rtlpriv->
2269                                                       sec.key_buf[key_index]);
2270                         } else {
2271                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2272                                          "set group key\n");
2273                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2274                                         rtl_cam_add_one_entry(hw,
2275                                                 rtlefuse->dev_addr,
2276                                                 PAIRWISE_KEYIDX,
2277                                                 CAM_PAIRWISE_KEY_POSITION,
2278                                                 enc_algo, CAM_CONFIG_NO_USEDK,
2279                                                 rtlpriv->sec.key_buf[entry_id]);
2280                                 }
2281                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2282                                                 entry_id, enc_algo,
2283                                                 CAM_CONFIG_NO_USEDK,
2284                                                 rtlpriv->sec.key_buf
2285                                                 [entry_id]);
2286                         }
2287                 }
2288         }
2289 }
2290
2291 void rtl92de_suspend(struct ieee80211_hw *hw)
2292 {
2293         struct rtl_priv *rtlpriv = rtl_priv(hw);
2294
2295         rtlpriv->rtlhal.macphyctl_reg = rtl_read_byte(rtlpriv,
2296                 REG_MAC_PHY_CTRL_NORMAL);
2297 }
2298
2299 void rtl92de_resume(struct ieee80211_hw *hw)
2300 {
2301         struct rtl_priv *rtlpriv = rtl_priv(hw);
2302
2303         rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL,
2304                        rtlpriv->rtlhal.macphyctl_reg);
2305 }