drivers/net/wireless/rtlwifi/rtl8192ee/trx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2014  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../pci.h"
  28 #include "../base.h"
  29 #include "../stats.h"
  30 #include "reg.h"
  31 #include "def.h"
  32 #include "phy.h"
  33 #include "trx.h"
  34 #include "led.h"
  35 #include "dm.h"
  36 #include "fw.h"
  37
  38 static u8 _rtl92ee_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
  39 {
  40         __le16 fc = rtl_get_fc(skb);
  41
  42         if (unlikely(ieee80211_is_beacon(fc)))
  43                 return QSLT_BEACON;
  44         if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
  45                 return QSLT_MGNT;
  46
  47         return skb->priority;
  48 }
  49
  50 /* mac80211's rate_idx is like this:
  51  *
  52  * 2.4G band:rx_status->band == IEEE80211_BAND_2GHZ
  53  *
  54  * B/G rate:
  55  * (rx_status->flag & RX_FLAG_HT) = 0,
  56  * DESC92C_RATE1M-->DESC92C_RATE54M ==> idx is 0-->11,
  57  *
  58  * N rate:
  59  * (rx_status->flag & RX_FLAG_HT) = 1,
  60  * DESC92C_RATEMCS0-->DESC92C_RATEMCS15 ==> idx is 0-->15
  61  *
  62  * 5G band:rx_status->band == IEEE80211_BAND_5GHZ
  63  * A rate:
  64  * (rx_status->flag & RX_FLAG_HT) = 0,
  65  * DESC92C_RATE6M-->DESC92C_RATE54M ==> idx is 0-->7,
  66  *
  67  * N rate:
  68  * (rx_status->flag & RX_FLAG_HT) = 1,
  69  * DESC92C_RATEMCS0-->DESC92C_RATEMCS15 ==> idx is 0-->15
  70  */
  71 static int _rtl92ee_rate_mapping(struct ieee80211_hw *hw,
  72                                  bool isht, u8 desc_rate)
  73 {
  74         int rate_idx;
  75
  76         if (!isht) {
  77                 if (IEEE80211_BAND_2GHZ == hw->conf.chandef.chan->band) {
  78                         switch (desc_rate) {
  79                         case DESC92C_RATE1M:
  80                                 rate_idx = 0;
  81                                 break;
  82                         case DESC92C_RATE2M:
  83                                 rate_idx = 1;
  84                                 break;
  85                         case DESC92C_RATE5_5M:
  86                                 rate_idx = 2;
  87                                 break;
  88                         case DESC92C_RATE11M:
  89                                 rate_idx = 3;
  90                                 break;
  91                         case DESC92C_RATE6M:
  92                                 rate_idx = 4;
  93                                 break;
  94                         case DESC92C_RATE9M:
  95                                 rate_idx = 5;
  96                                 break;
  97                         case DESC92C_RATE12M:
  98                                 rate_idx = 6;
  99                                 break;
 100                         case DESC92C_RATE18M:
 101                                 rate_idx = 7;
 102                                 break;
 103                         case DESC92C_RATE24M:
 104                                 rate_idx = 8;
 105                                 break;
 106                         case DESC92C_RATE36M:
 107                                 rate_idx = 9;
 108                                 break;
 109                         case DESC92C_RATE48M:
 110                                 rate_idx = 10;
 111                                 break;
 112                         case DESC92C_RATE54M:
 113                                 rate_idx = 11;
 114                                 break;
 115                         default:
 116                                 rate_idx = 0;
 117                                 break;
 118                         }
 119                 } else {
 120                         switch (desc_rate) {
 121                         case DESC92C_RATE6M:
 122                                 rate_idx = 0;
 123                                 break;
 124                         case DESC92C_RATE9M:
 125                                 rate_idx = 1;
 126                                 break;
 127                         case DESC92C_RATE12M:
 128                                 rate_idx = 2;
 129                                 break;
 130                         case DESC92C_RATE18M:
 131                                 rate_idx = 3;
 132                                 break;
 133                         case DESC92C_RATE24M:
 134                                 rate_idx = 4;
 135                                 break;
 136                         case DESC92C_RATE36M:
 137                                 rate_idx = 5;
 138                                 break;
 139                         case DESC92C_RATE48M:
 140                                 rate_idx = 6;
 141                                 break;
 142                         case DESC92C_RATE54M:
 143                                 rate_idx = 7;
 144                                 break;
 145                         default:
 146                                 rate_idx = 0;
 147                                 break;
 148                         }
 149                 }
 150         } else {
 151                 switch (desc_rate) {
 152                 case DESC92C_RATEMCS0:
 153                         rate_idx = 0;
 154                         break;
 155                 case DESC92C_RATEMCS1:
 156                         rate_idx = 1;
 157                         break;
 158                 case DESC92C_RATEMCS2:
 159                         rate_idx = 2;
 160                         break;
 161                 case DESC92C_RATEMCS3:
 162                         rate_idx = 3;
 163                         break;
 164                 case DESC92C_RATEMCS4:
 165                         rate_idx = 4;
 166                         break;
 167                 case DESC92C_RATEMCS5:
 168                         rate_idx = 5;
 169                         break;
 170                 case DESC92C_RATEMCS6:
 171                         rate_idx = 6;
 172                         break;
 173                 case DESC92C_RATEMCS7:
 174                         rate_idx = 7;
 175                         break;
 176                 case DESC92C_RATEMCS8:
 177                         rate_idx = 8;
 178                         break;
 179                 case DESC92C_RATEMCS9:
 180                         rate_idx = 9;
 181                         break;
 182                 case DESC92C_RATEMCS10:
 183                         rate_idx = 10;
 184                         break;
 185                 case DESC92C_RATEMCS11:
 186                         rate_idx = 11;
 187                         break;
 188                 case DESC92C_RATEMCS12:
 189                         rate_idx = 12;
 190                         break;
 191                 case DESC92C_RATEMCS13:
 192                         rate_idx = 13;
 193                         break;
 194                 case DESC92C_RATEMCS14:
 195                         rate_idx = 14;
 196                         break;
 197                 case DESC92C_RATEMCS15:
 198                         rate_idx = 15;
 199                         break;
 200                 default:
 201                         rate_idx = 0;
 202                         break;
 203                 }
 204         }
 205         return rate_idx;
 206 }
 207
 208 static void _rtl92ee_query_rxphystatus(struct ieee80211_hw *hw,
 209                                        struct rtl_stats *pstatus, u8 *pdesc,
 210                                        struct rx_fwinfo *p_drvinfo,
 211                                        bool bpacket_match_bssid,
 212                                        bool bpacket_toself,
 213                                        bool packet_beacon)
 214 {
 215         struct rtl_priv *rtlpriv = rtl_priv(hw);
 216         struct phy_status_rpt *p_phystrpt = (struct phy_status_rpt *)p_drvinfo;
 217         char rx_pwr_all = 0, rx_pwr[4];
 218         u8 rf_rx_num = 0, evm, pwdb_all;
 219         u8 i, max_spatial_stream;
 220         u32 rssi, total_rssi = 0;
 221         bool is_cck = pstatus->is_cck;
 222         u8 lan_idx, vga_idx;
 223
 224         /* Record it for next packet processing */
 225         pstatus->packet_matchbssid = bpacket_match_bssid;
 226         pstatus->packet_toself = bpacket_toself;
 227         pstatus->packet_beacon = packet_beacon;
 228         pstatus->rx_mimo_signalquality[0] = -1;
 229         pstatus->rx_mimo_signalquality[1] = -1;
 230
 231         if (is_cck) {
 232                 u8 cck_highpwr;
 233                 u8 cck_agc_rpt;
 234                 /* CCK Driver info Structure is not the same as OFDM packet. */
 235                 cck_agc_rpt = p_phystrpt->cck_agc_rpt_ofdm_cfosho_a;
 236
 237                 /* (1)Hardware does not provide RSSI for CCK
 238                  * (2)PWDB, Average PWDB cacluated by
 239                  * hardware (for rate adaptive)
 240                  */
 241                 cck_highpwr = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2,
 242                                                  BIT(9));
 243
 244                 lan_idx = ((cck_agc_rpt & 0xE0) >> 5);
 245                 vga_idx = (cck_agc_rpt & 0x1f);
 246                 switch (lan_idx) {
 247                 case 7: /*VGA_idx = 27~2*/
 248                                 if (vga_idx <= 27)
 249                                         rx_pwr_all = -100 + 2 * (27 - vga_idx);
 250                                 else
 251                                         rx_pwr_all = -100;
 252                                 break;
 253                 case 6: /*VGA_idx = 2~0*/
 254                                 rx_pwr_all = -48 + 2 * (2 - vga_idx);
 255                                 break;
 256                 case 5: /*VGA_idx = 7~5*/
 257                                 rx_pwr_all = -42 + 2 * (7 - vga_idx);
 258                                 break;
 259                 case 4: /*VGA_idx = 7~4*/
 260                                 rx_pwr_all = -36 + 2 * (7 - vga_idx);
 261                                 break;
 262                 case 3: /*VGA_idx = 7~0*/
 263                                 rx_pwr_all = -24 + 2 * (7 - vga_idx);
 264                                 break;
 265                 case 2: /*VGA_idx = 5~0*/
 266                                 if (cck_highpwr)
 267                                         rx_pwr_all = -12 + 2 * (5 - vga_idx);
 268                                 else
 269                                         rx_pwr_all = -6 + 2 * (5 - vga_idx);
 270                                 break;
 271                 case 1:
 272                                 rx_pwr_all = 8 - 2 * vga_idx;
 273                                 break;
 274                 case 0:
 275                                 rx_pwr_all = 14 - 2 * vga_idx;
 276                                 break;
 277                 default:
 278                                 break;
 279                 }
 280                 rx_pwr_all += 16;
 281                 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
 282
 283                 if (!cck_highpwr) {
 284                         if (pwdb_all >= 80)
 285                                 pwdb_all = ((pwdb_all - 80) << 1) +
 286                                            ((pwdb_all - 80) >> 1) + 80;
 287                         else if ((pwdb_all <= 78) && (pwdb_all >= 20))
 288                                 pwdb_all += 3;
 289                         if (pwdb_all > 100)
 290                                 pwdb_all = 100;
 291                 }
 292
 293                 pstatus->rx_pwdb_all = pwdb_all;
 294                 pstatus->bt_rx_rssi_percentage = pwdb_all;
 295                 pstatus->recvsignalpower = rx_pwr_all;
 296
 297                 /* (3) Get Signal Quality (EVM) */
 298                 if (bpacket_match_bssid) {
 299                         u8 sq, sq_rpt;
 300
 301                         if (pstatus->rx_pwdb_all > 40) {
 302                                 sq = 100;
 303                         } else {
 304                                 sq_rpt = p_phystrpt->cck_sig_qual_ofdm_pwdb_all;
 305                                 if (sq_rpt > 64)
 306                                         sq = 0;
 307                                 else if (sq_rpt < 20)
 308                                         sq = 100;
 309                                 else
 310                                         sq = ((64 - sq_rpt) * 100) / 44;
 311                         }
 312
 313                         pstatus->signalquality = sq;
 314                         pstatus->rx_mimo_signalquality[0] = sq;
 315                         pstatus->rx_mimo_signalquality[1] = -1;
 316                 }
 317         } else {
 318                 /* (1)Get RSSI for HT rate */
 319                 for (i = RF90_PATH_A; i < RF6052_MAX_PATH; i++) {
 320                         /* we will judge RF RX path now. */
 321                         if (rtlpriv->dm.rfpath_rxenable[i])
 322                                 rf_rx_num++;
 323
 324                         rx_pwr[i] = ((p_phystrpt->path_agc[i].gain & 0x3f) * 2)
 325                                     - 110;
 326
 327                         pstatus->rx_pwr[i] = rx_pwr[i];
 328                         /* Translate DBM to percentage. */
 329                         rssi = rtl_query_rxpwrpercentage(rx_pwr[i]);
 330                         total_rssi += rssi;
 331
 332                         pstatus->rx_mimo_signalstrength[i] = (u8)rssi;
 333                 }
 334
 335                 /* (2)PWDB, Average PWDB cacluated by
 336                  * hardware (for rate adaptive)
 337                  */
 338                 rx_pwr_all = ((p_phystrpt->cck_sig_qual_ofdm_pwdb_all >> 1)
 339                               & 0x7f) - 110;
 340
 341                 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
 342                 pstatus->rx_pwdb_all = pwdb_all;
 343                 pstatus->bt_rx_rssi_percentage = pwdb_all;
 344                 pstatus->rxpower = rx_pwr_all;
 345                 pstatus->recvsignalpower = rx_pwr_all;
 346
 347                 /* (3)EVM of HT rate */
 348                 if (pstatus->rate >= DESC92C_RATEMCS8 &&
 349                     pstatus->rate <= DESC92C_RATEMCS15)
 350                         max_spatial_stream = 2;
 351                 else
 352                         max_spatial_stream = 1;
 353
 354                 for (i = 0; i < max_spatial_stream; i++) {
 355                         evm = rtl_evm_db_to_percentage(
 356                                                 p_phystrpt->stream_rxevm[i]);
 357
 358                         if (bpacket_match_bssid) {
 359                                 /* Fill value in RFD, Get the first
 360                                  * spatial stream only
 361                                  */
 362                                 if (i == 0)
 363                                         pstatus->signalquality = (u8)(evm &
 364                                                                        0xff);
 365                                 pstatus->rx_mimo_signalquality[i] = (u8)(evm &
 366                                                                           0xff);
 367                         }
 368                 }
 369
 370                 if (bpacket_match_bssid) {
 371                         for (i = RF90_PATH_A; i <= RF90_PATH_B; i++)
 372                                 rtl_priv(hw)->dm.cfo_tail[i] =
 373                                         (int)p_phystrpt->path_cfotail[i];
 374
 375                         if (rtl_priv(hw)->dm.packet_count == 0xffffffff)
 376                                 rtl_priv(hw)->dm.packet_count = 0;
 377                         else
 378                                 rtl_priv(hw)->dm.packet_count++;
 379                 }
 380         }
 381
 382         /* UI BSS List signal strength(in percentage),
 383          * make it good looking, from 0~100.
 384          */
 385         if (is_cck)
 386                 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw,
 387                                                                      pwdb_all));
 388         else if (rf_rx_num != 0)
 389                 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw,
 390                                                       total_rssi /= rf_rx_num));
 391 }
 392
 393 static void _rtl92ee_translate_rx_signal_stuff(struct ieee80211_hw *hw,
 394                                                struct sk_buff *skb,
 395                                                struct rtl_stats *pstatus,
 396                                                u8 *pdesc,
 397                                                struct rx_fwinfo *p_drvinfo)
 398 {
 399         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 400         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 401         struct ieee80211_hdr *hdr;
 402         u8 *tmp_buf;
 403         u8 *praddr;
 404         u8 *psaddr;
 405         __le16 fc;
 406         bool packet_matchbssid, packet_toself, packet_beacon;
 407
 408         tmp_buf = skb->data + pstatus->rx_drvinfo_size +
 409                   pstatus->rx_bufshift + 24;
 410
 411         hdr = (struct ieee80211_hdr *)tmp_buf;
 412         fc = hdr->frame_control;
 413         praddr = hdr->addr1;
 414         psaddr = ieee80211_get_SA(hdr);
 415         ether_addr_copy(pstatus->psaddr, psaddr);
 416
 417         packet_matchbssid = (!ieee80211_is_ctl(fc) &&
 418                                (ether_addr_equal(mac->bssid,
 419                                                 ieee80211_has_tods(fc) ?
 420                                                 hdr->addr1 :
 421                                                 ieee80211_has_fromds(fc) ?
 422                                                 hdr->addr2 : hdr->addr3)) &&
 423                                 (!pstatus->hwerror) && (!pstatus->crc) &&
 424                                 (!pstatus->icv));
 425
 426         packet_toself = packet_matchbssid &&
 427                          (ether_addr_equal(praddr, rtlefuse->dev_addr));
 428
 429         if (ieee80211_is_beacon(fc))
 430                 packet_beacon = true;
 431         else
 432                 packet_beacon = false;
 433
 434         if (packet_beacon && packet_matchbssid)
 435                 rtl_priv(hw)->dm.dbginfo.num_qry_beacon_pkt++;
 436
 437         if (packet_matchbssid && ieee80211_is_data_qos(hdr->frame_control) &&
 438             !is_multicast_ether_addr(ieee80211_get_DA(hdr))) {
 439                 struct ieee80211_qos_hdr *hdr_qos =
 440                                             (struct ieee80211_qos_hdr *)tmp_buf;
 441                 u16 tid = le16_to_cpu(hdr_qos->qos_ctrl) & 0xf;
 442
 443                 if (tid != 0 && tid != 3)
 444                         rtl_priv(hw)->dm.dbginfo.num_non_be_pkt++;
 445         }
 446
 447         _rtl92ee_query_rxphystatus(hw, pstatus, pdesc, p_drvinfo,
 448                                    packet_matchbssid, packet_toself,
 449                                    packet_beacon);
 450         rtl_process_phyinfo(hw, tmp_buf, pstatus);
 451 }
 452
 453 static void _rtl92ee_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,
 454                                       u8 *virtualaddress)
 455 {
 456         u32 dwtmp = 0;
 457
 458         memset(virtualaddress, 0, 8);
 459
 460         SET_EARLYMODE_PKTNUM(virtualaddress, ptcb_desc->empkt_num);
 461         if (ptcb_desc->empkt_num == 1) {
 462                 dwtmp = ptcb_desc->empkt_len[0];
 463         } else {
 464                 dwtmp = ptcb_desc->empkt_len[0];
 465                 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
 466                 dwtmp += ptcb_desc->empkt_len[1];
 467         }
 468         SET_EARLYMODE_LEN0(virtualaddress, dwtmp);
 469
 470         if (ptcb_desc->empkt_num <= 3) {
 471                 dwtmp = ptcb_desc->empkt_len[2];
 472         } else {
 473                 dwtmp = ptcb_desc->empkt_len[2];
 474                 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
 475                 dwtmp += ptcb_desc->empkt_len[3];
 476         }
 477         SET_EARLYMODE_LEN1(virtualaddress, dwtmp);
 478         if (ptcb_desc->empkt_num <= 5) {
 479                 dwtmp = ptcb_desc->empkt_len[4];
 480         } else {
 481                 dwtmp = ptcb_desc->empkt_len[4];
 482                 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
 483                 dwtmp += ptcb_desc->empkt_len[5];
 484         }
 485         SET_EARLYMODE_LEN2_1(virtualaddress, dwtmp & 0xF);
 486         SET_EARLYMODE_LEN2_2(virtualaddress, dwtmp >> 4);
 487         if (ptcb_desc->empkt_num <= 7) {
 488                 dwtmp = ptcb_desc->empkt_len[6];
 489         } else {
 490                 dwtmp = ptcb_desc->empkt_len[6];
 491                 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
 492                 dwtmp += ptcb_desc->empkt_len[7];
 493         }
 494         SET_EARLYMODE_LEN3(virtualaddress, dwtmp);
 495         if (ptcb_desc->empkt_num <= 9) {
 496                 dwtmp = ptcb_desc->empkt_len[8];
 497         } else {
 498                 dwtmp = ptcb_desc->empkt_len[8];
 499                 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
 500                 dwtmp += ptcb_desc->empkt_len[9];
 501         }
 502         SET_EARLYMODE_LEN4(virtualaddress, dwtmp);
 503 }
 504
 505 bool rtl92ee_rx_query_desc(struct ieee80211_hw *hw,
 506                            struct rtl_stats *status,
 507                            struct ieee80211_rx_status *rx_status,
 508                            u8 *pdesc, struct sk_buff *skb)
 509 {
 510         struct rtl_priv *rtlpriv = rtl_priv(hw);
 511         struct rx_fwinfo *p_drvinfo;
 512         struct ieee80211_hdr *hdr;
 513         u32 phystatus = GET_RX_DESC_PHYST(pdesc);
 514
 515         status->length = (u16)GET_RX_DESC_PKT_LEN(pdesc);
 516         status->rx_drvinfo_size = (u8)GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
 517                                   RX_DRV_INFO_SIZE_UNIT;
 518         status->rx_bufshift = (u8)(GET_RX_DESC_SHIFT(pdesc) & 0x03);
 519         status->icv = (u16)GET_RX_DESC_ICV(pdesc);
 520         status->crc = (u16)GET_RX_DESC_CRC32(pdesc);
 521         status->hwerror = (status->crc | status->icv);
 522         status->decrypted = !GET_RX_DESC_SWDEC(pdesc);
 523         status->rate = (u8)GET_RX_DESC_RXMCS(pdesc);
 524         status->isampdu = (bool)(GET_RX_DESC_PAGGR(pdesc) == 1);
 525                 status->timestamp_low = GET_RX_DESC_TSFL(pdesc);
 526         status->is_cck = RTL92EE_RX_HAL_IS_CCK_RATE(status->rate);
 527
 528         status->macid = GET_RX_DESC_MACID(pdesc);
 529         if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc))
 530                 status->wake_match = BIT(2);
 531         else if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc))
 532                 status->wake_match = BIT(1);
 533         else if (GET_RX_STATUS_DESC_UNICAST_MATCH(pdesc))
 534                 status->wake_match = BIT(0);
 535         else
 536                 status->wake_match = 0;
 537         if (status->wake_match)
 538                 RT_TRACE(rtlpriv, COMP_RXDESC, DBG_LOUD,
 539                          "GGGGGGGGGGGGGet Wakeup Packet!! WakeMatch=%d\n",
 540                          status->wake_match);
 541         rx_status->freq = hw->conf.chandef.chan->center_freq;
 542         rx_status->band = hw->conf.chandef.chan->band;
 543
 544         hdr = (struct ieee80211_hdr *)(skb->data + status->rx_drvinfo_size +
 545                                        status->rx_bufshift + 24);
 546
 547         if (status->crc)
 548                 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
 549
 550         if (status->rx_is40Mhzpacket)
 551                 rx_status->flag |= RX_FLAG_40MHZ;
 552
 553         if (status->is_ht)
 554                 rx_status->flag |= RX_FLAG_HT;
 555
 556         rx_status->flag |= RX_FLAG_MACTIME_START;
 557
 558         /* hw will set status->decrypted true, if it finds the
 559          * frame is open data frame or mgmt frame.
 560          * So hw will not decryption robust managment frame
 561          * for IEEE80211w but still set status->decrypted
 562          * true, so here we should set it back to undecrypted
 563          * for IEEE80211w frame, and mac80211 sw will help
 564          * to decrypt it
 565          */
 566         if (status->decrypted) {
 567                 if ((!_ieee80211_is_robust_mgmt_frame(hdr)) &&
 568                     (ieee80211_has_protected(hdr->frame_control)))
 569                         rx_status->flag |= RX_FLAG_DECRYPTED;
 570                 else
 571                         rx_status->flag &= ~RX_FLAG_DECRYPTED;
 572         }
 573
 574         /* rate_idx: index of data rate into band's
 575          * supported rates or MCS index if HT rates
 576          * are use (RX_FLAG_HT)
 577          * Notice: this is diff with windows define
 578          */
 579         rx_status->rate_idx = _rtl92ee_rate_mapping(hw,
 580                                                     status->is_ht,
 581                                                     status->rate);
 582
 583         rx_status->mactime = status->timestamp_low;
 584         if (phystatus) {
 585                 p_drvinfo = (struct rx_fwinfo *)(skb->data +
 586                                                  status->rx_bufshift + 24);
 587
 588                 _rtl92ee_translate_rx_signal_stuff(hw, skb, status, pdesc,
 589                                                    p_drvinfo);
 590         }
 591         rx_status->signal = status->recvsignalpower + 10;
 592         if (status->packet_report_type == TX_REPORT2) {
 593                 status->macid_valid_entry[0] =
 594                         GET_RX_RPT2_DESC_MACID_VALID_1(pdesc);
 595                 status->macid_valid_entry[1] =
 596                         GET_RX_RPT2_DESC_MACID_VALID_2(pdesc);
 597         }
 598         return true;
 599 }
 600
 601 /*in Windows, this == Rx_92EE_Interrupt*/
 602 void rtl92ee_rx_check_dma_ok(struct ieee80211_hw *hw, u8 *header_desc,
 603                              u8 queue_index)
 604 {
 605         u8 first_seg = 0;
 606         u8 last_seg = 0;
 607         u16 total_len = 0;
 608         u16 read_cnt = 0;
 609
 610         if (header_desc == NULL)
 611                 return;
 612
 613         total_len = (u16)GET_RX_BUFFER_DESC_TOTAL_LENGTH(header_desc);
 614
 615         first_seg = (u8)GET_RX_BUFFER_DESC_FS(header_desc);
 616
 617         last_seg = (u8)GET_RX_BUFFER_DESC_LS(header_desc);
 618
 619         while (total_len == 0 && first_seg == 0 && last_seg == 0) {
 620                 read_cnt++;
 621                 total_len = (u16)GET_RX_BUFFER_DESC_TOTAL_LENGTH(header_desc);
 622                 first_seg = (u8)GET_RX_BUFFER_DESC_FS(header_desc);
 623                 last_seg = (u8)GET_RX_BUFFER_DESC_LS(header_desc);
 624
 625                 if (read_cnt > 20)
 626                         break;
 627         }
 628 }
 629
 630 u16 rtl92ee_rx_desc_buff_remained_cnt(struct ieee80211_hw *hw, u8 queue_index)
 631 {
 632         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 633         struct rtl_priv *rtlpriv = rtl_priv(hw);
 634         u16 read_point = 0, write_point = 0, remind_cnt = 0;
 635         u32 tmp_4byte = 0;
 636         static u16 last_read_point;
 637         static bool start_rx;
 638
 639         tmp_4byte = rtl_read_dword(rtlpriv, REG_RXQ_TXBD_IDX);
 640         read_point = (u16)((tmp_4byte>>16) & 0x7ff);
 641         write_point = (u16)(tmp_4byte & 0x7ff);
 642
 643         if (write_point != rtlpci->rx_ring[queue_index].next_rx_rp) {
 644                 RT_TRACE(rtlpriv, COMP_RXDESC, DBG_DMESG,
 645                          "!!!write point is 0x%x, reg 0x3B4 value is 0x%x\n",
 646                           write_point, tmp_4byte);
 647                 tmp_4byte = rtl_read_dword(rtlpriv, REG_RXQ_TXBD_IDX);
 648                 read_point = (u16)((tmp_4byte>>16) & 0x7ff);
 649                 write_point = (u16)(tmp_4byte & 0x7ff);
 650         }
 651
 652         if (read_point > 0)
 653                 start_rx = true;
 654         if (!start_rx)
 655                 return 0;
 656
 657         if ((last_read_point > (RX_DESC_NUM_92E / 2)) &&
 658             (read_point <= (RX_DESC_NUM_92E / 2))) {
 659                 remind_cnt = RX_DESC_NUM_92E - write_point;
 660         } else {
 661                 remind_cnt = (read_point >= write_point) ?
 662                              (read_point - write_point) :
 663                              (RX_DESC_NUM_92E - write_point + read_point);
 664         }
 665
 666         if (remind_cnt == 0)
 667                 return 0;
 668
 669         rtlpci->rx_ring[queue_index].next_rx_rp = write_point;
 670
 671         last_read_point = read_point;
 672         return remind_cnt;
 673 }
 674
 675 static u16 get_desc_addr_fr_q_idx(u16 queue_index)
 676 {
 677         u16 desc_address = REG_BEQ_TXBD_IDX;
 678
 679         switch (queue_index) {
 680         case BK_QUEUE:
 681                 desc_address = REG_BKQ_TXBD_IDX;
 682                 break;
 683         case BE_QUEUE:
 684                 desc_address = REG_BEQ_TXBD_IDX;
 685                 break;
 686         case VI_QUEUE:
 687                 desc_address = REG_VIQ_TXBD_IDX;
 688                 break;
 689         case VO_QUEUE:
 690                 desc_address = REG_VOQ_TXBD_IDX;
 691                 break;
 692         case BEACON_QUEUE:
 693                 desc_address = REG_BEQ_TXBD_IDX;
 694                 break;
 695         case TXCMD_QUEUE:
 696                 desc_address = REG_BEQ_TXBD_IDX;
 697                 break;
 698         case MGNT_QUEUE:
 699                 desc_address = REG_MGQ_TXBD_IDX;
 700                 break;
 701         case HIGH_QUEUE:
 702                 desc_address = REG_HI0Q_TXBD_IDX;
 703                 break;
 704         case HCCA_QUEUE:
 705                 desc_address = REG_BEQ_TXBD_IDX;
 706                 break;
 707         default:
 708                 break;
 709         }
 710         return desc_address;
 711 }
 712
 713 void rtl92ee_get_available_desc(struct ieee80211_hw *hw, u8 q_idx)
 714 {
 715         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 716         struct rtl_priv *rtlpriv = rtl_priv(hw);
 717         u16 point_diff = 0;
 718         u16 current_tx_read_point = 0, current_tx_write_point = 0;
 719         u32 tmp_4byte;
 720
 721         tmp_4byte = rtl_read_dword(rtlpriv,
 722                                    get_desc_addr_fr_q_idx(q_idx));
 723         current_tx_read_point = (u16)((tmp_4byte >> 16) & 0x0fff);
 724         current_tx_write_point = (u16)((tmp_4byte) & 0x0fff);
 725
 726         point_diff = ((current_tx_read_point > current_tx_write_point) ?
 727                       (current_tx_read_point - current_tx_write_point) :
 728                       (TX_DESC_NUM_92E - current_tx_write_point +
 729                        current_tx_read_point));
 730
 731         rtlpci->tx_ring[q_idx].avl_desc = point_diff;
 732 }
 733
 734 void rtl92ee_pre_fill_tx_bd_desc(struct ieee80211_hw *hw,
 735                                  u8 *tx_bd_desc, u8 *desc, u8 queue_index,
 736                                  struct sk_buff *skb, dma_addr_t addr)
 737 {
 738         struct rtl_priv *rtlpriv = rtl_priv(hw);
 739         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 740         u32 pkt_len = skb->len;
 741         u16 desc_size = 40; /*tx desc size*/
 742         u32 psblen = 0;
 743         u16 tx_page_size = 0;
 744         u32 total_packet_size = 0;
 745         u16 current_bd_desc;
 746         u8 i = 0;
 747         u16 real_desc_size = 0x28;
 748         u16     append_early_mode_size = 0;
 749 #if (RTL8192EE_SEG_NUM == 0)
 750         u8 segmentnum = 2;
 751 #elif (RTL8192EE_SEG_NUM == 1)
 752         u8 segmentnum = 4;
 753 #elif (RTL8192EE_SEG_NUM == 2)
 754         u8 segmentnum = 8;
 755 #endif
 756
 757         tx_page_size = 2;
 758         current_bd_desc = rtlpci->tx_ring[queue_index].cur_tx_wp;
 759
 760         total_packet_size = desc_size+pkt_len;
 761
 762         if (rtlpriv->rtlhal.earlymode_enable)   {
 763                 if (queue_index < BEACON_QUEUE) {
 764                         append_early_mode_size = 8;
 765                         total_packet_size += append_early_mode_size;
 766                 }
 767         }
 768
 769         if (tx_page_size > 0) {
 770                 psblen = (pkt_len + real_desc_size + append_early_mode_size) /
 771                          (tx_page_size * 128);
 772
 773                 if (psblen * (tx_page_size * 128) < total_packet_size)
 774                         psblen += 1;
 775         }
 776
 777         /* Reset */
 778         SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, 0);
 779         SET_TX_BUFF_DESC_PSB(tx_bd_desc, 0);
 780         SET_TX_BUFF_DESC_OWN(tx_bd_desc, 0);
 781
 782         for (i = 1; i < segmentnum; i++) {
 783                 SET_TXBUFFER_DESC_LEN_WITH_OFFSET(tx_bd_desc, i, 0);
 784                 SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(tx_bd_desc, i, 0);
 785                 SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(tx_bd_desc, i, 0);
 786 #if (DMA_IS_64BIT == 1)
 787                 SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(tx_bd_desc, i, 0);
 788 #endif
 789         }
 790         SET_TX_BUFF_DESC_LEN_1(tx_bd_desc, 0);
 791         SET_TX_BUFF_DESC_AMSDU_1(tx_bd_desc, 0);
 792
 793         SET_TX_BUFF_DESC_LEN_2(tx_bd_desc, 0);
 794         SET_TX_BUFF_DESC_AMSDU_2(tx_bd_desc, 0);
 795         SET_TX_BUFF_DESC_LEN_3(tx_bd_desc, 0);
 796         SET_TX_BUFF_DESC_AMSDU_3(tx_bd_desc, 0);
 797         /* Clear all status */
 798         CLEAR_PCI_TX_DESC_CONTENT(desc, TX_DESC_SIZE);
 799
 800         if (rtlpriv->rtlhal.earlymode_enable) {
 801                 if (queue_index < BEACON_QUEUE) {
 802                         /* This if needs braces */
 803                         SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size + 8);
 804                 } else {
 805                         SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size);
 806                 }
 807         } else {
 808                 SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size);
 809         }
 810         SET_TX_BUFF_DESC_PSB(tx_bd_desc, psblen);
 811         SET_TX_BUFF_DESC_ADDR_LOW_0(tx_bd_desc,
 812                                     rtlpci->tx_ring[queue_index].dma +
 813                                     (current_bd_desc * TX_DESC_SIZE));
 814
 815         SET_TXBUFFER_DESC_LEN_WITH_OFFSET(tx_bd_desc, 1, pkt_len);
 816         /* don't using extendsion mode. */
 817         SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(tx_bd_desc, 1, 0);
 818         SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(tx_bd_desc, 1, addr);
 819
 820         SET_TX_DESC_PKT_SIZE(desc, (u16)(pkt_len));
 821         SET_TX_DESC_TX_BUFFER_SIZE(desc, (u16)(pkt_len));
 822 }
 823
 824 void rtl92ee_tx_fill_desc(struct ieee80211_hw *hw,
 825                           struct ieee80211_hdr *hdr, u8 *pdesc_tx,
 826                           u8 *pbd_desc_tx,
 827                           struct ieee80211_tx_info *info,
 828                           struct ieee80211_sta *sta,
 829                           struct sk_buff *skb,
 830                           u8 hw_queue, struct rtl_tcb_desc *ptcb_desc)
 831 {
 832         struct rtl_priv *rtlpriv = rtl_priv(hw);
 833         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 834         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 835         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 836         u8 *pdesc = (u8 *)pdesc_tx;
 837         u16 seq_number;
 838         __le16 fc = hdr->frame_control;
 839         unsigned int buf_len = 0;
 840         u8 fw_qsel = _rtl92ee_map_hwqueue_to_fwqueue(skb, hw_queue);
 841         bool firstseg = ((hdr->seq_ctrl &
 842                             cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
 843         bool lastseg = ((hdr->frame_control &
 844                            cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
 845         dma_addr_t mapping;
 846         u8 bw_40 = 0;
 847         u8 short_gi = 0;
 848
 849         if (mac->opmode == NL80211_IFTYPE_STATION) {
 850                 bw_40 = mac->bw_40;
 851         } else if (mac->opmode == NL80211_IFTYPE_AP ||
 852                    mac->opmode == NL80211_IFTYPE_ADHOC) {
 853                 if (sta)
 854                         bw_40 = sta->ht_cap.cap &
 855                                 IEEE80211_HT_CAP_SUP_WIDTH_20_40;
 856         }
 857         seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
 858         rtl_get_tcb_desc(hw, info, sta, skb, ptcb_desc);
 859         /* reserve 8 byte for AMPDU early mode */
 860         if (rtlhal->earlymode_enable) {
 861                 skb_push(skb, EM_HDR_LEN);
 862                 memset(skb->data, 0, EM_HDR_LEN);
 863         }
 864         buf_len = skb->len;
 865         mapping = pci_map_single(rtlpci->pdev, skb->data, skb->len,
 866                                  PCI_DMA_TODEVICE);
 867         if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
 868                 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 869                          "DMA mapping error");
 870                 return;
 871         }
 872
 873         if (pbd_desc_tx != NULL)
 874                 rtl92ee_pre_fill_tx_bd_desc(hw, pbd_desc_tx, pdesc, hw_queue,
 875                                             skb, mapping);
 876
 877         if (ieee80211_is_nullfunc(fc) || ieee80211_is_ctl(fc)) {
 878                 firstseg = true;
 879                 lastseg = true;
 880         }
 881         if (firstseg) {
 882                 if (rtlhal->earlymode_enable) {
 883                         SET_TX_DESC_PKT_OFFSET(pdesc, 1);
 884                         SET_TX_DESC_OFFSET(pdesc,
 885                                            USB_HWDESC_HEADER_LEN + EM_HDR_LEN);
 886                         if (ptcb_desc->empkt_num) {
 887                                 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 888                                          "Insert 8 byte.pTcb->EMPktNum:%d\n",
 889                                           ptcb_desc->empkt_num);
 890                                 _rtl92ee_insert_emcontent(ptcb_desc,
 891                                                           (u8 *)(skb->data));
 892                         }
 893                 } else {
 894                         SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
 895                 }
 896
 897                 SET_TX_DESC_TX_RATE(pdesc, ptcb_desc->hw_rate);
 898
 899                 if (ieee80211_is_mgmt(fc)) {
 900                         ptcb_desc->use_driver_rate = true;
 901                 } else {
 902                         if (rtlpriv->ra.is_special_data) {
 903                                 ptcb_desc->use_driver_rate = true;
 904                                 SET_TX_DESC_TX_RATE(pdesc, DESC92C_RATE11M);
 905                         } else {
 906                                 ptcb_desc->use_driver_rate = false;
 907                         }
 908                 }
 909
 910                 if (ptcb_desc->hw_rate > DESC92C_RATEMCS0)
 911                         short_gi = (ptcb_desc->use_shortgi) ? 1 : 0;
 912                 else
 913                         short_gi = (ptcb_desc->use_shortpreamble) ? 1 : 0;
 914
 915                 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
 916                         SET_TX_DESC_AGG_ENABLE(pdesc, 1);
 917                         SET_TX_DESC_MAX_AGG_NUM(pdesc, 0x14);
 918                 }
 919                 SET_TX_DESC_SEQ(pdesc, seq_number);
 920                 SET_TX_DESC_RTS_ENABLE(pdesc,
 921                                        ((ptcb_desc->rts_enable &&
 922                                          !ptcb_desc->cts_enable) ? 1 : 0));
 923                 SET_TX_DESC_HW_RTS_ENABLE(pdesc, 0);
 924                 SET_TX_DESC_CTS2SELF(pdesc,
 925                                      ((ptcb_desc->cts_enable) ? 1 : 0));
 926
 927                 SET_TX_DESC_RTS_RATE(pdesc, ptcb_desc->rts_rate);
 928                 SET_TX_DESC_RTS_SC(pdesc, ptcb_desc->rts_sc);
 929                 SET_TX_DESC_RTS_SHORT(pdesc,
 930                                 ((ptcb_desc->rts_rate <= DESC92C_RATE54M) ?
 931                                  (ptcb_desc->rts_use_shortpreamble ? 1 : 0) :
 932                                  (ptcb_desc->rts_use_shortgi ? 1 : 0)));
 933
 934                 if (ptcb_desc->tx_enable_sw_calc_duration)
 935                         SET_TX_DESC_NAV_USE_HDR(pdesc, 1);
 936
 937                 if (bw_40) {
 938                         if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40) {
 939                                 SET_TX_DESC_DATA_BW(pdesc, 1);
 940                                 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3);
 941                         } else {
 942                                 SET_TX_DESC_DATA_BW(pdesc, 0);
 943                                 SET_TX_DESC_TX_SUB_CARRIER(pdesc,
 944                                                            mac->cur_40_prime_sc);
 945                         }
 946                 } else {
 947                         SET_TX_DESC_DATA_BW(pdesc, 0);
 948                         SET_TX_DESC_TX_SUB_CARRIER(pdesc, 0);
 949                 }
 950
 951                 SET_TX_DESC_LINIP(pdesc, 0);
 952                 if (sta) {
 953                         u8 ampdu_density = sta->ht_cap.ampdu_density;
 954
 955                         SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density);
 956                 }
 957                 if (info->control.hw_key) {
 958                         struct ieee80211_key_conf *key = info->control.hw_key;
 959
 960                         switch (key->cipher) {
 961                         case WLAN_CIPHER_SUITE_WEP40:
 962                         case WLAN_CIPHER_SUITE_WEP104:
 963                         case WLAN_CIPHER_SUITE_TKIP:
 964                                 SET_TX_DESC_SEC_TYPE(pdesc, 0x1);
 965                                 break;
 966                         case WLAN_CIPHER_SUITE_CCMP:
 967                                 SET_TX_DESC_SEC_TYPE(pdesc, 0x3);
 968                                 break;
 969                         default:
 970                                 SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
 971                                 break;
 972                         }
 973                 }
 974
 975                 SET_TX_DESC_QUEUE_SEL(pdesc, fw_qsel);
 976                 SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F);
 977                 SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF);
 978                 SET_TX_DESC_DISABLE_FB(pdesc,
 979                                        ptcb_desc->disable_ratefallback ? 1 : 0);
 980                 SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0);
 981
 982                 /*SET_TX_DESC_PWR_STATUS(pdesc, pwr_status);*/
 983                 /* Set TxRate and RTSRate in TxDesc  */
 984                 /* This prevent Tx initial rate of new-coming packets */
 985                 /* from being overwritten by retried  packet rate.*/
 986                 if (!ptcb_desc->use_driver_rate) {
 987                         /*SET_TX_DESC_RTS_RATE(pdesc, 0x08); */
 988                         /* SET_TX_DESC_TX_RATE(pdesc, 0x0b); */
 989                 }
 990                 if (ieee80211_is_data_qos(fc)) {
 991                         if (mac->rdg_en) {
 992                                 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 993                                          "Enable RDG function.\n");
 994                                 SET_TX_DESC_RDG_ENABLE(pdesc, 1);
 995                                 SET_TX_DESC_HTC(pdesc, 1);
 996                         }
 997                 }
 998         }
 999
1000         SET_TX_DESC_FIRST_SEG(pdesc, (firstseg ? 1 : 0));
1001         SET_TX_DESC_LAST_SEG(pdesc, (lastseg ? 1 : 0));
1002         SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
1003         if (rtlpriv->dm.useramask) {
1004                 SET_TX_DESC_RATE_ID(pdesc, ptcb_desc->ratr_index);
1005                 SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
1006         } else {
1007                 SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcb_desc->ratr_index);
1008                 SET_TX_DESC_MACID(pdesc, ptcb_desc->ratr_index);
1009         }
1010
1011         SET_TX_DESC_MORE_FRAG(pdesc, (lastseg ? 0 : 1));
1012         if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
1013             is_broadcast_ether_addr(ieee80211_get_DA(hdr))) {
1014                 SET_TX_DESC_BMC(pdesc, 1);
1015         }
1016         RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "\n");
1017 }
1018
1019 void rtl92ee_tx_fill_cmddesc(struct ieee80211_hw *hw,
1020                              u8 *pdesc, bool firstseg,
1021                              bool lastseg, struct sk_buff *skb)
1022 {
1023         struct rtl_priv *rtlpriv = rtl_priv(hw);
1024         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1025         u8 fw_queue = QSLT_BEACON;
1026         dma_addr_t mapping = pci_map_single(rtlpci->pdev,
1027                                             skb->data, skb->len,
1028                                             PCI_DMA_TODEVICE);
1029         u8 txdesc_len = 40;
1030
1031         if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
1032                 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
1033                          "DMA mapping error");
1034                 return;
1035         }
1036         CLEAR_PCI_TX_DESC_CONTENT(pdesc, txdesc_len);
1037
1038         if (firstseg)
1039                 SET_TX_DESC_OFFSET(pdesc, txdesc_len);
1040
1041         SET_TX_DESC_TX_RATE(pdesc, DESC92C_RATE1M);
1042
1043         SET_TX_DESC_SEQ(pdesc, 0);
1044
1045         SET_TX_DESC_LINIP(pdesc, 0);
1046
1047         SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue);
1048
1049         SET_TX_DESC_FIRST_SEG(pdesc, 1);
1050         SET_TX_DESC_LAST_SEG(pdesc, 1);
1051
1052         SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)(skb->len));
1053
1054         SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
1055
1056         SET_TX_DESC_RATE_ID(pdesc, 7);
1057         SET_TX_DESC_MACID(pdesc, 0);
1058
1059         SET_TX_DESC_OWN(pdesc, 1);
1060
1061         SET_TX_DESC_PKT_SIZE((u8 *)pdesc, (u16)(skb->len));
1062
1063         SET_TX_DESC_FIRST_SEG(pdesc, 1);
1064         SET_TX_DESC_LAST_SEG(pdesc, 1);
1065
1066         SET_TX_DESC_OFFSET(pdesc, 40);
1067
1068         SET_TX_DESC_USE_RATE(pdesc, 1);
1069
1070         RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
1071                       "H2C Tx Cmd Content\n", pdesc, txdesc_len);
1072 }
1073
1074 void rtl92ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
1075                       u8 desc_name, u8 *val)
1076 {
1077         struct rtl_priv *rtlpriv = rtl_priv(hw);
1078         u16 cur_tx_rp = 0;
1079         u16 cur_tx_wp = 0;
1080         static u16 last_txw_point;
1081         static bool over_run;
1082         u32 tmp = 0;
1083         u8 q_idx = *val;
1084
1085         if (istx) {
1086                 switch (desc_name) {
1087                 case HW_DESC_TX_NEXTDESC_ADDR:
1088                         SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *)val);
1089                         break;
1090                 case HW_DESC_OWN:{
1091                         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1092                         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[q_idx];
1093                         u16 max_tx_desc = ring->entries;
1094
1095                         if (q_idx == BEACON_QUEUE) {
1096                                 ring->cur_tx_wp = 0;
1097                                 ring->cur_tx_rp = 0;
1098                                 SET_TX_BUFF_DESC_OWN(pdesc, 1);
1099                                 return;
1100                         }
1101
1102                         ring->cur_tx_wp = ((ring->cur_tx_wp + 1) % max_tx_desc);
1103
1104                         if (over_run) {
1105                                 ring->cur_tx_wp = 0;
1106                                 over_run = false;
1107                         }
1108                         if (ring->avl_desc > 1) {
1109                                 ring->avl_desc--;
1110
1111                                 rtl_write_word(rtlpriv,
1112                                                get_desc_addr_fr_q_idx(q_idx),
1113                                                ring->cur_tx_wp);
1114
1115                                 if (q_idx == 1)
1116                                         last_txw_point = cur_tx_wp;
1117                         }
1118
1119                         if (ring->avl_desc < (max_tx_desc - 15)) {
1120                                 u16 point_diff = 0;
1121
1122                                 tmp =
1123                                   rtl_read_dword(rtlpriv,
1124                                                  get_desc_addr_fr_q_idx(q_idx));
1125                                 cur_tx_rp = (u16)((tmp >> 16) & 0x0fff);
1126                                 cur_tx_wp = (u16)(tmp & 0x0fff);
1127
1128                                 ring->cur_tx_wp = cur_tx_wp;
1129                                 ring->cur_tx_rp = cur_tx_rp;
1130                                 point_diff = ((cur_tx_rp > cur_tx_wp) ?
1131                                               (cur_tx_rp - cur_tx_wp) :
1132                                               (TX_DESC_NUM_92E - 1 -
1133                                                cur_tx_wp + cur_tx_rp));
1134
1135                                 ring->avl_desc = point_diff;
1136                         }
1137                 }
1138                 break;
1139                 }
1140         } else {
1141                 switch (desc_name) {
1142                 case HW_DESC_RX_PREPARE:
1143                         SET_RX_BUFFER_DESC_LS(pdesc, 0);
1144                         SET_RX_BUFFER_DESC_FS(pdesc, 0);
1145                         SET_RX_BUFFER_DESC_TOTAL_LENGTH(pdesc, 0);
1146
1147                         SET_RX_BUFFER_DESC_DATA_LENGTH(pdesc,
1148                                                        MAX_RECEIVE_BUFFER_SIZE +
1149                                                        RX_DESC_SIZE);
1150
1151                         SET_RX_BUFFER_PHYSICAL_LOW(pdesc, *(u32 *)val);
1152                         break;
1153                 case HW_DESC_RXERO:
1154                         SET_RX_DESC_EOR(pdesc, 1);
1155                         break;
1156                 default:
1157                         RT_ASSERT(false,
1158                                   "ERR rxdesc :%d not process\n", desc_name);
1159                         break;
1160                 }
1161         }
1162 }
1163
1164 u32 rtl92ee_get_desc(u8 *pdesc, bool istx, u8 desc_name)
1165 {
1166         u32 ret = 0;
1167
1168         if (istx) {
1169                 switch (desc_name) {
1170                 case HW_DESC_OWN:
1171                         ret = GET_TX_DESC_OWN(pdesc);
1172                         break;
1173                 case HW_DESC_TXBUFF_ADDR:
1174                         ret = GET_TXBUFFER_DESC_ADDR_LOW(pdesc, 1);
1175                         break;
1176                 default:
1177                         RT_ASSERT(false,
1178                                   "ERR txdesc :%d not process\n", desc_name);
1179                         break;
1180                 }
1181         } else {
1182                 switch (desc_name) {
1183                 case HW_DESC_OWN:
1184                         ret = GET_RX_DESC_OWN(pdesc);
1185                         break;
1186                 case HW_DESC_RXPKT_LEN:
1187                         ret = GET_RX_DESC_PKT_LEN(pdesc);
1188                         break;
1189                 case HW_DESC_RXBUFF_ADDR:
1190                         ret = GET_RX_DESC_BUFF_ADDR(pdesc);
1191                         break;
1192                 default:
1193                         RT_ASSERT(false,
1194                                   "ERR rxdesc :%d not process\n", desc_name);
1195                         break;
1196                 }
1197         }
1198         return ret;
1199 }
1200
1201 bool rtl92ee_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, u16 index)
1202 {
1203         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1204         struct rtl_priv *rtlpriv = rtl_priv(hw);
1205         u16 read_point, write_point, available_desc_num;
1206         bool ret = false;
1207         static u8 stop_report_cnt;
1208         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
1209
1210         /*checking Read/Write Point each interrupt wastes CPU */
1211         if (stop_report_cnt > 15 || !rtlpriv->link_info.busytraffic) {
1212                 u16 point_diff = 0;
1213                 u16 cur_tx_rp, cur_tx_wp;
1214                 u32 tmpu32 = 0;
1215
1216                 tmpu32 =
1217                   rtl_read_dword(rtlpriv,
1218                                  get_desc_addr_fr_q_idx(hw_queue));
1219                 cur_tx_rp = (u16)((tmpu32 >> 16) & 0x0fff);
1220                 cur_tx_wp = (u16)(tmpu32 & 0x0fff);
1221
1222                 ring->cur_tx_wp = cur_tx_wp;
1223                 ring->cur_tx_rp = cur_tx_rp;
1224                 point_diff = ((cur_tx_rp > cur_tx_wp) ?
1225                               (cur_tx_rp - cur_tx_wp) :
1226                               (TX_DESC_NUM_92E - cur_tx_wp + cur_tx_rp));
1227
1228                 ring->avl_desc = point_diff;
1229         }
1230
1231         read_point = ring->cur_tx_rp;
1232         write_point = ring->cur_tx_wp;
1233         available_desc_num = ring->avl_desc;
1234
1235         if (write_point > read_point) {
1236                 if (index < write_point && index >= read_point)
1237                         ret = false;
1238                 else
1239                         ret = true;
1240         } else if (write_point < read_point) {
1241                 if (index > write_point && index < read_point)
1242                         ret = true;
1243                 else
1244                         ret = false;
1245         } else {
1246                 if (index != read_point)
1247                         ret = true;
1248         }
1249
1250         if (hw_queue == BEACON_QUEUE)
1251                 ret = true;
1252
1253         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1254             rtlpriv->psc.rfoff_reason > RF_CHANGE_BY_PS)
1255                 ret = true;
1256
1257         if (hw_queue < BEACON_QUEUE) {
1258                 if (!ret)
1259                         stop_report_cnt++;
1260                 else
1261                         stop_report_cnt = 0;
1262         }
1263
1264         return ret;
1265 }
1266
1267 void rtl92ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
1268 {
1269 }
1270
1271 u32 rtl92ee_rx_command_packet(struct ieee80211_hw *hw,
1272                               struct rtl_stats status,
1273                               struct sk_buff *skb)
1274 {
1275         u32 result = 0;
1276         struct rtl_priv *rtlpriv = rtl_priv(hw);
1277
1278         switch (status.packet_report_type) {
1279         case NORMAL_RX:
1280                 result = 0;
1281                 break;
1282         case C2H_PACKET:
1283                 rtl92ee_c2h_packet_handler(hw, skb->data, (u8)skb->len);
1284                 result = 1;
1285                 break;
1286         default:
1287                 RT_TRACE(rtlpriv, COMP_RECV, DBG_TRACE,
1288                          "Unknown packet type %d\n", status.packet_report_type);
1289                 break;
1290         }
1291
1292         return result;
1293 }