drivers/net/wireless/rtlwifi/rtl8821ae/def.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #ifndef __RTL8821AE_DEF_H__
  27 #define __RTL8821AE_DEF_H__
  28
  29 /*--------------------------Define -------------------------------------------*/
  30 #define USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN       1
  31
  32 /* BIT 7 HT Rate*/
  33 /*TxHT = 0*/
  34 #define MGN_1M                          0x02
  35 #define MGN_2M                          0x04
  36 #define MGN_5_5M                        0x0b
  37 #define MGN_11M                         0x16
  38
  39 #define MGN_6M                          0x0c
  40 #define MGN_9M                          0x12
  41 #define MGN_12M                         0x18
  42 #define MGN_18M                         0x24
  43 #define MGN_24M                         0x30
  44 #define MGN_36M                         0x48
  45 #define MGN_48M                         0x60
  46 #define MGN_54M                         0x6c
  47
  48 /* TxHT = 1 */
  49 #define MGN_MCS0                        0x80
  50 #define MGN_MCS1                        0x81
  51 #define MGN_MCS2                        0x82
  52 #define MGN_MCS3                        0x83
  53 #define MGN_MCS4                        0x84
  54 #define MGN_MCS5                        0x85
  55 #define MGN_MCS6                        0x86
  56 #define MGN_MCS7                        0x87
  57 #define MGN_MCS8                        0x88
  58 #define MGN_MCS9                        0x89
  59 #define MGN_MCS10                       0x8a
  60 #define MGN_MCS11                       0x8b
  61 #define MGN_MCS12                       0x8c
  62 #define MGN_MCS13                       0x8d
  63 #define MGN_MCS14                       0x8e
  64 #define MGN_MCS15                       0x8f
  65 /* VHT rate */
  66 #define MGN_VHT1SS_MCS0         0x90
  67 #define MGN_VHT1SS_MCS1         0x91
  68 #define MGN_VHT1SS_MCS2         0x92
  69 #define MGN_VHT1SS_MCS3         0x93
  70 #define MGN_VHT1SS_MCS4         0x94
  71 #define MGN_VHT1SS_MCS5         0x95
  72 #define MGN_VHT1SS_MCS6         0x96
  73 #define MGN_VHT1SS_MCS7         0x97
  74 #define MGN_VHT1SS_MCS8         0x98
  75 #define MGN_VHT1SS_MCS9         0x99
  76 #define MGN_VHT2SS_MCS0         0x9a
  77 #define MGN_VHT2SS_MCS1         0x9b
  78 #define MGN_VHT2SS_MCS2         0x9c
  79 #define MGN_VHT2SS_MCS3         0x9d
  80 #define MGN_VHT2SS_MCS4         0x9e
  81 #define MGN_VHT2SS_MCS5         0x9f
  82 #define MGN_VHT2SS_MCS6         0xa0
  83 #define MGN_VHT2SS_MCS7         0xa1
  84 #define MGN_VHT2SS_MCS8         0xa2
  85 #define MGN_VHT2SS_MCS9         0xa3
  86
  87 #define MGN_VHT3SS_MCS0         0xa4
  88 #define MGN_VHT3SS_MCS1         0xa5
  89 #define MGN_VHT3SS_MCS2         0xa6
  90 #define MGN_VHT3SS_MCS3         0xa7
  91 #define MGN_VHT3SS_MCS4         0xa8
  92 #define MGN_VHT3SS_MCS5         0xa9
  93 #define MGN_VHT3SS_MCS6         0xaa
  94 #define MGN_VHT3SS_MCS7         0xab
  95 #define MGN_VHT3SS_MCS8         0xac
  96 #define MGN_VHT3SS_MCS9         0xad
  97
  98 #define MGN_MCS0_SG                     0xc0
  99 #define MGN_MCS1_SG                     0xc1
 100 #define MGN_MCS2_SG                     0xc2
 101 #define MGN_MCS3_SG                     0xc3
 102 #define MGN_MCS4_SG                     0xc4
 103 #define MGN_MCS5_SG                     0xc5
 104 #define MGN_MCS6_SG                     0xc6
 105 #define MGN_MCS7_SG                     0xc7
 106 #define MGN_MCS8_SG                     0xc8
 107 #define MGN_MCS9_SG                     0xc9
 108 #define MGN_MCS10_SG            0xca
 109 #define MGN_MCS11_SG            0xcb
 110 #define MGN_MCS12_SG            0xcc
 111 #define MGN_MCS13_SG            0xcd
 112 #define MGN_MCS14_SG            0xce
 113 #define MGN_MCS15_SG            0xcf
 114
 115 #define MGN_UNKNOWN                     0xff
 116
 117 /* 30 ms */
 118 #define WIFI_NAV_UPPER_US                               30000
 119 #define HAL_92C_NAV_UPPER_UNIT                  128
 120
 121 #define HAL_RETRY_LIMIT_INFRA                           48
 122 #define HAL_RETRY_LIMIT_AP_ADHOC                        7
 123
 124 #define RESET_DELAY_8185                                        20
 125
 126 #define RT_IBSS_INT_MASKS       (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
 127 #define RT_AC_INT_MASKS         (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
 128
 129 #define NUM_OF_FIRMWARE_QUEUE                           10
 130 #define NUM_OF_PAGES_IN_FW                                      0x100
 131 #define NUM_OF_PAGE_IN_FW_QUEUE_BK                      0x07
 132 #define NUM_OF_PAGE_IN_FW_QUEUE_BE                      0x07
 133 #define NUM_OF_PAGE_IN_FW_QUEUE_VI                      0x07
 134 #define NUM_OF_PAGE_IN_FW_QUEUE_VO                      0x07
 135 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA            0x0
 136 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD                     0x0
 137 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT            0x02
 138 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH            0x02
 139 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN                     0x2
 140 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB                     0xA1
 141
 142 #define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM          0x026
 143 #define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM          0x048
 144 #define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM          0x048
 145 #define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM          0x026
 146 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM         0x00
 147
 148 #define MAX_RX_DMA_BUFFER_SIZE                          0x3E80
 149
 150 #define MAX_LINES_HWCONFIG_TXT                          1000
 151 #define MAX_BYTES_LINE_HWCONFIG_TXT                     256
 152
 153 #define SW_THREE_WIRE                                           0
 154 #define HW_THREE_WIRE                                           2
 155
 156 #define BT_DEMO_BOARD                                           0
 157 #define BT_QA_BOARD                                                     1
 158 #define BT_FPGA                                                         2
 159
 160 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE         0
 161 #define HAL_PRIME_CHNL_OFFSET_LOWER                     1
 162 #define HAL_PRIME_CHNL_OFFSET_UPPER                     2
 163
 164 #define MAX_H2C_QUEUE_NUM                                       10
 165
 166 #define RX_MPDU_QUEUE                                           0
 167 #define RX_CMD_QUEUE                                            1
 168 #define RX_MAX_QUEUE                                            2
 169 #define AC2QUEUEID(_AC)                                         (_AC)
 170
 171 #define MAX_RX_DMA_BUFFER_SIZE_8812     0x3E80
 172
 173 #define C2H_RX_CMD_HDR_LEN                                      8
 174 #define GET_C2H_CMD_CMD_LEN(__prxhdr)           \
 175         LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
 176 #define GET_C2H_CMD_ELEMENT_ID(__prxhdr)        \
 177         LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
 178 #define GET_C2H_CMD_CMD_SEQ(__prxhdr)           \
 179         LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
 180 #define GET_C2H_CMD_CONTINUE(__prxhdr)          \
 181         LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
 182 #define GET_C2H_CMD_CONTENT(__prxhdr)           \
 183         ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
 184
 185 #define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr)    \
 186         LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
 187 #define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr)               \
 188         LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
 189 #define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr)   \
 190         LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
 191 #define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr)    \
 192         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
 193 #define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr)             \
 194         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
 195 #define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
 196         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
 197 #define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr)               \
 198         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
 199 #define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr)              \
 200         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
 201 #define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr)               \
 202         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
 203
 204 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
 205
 206 #define CHIP_8812                               BIT(2)
 207 #define CHIP_8821                               (BIT(0)|BIT(2))
 208
 209 #define CHIP_8821A                              (BIT(0)|BIT(2))
 210 #define NORMAL_CHIP                             BIT(3)
 211 #define RF_TYPE_1T1R                            (~(BIT(4)|BIT(5)|BIT(6)))
 212 #define RF_TYPE_1T2R                            BIT(4)
 213 #define RF_TYPE_2T2R                            BIT(5)
 214 #define CHIP_VENDOR_UMC                         BIT(7)
 215 #define B_CUT_VERSION                           BIT(12)
 216 #define C_CUT_VERSION                           BIT(13)
 217 #define D_CUT_VERSION                           ((BIT(12)|BIT(13)))
 218 #define E_CUT_VERSION                           BIT(14)
 219 #define RF_RL_ID                        (BIT(31)|BIT(30)|BIT(29)|BIT(28))
 220
 221 enum version_8821ae {
 222         VERSION_TEST_CHIP_1T1R_8812 = 0x0004,
 223         VERSION_TEST_CHIP_2T2R_8812 = 0x0024,
 224         VERSION_NORMAL_TSMC_CHIP_1T1R_8812 = 0x100c,
 225         VERSION_NORMAL_TSMC_CHIP_2T2R_8812 = 0x102c,
 226         VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT = 0x200c,
 227         VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT = 0x202c,
 228         VERSION_TEST_CHIP_8821 = 0x0005,
 229         VERSION_NORMAL_TSMC_CHIP_8821 = 0x000d,
 230         VERSION_NORMAL_TSMC_CHIP_8821_B_CUT = 0x100d,
 231         VERSION_UNKNOWN = 0xFF,
 232 };
 233
 234 enum vht_data_sc {
 235         VHT_DATA_SC_DONOT_CARE = 0,
 236         VHT_DATA_SC_20_UPPER_OF_80MHZ = 1,
 237         VHT_DATA_SC_20_LOWER_OF_80MHZ = 2,
 238         VHT_DATA_SC_20_UPPERST_OF_80MHZ = 3,
 239         VHT_DATA_SC_20_LOWEST_OF_80MHZ = 4,
 240         VHT_DATA_SC_20_RECV1 = 5,
 241         VHT_DATA_SC_20_RECV2 = 6,
 242         VHT_DATA_SC_20_RECV3 = 7,
 243         VHT_DATA_SC_20_RECV4 = 8,
 244         VHT_DATA_SC_40_UPPER_OF_80MHZ = 9,
 245         VHT_DATA_SC_40_LOWER_OF_80MHZ = 10,
 246 };
 247
 248 /* MASK */
 249 #define IC_TYPE_MASK                    (BIT(0)|BIT(1)|BIT(2))
 250 #define CHIP_TYPE_MASK                  BIT(3)
 251 #define RF_TYPE_MASK                    (BIT(4)|BIT(5)|BIT(6))
 252 #define MANUFACTUER_MASK                BIT(7)
 253 #define ROM_VERSION_MASK                (BIT(11)|BIT(10)|BIT(9)|BIT(8))
 254 #define CUT_VERSION_MASK                (BIT(15)|BIT(14)|BIT(13)|BIT(12))
 255
 256 /* Get element */
 257 #define GET_CVID_IC_TYPE(version)       ((version) & IC_TYPE_MASK)
 258 #define GET_CVID_CHIP_TYPE(version)     ((version) & CHIP_TYPE_MASK)
 259 #define GET_CVID_RF_TYPE(version)       ((version) & RF_TYPE_MASK)
 260 #define GET_CVID_MANUFACTUER(version)   ((version) & MANUFACTUER_MASK)
 261 #define GET_CVID_ROM_VERSION(version)   ((version) & ROM_VERSION_MASK)
 262 #define GET_CVID_CUT_VERSION(version)   ((version) & CUT_VERSION_MASK)
 263
 264 #define IS_1T1R(version)        ((GET_CVID_RF_TYPE(version)) ? false : true)
 265 #define IS_1T2R(version)        ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)\
 266                                                         ? true : false)
 267 #define IS_2T2R(version)        ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)\
 268                                                         ? true : false)
 269
 270 #define IS_8812_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8812) ? \
 271                                                                 true : false)
 272 #define IS_8821_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821) ? \
 273                                                                 true : false)
 274
 275 #define IS_VENDOR_8812A_TEST_CHIP(version)      ((IS_8812_SERIES(version)) ? \
 276                                         ((IS_NORMAL_CHIP(version)) ? \
 277                                                 false : true) : false)
 278 #define IS_VENDOR_8812A_MP_CHIP(version)        ((IS_8812_SERIES(version)) ? \
 279                                         ((IS_NORMAL_CHIP(version)) ? \
 280                                                 true : false) : false)
 281 #define IS_VENDOR_8812A_C_CUT(version)          ((IS_8812_SERIES(version)) ? \
 282                                         ((GET_CVID_CUT_VERSION(version) == \
 283                                         C_CUT_VERSION) ? \
 284                                         true : false) : false)
 285
 286 #define IS_VENDOR_8821A_TEST_CHIP(version)      ((IS_8821_SERIES(version)) ? \
 287                                         ((IS_NORMAL_CHIP(version)) ? \
 288                                         false : true) : false)
 289 #define IS_VENDOR_8821A_MP_CHIP(version)        ((IS_8821_SERIES(version)) ? \
 290                                         ((IS_NORMAL_CHIP(version)) ? \
 291                                                 true : false) : false)
 292 #define IS_VENDOR_8821A_B_CUT(version)          ((IS_8821_SERIES(version)) ? \
 293                                         ((GET_CVID_CUT_VERSION(version) == \
 294                                         B_CUT_VERSION) ? \
 295                                         true : false) : false)
 296 enum board_type {
 297         ODM_BOARD_DEFAULT = 0,    /* The DEFAULT case. */
 298         ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1 = mini card. */
 299         ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */
 300         ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */
 301         ODM_BOARD_EXT_PA = BIT(3), /* 1 = existing 2G ext-PA */
 302         ODM_BOARD_EXT_LNA = BIT(4), /* 1 = existing 2G ext-LNA */
 303         ODM_BOARD_EXT_TRSW = BIT(5), /* 1 = existing ext-TRSW */
 304         ODM_BOARD_EXT_PA_5G = BIT(6), /* 1 = existing 5G ext-PA */
 305         ODM_BOARD_EXT_LNA_5G = BIT(7), /* 1 = existing 5G ext-LNA */
 306 };
 307
 308 enum rf_optype {
 309         RF_OP_BY_SW_3WIRE = 0,
 310         RF_OP_BY_FW,
 311         RF_OP_MAX
 312 };
 313
 314 enum rf_power_state {
 315         RF_ON,
 316         RF_OFF,
 317         RF_SLEEP,
 318         RF_SHUT_DOWN,
 319 };
 320
 321 enum power_save_mode {
 322         POWER_SAVE_MODE_ACTIVE,
 323         POWER_SAVE_MODE_SAVE,
 324 };
 325
 326 enum power_polocy_config {
 327         POWERCFG_MAX_POWER_SAVINGS,
 328         POWERCFG_GLOBAL_POWER_SAVINGS,
 329         POWERCFG_LOCAL_POWER_SAVINGS,
 330         POWERCFG_LENOVO,
 331 };
 332
 333 enum interface_select_pci {
 334         INTF_SEL1_MINICARD = 0,
 335         INTF_SEL0_PCIE = 1,
 336         INTF_SEL2_RSV = 2,
 337         INTF_SEL3_RSV = 3,
 338 };
 339
 340 enum hal_fw_c2h_cmd_id {
 341         HAL_FW_C2H_CMD_READ_MACREG = 0,
 342         HAL_FW_C2H_CMD_READ_BBREG = 1,
 343         HAL_FW_C2H_CMD_READ_RFREG = 2,
 344         HAL_FW_C2H_CMD_READ_EEPROM = 3,
 345         HAL_FW_C2H_CMD_READ_EFUSE = 4,
 346         HAL_FW_C2H_CMD_READ_CAM = 5,
 347         HAL_FW_C2H_CMD_GET_BASICRATE = 6,
 348         HAL_FW_C2H_CMD_GET_DATARATE = 7,
 349         HAL_FW_C2H_CMD_SURVEY = 8,
 350         HAL_FW_C2H_CMD_SURVEYDONE = 9,
 351         HAL_FW_C2H_CMD_JOINBSS = 10,
 352         HAL_FW_C2H_CMD_ADDSTA = 11,
 353         HAL_FW_C2H_CMD_DELSTA = 12,
 354         HAL_FW_C2H_CMD_ATIMDONE = 13,
 355         HAL_FW_C2H_CMD_TX_REPORT = 14,
 356         HAL_FW_C2H_CMD_CCX_REPORT = 15,
 357         HAL_FW_C2H_CMD_DTM_REPORT = 16,
 358         HAL_FW_C2H_CMD_TX_RATE_STATISTICS = 17,
 359         HAL_FW_C2H_CMD_C2HLBK = 18,
 360         HAL_FW_C2H_CMD_C2HDBG = 19,
 361         HAL_FW_C2H_CMD_C2HFEEDBACK = 20,
 362         HAL_FW_C2H_CMD_MAX
 363 };
 364
 365 enum rtl_desc_qsel {
 366         QSLT_BK = 0x2,
 367         QSLT_BE = 0x0,
 368         QSLT_VI = 0x5,
 369         QSLT_VO = 0x7,
 370         QSLT_BEACON = 0x10,
 371         QSLT_HIGH = 0x11,
 372         QSLT_MGNT = 0x12,
 373         QSLT_CMD = 0x13,
 374 };
 375
 376 enum rtl_desc8821ae_rate {
 377         DESC_RATE1M = 0x00,
 378         DESC_RATE2M = 0x01,
 379         DESC_RATE5_5M = 0x02,
 380         DESC_RATE11M = 0x03,
 381
 382         DESC_RATE6M = 0x04,
 383         DESC_RATE9M = 0x05,
 384         DESC_RATE12M = 0x06,
 385         DESC_RATE18M = 0x07,
 386         DESC_RATE24M = 0x08,
 387         DESC_RATE36M = 0x09,
 388         DESC_RATE48M = 0x0a,
 389         DESC_RATE54M = 0x0b,
 390
 391         DESC_RATEMCS0 = 0x0c,
 392         DESC_RATEMCS1 = 0x0d,
 393         DESC_RATEMCS2 = 0x0e,
 394         DESC_RATEMCS3 = 0x0f,
 395         DESC_RATEMCS4 = 0x10,
 396         DESC_RATEMCS5 = 0x11,
 397         DESC_RATEMCS6 = 0x12,
 398         DESC_RATEMCS7 = 0x13,
 399         DESC_RATEMCS8 = 0x14,
 400         DESC_RATEMCS9 = 0x15,
 401         DESC_RATEMCS10 = 0x16,
 402         DESC_RATEMCS11 = 0x17,
 403         DESC_RATEMCS12 = 0x18,
 404         DESC_RATEMCS13 = 0x19,
 405         DESC_RATEMCS14 = 0x1a,
 406         DESC_RATEMCS15 = 0x1b,
 407
 408         DESC_RATEVHT1SS_MCS0 = 0x2c,
 409         DESC_RATEVHT1SS_MCS1 = 0x2d,
 410         DESC_RATEVHT1SS_MCS2 = 0x2e,
 411         DESC_RATEVHT1SS_MCS3 = 0x2f,
 412         DESC_RATEVHT1SS_MCS4 = 0x30,
 413         DESC_RATEVHT1SS_MCS5 = 0x31,
 414         DESC_RATEVHT1SS_MCS6 = 0x32,
 415         DESC_RATEVHT1SS_MCS7 = 0x33,
 416         DESC_RATEVHT1SS_MCS8 = 0x34,
 417         DESC_RATEVHT1SS_MCS9 = 0x35,
 418         DESC_RATEVHT2SS_MCS0 = 0x36,
 419         DESC_RATEVHT2SS_MCS1 = 0x37,
 420         DESC_RATEVHT2SS_MCS2 = 0x38,
 421         DESC_RATEVHT2SS_MCS3 = 0x39,
 422         DESC_RATEVHT2SS_MCS4 = 0x3a,
 423         DESC_RATEVHT2SS_MCS5 = 0x3b,
 424         DESC_RATEVHT2SS_MCS6 = 0x3c,
 425         DESC_RATEVHT2SS_MCS7 = 0x3d,
 426         DESC_RATEVHT2SS_MCS8 = 0x3e,
 427         DESC_RATEVHT2SS_MCS9 = 0x3f,
 428 };
 429
 430 enum rx_packet_type {
 431         NORMAL_RX,
 432         TX_REPORT1,
 433         TX_REPORT2,
 434         HIS_REPORT,
 435         C2H_PACKET,
 436 };
 437
 438 struct phy_sts_cck_8821ae_t {
 439         u8 adc_pwdb_X[4];
 440         u8 sq_rpt;
 441         u8 cck_agc_rpt;
 442 };
 443
 444 struct h2c_cmd_8821ae {
 445         u8 element_id;
 446         u32 cmd_len;
 447         u8 *p_cmdbuffer;
 448 };
 449
 450 #endif