1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
26 #ifndef __RTL_WIFI_H__
27 #define __RTL_WIFI_H__
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sched.h>
32 #include <linux/firmware.h>
33 #include <linux/etherdevice.h>
34 #include <linux/vmalloc.h>
35 #include <linux/usb.h>
36 #include <net/mac80211.h>
37 #include <linux/completion.h>
40 #define MASKBYTE0 0xff
41 #define MASKBYTE1 0xff00
42 #define MASKBYTE2 0xff0000
43 #define MASKBYTE3 0xff000000
44 #define MASKHWORD 0xffff0000
45 #define MASKLWORD 0x0000ffff
46 #define MASKDWORD 0xffffffff
47 #define MASK12BITS 0xfff
48 #define MASKH4BITS 0xf0000000
49 #define MASKOFDM_D 0xffc00000
50 #define MASKCCK 0x3f3f3f3f
52 #define MASK4BITS 0x0f
53 #define MASK20BITS 0xfffff
54 #define RFREG_OFFSET_MASK 0xfffff
56 #define MASKBYTE0 0xff
57 #define MASKBYTE1 0xff00
58 #define MASKBYTE2 0xff0000
59 #define MASKBYTE3 0xff000000
60 #define MASKHWORD 0xffff0000
61 #define MASKLWORD 0x0000ffff
62 #define MASKDWORD 0xffffffff
63 #define MASK12BITS 0xfff
64 #define MASKH4BITS 0xf0000000
65 #define MASKOFDM_D 0xffc00000
66 #define MASKCCK 0x3f3f3f3f
68 #define MASK4BITS 0x0f
69 #define MASK20BITS 0xfffff
70 #define RFREG_OFFSET_MASK 0xfffff
72 #define RF_CHANGE_BY_INIT 0
73 #define RF_CHANGE_BY_IPS BIT(28)
74 #define RF_CHANGE_BY_PS BIT(29)
75 #define RF_CHANGE_BY_HW BIT(30)
76 #define RF_CHANGE_BY_SW BIT(31)
78 #define IQK_ADDA_REG_NUM 16
79 #define IQK_MAC_REG_NUM 4
80 #define IQK_THRESHOLD 8
82 #define MAX_KEY_LEN 61
83 #define KEY_BUF_SIZE 5
86 /*aci: 0x00 Best Effort*/
87 /*aci: 0x01 Background*/
90 /*Max: define total number.*/
96 #define QOS_QUEUE_NUM 4
97 #define RTL_MAC80211_NUM_QUEUE 5
98 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
99 #define RTL_USB_MAX_RX_COUNT 100
100 #define QBSS_LOAD_SIZE 5
101 #define MAX_WMMELE_LENGTH 64
103 #define TOTAL_CAM_ENTRY 32
105 /*slot time for 11g. */
106 #define RTL_SLOT_TIME_9 9
107 #define RTL_SLOT_TIME_20 20
109 /*related to tcp/ip. */
111 #define PROTOC_TYPE_SIZE 2
113 /*related with 802.11 frame*/
114 #define MAC80211_3ADDR_LEN 24
115 #define MAC80211_4ADDR_LEN 30
117 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
118 #define CHANNEL_MAX_NUMBER_2G 14
119 #define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to
120 *"phy_GetChnlGroup8812A" and
121 * "Hal_ReadTxPowerInfo8812A"
123 #define CHANNEL_MAX_NUMBER_5G_80M 7
124 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
125 #define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to
126 *"phy_GetChnlGroup8812A" and
127 * "Hal_ReadTxPowerInfo8812A"
129 #define CHANNEL_MAX_NUMBER_5G_80M 7
130 #define MAX_PG_GROUP 13
131 #define CHANNEL_GROUP_MAX_2G 3
132 #define CHANNEL_GROUP_IDX_5GL 3
133 #define CHANNEL_GROUP_IDX_5GM 6
134 #define CHANNEL_GROUP_IDX_5GH 9
135 #define CHANNEL_GROUP_MAX_5G 9
136 #define CHANNEL_MAX_NUMBER_2G 14
137 #define AVG_THERMAL_NUM 8
138 #define AVG_THERMAL_NUM_88E 4
139 #define AVG_THERMAL_NUM_8723BE 4
140 #define MAX_TID_COUNT 9
146 enum rtl8192c_h2c_cmd {
153 H2C_MACID_PS_MODE = 7,
154 H2C_P2P_PS_OFFLOAD = 8,
155 H2C_MAC_MODE_SEL = 9,
157 H2C_P2P_PS_CTW_CMD = 24,
161 #define MAX_TX_COUNT 4
162 #define MAX_REGULATION_NUM 4
163 #define MAX_RF_PATH_NUM 4
164 #define MAX_RATE_SECTION_NUM 6
165 #define MAX_2_4G_BANDWITH_NUM 4
166 #define MAX_5G_BANDWITH_NUM 4
167 #define MAX_RF_PATH 4
168 #define MAX_CHNL_GROUP_24G 6
169 #define MAX_CHNL_GROUP_5G 14
171 #define TX_PWR_BY_RATE_NUM_BAND 2
172 #define TX_PWR_BY_RATE_NUM_RF 4
173 #define TX_PWR_BY_RATE_NUM_SECTION 12
174 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6
175 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5
177 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
179 #define DEL_SW_IDX_SZ 30
182 /* For now, it's just for 8192ee
183 * but not OK yet, keep it 0
185 #define DMA_IS_64BIT 0
186 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
192 RF_TX_NUM_NONIMPLEMENT,
195 #define PACKET_NORMAL 0
196 #define PACKET_DHCP 1
198 #define PACKET_EAPOL 3
200 #define MAX_SUPPORT_WOL_PATTERN_NUM 16
201 #define RSVD_WOL_PATTERN_NUM 1
202 #define WKFMCAM_ADDR_NUM 6
203 #define WKFMCAM_SIZE 24
205 #define MAX_WOL_BIT_MASK_SIZE 16
206 /* MIN LEN keeps 13 here */
207 #define MIN_WOL_PATTERN_SIZE 13
208 #define MAX_WOL_PATTERN_SIZE 128
210 #define WAKE_ON_MAGIC_PACKET BIT(0)
211 #define WAKE_ON_PATTERN_MATCH BIT(1)
213 #define WOL_REASON_PTK_UPDATE BIT(0)
214 #define WOL_REASON_GTK_UPDATE BIT(1)
215 #define WOL_REASON_DISASSOC BIT(2)
216 #define WOL_REASON_DEAUTH BIT(3)
217 #define WOL_REASON_AP_LOST BIT(4)
218 #define WOL_REASON_MAGIC_PKT BIT(5)
219 #define WOL_REASON_UNICAST_PKT BIT(6)
220 #define WOL_REASON_PATTERN_PKT BIT(7)
221 #define WOL_REASON_RTD3_SSID_MATCH BIT(8)
222 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9)
223 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10)
225 struct txpower_info_2g {
226 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
227 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
228 /*If only one tx, only BW20 and OFDM are used.*/
229 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
230 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
231 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
232 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
233 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
234 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
237 struct txpower_info_5g {
238 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
239 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
240 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
241 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
242 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
243 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
244 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
268 enum regulation_txpwr_lmt {
274 TXPWR_LMT_MAX_REGULATION_NUM = 4
277 enum rt_eeprom_type {
284 RTL_STATUS_INTERFACE_START = 0,
288 HARDWARE_TYPE_RTL8192E,
289 HARDWARE_TYPE_RTL8192U,
290 HARDWARE_TYPE_RTL8192SE,
291 HARDWARE_TYPE_RTL8192SU,
292 HARDWARE_TYPE_RTL8192CE,
293 HARDWARE_TYPE_RTL8192CU,
294 HARDWARE_TYPE_RTL8192DE,
295 HARDWARE_TYPE_RTL8192DU,
296 HARDWARE_TYPE_RTL8723AE,
297 HARDWARE_TYPE_RTL8723U,
298 HARDWARE_TYPE_RTL8188EE,
299 HARDWARE_TYPE_RTL8723BE,
300 HARDWARE_TYPE_RTL8192EE,
301 HARDWARE_TYPE_RTL8821AE,
302 HARDWARE_TYPE_RTL8812AE,
308 #define IS_HARDWARE_TYPE_8192SU(rtlhal) \
309 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
310 #define IS_HARDWARE_TYPE_8192SE(rtlhal) \
311 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
312 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \
313 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
314 #define IS_HARDWARE_TYPE_8192CU(rtlhal) \
315 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
316 #define IS_HARDWARE_TYPE_8192DE(rtlhal) \
317 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
318 #define IS_HARDWARE_TYPE_8192DU(rtlhal) \
319 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
320 #define IS_HARDWARE_TYPE_8723E(rtlhal) \
321 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
322 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
323 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
324 #define IS_HARDWARE_TYPE_8192S(rtlhal) \
325 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
326 #define IS_HARDWARE_TYPE_8192C(rtlhal) \
327 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
328 #define IS_HARDWARE_TYPE_8192D(rtlhal) \
329 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
330 #define IS_HARDWARE_TYPE_8723(rtlhal) \
331 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
333 #define RX_HAL_IS_CCK_RATE(rxmcs) \
334 ((rxmcs) == DESC_RATE1M || \
335 (rxmcs) == DESC_RATE2M || \
336 (rxmcs) == DESC_RATE5_5M || \
337 (rxmcs) == DESC_RATE11M)
339 enum scan_operation_backup_opt {
341 SCAN_OPT_BACKUP_BAND0 = 0,
342 SCAN_OPT_BACKUP_BAND1,
371 u32 rf_rb; /* rflssi_readback */
372 u32 rf_rbpi; /* rflssi_readbackpi */
376 IO_CMD_PAUSE_DM_BY_SCAN = 0,
377 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
378 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
379 IO_CMD_RESUME_DM_BY_SCAN = 2,
384 HW_VAR_MULTICAST_REG,
388 HW_VAR_SECURITY_CONF,
389 HW_VAR_BEACON_INTERVAL,
391 HW_VAR_LISTEN_INTERVAL,
405 HW_VAR_RATE_FALLBACK_CONTROL,
406 HW_VAR_CONTENTION_WINDOW,
411 HW_VAR_AMPDU_MIN_SPACE,
412 HW_VAR_SHORTGI_DENSITY,
414 HW_VAR_MCS_RATE_AVAILABLE,
417 HW_VAR_DIS_Req_Qsize,
418 HW_VAR_CCX_CHNL_LOAD,
419 HW_VAR_CCX_NOISE_HISTOGRAM,
426 HW_VAR_SET_DEV_POWER,
436 HW_VAR_USER_CONTROL_TURBO_MODE,
442 HW_VAR_AUTOLOAD_STATUS,
443 HW_VAR_RF_2R_DISABLE,
445 HW_VAR_H2C_FW_PWRMODE,
446 HW_VAR_H2C_FW_JOINBSSRPT,
447 HW_VAR_H2C_FW_MEDIASTATUSRPT,
448 HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
449 HW_VAR_FW_PSMODE_STATUS,
450 HW_VAR_INIT_RTS_RATE,
451 HW_VAR_RESUME_CLK_ON,
452 HW_VAR_FW_LPS_ACTION,
453 HW_VAR_1X1_RECV_COMBINE,
454 HW_VAR_STOP_SEND_BEACON,
459 HW_VAR_H2C_FW_UPDATE_GTK,
462 HW_VAR_WF_IS_MAC_ADDR,
463 HW_VAR_H2C_FW_OFFLOAD,
466 HW_VAR_HANDLE_FW_C2H,
467 HW_VAR_DL_FW_RSVD_PAGE,
469 HW_VAR_HW_SEQ_ENABLE,
474 HW_VAR_SWITCH_EPHY_WoWLAN,
475 HW_VAR_INT_MIGRATION,
489 enum rt_media_status {
490 RT_MEDIA_DISCONNECT = 0,
496 RT_CID_8187_ALPHA0 = 1,
497 RT_CID_8187_SERCOMM_PS = 2,
498 RT_CID_8187_HW_LED = 3,
499 RT_CID_8187_NETGEAR = 4,
501 RT_CID_819X_CAMEO = 6,
502 RT_CID_819X_RUNTOP = 7,
503 RT_CID_819X_SENAO = 8,
505 RT_CID_819X_NETCORE = 10,
506 RT_CID_NETTRONIX = 11,
510 RT_CID_819X_ALPHA = 15,
511 RT_CID_819X_SITECOM = 16,
513 RT_CID_819X_LENOVO = 18,
514 RT_CID_819X_QMI = 19,
515 RT_CID_819X_EDIMAX_BELKIN = 20,
516 RT_CID_819X_SERCOMM_BELKIN = 21,
517 RT_CID_819X_CAMEO1 = 22,
518 RT_CID_819X_MSI = 23,
519 RT_CID_819X_ACER = 24,
521 RT_CID_819X_CLEVO = 28,
522 RT_CID_819X_ARCADYAN_BELKIN = 29,
523 RT_CID_819X_SAMSUNG = 30,
524 RT_CID_819X_WNC_COREGA = 31,
525 RT_CID_819X_FOXCOON = 32,
526 RT_CID_819X_DELL = 33,
527 RT_CID_819X_PRONETS = 34,
528 RT_CID_819X_EDIMAX_ASUS = 35,
537 HW_DESC_TX_NEXTDESC_ADDR,
546 PRIME_CHNL_OFFSET_DONT_CARE = 0,
547 PRIME_CHNL_OFFSET_LOWER = 1,
548 PRIME_CHNL_OFFSET_UPPER = 2,
558 enum ht_channel_width {
559 HT_CHANNEL_WIDTH_20 = 0,
560 HT_CHANNEL_WIDTH_20_40 = 1,
561 HT_CHANNEL_WIDTH_80 = 2,
564 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
565 Cipher Suites Encryption Algorithms */
568 WEP40_ENCRYPTION = 1,
570 RSERVED_ENCRYPTION = 3,
571 AESCCMP_ENCRYPTION = 4,
572 WEP104_ENCRYPTION = 5,
573 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
578 _HAL_STATE_START = 1,
581 enum rtl_desc92_rate {
584 DESC_RATE5_5M = 0x02,
596 DESC_RATEMCS0 = 0x0c,
597 DESC_RATEMCS1 = 0x0d,
598 DESC_RATEMCS2 = 0x0e,
599 DESC_RATEMCS3 = 0x0f,
600 DESC_RATEMCS4 = 0x10,
601 DESC_RATEMCS5 = 0x11,
602 DESC_RATEMCS6 = 0x12,
603 DESC_RATEMCS7 = 0x13,
604 DESC_RATEMCS8 = 0x14,
605 DESC_RATEMCS9 = 0x15,
606 DESC_RATEMCS10 = 0x16,
607 DESC_RATEMCS11 = 0x17,
608 DESC_RATEMCS12 = 0x18,
609 DESC_RATEMCS13 = 0x19,
610 DESC_RATEMCS14 = 0x1a,
611 DESC_RATEMCS15 = 0x1b,
612 DESC_RATEMCS15_SG = 0x1c,
613 DESC_RATEMCS32 = 0x20,
615 DESC_RATEVHT1SS_MCS0 = 0x2c,
616 DESC_RATEVHT1SS_MCS1 = 0x2d,
617 DESC_RATEVHT1SS_MCS2 = 0x2e,
618 DESC_RATEVHT1SS_MCS3 = 0x2f,
619 DESC_RATEVHT1SS_MCS4 = 0x30,
620 DESC_RATEVHT1SS_MCS5 = 0x31,
621 DESC_RATEVHT1SS_MCS6 = 0x32,
622 DESC_RATEVHT1SS_MCS7 = 0x33,
623 DESC_RATEVHT1SS_MCS8 = 0x34,
624 DESC_RATEVHT1SS_MCS9 = 0x35,
625 DESC_RATEVHT2SS_MCS0 = 0x36,
626 DESC_RATEVHT2SS_MCS1 = 0x37,
627 DESC_RATEVHT2SS_MCS2 = 0x38,
628 DESC_RATEVHT2SS_MCS3 = 0x39,
629 DESC_RATEVHT2SS_MCS4 = 0x3a,
630 DESC_RATEVHT2SS_MCS5 = 0x3b,
631 DESC_RATEVHT2SS_MCS6 = 0x3c,
632 DESC_RATEVHT2SS_MCS7 = 0x3d,
633 DESC_RATEVHT2SS_MCS8 = 0x3e,
634 DESC_RATEVHT2SS_MCS9 = 0x3f,
660 EFUSE_HWSET_MAX_SIZE,
661 EFUSE_MAX_SECTION_MAP,
662 EFUSE_REAL_CONTENT_SIZE,
663 EFUSE_OOB_PROTECT_BYTES_LEN,
679 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
680 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
681 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
682 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
683 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
684 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
685 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
686 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
687 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
688 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
689 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
690 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
691 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
692 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
693 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
694 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
695 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
696 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
697 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
698 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
699 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
700 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
701 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
702 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
703 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
704 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
705 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
706 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
707 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
708 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
709 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
710 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
711 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
712 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/
713 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
715 RTL_IMR_C2HCMD, /*fw interrupt*/
717 /*CCK Rates, TxHT = 0 */
723 /*OFDM Rates, TxHT = 0 */
736 RTL_RC_VHT_RATE_1SS_MCS7,
737 RTL_RC_VHT_RATE_1SS_MCS8,
738 RTL_RC_VHT_RATE_1SS_MCS9,
739 RTL_RC_VHT_RATE_2SS_MCS7,
740 RTL_RC_VHT_RATE_2SS_MCS8,
741 RTL_RC_VHT_RATE_2SS_MCS9,
747 /*Firmware PS mode for control LPS.*/
749 FW_PS_ACTIVE_MODE = 0,
754 FW_PS_UAPSD_WMM_MODE = 5,
755 FW_PS_UAPSD_MODE = 6,
757 FW_PS_WWLAN_MODE = 8,
758 FW_PS_PM_Radio_Off = 9,
759 FW_PS_PM_Card_Disable = 10,
763 EACTIVE, /*Active/Continuous access. */
764 EMAXPS, /*Max power save mode. */
765 EFASTPS, /*Fast power save mode. */
766 EAUTOPS, /*Auto power save mode. */
771 LED_CTL_POWER_ON = 1,
776 LED_CTL_SITE_SURVEY = 6,
777 LED_CTL_POWER_OFF = 7,
778 LED_CTL_START_TO_LINK = 8,
779 LED_CTL_START_WPS = 9,
780 LED_CTL_STOP_WPS = 10,
791 /*acm implementation method.*/
793 eAcmWay0_SwAndHw = 0,
799 SINGLEMAC_SINGLEPHY = 0,
812 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
826 WIRELESS_MODE_UNKNOWN = 0x00,
827 WIRELESS_MODE_A = 0x01,
828 WIRELESS_MODE_B = 0x02,
829 WIRELESS_MODE_G = 0x04,
830 WIRELESS_MODE_AUTO = 0x08,
831 WIRELESS_MODE_N_24G = 0x10,
832 WIRELESS_MODE_N_5G = 0x20,
833 WIRELESS_MODE_AC_5G = 0x40,
834 WIRELESS_MODE_AC_24G = 0x80,
835 WIRELESS_MODE_AC_ONLY = 0x100,
836 WIRELESS_MODE_MAX = 0x800
839 #define IS_WIRELESS_MODE_A(wirelessmode) \
840 (wirelessmode == WIRELESS_MODE_A)
841 #define IS_WIRELESS_MODE_B(wirelessmode) \
842 (wirelessmode == WIRELESS_MODE_B)
843 #define IS_WIRELESS_MODE_G(wirelessmode) \
844 (wirelessmode == WIRELESS_MODE_G)
845 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
846 (wirelessmode == WIRELESS_MODE_N_24G)
847 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
848 (wirelessmode == WIRELESS_MODE_N_5G)
850 enum ratr_table_mode {
851 RATR_INX_WIRELESS_NGB = 0,
852 RATR_INX_WIRELESS_NG = 1,
853 RATR_INX_WIRELESS_NB = 2,
854 RATR_INX_WIRELESS_N = 3,
855 RATR_INX_WIRELESS_GB = 4,
856 RATR_INX_WIRELESS_G = 5,
857 RATR_INX_WIRELESS_B = 6,
858 RATR_INX_WIRELESS_MC = 7,
859 RATR_INX_WIRELESS_A = 8,
860 RATR_INX_WIRELESS_AC_5N = 8,
861 RATR_INX_WIRELESS_AC_24N = 9,
864 enum rtl_link_state {
866 MAC80211_LINKING = 1,
868 MAC80211_LINKED_SCANNING = 3,
885 enum rt_polarity_ctl {
886 RT_POLARITY_LOW_ACT = 0,
887 RT_POLARITY_HIGH_ACT = 1,
890 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */
891 enum fw_wow_reason_v2 {
892 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01,
893 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02,
894 FW_WOW_V2_DISASSOC_EVENT = 0x04,
895 FW_WOW_V2_DEAUTH_EVENT = 0x08,
896 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10,
897 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21,
898 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22,
899 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23,
900 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24,
901 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30,
902 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31,
903 FW_WOW_V2_REASON_MAX = 0xff,
906 enum wolpattern_type {
908 MULTICAST_PATTERN = 1,
909 BROADCAST_PATTERN = 2,
914 struct octet_string {
919 struct rtl_hdr_3addr {
929 struct rtl_info_element {
935 struct rtl_probe_rsp {
936 struct rtl_hdr_3addr header;
938 __le16 beacon_interval;
940 /*SSID, supported rates, FH params, DS params,
941 CF params, IBSS params, TIM (if beacon), RSN */
942 struct rtl_info_element info_element[0];
946 /*ledpin Identify how to implement this SW led.*/
949 enum rtl_led_pin ledpin;
955 struct rtl_led sw_led0;
956 struct rtl_led sw_led1;
959 struct rtl_qos_parameters {
967 struct rt_smooth_data {
968 u32 elements[100]; /*array to store values */
969 u32 index; /*index to current array to store */
970 u32 total_num; /*num of valid elements */
971 u32 total_val; /*sum of valid elements */
974 struct false_alarm_statistics {
976 u32 cnt_rate_illegal;
979 u32 cnt_fast_fsync_fail;
980 u32 cnt_sb_search_fail;
1000 struct wireless_stats {
1001 unsigned long txbytesunicast;
1002 unsigned long txbytesmulticast;
1003 unsigned long txbytesbroadcast;
1004 unsigned long rxbytesunicast;
1007 /*Correct smoothed ss in Dbm, only used
1008 in driver to report real power now. */
1009 long recv_signal_power;
1010 long signal_quality;
1011 long last_sigstrength_inpercent;
1013 u32 rssi_calculate_cnt;
1016 /*Transformed, in dbm. Beautified signal
1017 strength for UI, not correct. */
1018 long signal_strength;
1020 u8 rx_rssi_percentage[4];
1022 u8 rx_evm_percentage[2];
1024 u16 rx_cfo_short[4];
1027 struct rt_smooth_data ui_rssi;
1028 struct rt_smooth_data ui_link_quality;
1031 struct rate_adaptive {
1032 u8 rate_adaptive_disabled;
1036 u32 high_rssi_thresh_for_ra;
1037 u32 high2low_rssi_thresh_for_ra;
1038 u8 low2high_rssi_thresh_for_ra40m;
1039 u32 low_rssi_thresh_for_ra40m;
1040 u8 low2high_rssi_thresh_for_ra20m;
1041 u32 low_rssi_thresh_for_ra20m;
1042 u32 upper_rssi_threshold_ratr;
1043 u32 middleupper_rssi_threshold_ratr;
1044 u32 middle_rssi_threshold_ratr;
1045 u32 middlelow_rssi_threshold_ratr;
1046 u32 low_rssi_threshold_ratr;
1047 u32 ultralow_rssi_threshold_ratr;
1048 u32 low_rssi_threshold_ratr_40m;
1049 u32 low_rssi_threshold_ratr_20m;
1050 u8 ping_rssi_enable;
1052 u32 ping_rssi_thresh_for_ra;
1057 bool lower_rts_rate;
1058 bool is_special_data;
1061 struct regd_pair_mapping {
1067 struct dynamic_primary_cca {
1077 struct rtl_regulatory {
1080 u16 max_power_level;
1084 int16_t power_limit;
1085 struct regd_pair_mapping *regpair;
1089 bool rfkill_state; /*0 is off, 1 is on */
1093 #define P2P_MAX_NOA_NUM 2
1096 P2P_ROLE_DISABLE = 0,
1097 P2P_ROLE_DEVICE = 1,
1098 P2P_ROLE_CLIENT = 2,
1106 P2P_PS_SCAN_DONE = 3,
1107 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
1112 P2P_PS_CTWINDOW = 1,
1114 P2P_PS_MIX = 3, /* CTWindow and NoA */
1117 struct rtl_p2p_ps_info {
1118 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
1119 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
1120 u8 noa_index; /* Identifies instance of Notice of Absence timing. */
1121 /* Client traffic window. A period of time in TU after TBTT. */
1123 u8 opp_ps; /* opportunistic power save. */
1124 u8 noa_num; /* number of NoA descriptor in P2P IE. */
1125 /* Count for owner, Type of client. */
1126 u8 noa_count_type[P2P_MAX_NOA_NUM];
1127 /* Max duration for owner, preferred or min acceptable duration
1130 u32 noa_duration[P2P_MAX_NOA_NUM];
1131 /* Length of interval for owner, preferred or max acceptable intervali
1134 u32 noa_interval[P2P_MAX_NOA_NUM];
1135 /* schedule in terms of the lower 4 bytes of the TSF timer. */
1136 u32 noa_start_time[P2P_MAX_NOA_NUM];
1139 struct p2p_ps_offload_t {
1141 u8 role:1; /* 1: Owner, 0: Client */
1150 #define IQK_MATRIX_REG_NUM 8
1151 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
1153 struct iqk_matrix_regs {
1155 long value[1][IQK_MATRIX_REG_NUM];
1158 struct phy_parameters {
1163 enum hw_param_tab_index {
1178 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
1179 struct init_gain initgain_backup;
1180 enum io_type current_io_type;
1185 u8 set_bwmode_inprogress;
1186 u8 sw_chnl_inprogress;
1191 u8 set_io_inprogress;
1194 /* record for power tracking */
1206 u32 reg_c04, reg_c08, reg_874;
1207 u32 adda_backup[16];
1208 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1209 u32 iqk_bb_backup[10];
1210 bool iqk_initialized;
1212 bool rfpath_rx_enable[MAX_RF_PATH];
1216 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1219 bool iqk_in_progress;
1223 /* this is for 88E & 8723A */
1224 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1225 /* MAX_PG_GROUP groups of pwr diff by rates */
1226 u32 mcs_offset[MAX_PG_GROUP][16];
1227 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1228 [TX_PWR_BY_RATE_NUM_RF]
1229 [TX_PWR_BY_RATE_NUM_RF]
1230 [TX_PWR_BY_RATE_NUM_SECTION];
1231 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1232 [TX_PWR_BY_RATE_NUM_RF]
1233 [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
1234 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1235 [TX_PWR_BY_RATE_NUM_RF]
1236 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
1237 u8 default_initialgain[4];
1239 /* the current Tx power level */
1240 u8 cur_cck_txpwridx;
1241 u8 cur_ofdm24g_txpwridx;
1242 u8 cur_bw20_txpwridx;
1243 u8 cur_bw40_txpwridx;
1245 char txpwr_limit_2_4g[MAX_REGULATION_NUM]
1246 [MAX_2_4G_BANDWITH_NUM]
1247 [MAX_RATE_SECTION_NUM]
1248 [CHANNEL_MAX_NUMBER_2G]
1250 char txpwr_limit_5g[MAX_REGULATION_NUM]
1251 [MAX_5G_BANDWITH_NUM]
1252 [MAX_RATE_SECTION_NUM]
1253 [CHANNEL_MAX_NUMBER_5G]
1256 u32 rfreg_chnlval[2];
1258 u32 reg_rf3c[2]; /* pathA / pathB */
1260 u32 backup_rf_0x1a;/*92ee*/
1265 u8 num_total_rfpath;
1266 struct phy_parameters hwparam_tables[MAX_TAB];
1269 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1270 enum rt_polarity_ctl polarity_ctl;
1273 #define MAX_TID_COUNT 9
1274 #define RTL_AGG_STOP 0
1275 #define RTL_AGG_PROGRESS 1
1276 #define RTL_AGG_START 2
1277 #define RTL_AGG_OPERATIONAL 3
1278 #define RTL_AGG_OFF 0
1279 #define RTL_AGG_ON 1
1280 #define RTL_RX_AGG_START 1
1281 #define RTL_RX_AGG_STOP 0
1282 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
1283 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
1300 struct rtl_tid_data {
1302 struct rtl_ht_agg agg;
1305 struct rtl_sta_info {
1306 struct list_head list;
1310 u8 mac_addr[ETH_ALEN];
1311 struct rtl_tid_data tids[MAX_TID_COUNT];
1313 /* just used for ap adhoc or mesh*/
1314 struct rssi_sta rssi_stat;
1320 struct mutex bb_mutex;
1323 unsigned long pci_mem_end; /*shared mem end */
1324 unsigned long pci_mem_start; /*shared mem start */
1327 unsigned long pci_base_addr; /*device I/O address */
1329 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
1330 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
1331 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
1332 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
1335 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
1336 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
1337 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
1342 u8 mac_addr[ETH_ALEN];
1343 u8 mac80211_registered;
1349 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1350 struct ieee80211_hw *hw;
1351 struct ieee80211_vif *vif;
1352 enum nl80211_iftype opmode;
1354 /*Probe Beacon management */
1355 struct rtl_tid_data tids[MAX_TID_COUNT];
1356 enum rtl_link_state link_state;
1362 u8 p2p; /*using p2p role*/
1372 u8 cnt_after_linked;
1376 /* skb wait queue */
1377 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1394 u8 bssid[ETH_ALEN] __aligned(2);
1396 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1397 u32 basic_rates; /* b/g rates */
1402 u16 mode; /* wireless mode */
1407 u8 cur_40_prime_sc_bk;
1416 int beacon_interval;
1419 u8 min_space_cfg; /*For Min spacing configurations */
1421 u8 current_ampdu_factor;
1422 u8 current_ampdu_density;
1425 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1426 struct rtl_qos_parameters ac[AC_MAX];
1431 u32 last_bt_edca_ul;
1432 u32 last_bt_edca_dl;
1438 bool adc_back_off_on;
1440 bool low_penalty_rate_adaptive;
1441 bool rf_rx_lpf_shrink;
1442 bool reject_aggre_pkt;
1450 u8 fw_dac_swing_lvl;
1457 bool sw_dac_swing_on;
1458 u32 sw_dac_swing_lvl;
1463 bool ignore_wlan_act;
1466 struct bt_coexist_8723 {
1467 u32 high_priority_tx;
1468 u32 high_priority_rx;
1469 u32 low_priority_tx;
1470 u32 low_priority_rx;
1472 bool c2h_bt_info_req_sent;
1473 bool c2h_bt_inquiry_page;
1474 u32 bt_inq_page_start_time;
1476 u8 c2h_bt_info_original;
1477 u8 bt_inquiry_page_cnt;
1478 struct btdm_8723 btdm;
1482 struct ieee80211_hw *hw;
1483 bool driver_is_goingto_unload;
1486 bool being_init_adapter;
1488 bool mac_func_enable;
1489 bool pre_edcca_enable;
1490 struct bt_coexist_8723 hal_coex_8723;
1492 enum intf_type interface;
1493 u16 hw_type; /*92c or 92d or 92s and so on */
1496 u32 version; /*version of chip */
1497 u8 state; /*stop 0, start 1 */
1517 bool h2c_setinprogress;
1520 /*Reserve page start offset except beacon in TxQ. */
1521 u8 fw_rsvdpage_startoffset;
1525 /* FW Cmd IO related */
1528 bool set_fwcmd_inprogress;
1529 u8 current_fwcmd_io;
1531 struct p2p_ps_offload_t p2p_ps_offload;
1532 bool fw_clk_change_in_progress;
1533 bool allow_sw_to_change_hwclc;
1536 bool driver_going2unload;
1538 /*AMPDU init min space*/
1539 u8 minspace_cfg; /*For Min spacing configurations */
1542 enum macphy_mode macphymode;
1543 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1544 enum band_type current_bandtypebackup;
1545 enum band_type bandset;
1546 /* dual MAC 0--Mac0 1--Mac1 */
1548 /* just for DualMac S3S4 */
1550 bool earlymode_enable;
1551 u8 max_earlymode_num;
1553 bool during_mac0init_radiob;
1554 bool during_mac1init_radioa;
1555 bool reloadtxpowerindex;
1556 /* True if IMR or IQK have done
1557 for 2.4G in scan progress */
1558 bool load_imrandiqk_setting_for2g;
1560 bool disable_amsdu_8k;
1561 bool master_of_dmsp;
1564 u16 rx_tag;/*for 92ee*/
1569 bool enter_pnp_sleep;
1570 bool wake_from_pnp_sleep;
1572 __kernel_time_t last_suspend_sec;
1574 u8 *wowlan_firmware;
1576 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1578 bool real_wow_v2_enable;
1579 bool re_init_llt_table;
1582 struct rtl_security {
1587 bool use_defaultkey;
1588 /*Encryption Algorithm for Unicast Packet */
1589 enum rt_enc_alg pairwise_enc_algorithm;
1590 /*Encryption Algorithm for Brocast/Multicast */
1591 enum rt_enc_alg group_enc_algorithm;
1592 /*Cam Entry Bitmap */
1593 u32 hwsec_cam_bitmap;
1594 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1595 /*local Key buffer, indx 0 is for
1596 pairwise key 1-4 is for agoup key. */
1597 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1598 u8 key_len[KEY_BUF_SIZE];
1600 /*The pointer of Pairwise Key,
1601 it always points to KeyBuf[4] */
1605 #define ASSOCIATE_ENTRY_NUM 33
1607 struct fast_ant_training {
1609 u8 antsel_rx_keep_0;
1610 u8 antsel_rx_keep_1;
1611 u8 antsel_rx_keep_2;
1617 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1618 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1619 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1620 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1621 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1622 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1623 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1628 struct dm_phy_dbg_info {
1630 u64 num_qry_phy_status;
1631 u64 num_qry_phy_status_cck;
1632 u64 num_qry_phy_status_ofdm;
1633 u16 num_qry_beacon_pkt;
1639 /*PHY status for Dynamic Management */
1640 long entry_min_undec_sm_pwdb;
1642 long undec_sm_pwdb; /*out dm */
1643 long entry_max_undec_sm_pwdb;
1645 bool dm_initialgain_enable;
1646 bool dynamic_txpower_enable;
1647 bool current_turbo_edca;
1648 bool is_any_nonbepkts; /*out dm */
1649 bool is_cur_rdlstate;
1650 bool txpower_trackinginit;
1651 bool disable_framebursting;
1653 bool txpower_tracking;
1655 bool rfpath_rxenable[4];
1656 bool inform_fw_driverctrldm;
1657 bool current_mrc_switch;
1659 u8 powerindex_backup[6];
1661 u8 thermalvalue_rxgain;
1662 u8 thermalvalue_iqk;
1663 u8 thermalvalue_lck;
1666 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1667 u8 thermalvalue_avg_index;
1669 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1670 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1674 u8 txpower_track_control;
1675 bool interrupt_migration;
1676 bool disable_tx_int;
1677 char ofdm_index[MAX_RF_PATH];
1678 u8 default_ofdm_index;
1679 u8 default_cck_index;
1681 char delta_power_index[MAX_RF_PATH];
1682 char delta_power_index_last[MAX_RF_PATH];
1683 char power_index_offset[MAX_RF_PATH];
1684 char absolute_ofdm_swing_idx[MAX_RF_PATH];
1685 char remnant_ofdm_swing_idx[MAX_RF_PATH];
1686 char remnant_cck_idx;
1687 bool modify_txagc_flag_path_a;
1688 bool modify_txagc_flag_path_b;
1690 bool one_entry_only;
1691 struct dm_phy_dbg_info dbginfo;
1693 /* Dynamic ATC switch */
1702 u32 packet_count_pre;
1705 /*88e tx power tracking*/
1706 u8 swing_idx_ofdm[MAX_RF_PATH];
1707 u8 swing_idx_ofdm_cur;
1708 u8 swing_idx_ofdm_base[MAX_RF_PATH];
1709 bool swing_flag_ofdm;
1711 u8 swing_idx_cck_cur;
1712 u8 swing_idx_cck_base;
1713 bool swing_flag_cck;
1718 u8 delta_swing_table_idx_24gccka_p[DEL_SW_IDX_SZ];
1719 u8 delta_swing_table_idx_24gccka_n[DEL_SW_IDX_SZ];
1720 u8 delta_swing_table_idx_24gcckb_p[DEL_SW_IDX_SZ];
1721 u8 delta_swing_table_idx_24gcckb_n[DEL_SW_IDX_SZ];
1722 u8 delta_swing_table_idx_24ga_p[DEL_SW_IDX_SZ];
1723 u8 delta_swing_table_idx_24ga_n[DEL_SW_IDX_SZ];
1724 u8 delta_swing_table_idx_24gb_p[DEL_SW_IDX_SZ];
1725 u8 delta_swing_table_idx_24gb_n[DEL_SW_IDX_SZ];
1726 u8 delta_swing_table_idx_5ga_p[BAND_NUM][DEL_SW_IDX_SZ];
1727 u8 delta_swing_table_idx_5ga_n[BAND_NUM][DEL_SW_IDX_SZ];
1728 u8 delta_swing_table_idx_5gb_p[BAND_NUM][DEL_SW_IDX_SZ];
1729 u8 delta_swing_table_idx_5gb_n[BAND_NUM][DEL_SW_IDX_SZ];
1730 u8 delta_swing_table_idx_24ga_p_8188e[DEL_SW_IDX_SZ];
1731 u8 delta_swing_table_idx_24ga_n_8188e[DEL_SW_IDX_SZ];
1734 bool supp_phymode_switch;
1737 struct fast_ant_training fat_table;
1754 #define EFUSE_MAX_LOGICAL_SIZE 512
1759 u16 max_physical_size;
1761 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1762 u16 efuse_usedbytes;
1763 u8 efuse_usedpercentage;
1764 #ifdef EFUSE_REPG_WORKAROUND
1765 bool efuse_re_pg_sec1flag;
1766 u8 efuse_re_pg_data[8];
1769 u8 autoload_failflag;
1778 u16 eeprom_channelplan;
1786 u8 antenna_div_type;
1788 bool txpwr_fromeprom;
1789 u8 eeprom_crystalcap;
1791 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1792 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1793 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1794 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
1795 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1796 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1798 u8 internal_pa_5g[2]; /* pathA / pathB */
1802 /*For power group */
1803 u8 eeprom_pwrgroup[2][3];
1804 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1805 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1807 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1808 /*For HT 40MHZ pwr */
1809 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1810 /*For HT 40MHZ pwr */
1811 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1813 /*--------------------------------------------------------*
1814 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
1815 * other ICs (8188EE\8723BE\8192EE\8812AE...)
1816 * define new arrays in Windows code.
1817 * BUT, in linux code, we use the same array for all ICs.
1819 * The Correspondance relation between two arrays is:
1820 * txpwr_cckdiff[][] == CCK_24G_Diff[][]
1821 * txpwr_ht20diff[][] == BW20_24G_Diff[][]
1822 * txpwr_ht40diff[][] == BW40_24G_Diff[][]
1823 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
1825 * Sizes of these arrays are decided by the larger ones.
1827 char txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1828 char txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1829 char txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1830 char txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1832 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1833 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1834 char txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
1835 char txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
1836 char txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
1837 char txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
1839 u8 txpwr_safetyflag; /* Band edge enable flag */
1840 u16 eeprom_txpowerdiff;
1841 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1842 u8 antenna_txpwdiff[3];
1844 u8 eeprom_regulatory;
1845 u8 eeprom_thermalmeter;
1846 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1848 u8 crystalcap; /* CrystalCap. */
1852 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1853 bool apk_thermalmeterignore;
1855 bool b1x1_recvcombine;
1863 bool pwrdomain_protect;
1864 bool in_powersavemode;
1865 bool rfchange_inprogress;
1866 bool swrf_processing;
1869 * just for PCIE ASPM
1870 * If it supports ASPM, Offset[560h] = 0x40,
1871 * otherwise Offset[560h] = 0x00.
1874 bool support_backdoor;
1877 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1882 /*For Fw control LPS mode */
1884 /*Record Fw PS mode status. */
1885 bool fw_current_inpsmode;
1886 u8 reg_max_lps_awakeintvl;
1888 bool low_power_enable;/*for 32k*/
1899 /*just for PCIE ASPM */
1900 u8 const_amdpci_aspm;
1903 enum rf_pwrstate inactive_pwrstate;
1904 enum rf_pwrstate rfpwr_state; /*cur power state */
1910 bool multi_buffered;
1912 unsigned int dtim_counter;
1913 unsigned int sleep_ms;
1914 unsigned long last_sleep_jiffies;
1915 unsigned long last_awake_jiffies;
1916 unsigned long last_delaylps_stamp_jiffies;
1917 unsigned long last_dtim;
1918 unsigned long last_beacon;
1919 unsigned long last_action;
1920 unsigned long last_slept;
1923 struct rtl_p2p_ps_info p2p_ps_info;
1927 /* wake up on line */
1929 u8 arp_offload_enable;
1930 u8 gtk_offload_enable;
1931 /* Used for WOL, indicates the reason for waking event.*/
1933 /* Record the last waking time for comparison with setting key. */
1934 u64 last_wakeup_time;
1938 u8 psaddr[ETH_ALEN];
1943 u8 rate; /* hw desc rate */
1944 u8 received_channel;
1953 u8 signalquality; /*in 0-100 index. */
1955 * Real power in dBm for this packet,
1956 * no beautification and aggregation.
1958 s32 recvsignalpower;
1959 s8 rxpower; /*in dBm Translate from PWdB */
1960 u8 signalstrength; /*in 0-100 index. */
1964 u16 shortpreamble:1;
1976 bool rx_is40Mhzpacket;
1979 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1980 s8 rx_mimo_signalquality[4];
1981 u8 rx_mimo_evm_dbm[4];
1982 u16 cfo_short[4]; /* per-path's Cfo_short */
1985 s8 rx_mimo_sig_qual[4];
1986 u8 rx_pwr[4]; /* per-path's pwdb */
1987 u8 rx_snr[4]; /* per-path's SNR */
1989 u8 bt_coex_pwr_adjust;
1990 bool packet_matchbssid;
1994 bool packet_beacon; /*for rssi */
1995 char cck_adc_pwdb[4]; /*for rx path selection */
2001 u8 packet_report_type;
2005 u32 bt_rx_rssi_percentage;
2006 u32 macid_valid_entry[2];
2010 struct rt_link_detect {
2011 /* count for roaming */
2012 u32 bcn_rx_inperiod;
2015 u32 num_tx_in4period[4];
2016 u32 num_rx_in4period[4];
2018 u32 num_tx_inperiod;
2019 u32 num_rx_inperiod;
2022 bool tx_busy_traffic;
2023 bool rx_busy_traffic;
2024 bool higher_busytraffic;
2025 bool higher_busyrxtraffic;
2027 u32 tidtx_in4period[MAX_TID_COUNT][4];
2028 u32 tidtx_inperiod[MAX_TID_COUNT];
2029 bool higher_busytxtraffic[MAX_TID_COUNT];
2032 struct rtl_tcb_desc {
2040 u8 rts_use_shortpreamble:1;
2041 u8 rts_use_shortgi:1;
2047 u8 use_shortpreamble:1;
2048 u8 use_driver_rate:1;
2049 u8 disable_ratefallback:1;
2061 /* The max value by HW */
2063 bool tx_enable_sw_calc_duration;
2066 struct rtl92c_firmware_header;
2068 struct rtl_wow_pattern {
2074 struct rtl8723e_firmware_header;
2076 struct rtl_hal_ops {
2077 int (*init_sw_vars) (struct ieee80211_hw *hw);
2078 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
2079 void (*read_chip_version)(struct ieee80211_hw *hw);
2080 void (*read_eeprom_info) (struct ieee80211_hw *hw);
2081 void (*interrupt_recognized) (struct ieee80211_hw *hw,
2082 u32 *p_inta, u32 *p_intb);
2083 int (*hw_init) (struct ieee80211_hw *hw);
2084 void (*hw_disable) (struct ieee80211_hw *hw);
2085 void (*hw_suspend) (struct ieee80211_hw *hw);
2086 void (*hw_resume) (struct ieee80211_hw *hw);
2087 void (*enable_interrupt) (struct ieee80211_hw *hw);
2088 void (*disable_interrupt) (struct ieee80211_hw *hw);
2089 int (*set_network_type) (struct ieee80211_hw *hw,
2090 enum nl80211_iftype type);
2091 void (*set_chk_bssid)(struct ieee80211_hw *hw,
2093 void (*set_bw_mode) (struct ieee80211_hw *hw,
2094 enum nl80211_channel_type ch_type);
2095 u8(*switch_channel) (struct ieee80211_hw *hw);
2096 void (*set_qos) (struct ieee80211_hw *hw, int aci);
2097 void (*set_bcn_reg) (struct ieee80211_hw *hw);
2098 void (*set_bcn_intv) (struct ieee80211_hw *hw);
2099 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
2100 u32 add_msr, u32 rm_msr);
2101 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
2102 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
2103 void (*update_rate_tbl) (struct ieee80211_hw *hw,
2104 struct ieee80211_sta *sta, u8 rssi_level);
2105 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc,
2106 u8 *desc, u8 queue_index,
2107 struct sk_buff *skb, dma_addr_t addr);
2108 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
2109 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw,
2111 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
2113 void (*fill_tx_desc) (struct ieee80211_hw *hw,
2114 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
2116 struct ieee80211_tx_info *info,
2117 struct ieee80211_sta *sta,
2118 struct sk_buff *skb, u8 hw_queue,
2119 struct rtl_tcb_desc *ptcb_desc);
2120 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
2121 u32 buffer_len, bool bIsPsPoll);
2122 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
2123 bool firstseg, bool lastseg,
2124 struct sk_buff *skb);
2125 bool (*query_rx_desc) (struct ieee80211_hw *hw,
2126 struct rtl_stats *stats,
2127 struct ieee80211_rx_status *rx_status,
2128 u8 *pdesc, struct sk_buff *skb);
2129 void (*set_channel_access) (struct ieee80211_hw *hw);
2130 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
2131 void (*dm_watchdog) (struct ieee80211_hw *hw);
2132 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
2133 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
2134 enum rf_pwrstate rfpwr_state);
2135 void (*led_control) (struct ieee80211_hw *hw,
2136 enum led_ctl_mode ledaction);
2137 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2138 u8 desc_name, u8 *val);
2139 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
2140 bool (*is_tx_desc_closed) (struct ieee80211_hw *hw,
2141 u8 hw_queue, u16 index);
2142 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
2143 void (*enable_hw_sec) (struct ieee80211_hw *hw);
2144 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
2145 u8 *macaddr, bool is_group, u8 enc_algo,
2146 bool is_wepkey, bool clear_all);
2147 void (*init_sw_leds) (struct ieee80211_hw *hw);
2148 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
2149 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
2150 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
2152 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
2153 u32 regaddr, u32 bitmask);
2154 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
2155 u32 regaddr, u32 bitmask, u32 data);
2156 void (*linked_set_reg) (struct ieee80211_hw *hw);
2157 void (*chk_switch_dmdp) (struct ieee80211_hw *hw);
2158 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw);
2159 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw);
2160 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
2161 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
2163 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
2164 u8 *ppowerlevel, u8 channel);
2165 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
2167 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
2169 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
2170 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
2171 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
2172 void (*c2h_command_handle) (struct ieee80211_hw *hw);
2173 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
2175 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
2176 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
2177 u32 cmd_len, u8 *p_cmdbuffer);
2178 bool (*get_btc_status) (void);
2179 bool (*is_fw_header)(struct rtl8723e_firmware_header *hdr);
2180 u32 (*rx_command_packet)(struct ieee80211_hw *hw,
2181 struct rtl_stats status, struct sk_buff *skb);
2182 void (*add_wowlan_pattern)(struct ieee80211_hw *hw,
2183 struct rtl_wow_pattern *rtl_pattern,
2187 struct rtl_intf_ops {
2189 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
2190 int (*adapter_start) (struct ieee80211_hw *hw);
2191 void (*adapter_stop) (struct ieee80211_hw *hw);
2192 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
2193 struct rtl_priv **buddy_priv);
2195 int (*adapter_tx) (struct ieee80211_hw *hw,
2196 struct ieee80211_sta *sta,
2197 struct sk_buff *skb,
2198 struct rtl_tcb_desc *ptcb_desc);
2199 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
2200 int (*reset_trx_ring) (struct ieee80211_hw *hw);
2201 bool (*waitq_insert) (struct ieee80211_hw *hw,
2202 struct ieee80211_sta *sta,
2203 struct sk_buff *skb);
2206 void (*disable_aspm) (struct ieee80211_hw *hw);
2207 void (*enable_aspm) (struct ieee80211_hw *hw);
2212 struct rtl_mod_params {
2213 /* default: 0 = using hardware encryption */
2216 /* default: 0 = DBG_EMERG (0)*/
2219 /* default: 1 = using no linked power save */
2222 /* default: 1 = using linked sw power save */
2225 /* default: 1 = using linked fw power save */
2228 /* default: 0 = not using MSI interrupts mode
2229 * submodules should set their own default value
2233 /* default 0: 1 means disable */
2234 bool disable_watchdog;
2237 struct rtl_hal_usbint_cfg {
2244 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
2245 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
2246 struct sk_buff_head *);
2249 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
2250 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
2252 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
2253 struct sk_buff_head *);
2255 /* endpoint mapping */
2256 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
2257 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
2260 struct rtl_hal_cfg {
2262 bool write_readback;
2266 char *wowlan_fw_name;
2267 struct rtl_hal_ops *ops;
2268 struct rtl_mod_params *mod_params;
2269 struct rtl_hal_usbint_cfg *usb_interface_cfg;
2271 /*this map used for some registers or vars
2272 defined int HAL but used in MAIN */
2273 u32 maps[RTL_VAR_MAP_MAX];
2279 struct mutex conf_mutex;
2280 struct mutex ps_mutex;
2283 spinlock_t ips_lock;
2284 spinlock_t irq_th_lock;
2285 spinlock_t irq_pci_lock;
2287 spinlock_t h2c_lock;
2288 spinlock_t rf_ps_lock;
2290 spinlock_t lps_lock;
2291 spinlock_t waitq_lock;
2292 spinlock_t entry_list_lock;
2293 spinlock_t usb_lock;
2295 /*FW clock change */
2296 spinlock_t fw_ps_lock;
2299 spinlock_t cck_and_rw_pagea_lock;
2302 spinlock_t check_sendpkt_lock;
2304 spinlock_t iqk_lock;
2308 struct ieee80211_hw *hw;
2311 struct timer_list watchdog_timer;
2312 struct timer_list dualmac_easyconcurrent_retrytimer;
2313 struct timer_list fw_clockoff_timer;
2314 struct timer_list fast_antenna_training_timer;
2316 struct tasklet_struct irq_tasklet;
2317 struct tasklet_struct irq_prepare_bcn_tasklet;
2320 struct workqueue_struct *rtl_wq;
2321 struct delayed_work watchdog_wq;
2322 struct delayed_work ips_nic_off_wq;
2325 struct delayed_work ps_work;
2326 struct delayed_work ps_rfon_wq;
2327 struct delayed_work fwevt_wq;
2329 struct work_struct lps_change_work;
2330 struct work_struct fill_h2c_cmd;
2334 u32 dbgp_type[DBGP_TYPE_MAX];
2335 int global_debuglevel;
2336 u64 global_debugcomponents;
2338 /* add for proc debug */
2339 struct proc_dir_entry *proc_dir;
2343 #define MIMO_PS_STATIC 0
2344 #define MIMO_PS_DYNAMIC 1
2345 #define MIMO_PS_NOLIMIT 3
2347 struct rtl_dualmac_easy_concurrent_ctl {
2348 enum band_type currentbandtype_backfordmdp;
2349 bool close_bbandrf_for_dmsp;
2350 bool change_to_dmdp;
2351 bool change_to_dmsp;
2352 bool switch_in_process;
2355 struct rtl_dmsp_ctl {
2356 bool activescan_for_slaveofdmsp;
2357 bool scan_for_anothermac_fordmsp;
2358 bool scan_for_itself_fordmsp;
2359 bool writedig_for_anothermacofdmsp;
2360 u32 curdigvalue_for_anothermacofdmsp;
2361 bool changecckpdstate_for_anothermacofdmsp;
2362 u8 curcckpdstate_for_anothermacofdmsp;
2363 bool changetxhighpowerlvl_for_anothermacofdmsp;
2364 u8 curtxhighlvl_for_anothermacofdmsp;
2365 long rssivalmin_for_anothermacofdmsp;
2379 u32 rssi_highthresh;
2382 long last_min_undec_pwdb_for_dm;
2383 long rssi_highpower_lowthresh;
2384 long rssi_highpower_highthresh;
2390 u8 dig_ext_port_stage;
2392 u8 dig_twoport_algorithm;
2394 u8 dig_slgorithm_switch;
2397 u8 curmultista_cstate;
2400 char back_range_max;
2401 char back_range_min;
2404 u8 min_undec_pwdb_for_dm;
2406 u8 pre_cck_cca_thres;
2407 u8 cur_cck_cca_thres;
2408 u8 pre_cck_pd_state;
2409 u8 cur_cck_pd_state;
2410 u8 pre_cck_fa_state;
2411 u8 cur_cck_fa_state;
2416 u8 dig_dynamic_min_1;
2419 u8 dig_highpwrstate;
2426 u8 cur_cs_ratiostate;
2427 u8 pre_cs_ratiostate;
2428 u8 backoff_enable_flag;
2429 char backoffval_range_max;
2430 char backoffval_range_min;
2434 bool media_connect_0;
2435 bool media_connect_1;
2437 u32 antdiv_rssi_max;
2441 struct rtl_global_var {
2442 /* from this list we can get
2443 * other adapter's rtl_priv */
2444 struct list_head glb_priv_list;
2445 spinlock_t glb_list_lock;
2448 struct rtl_btc_info {
2454 struct bt_coexist_info {
2455 struct rtl_btc_ops *btc_ops;
2456 struct rtl_btc_info btc_info;
2457 /* EEPROM BT info. */
2458 u8 eeprom_bt_coexist;
2460 u8 eeprom_bt_ant_num;
2461 u8 eeprom_bt_ant_isol;
2462 u8 eeprom_bt_radio_shared;
2468 u8 bt_cur_state; /* 0:on, 1:off */
2469 u8 bt_ant_isolation; /* 0:good, 1:bad */
2470 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2472 u8 bt_radio_shared_type;
2473 u8 bt_rfreg_origin_1e;
2474 u8 bt_rfreg_origin_1f;
2482 bool bt_busy_traffic;
2483 bool bt_traffic_mode_set;
2484 bool bt_non_traffic_mode_set;
2486 bool fw_coexist_all_off;
2487 bool sw_coexist_all_off;
2488 bool hw_coexist_all_off;
2492 u32 previous_state_h;
2494 u8 bt_pre_rssi_state;
2495 u8 bt_pre_rssi_state1;
2500 u8 bt_active_zero_cnt;
2501 bool cur_bt_disabled;
2502 bool pre_bt_disabled;
2505 u8 bt_profile_action;
2507 bool hold_for_bt_operation;
2511 struct rtl_btc_ops {
2512 void (*btc_init_variables) (struct rtl_priv *rtlpriv);
2513 void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv);
2514 void (*btc_init_hw_config) (struct rtl_priv *rtlpriv);
2515 void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type);
2516 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type);
2517 void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype);
2518 void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action);
2519 void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv,
2520 enum rt_media_status mstatus);
2521 void (*btc_periodical) (struct rtl_priv *rtlpriv);
2522 void (*btc_halt_notify) (void);
2523 void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv,
2524 u8 *tmp_buf, u8 length);
2525 bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv);
2526 bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv);
2527 bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv);
2528 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv,
2535 void *proximity_priv;
2536 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
2537 struct sk_buff *skb);
2538 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
2542 struct ieee80211_hw *hw;
2543 struct completion firmware_loading_complete;
2544 struct list_head list;
2545 struct rtl_priv *buddy_priv;
2546 struct rtl_global_var *glb_var;
2547 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
2548 struct rtl_dmsp_ctl dmsp_ctl;
2549 struct rtl_locks locks;
2550 struct rtl_works works;
2551 struct rtl_mac mac80211;
2552 struct rtl_hal rtlhal;
2553 struct rtl_regulatory regd;
2554 struct rtl_rfkill rfkill;
2558 struct rtl_security sec;
2559 struct rtl_efuse efuse;
2561 struct rtl_ps_ctl psc;
2562 struct rate_adaptive ra;
2563 struct dynamic_primary_cca primarycca;
2564 struct wireless_stats stats;
2565 struct rt_link_detect link_info;
2566 struct false_alarm_statistics falsealm_cnt;
2568 struct rtl_rate_priv *rate_priv;
2570 /* sta entry list for ap adhoc or mesh */
2571 struct list_head entry_list;
2573 struct rtl_debug dbg;
2577 *hal_cfg : for diff cards
2578 *intf_ops : for diff interrface usb/pcie
2580 struct rtl_hal_cfg *cfg;
2581 struct rtl_intf_ops *intf_ops;
2583 /*this var will be set by set_bit,
2584 and was used to indicate status of
2585 interface or hardware */
2586 unsigned long status;
2589 struct dig_t dm_digtable;
2590 struct ps_t dm_pstable;
2596 bool reg_init; /* true if regs saved */
2597 bool bt_operation_on;
2601 bool enter_ps; /* true when entering PS */
2604 /* intel Proximity, should be alloc mem
2605 * in intel Proximity module and can only
2606 * be used in intel Proximity mode
2608 struct proxim proximity;
2610 /*for bt coexist use*/
2611 struct bt_coexist_info btcoexist;
2613 /* separate 92ee from other ICs,
2614 * 92ee use new trx flow.
2616 bool use_new_trx_flow;
2619 struct wiphy_wowlan_support wowlan;
2621 /*This must be the last item so
2622 that it points to the data allocated
2623 beyond this structure like:
2624 rtl_pci_priv or rtl_usb_priv */
2625 u8 priv[0] __aligned(sizeof(void *));
2628 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2629 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2630 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2631 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2632 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2635 /***************************************
2636 Bluetooth Co-existence Related
2637 ****************************************/
2658 enum bt_total_ant_num {
2668 enum bt_service_type {
2675 BT_OTHER_ACTION = 6,
2681 enum bt_radio_shared {
2682 BT_RADIO_SHARED = 0,
2683 BT_RADIO_INDIVIDUAL = 1,
2687 /****************************************
2688 mem access macro define start
2689 Call endian free function when
2690 1. Read/write packet content.
2691 2. Before write integer to IO.
2692 3. After read integer from IO.
2693 ****************************************/
2694 /* Convert little data endian to host ordering */
2695 #define EF1BYTE(_val) \
2697 #define EF2BYTE(_val) \
2699 #define EF4BYTE(_val) \
2702 /* Read data from memory */
2703 #define READEF1BYTE(_ptr) \
2704 EF1BYTE(*((u8 *)(_ptr)))
2705 /* Read le16 data from memory and convert to host ordering */
2706 #define READEF2BYTE(_ptr) \
2708 #define READEF4BYTE(_ptr) \
2711 /* Write data to memory */
2712 #define WRITEEF1BYTE(_ptr, _val) \
2713 (*((u8 *)(_ptr))) = EF1BYTE(_val)
2714 /* Write le16 data to memory in host ordering */
2715 #define WRITEEF2BYTE(_ptr, _val) \
2716 (*((u16 *)(_ptr))) = EF2BYTE(_val)
2717 #define WRITEEF4BYTE(_ptr, _val) \
2718 (*((u32 *)(_ptr))) = EF2BYTE(_val)
2720 /* Create a bit mask
2722 * BIT_LEN_MASK_32(0) => 0x00000000
2723 * BIT_LEN_MASK_32(1) => 0x00000001
2724 * BIT_LEN_MASK_32(2) => 0x00000003
2725 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
2727 #define BIT_LEN_MASK_32(__bitlen) \
2728 (0xFFFFFFFF >> (32 - (__bitlen)))
2729 #define BIT_LEN_MASK_16(__bitlen) \
2730 (0xFFFF >> (16 - (__bitlen)))
2731 #define BIT_LEN_MASK_8(__bitlen) \
2732 (0xFF >> (8 - (__bitlen)))
2734 /* Create an offset bit mask
2736 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2737 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
2739 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2740 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2741 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2742 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2743 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2744 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2747 * Return 4-byte value in host byte ordering from
2748 * 4-byte pointer in little-endian system.
2750 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
2751 (EF4BYTE(*((__le32 *)(__pstart))))
2752 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
2753 (EF2BYTE(*((__le16 *)(__pstart))))
2754 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2755 (EF1BYTE(*((u8 *)(__pstart))))
2758 Translate subfield (continuous bits in little-endian) of 4-byte
2759 value to host byte ordering.*/
2760 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2762 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
2763 BIT_LEN_MASK_32(__bitlen) \
2765 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2767 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
2768 BIT_LEN_MASK_16(__bitlen) \
2770 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2772 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
2773 BIT_LEN_MASK_8(__bitlen) \
2777 * Mask subfield (continuous bits in little-endian) of 4-byte value
2778 * and return the result in 4-byte value in host byte ordering.
2780 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2782 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
2783 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
2785 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2787 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2788 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
2790 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2792 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2793 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
2797 * Set subfield of little-endian 4-byte value to specified value.
2799 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
2800 *((u32 *)(__pstart)) = \
2802 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2803 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
2805 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
2806 *((u16 *)(__pstart)) = \
2808 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2809 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
2811 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2812 *((u8 *)(__pstart)) = EF1BYTE \
2814 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2815 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
2818 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2819 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2821 /****************************************
2822 mem access macro define end
2823 ****************************************/
2825 #define byte(x, n) ((x >> (8 * n)) & 0xff)
2827 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2828 #define RTL_WATCH_DOG_TIME 2000
2829 #define MSECS(t) msecs_to_jiffies(t)
2830 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2831 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2832 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2833 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
2834 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
2836 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2837 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2838 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2839 /*NIC halt, re-initialize hw parameters*/
2840 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2841 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2842 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2843 /*Always enable ASPM and Clock Req in initialization.*/
2844 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
2845 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2846 #define RT_PS_LEVEL_ASPM BIT(7)
2847 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
2848 #define RT_RF_LPS_DISALBE_2R BIT(30)
2849 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2850 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2851 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2852 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2853 (ppsc->cur_ps_level &= (~(_ps_flg)))
2854 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2855 (ppsc->cur_ps_level |= _ps_flg)
2857 #define container_of_dwork_rtl(x, y, z) \
2858 container_of(container_of(x, struct delayed_work, work), y, z)
2860 #define FILL_OCTET_STRING(_os, _octet, _len) \
2861 (_os).octet = (u8 *)(_octet); \
2862 (_os).length = (_len);
2864 #define CP_MACADDR(des, src) \
2865 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
2866 (des)[2] = (src)[2], (des)[3] = (src)[3],\
2867 (des)[4] = (src)[4], (des)[5] = (src)[5])
2869 #define LDPC_HT_ENABLE_RX BIT(0)
2870 #define LDPC_HT_ENABLE_TX BIT(1)
2871 #define LDPC_HT_TEST_TX_ENABLE BIT(2)
2872 #define LDPC_HT_CAP_TX BIT(3)
2874 #define STBC_HT_ENABLE_RX BIT(0)
2875 #define STBC_HT_ENABLE_TX BIT(1)
2876 #define STBC_HT_TEST_TX_ENABLE BIT(2)
2877 #define STBC_HT_CAP_TX BIT(3)
2879 #define LDPC_VHT_ENABLE_RX BIT(0)
2880 #define LDPC_VHT_ENABLE_TX BIT(1)
2881 #define LDPC_VHT_TEST_TX_ENABLE BIT(2)
2882 #define LDPC_VHT_CAP_TX BIT(3)
2884 #define STBC_VHT_ENABLE_RX BIT(0)
2885 #define STBC_VHT_ENABLE_TX BIT(1)
2886 #define STBC_VHT_TEST_TX_ENABLE BIT(2)
2887 #define STBC_VHT_CAP_TX BIT(3)
2889 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2891 return rtlpriv->io.read8_sync(rtlpriv, addr);
2894 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2896 return rtlpriv->io.read16_sync(rtlpriv, addr);
2899 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2901 return rtlpriv->io.read32_sync(rtlpriv, addr);
2904 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2906 rtlpriv->io.write8_async(rtlpriv, addr, val8);
2908 if (rtlpriv->cfg->write_readback)
2909 rtlpriv->io.read8_sync(rtlpriv, addr);
2912 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2914 rtlpriv->io.write16_async(rtlpriv, addr, val16);
2916 if (rtlpriv->cfg->write_readback)
2917 rtlpriv->io.read16_sync(rtlpriv, addr);
2920 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2921 u32 addr, u32 val32)
2923 rtlpriv->io.write32_async(rtlpriv, addr, val32);
2925 if (rtlpriv->cfg->write_readback)
2926 rtlpriv->io.read32_sync(rtlpriv, addr);
2929 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2930 u32 regaddr, u32 bitmask)
2932 struct rtl_priv *rtlpriv = hw->priv;
2934 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
2937 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
2938 u32 bitmask, u32 data)
2940 struct rtl_priv *rtlpriv = hw->priv;
2942 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
2945 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
2946 enum radio_path rfpath, u32 regaddr,
2949 struct rtl_priv *rtlpriv = hw->priv;
2951 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
2954 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
2955 enum radio_path rfpath, u32 regaddr,
2956 u32 bitmask, u32 data)
2958 struct rtl_priv *rtlpriv = hw->priv;
2960 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
2963 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
2965 return (_HAL_STATE_STOP == rtlhal->state);
2968 static inline void set_hal_start(struct rtl_hal *rtlhal)
2970 rtlhal->state = _HAL_STATE_START;
2973 static inline void set_hal_stop(struct rtl_hal *rtlhal)
2975 rtlhal->state = _HAL_STATE_STOP;
2978 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2980 return rtlphy->rf_type;
2983 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
2985 return (struct ieee80211_hdr *)(skb->data);
2988 static inline __le16 rtl_get_fc(struct sk_buff *skb)
2990 return rtl_get_hdr(skb)->frame_control;
2993 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
2995 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
2998 static inline u16 rtl_get_tid(struct sk_buff *skb)
3000 return rtl_get_tid_h(rtl_get_hdr(skb));
3003 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
3004 struct ieee80211_vif *vif,
3007 return ieee80211_find_sta(vif, bssid);
3010 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
3013 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3014 return ieee80211_find_sta(mac->vif, mac_addr);