3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 /* This file implements all the hardware specific functions for the ZD1211
19 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
20 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
28 #include "zd_ieee80211.h"
33 void zd_chip_init(struct zd_chip *chip,
34 struct net_device *netdev,
35 struct usb_interface *intf)
37 memset(chip, 0, sizeof(*chip));
38 mutex_init(&chip->mutex);
39 zd_usb_init(&chip->usb, netdev, intf);
40 zd_rf_init(&chip->rf);
43 void zd_chip_clear(struct zd_chip *chip)
45 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
46 zd_usb_clear(&chip->usb);
47 zd_rf_clear(&chip->rf);
48 mutex_destroy(&chip->mutex);
49 ZD_MEMCLEAR(chip, sizeof(*chip));
52 static int scnprint_mac_oui(struct zd_chip *chip, char *buffer, size_t size)
54 u8 *addr = zd_usb_to_netdev(&chip->usb)->dev_addr;
55 return scnprintf(buffer, size, "%02x-%02x-%02x",
56 addr[0], addr[1], addr[2]);
59 /* Prints an identifier line, which will support debugging. */
60 static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
64 i = scnprintf(buffer, size, "zd1211%s chip ",
65 zd_chip_is_zd1211b(chip) ? "b" : "");
66 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
67 i += scnprintf(buffer+i, size-i, " ");
68 i += scnprint_mac_oui(chip, buffer+i, size-i);
69 i += scnprintf(buffer+i, size-i, " ");
70 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
71 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type,
72 chip->patch_cck_gain ? 'g' : '-',
73 chip->patch_cr157 ? '7' : '-',
74 chip->patch_6m_band_edge ? '6' : '-',
75 chip->new_phy_layout ? 'N' : '-',
76 chip->al2230s_bit ? 'S' : '-');
80 static void print_id(struct zd_chip *chip)
84 scnprint_id(chip, buffer, sizeof(buffer));
85 buffer[sizeof(buffer)-1] = 0;
86 dev_info(zd_chip_dev(chip), "%s\n", buffer);
89 static zd_addr_t inc_addr(zd_addr_t addr)
92 /* Control registers use byte addressing, but everything else uses word
94 if ((a & 0xf000) == CR_START)
101 /* Read a variable number of 32-bit values. Parameter count is not allowed to
102 * exceed USB_MAX_IOREAD32_COUNT.
104 int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
111 unsigned int count16;
113 if (count > USB_MAX_IOREAD32_COUNT)
116 /* Allocate a single memory block for values and addresses. */
118 a16 = (zd_addr_t *) kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
121 dev_dbg_f(zd_chip_dev(chip),
122 "error ENOMEM in allocation of a16\n");
126 v16 = (u16 *)(a16 + count16);
128 for (i = 0; i < count; i++) {
130 /* We read the high word always first. */
131 a16[j] = inc_addr(addr[i]);
135 r = zd_ioread16v_locked(chip, v16, a16, count16);
137 dev_dbg_f(zd_chip_dev(chip),
138 "error: zd_ioread16v_locked. Error number %d\n", r);
142 for (i = 0; i < count; i++) {
144 values[i] = (v16[j] << 16) | v16[j+1];
152 int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
156 struct zd_ioreq16 *ioreqs16;
157 unsigned int count16;
159 ZD_ASSERT(mutex_is_locked(&chip->mutex));
163 if (count > USB_MAX_IOWRITE32_COUNT)
166 /* Allocate a single memory block for values and addresses. */
168 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_KERNEL);
171 dev_dbg_f(zd_chip_dev(chip),
172 "error %d in ioreqs16 allocation\n", r);
176 for (i = 0; i < count; i++) {
178 /* We write the high word always first. */
179 ioreqs16[j].value = ioreqs[i].value >> 16;
180 ioreqs16[j].addr = inc_addr(ioreqs[i].addr);
181 ioreqs16[j+1].value = ioreqs[i].value;
182 ioreqs16[j+1].addr = ioreqs[i].addr;
185 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
188 dev_dbg_f(zd_chip_dev(chip),
189 "error %d in zd_usb_write16v\n", r);
197 int zd_iowrite16a_locked(struct zd_chip *chip,
198 const struct zd_ioreq16 *ioreqs, unsigned int count)
201 unsigned int i, j, t, max;
203 ZD_ASSERT(mutex_is_locked(&chip->mutex));
204 for (i = 0; i < count; i += j + t) {
207 if (max > USB_MAX_IOWRITE16_COUNT)
208 max = USB_MAX_IOWRITE16_COUNT;
209 for (j = 0; j < max; j++) {
210 if (!ioreqs[i+j].addr) {
216 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
218 dev_dbg_f(zd_chip_dev(chip),
219 "error zd_usb_iowrite16v. Error number %d\n",
228 /* Writes a variable number of 32 bit registers. The functions will split
229 * that in several USB requests. A split can be forced by inserting an IO
230 * request with an zero address field.
232 int zd_iowrite32a_locked(struct zd_chip *chip,
233 const struct zd_ioreq32 *ioreqs, unsigned int count)
236 unsigned int i, j, t, max;
238 for (i = 0; i < count; i += j + t) {
241 if (max > USB_MAX_IOWRITE32_COUNT)
242 max = USB_MAX_IOWRITE32_COUNT;
243 for (j = 0; j < max; j++) {
244 if (!ioreqs[i+j].addr) {
250 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
252 dev_dbg_f(zd_chip_dev(chip),
253 "error _zd_iowrite32v_locked."
254 " Error number %d\n", r);
262 int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
266 mutex_lock(&chip->mutex);
267 r = zd_ioread16_locked(chip, value, addr);
268 mutex_unlock(&chip->mutex);
272 int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
276 mutex_lock(&chip->mutex);
277 r = zd_ioread32_locked(chip, value, addr);
278 mutex_unlock(&chip->mutex);
282 int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
286 mutex_lock(&chip->mutex);
287 r = zd_iowrite16_locked(chip, value, addr);
288 mutex_unlock(&chip->mutex);
292 int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
296 mutex_lock(&chip->mutex);
297 r = zd_iowrite32_locked(chip, value, addr);
298 mutex_unlock(&chip->mutex);
302 int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
303 u32 *values, unsigned int count)
307 mutex_lock(&chip->mutex);
308 r = zd_ioread32v_locked(chip, values, addresses, count);
309 mutex_unlock(&chip->mutex);
313 int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
318 mutex_lock(&chip->mutex);
319 r = zd_iowrite32a_locked(chip, ioreqs, count);
320 mutex_unlock(&chip->mutex);
324 static int read_pod(struct zd_chip *chip, u8 *rf_type)
329 ZD_ASSERT(mutex_is_locked(&chip->mutex));
330 r = zd_ioread32_locked(chip, &value, E2P_POD);
333 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
335 /* FIXME: AL2230 handling (Bit 7 in POD) */
336 *rf_type = value & 0x0f;
337 chip->pa_type = (value >> 16) & 0x0f;
338 chip->patch_cck_gain = (value >> 8) & 0x1;
339 chip->patch_cr157 = (value >> 13) & 0x1;
340 chip->patch_6m_band_edge = (value >> 21) & 0x1;
341 chip->new_phy_layout = (value >> 31) & 0x1;
342 chip->al2230s_bit = (value >> 7) & 0x1;
343 chip->link_led = ((value >> 4) & 1) ? LED1 : LED2;
344 chip->supports_tx_led = 1;
345 if (value & (1 << 24)) { /* LED scenario */
346 if (value & (1 << 29))
347 chip->supports_tx_led = 0;
350 dev_dbg_f(zd_chip_dev(chip),
351 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
352 "patch 6M %d new PHY %d link LED%d tx led %d\n",
353 zd_rf_name(*rf_type), *rf_type,
354 chip->pa_type, chip->patch_cck_gain,
355 chip->patch_cr157, chip->patch_6m_band_edge,
356 chip->new_phy_layout,
357 chip->link_led == LED1 ? 1 : 2,
358 chip->supports_tx_led);
363 chip->patch_cck_gain = 0;
364 chip->patch_cr157 = 0;
365 chip->patch_6m_band_edge = 0;
366 chip->new_phy_layout = 0;
370 /* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and
371 * CR_MAC_ADDR_P2 must be overwritten
373 int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
376 struct zd_ioreq32 reqs[2] = {
377 [0] = { .addr = CR_MAC_ADDR_P1 },
378 [1] = { .addr = CR_MAC_ADDR_P2 },
380 DECLARE_MAC_BUF(mac);
382 reqs[0].value = (mac_addr[3] << 24)
383 | (mac_addr[2] << 16)
386 reqs[1].value = (mac_addr[5] << 8)
389 dev_dbg_f(zd_chip_dev(chip),
390 "mac addr %s\n", print_mac(mac, mac_addr));
392 mutex_lock(&chip->mutex);
393 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
394 mutex_unlock(&chip->mutex);
398 int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
403 mutex_lock(&chip->mutex);
404 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
405 mutex_unlock(&chip->mutex);
409 *regdomain = value >> 16;
410 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
415 static int read_values(struct zd_chip *chip, u8 *values, size_t count,
416 zd_addr_t e2p_addr, u32 guard)
422 ZD_ASSERT(mutex_is_locked(&chip->mutex));
424 r = zd_ioread32_locked(chip, &v,
425 (zd_addr_t)((u16)e2p_addr+i/2));
431 values[i++] = v >> 8;
432 values[i++] = v >> 16;
433 values[i++] = v >> 24;
436 for (;i < count; i++)
437 values[i] = v >> (8*(i%3));
442 static int read_pwr_cal_values(struct zd_chip *chip)
444 return read_values(chip, chip->pwr_cal_values,
445 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
449 static int read_pwr_int_values(struct zd_chip *chip)
451 return read_values(chip, chip->pwr_int_values,
452 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
456 static int read_ofdm_cal_values(struct zd_chip *chip)
460 static const zd_addr_t addresses[] = {
466 for (i = 0; i < 3; i++) {
467 r = read_values(chip, chip->ofdm_cal_values[i],
468 E2P_CHANNEL_COUNT, addresses[i], 0);
475 static int read_cal_int_tables(struct zd_chip *chip)
479 r = read_pwr_cal_values(chip);
482 r = read_pwr_int_values(chip);
485 r = read_ofdm_cal_values(chip);
491 /* phy means physical registers */
492 int zd_chip_lock_phy_regs(struct zd_chip *chip)
497 ZD_ASSERT(mutex_is_locked(&chip->mutex));
498 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
500 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
504 tmp &= ~UNLOCK_PHY_REGS;
506 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
508 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
512 int zd_chip_unlock_phy_regs(struct zd_chip *chip)
517 ZD_ASSERT(mutex_is_locked(&chip->mutex));
518 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
520 dev_err(zd_chip_dev(chip),
521 "error ioread32(CR_REG1): %d\n", r);
525 tmp |= UNLOCK_PHY_REGS;
527 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
529 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
533 /* CR157 can be optionally patched by the EEPROM for original ZD1211 */
534 static int patch_cr157(struct zd_chip *chip)
539 if (!chip->patch_cr157)
542 r = zd_ioread16_locked(chip, &value, E2P_PHY_REG);
546 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
547 return zd_iowrite32_locked(chip, value >> 8, CR157);
551 * 6M band edge can be optionally overwritten for certain RF's
552 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
553 * bit (for AL2230, AL2230S)
555 static int patch_6m_band_edge(struct zd_chip *chip, u8 channel)
557 ZD_ASSERT(mutex_is_locked(&chip->mutex));
558 if (!chip->patch_6m_band_edge)
561 return zd_rf_patch_6m_band_edge(&chip->rf, channel);
564 /* Generic implementation of 6M band edge patching, used by most RFs via
565 * zd_rf_generic_patch_6m() */
566 int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel)
568 struct zd_ioreq16 ioreqs[] = {
569 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
573 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
574 if (channel == 1 || channel == 11)
575 ioreqs[0].value = 0x12;
577 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
578 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
581 static int zd1211_hw_reset_phy(struct zd_chip *chip)
583 static const struct zd_ioreq16 ioreqs[] = {
584 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
585 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
586 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
587 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
588 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
589 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
590 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
591 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
592 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
593 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
594 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
595 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
596 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
597 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
598 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
599 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
600 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
601 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
602 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
603 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
604 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
605 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
606 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
607 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
608 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
609 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
610 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
611 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
612 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
613 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
614 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
615 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
616 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
618 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
619 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
620 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
621 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
622 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
623 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
624 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
625 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
626 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
627 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
628 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
629 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
630 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
631 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
632 { CR125, 0xaa }, { CR127, 0x03 }, { CR128, 0x14 },
633 { CR129, 0x12 }, { CR130, 0x10 }, { CR131, 0x0C },
634 { CR136, 0xdf }, { CR137, 0x40 }, { CR138, 0xa0 },
635 { CR139, 0xb0 }, { CR140, 0x99 }, { CR141, 0x82 },
636 { CR142, 0x54 }, { CR143, 0x1c }, { CR144, 0x6c },
637 { CR147, 0x07 }, { CR148, 0x4c }, { CR149, 0x50 },
638 { CR150, 0x0e }, { CR151, 0x18 }, { CR160, 0xfe },
639 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
640 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
641 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
642 { CR170, 0xba }, { CR171, 0xba },
643 /* Note: CR204 must lead the CR203 */
651 dev_dbg_f(zd_chip_dev(chip), "\n");
653 r = zd_chip_lock_phy_regs(chip);
657 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
661 r = patch_cr157(chip);
663 t = zd_chip_unlock_phy_regs(chip);
670 static int zd1211b_hw_reset_phy(struct zd_chip *chip)
672 static const struct zd_ioreq16 ioreqs[] = {
673 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
674 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
676 /* power control { { CR11, 1 << 6 }, */
678 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
679 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
680 { CR18, 0x0a }, { CR19, 0x48 },
681 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
682 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
683 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
684 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
685 { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
686 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
687 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
688 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
689 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
690 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
691 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
692 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
693 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
694 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
695 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
696 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
697 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
698 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
699 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
700 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
701 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
703 { CR95, 0x20 }, /* ZD1211B */
704 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
705 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
706 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
707 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
708 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
709 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
710 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
711 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
712 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
713 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
714 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
715 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
716 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
717 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
718 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
719 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
720 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
721 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
722 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
723 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
724 { CR170, 0xba }, { CR171, 0xba },
725 /* Note: CR204 must lead the CR203 */
733 dev_dbg_f(zd_chip_dev(chip), "\n");
735 r = zd_chip_lock_phy_regs(chip);
739 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
740 t = zd_chip_unlock_phy_regs(chip);
747 static int hw_reset_phy(struct zd_chip *chip)
749 return zd_chip_is_zd1211b(chip) ? zd1211b_hw_reset_phy(chip) :
750 zd1211_hw_reset_phy(chip);
753 static int zd1211_hw_init_hmac(struct zd_chip *chip)
755 static const struct zd_ioreq32 ioreqs[] = {
756 { CR_ZD1211_RETRY_MAX, 0x2 },
757 { CR_RX_THRESHOLD, 0x000c0640 },
760 dev_dbg_f(zd_chip_dev(chip), "\n");
761 ZD_ASSERT(mutex_is_locked(&chip->mutex));
762 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
765 static int zd1211b_hw_init_hmac(struct zd_chip *chip)
767 static const struct zd_ioreq32 ioreqs[] = {
768 { CR_ZD1211B_RETRY_MAX, 0x02020202 },
769 { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f },
770 { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f },
771 { CR_ZD1211B_TX_PWR_CTL2, 0x003f001f },
772 { CR_ZD1211B_TX_PWR_CTL1, 0x001f000f },
773 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
774 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
775 { CR_ZD1211B_TXOP, 0x01800824 },
776 { CR_RX_THRESHOLD, 0x000c0eff, },
779 dev_dbg_f(zd_chip_dev(chip), "\n");
780 ZD_ASSERT(mutex_is_locked(&chip->mutex));
781 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
784 static int hw_init_hmac(struct zd_chip *chip)
787 static const struct zd_ioreq32 ioreqs[] = {
788 { CR_ACK_TIMEOUT_EXT, 0x20 },
789 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
790 { CR_SNIFFER_ON, 0 },
791 { CR_RX_FILTER, STA_RX_FILTER },
792 { CR_GROUP_HASH_P1, 0x00 },
793 { CR_GROUP_HASH_P2, 0x80000000 },
795 { CR_ADDA_PWR_DWN, 0x7f },
796 { CR_BCN_PLCP_CFG, 0x00f00401 },
797 { CR_PHY_DELAY, 0x00 },
798 { CR_ACK_TIMEOUT_EXT, 0x80 },
799 { CR_ADDA_PWR_DWN, 0x00 },
800 { CR_ACK_TIME_80211, 0x100 },
801 { CR_RX_PE_DELAY, 0x70 },
802 { CR_PS_CTRL, 0x10000000 },
803 { CR_RTS_CTS_RATE, 0x02030203 },
804 { CR_AFTER_PNP, 0x1 },
805 { CR_WEP_PROTECT, 0x114 },
806 { CR_IFS_VALUE, IFS_VALUE_DEFAULT },
809 ZD_ASSERT(mutex_is_locked(&chip->mutex));
810 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
814 return zd_chip_is_zd1211b(chip) ?
815 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
824 static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
827 static const zd_addr_t aw_pt_bi_addr[] =
828 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
831 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
832 ARRAY_SIZE(aw_pt_bi_addr));
834 memset(s, 0, sizeof(*s));
838 s->atim_wnd_period = values[0];
839 s->pre_tbtt = values[1];
840 s->beacon_interval = values[2];
844 static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
846 struct zd_ioreq32 reqs[3];
848 if (s->beacon_interval <= 5)
849 s->beacon_interval = 5;
850 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
851 s->pre_tbtt = s->beacon_interval - 1;
852 if (s->atim_wnd_period >= s->pre_tbtt)
853 s->atim_wnd_period = s->pre_tbtt - 1;
855 reqs[0].addr = CR_ATIM_WND_PERIOD;
856 reqs[0].value = s->atim_wnd_period;
857 reqs[1].addr = CR_PRE_TBTT;
858 reqs[1].value = s->pre_tbtt;
859 reqs[2].addr = CR_BCN_INTERVAL;
860 reqs[2].value = s->beacon_interval;
862 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
866 static int set_beacon_interval(struct zd_chip *chip, u32 interval)
871 ZD_ASSERT(mutex_is_locked(&chip->mutex));
872 r = get_aw_pt_bi(chip, &s);
875 s.beacon_interval = interval;
876 return set_aw_pt_bi(chip, &s);
879 int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
883 mutex_lock(&chip->mutex);
884 r = set_beacon_interval(chip, interval);
885 mutex_unlock(&chip->mutex);
889 static int hw_init(struct zd_chip *chip)
893 dev_dbg_f(zd_chip_dev(chip), "\n");
894 ZD_ASSERT(mutex_is_locked(&chip->mutex));
895 r = hw_reset_phy(chip);
899 r = hw_init_hmac(chip);
903 return set_beacon_interval(chip, 100);
906 static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset)
908 return (zd_addr_t)((u16)chip->fw_regs_base + offset);
912 static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
913 const char *addr_string)
918 r = zd_ioread32_locked(chip, &value, addr);
920 dev_dbg_f(zd_chip_dev(chip),
921 "error reading %s. Error number %d\n", addr_string, r);
925 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
926 addr_string, (unsigned int)value);
930 static int test_init(struct zd_chip *chip)
934 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
937 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
940 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
943 static void dump_fw_registers(struct zd_chip *chip)
945 const zd_addr_t addr[4] = {
946 fw_reg_addr(chip, FW_REG_FIRMWARE_VER),
947 fw_reg_addr(chip, FW_REG_USB_SPEED),
948 fw_reg_addr(chip, FW_REG_FIX_TX_RATE),
949 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
955 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
958 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
963 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
964 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
965 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
966 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
970 static int print_fw_version(struct zd_chip *chip)
975 r = zd_ioread16_locked(chip, &version,
976 fw_reg_addr(chip, FW_REG_FIRMWARE_VER));
980 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
984 static int set_mandatory_rates(struct zd_chip *chip, enum ieee80211_std std)
987 ZD_ASSERT(mutex_is_locked(&chip->mutex));
988 /* This sets the mandatory rates, which only depend from the standard
989 * that the device is supporting. Until further notice we should try
990 * to support 802.11g also for full speed USB.
994 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
997 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
998 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
1003 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1006 int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip,
1007 u8 rts_rate, int preamble)
1009 int rts_mod = ZD_RX_CCK;
1012 /* Modulation bit */
1013 if (ZD_MODULATION_TYPE(rts_rate) == ZD_OFDM)
1014 rts_mod = ZD_RX_OFDM;
1016 dev_dbg_f(zd_chip_dev(chip), "rts_rate=%x preamble=%x\n",
1017 rts_rate, preamble);
1019 value |= ZD_PURE_RATE(rts_rate) << RTSCTS_SH_RTS_RATE;
1020 value |= rts_mod << RTSCTS_SH_RTS_MOD_TYPE;
1021 value |= preamble << RTSCTS_SH_RTS_PMB_TYPE;
1022 value |= preamble << RTSCTS_SH_CTS_PMB_TYPE;
1024 /* We always send 11M self-CTS messages, like the vendor driver. */
1025 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_CTS_RATE;
1026 value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE;
1028 return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE);
1031 int zd_chip_enable_hwint(struct zd_chip *chip)
1035 mutex_lock(&chip->mutex);
1036 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1037 mutex_unlock(&chip->mutex);
1041 static int disable_hwint(struct zd_chip *chip)
1043 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1046 int zd_chip_disable_hwint(struct zd_chip *chip)
1050 mutex_lock(&chip->mutex);
1051 r = disable_hwint(chip);
1052 mutex_unlock(&chip->mutex);
1056 static int read_fw_regs_offset(struct zd_chip *chip)
1060 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1061 r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base,
1065 dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n",
1066 (u16)chip->fw_regs_base);
1071 /* Read mac address using pre-firmware interface */
1072 int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr)
1074 dev_dbg_f(zd_chip_dev(chip), "\n");
1075 return zd_usb_read_fw(&chip->usb, E2P_MAC_ADDR_P1, addr,
1079 int zd_chip_init_hw(struct zd_chip *chip)
1084 dev_dbg_f(zd_chip_dev(chip), "\n");
1086 mutex_lock(&chip->mutex);
1089 r = test_init(chip);
1093 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1097 r = read_fw_regs_offset(chip);
1101 /* GPI is always disabled, also in the other driver.
1103 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1106 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1109 /* Currently we support IEEE 802.11g for full and high speed USB.
1110 * It might be discussed, whether we should suppport pure b mode for
1113 r = set_mandatory_rates(chip, IEEE80211G);
1116 /* Disabling interrupts is certainly a smart thing here.
1118 r = disable_hwint(chip);
1121 r = read_pod(chip, &rf_type);
1127 r = zd_rf_init_hw(&chip->rf, rf_type);
1131 r = print_fw_version(chip);
1136 dump_fw_registers(chip);
1137 r = test_init(chip);
1142 r = read_cal_int_tables(chip);
1148 mutex_unlock(&chip->mutex);
1152 static int update_pwr_int(struct zd_chip *chip, u8 channel)
1154 u8 value = chip->pwr_int_values[channel - 1];
1155 return zd_iowrite16_locked(chip, value, CR31);
1158 static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1160 u8 value = chip->pwr_cal_values[channel-1];
1161 return zd_iowrite16_locked(chip, value, CR68);
1164 static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1166 struct zd_ioreq16 ioreqs[3];
1168 ioreqs[0].addr = CR67;
1169 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1170 ioreqs[1].addr = CR66;
1171 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1172 ioreqs[2].addr = CR65;
1173 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1175 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1178 static int update_channel_integration_and_calibration(struct zd_chip *chip,
1183 if (!zd_rf_should_update_pwr_int(&chip->rf))
1186 r = update_pwr_int(chip, channel);
1189 if (zd_chip_is_zd1211b(chip)) {
1190 static const struct zd_ioreq16 ioreqs[] = {
1196 r = update_ofdm_cal(chip, channel);
1199 r = update_pwr_cal(chip, channel);
1202 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1210 /* The CCK baseband gain can be optionally patched by the EEPROM */
1211 static int patch_cck_gain(struct zd_chip *chip)
1216 if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(&chip->rf))
1219 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1220 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1223 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
1224 return zd_iowrite16_locked(chip, value & 0xff, CR47);
1227 int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1231 mutex_lock(&chip->mutex);
1232 r = zd_chip_lock_phy_regs(chip);
1235 r = zd_rf_set_channel(&chip->rf, channel);
1238 r = update_channel_integration_and_calibration(chip, channel);
1241 r = patch_cck_gain(chip);
1244 r = patch_6m_band_edge(chip, channel);
1247 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1249 t = zd_chip_unlock_phy_regs(chip);
1253 mutex_unlock(&chip->mutex);
1257 u8 zd_chip_get_channel(struct zd_chip *chip)
1261 mutex_lock(&chip->mutex);
1262 channel = chip->rf.channel;
1263 mutex_unlock(&chip->mutex);
1267 int zd_chip_control_leds(struct zd_chip *chip, enum led_status status)
1269 const zd_addr_t a[] = {
1270 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
1275 u16 v[ARRAY_SIZE(a)];
1276 struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = {
1277 [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) },
1282 mutex_lock(&chip->mutex);
1283 r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a));
1287 other_led = chip->link_led == LED1 ? LED2 : LED1;
1291 ioreqs[0].value = FW_LINK_OFF;
1292 ioreqs[1].value = v[1] & ~(LED1|LED2);
1295 ioreqs[0].value = FW_LINK_OFF;
1296 ioreqs[1].value = v[1] & ~other_led;
1297 if (get_seconds() % 3 == 0) {
1298 ioreqs[1].value &= ~chip->link_led;
1300 ioreqs[1].value |= chip->link_led;
1303 case LED_ASSOCIATED:
1304 ioreqs[0].value = FW_LINK_TX;
1305 ioreqs[1].value = v[1] & ~other_led;
1306 ioreqs[1].value |= chip->link_led;
1313 if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) {
1314 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1320 mutex_unlock(&chip->mutex);
1324 int zd_chip_set_basic_rates_locked(struct zd_chip *chip, u16 cr_rates)
1326 ZD_ASSERT((cr_rates & ~(CR_RATES_80211B | CR_RATES_80211G)) == 0);
1327 dev_dbg_f(zd_chip_dev(chip), "%x\n", cr_rates);
1329 return zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1332 static int ofdm_qual_db(u8 status_quality, u8 zd_rate, unsigned int size)
1334 static const u16 constants[] = {
1335 715, 655, 585, 540, 470, 410, 360, 315,
1336 270, 235, 205, 175, 150, 125, 105, 85,
1343 /* It seems that their quality parameter is somehow per signal
1344 * and is now transferred per bit.
1347 case ZD_OFDM_RATE_6M:
1348 case ZD_OFDM_RATE_12M:
1349 case ZD_OFDM_RATE_24M:
1352 case ZD_OFDM_RATE_9M:
1353 case ZD_OFDM_RATE_18M:
1354 case ZD_OFDM_RATE_36M:
1355 case ZD_OFDM_RATE_54M:
1359 case ZD_OFDM_RATE_48M:
1367 x = (10000 * status_quality)/size;
1368 for (i = 0; i < ARRAY_SIZE(constants); i++) {
1369 if (x > constants[i])
1374 case ZD_OFDM_RATE_6M:
1375 case ZD_OFDM_RATE_9M:
1378 case ZD_OFDM_RATE_12M:
1379 case ZD_OFDM_RATE_18M:
1382 case ZD_OFDM_RATE_24M:
1383 case ZD_OFDM_RATE_36M:
1386 case ZD_OFDM_RATE_48M:
1387 case ZD_OFDM_RATE_54M:
1397 static int ofdm_qual_percent(u8 status_quality, u8 zd_rate, unsigned int size)
1401 r = ofdm_qual_db(status_quality, zd_rate, size);
1407 return r <= 100 ? r : 100;
1410 static unsigned int log10times100(unsigned int x)
1412 static const u8 log10[] = {
1414 0, 30, 47, 60, 69, 77, 84, 90, 95, 100,
1415 104, 107, 111, 114, 117, 120, 123, 125, 127, 130,
1416 132, 134, 136, 138, 139, 141, 143, 144, 146, 147,
1417 149, 150, 151, 153, 154, 155, 156, 157, 159, 160,
1418 161, 162, 163, 164, 165, 166, 167, 168, 169, 169,
1419 170, 171, 172, 173, 174, 174, 175, 176, 177, 177,
1420 178, 179, 179, 180, 181, 181, 182, 183, 183, 184,
1421 185, 185, 186, 186, 187, 188, 188, 189, 189, 190,
1422 190, 191, 191, 192, 192, 193, 193, 194, 194, 195,
1423 195, 196, 196, 197, 197, 198, 198, 199, 199, 200,
1424 200, 200, 201, 201, 202, 202, 202, 203, 203, 204,
1425 204, 204, 205, 205, 206, 206, 206, 207, 207, 207,
1426 208, 208, 208, 209, 209, 210, 210, 210, 211, 211,
1427 211, 212, 212, 212, 213, 213, 213, 213, 214, 214,
1428 214, 215, 215, 215, 216, 216, 216, 217, 217, 217,
1429 217, 218, 218, 218, 219, 219, 219, 219, 220, 220,
1430 220, 220, 221, 221, 221, 222, 222, 222, 222, 223,
1431 223, 223, 223, 224, 224, 224, 224,
1434 return x < ARRAY_SIZE(log10) ? log10[x] : 225;
1438 MAX_CCK_EVM_DB = 45,
1441 static int cck_evm_db(u8 status_quality)
1443 return (20 * log10times100(status_quality)) / 100;
1446 static int cck_snr_db(u8 status_quality)
1448 int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality);
1453 static int cck_qual_percent(u8 status_quality)
1457 r = cck_snr_db(status_quality);
1459 return r <= 100 ? r : 100;
1462 static inline u8 zd_rate_from_ofdm_plcp_header(const void *rx_frame)
1464 return ZD_OFDM | zd_ofdm_plcp_header_rate(rx_frame);
1467 u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size,
1468 const struct rx_status *status)
1470 return (status->frame_status&ZD_RX_OFDM) ?
1471 ofdm_qual_percent(status->signal_quality_ofdm,
1472 zd_rate_from_ofdm_plcp_header(rx_frame),
1474 cck_qual_percent(status->signal_quality_cck);
1477 u8 zd_rx_strength_percent(u8 rssi)
1479 int r = (rssi*100) / 41;
1485 u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1487 static const u16 ofdm_rates[] = {
1488 [ZD_OFDM_PLCP_RATE_6M] = 60,
1489 [ZD_OFDM_PLCP_RATE_9M] = 90,
1490 [ZD_OFDM_PLCP_RATE_12M] = 120,
1491 [ZD_OFDM_PLCP_RATE_18M] = 180,
1492 [ZD_OFDM_PLCP_RATE_24M] = 240,
1493 [ZD_OFDM_PLCP_RATE_36M] = 360,
1494 [ZD_OFDM_PLCP_RATE_48M] = 480,
1495 [ZD_OFDM_PLCP_RATE_54M] = 540,
1498 if (status->frame_status & ZD_RX_OFDM) {
1499 /* Deals with PLCP OFDM rate (not zd_rates) */
1500 u8 ofdm_rate = zd_ofdm_plcp_header_rate(rx_frame);
1501 rate = ofdm_rates[ofdm_rate & 0xf];
1503 switch (zd_cck_plcp_header_signal(rx_frame)) {
1504 case ZD_CCK_PLCP_SIGNAL_1M:
1507 case ZD_CCK_PLCP_SIGNAL_2M:
1510 case ZD_CCK_PLCP_SIGNAL_5M5:
1513 case ZD_CCK_PLCP_SIGNAL_11M:
1524 int zd_chip_switch_radio_on(struct zd_chip *chip)
1528 mutex_lock(&chip->mutex);
1529 r = zd_switch_radio_on(&chip->rf);
1530 mutex_unlock(&chip->mutex);
1534 int zd_chip_switch_radio_off(struct zd_chip *chip)
1538 mutex_lock(&chip->mutex);
1539 r = zd_switch_radio_off(&chip->rf);
1540 mutex_unlock(&chip->mutex);
1544 int zd_chip_enable_int(struct zd_chip *chip)
1548 mutex_lock(&chip->mutex);
1549 r = zd_usb_enable_int(&chip->usb);
1550 mutex_unlock(&chip->mutex);
1554 void zd_chip_disable_int(struct zd_chip *chip)
1556 mutex_lock(&chip->mutex);
1557 zd_usb_disable_int(&chip->usb);
1558 mutex_unlock(&chip->mutex);
1561 int zd_chip_enable_rx(struct zd_chip *chip)
1565 mutex_lock(&chip->mutex);
1566 r = zd_usb_enable_rx(&chip->usb);
1567 mutex_unlock(&chip->mutex);
1571 void zd_chip_disable_rx(struct zd_chip *chip)
1573 mutex_lock(&chip->mutex);
1574 zd_usb_disable_rx(&chip->usb);
1575 mutex_unlock(&chip->mutex);
1578 int zd_rfwritev_locked(struct zd_chip *chip,
1579 const u32* values, unsigned int count, u8 bits)
1584 for (i = 0; i < count; i++) {
1585 r = zd_rfwrite_locked(chip, values[i], bits);
1594 * We can optionally program the RF directly through CR regs, if supported by
1595 * the hardware. This is much faster than the older method.
1597 int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
1599 struct zd_ioreq16 ioreqs[] = {
1600 { CR244, (value >> 16) & 0xff },
1601 { CR243, (value >> 8) & 0xff },
1602 { CR242, value & 0xff },
1604 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1605 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1608 int zd_rfwritev_cr_locked(struct zd_chip *chip,
1609 const u32 *values, unsigned int count)
1614 for (i = 0; i < count; i++) {
1615 r = zd_rfwrite_cr_locked(chip, values[i]);
1623 int zd_chip_set_multicast_hash(struct zd_chip *chip,
1624 struct zd_mc_hash *hash)
1626 struct zd_ioreq32 ioreqs[] = {
1627 { CR_GROUP_HASH_P1, hash->low },
1628 { CR_GROUP_HASH_P2, hash->high },
1631 return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs));