2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
7 * Copyright(c) 2012 Intel Corporation. All rights reserved.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
15 * Copyright(c) 2012 Intel Corporation. All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copy
24 * notice, this list of conditions and the following disclaimer in
25 * the documentation and/or other materials provided with the
27 * * Neither the name of Intel Corporation nor the names of its
28 * contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 * Intel PCIe NTB Linux driver
45 * Contact Information:
46 * Jon Mason <jon.mason@intel.com>
48 #include <linux/debugfs.h>
49 #include <linux/delay.h>
50 #include <linux/init.h>
51 #include <linux/interrupt.h>
52 #include <linux/module.h>
53 #include <linux/pci.h>
54 #include <linux/random.h>
55 #include <linux/slab.h>
59 #define NTB_NAME "Intel(R) PCI-E Non-Transparent Bridge Driver"
60 #define NTB_VER "0.25"
62 MODULE_DESCRIPTION(NTB_NAME);
63 MODULE_VERSION(NTB_VER);
64 MODULE_LICENSE("Dual BSD/GPL");
65 MODULE_AUTHOR("Intel Corporation");
67 static bool xeon_errata_workaround = true;
68 module_param(xeon_errata_workaround, bool, 0644);
69 MODULE_PARM_DESC(xeon_errata_workaround, "Workaround for the Xeon Errata");
87 static struct dentry *debugfs_dir;
89 #define BWD_LINK_RECOVERY_TIME 500
91 /* Translate memory window 0,1 to BAR 2,4 */
92 #define MW_TO_BAR(mw) (mw * NTB_MAX_NUM_MW + 2)
94 static DEFINE_PCI_DEVICE_TABLE(ntb_pci_tbl) = {
95 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_BWD)},
96 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_JSF)},
97 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_SNB)},
98 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_IVT)},
99 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_HSX)},
100 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_JSF)},
101 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_SNB)},
102 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_IVT)},
103 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_HSX)},
104 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_JSF)},
105 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_SNB)},
106 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_IVT)},
107 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_HSX)},
110 MODULE_DEVICE_TABLE(pci, ntb_pci_tbl);
113 * ntb_register_event_callback() - register event callback
114 * @ndev: pointer to ntb_device instance
115 * @func: callback function to register
117 * This function registers a callback for any HW driver events such as link
118 * up/down, power management notices and etc.
120 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
122 int ntb_register_event_callback(struct ntb_device *ndev,
123 void (*func)(void *handle, enum ntb_hw_event event))
128 ndev->event_cb = func;
134 * ntb_unregister_event_callback() - unregisters the event callback
135 * @ndev: pointer to ntb_device instance
137 * This function unregisters the existing callback from transport
139 void ntb_unregister_event_callback(struct ntb_device *ndev)
141 ndev->event_cb = NULL;
145 * ntb_register_db_callback() - register a callback for doorbell interrupt
146 * @ndev: pointer to ntb_device instance
147 * @idx: doorbell index to register callback, zero based
148 * @func: callback function to register
150 * This function registers a callback function for the doorbell interrupt
151 * on the primary side. The function will unmask the doorbell as well to
154 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
156 int ntb_register_db_callback(struct ntb_device *ndev, unsigned int idx,
157 void *data, void (*func)(void *data, int db_num))
161 if (idx >= ndev->max_cbs || ndev->db_cb[idx].callback) {
162 dev_warn(&ndev->pdev->dev, "Invalid Index.\n");
166 ndev->db_cb[idx].callback = func;
167 ndev->db_cb[idx].data = data;
169 /* unmask interrupt */
170 mask = readw(ndev->reg_ofs.pdb_mask);
171 clear_bit(idx * ndev->bits_per_vector, &mask);
172 writew(mask, ndev->reg_ofs.pdb_mask);
178 * ntb_unregister_db_callback() - unregister a callback for doorbell interrupt
179 * @ndev: pointer to ntb_device instance
180 * @idx: doorbell index to register callback, zero based
182 * This function unregisters a callback function for the doorbell interrupt
183 * on the primary side. The function will also mask the said doorbell.
185 void ntb_unregister_db_callback(struct ntb_device *ndev, unsigned int idx)
189 if (idx >= ndev->max_cbs || !ndev->db_cb[idx].callback)
192 mask = readw(ndev->reg_ofs.pdb_mask);
193 set_bit(idx * ndev->bits_per_vector, &mask);
194 writew(mask, ndev->reg_ofs.pdb_mask);
196 ndev->db_cb[idx].callback = NULL;
200 * ntb_find_transport() - find the transport pointer
201 * @transport: pointer to pci device
203 * Given the pci device pointer, return the transport pointer passed in when
204 * the transport attached when it was inited.
206 * RETURNS: pointer to transport.
208 void *ntb_find_transport(struct pci_dev *pdev)
210 struct ntb_device *ndev = pci_get_drvdata(pdev);
211 return ndev->ntb_transport;
215 * ntb_register_transport() - Register NTB transport with NTB HW driver
216 * @transport: transport identifier
218 * This function allows a transport to reserve the hardware driver for
221 * RETURNS: pointer to ntb_device, NULL on error.
223 struct ntb_device *ntb_register_transport(struct pci_dev *pdev, void *transport)
225 struct ntb_device *ndev = pci_get_drvdata(pdev);
227 if (ndev->ntb_transport)
230 ndev->ntb_transport = transport;
235 * ntb_unregister_transport() - Unregister the transport with the NTB HW driver
236 * @ndev - ntb_device of the transport to be freed
238 * This function unregisters the transport from the HW driver and performs any
239 * necessary cleanups.
241 void ntb_unregister_transport(struct ntb_device *ndev)
245 if (!ndev->ntb_transport)
248 for (i = 0; i < ndev->max_cbs; i++)
249 ntb_unregister_db_callback(ndev, i);
251 ntb_unregister_event_callback(ndev);
252 ndev->ntb_transport = NULL;
256 * ntb_write_local_spad() - write to the secondary scratchpad register
257 * @ndev: pointer to ntb_device instance
258 * @idx: index to the scratchpad register, 0 based
259 * @val: the data value to put into the register
261 * This function allows writing of a 32bit value to the indexed scratchpad
262 * register. This writes over the data mirrored to the local scratchpad register
263 * by the remote system.
265 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
267 int ntb_write_local_spad(struct ntb_device *ndev, unsigned int idx, u32 val)
269 if (idx >= ndev->limits.max_spads)
272 dev_dbg(&ndev->pdev->dev, "Writing %x to local scratch pad index %d\n",
274 writel(val, ndev->reg_ofs.spad_read + idx * 4);
280 * ntb_read_local_spad() - read from the primary scratchpad register
281 * @ndev: pointer to ntb_device instance
282 * @idx: index to scratchpad register, 0 based
283 * @val: pointer to 32bit integer for storing the register value
285 * This function allows reading of the 32bit scratchpad register on
286 * the primary (internal) side. This allows the local system to read data
287 * written and mirrored to the scratchpad register by the remote system.
289 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
291 int ntb_read_local_spad(struct ntb_device *ndev, unsigned int idx, u32 *val)
293 if (idx >= ndev->limits.max_spads)
296 *val = readl(ndev->reg_ofs.spad_write + idx * 4);
297 dev_dbg(&ndev->pdev->dev,
298 "Reading %x from local scratch pad index %d\n", *val, idx);
304 * ntb_write_remote_spad() - write to the secondary scratchpad register
305 * @ndev: pointer to ntb_device instance
306 * @idx: index to the scratchpad register, 0 based
307 * @val: the data value to put into the register
309 * This function allows writing of a 32bit value to the indexed scratchpad
310 * register. The register resides on the secondary (external) side. This allows
311 * the local system to write data to be mirrored to the remote systems
312 * scratchpad register.
314 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
316 int ntb_write_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 val)
318 if (idx >= ndev->limits.max_spads)
321 dev_dbg(&ndev->pdev->dev, "Writing %x to remote scratch pad index %d\n",
323 writel(val, ndev->reg_ofs.spad_write + idx * 4);
329 * ntb_read_remote_spad() - read from the primary scratchpad register
330 * @ndev: pointer to ntb_device instance
331 * @idx: index to scratchpad register, 0 based
332 * @val: pointer to 32bit integer for storing the register value
334 * This function allows reading of the 32bit scratchpad register on
335 * the primary (internal) side. This alloows the local system to read the data
336 * it wrote to be mirrored on the remote system.
338 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
340 int ntb_read_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 *val)
342 if (idx >= ndev->limits.max_spads)
345 *val = readl(ndev->reg_ofs.spad_read + idx * 4);
346 dev_dbg(&ndev->pdev->dev,
347 "Reading %x from remote scratch pad index %d\n", *val, idx);
353 * ntb_get_mw_base() - get addr for the NTB memory window
354 * @ndev: pointer to ntb_device instance
355 * @mw: memory window number
357 * This function provides the base address of the memory window specified.
359 * RETURNS: address, or NULL on error.
361 resource_size_t ntb_get_mw_base(struct ntb_device *ndev, unsigned int mw)
363 if (mw >= ntb_max_mw(ndev))
366 return pci_resource_start(ndev->pdev, MW_TO_BAR(mw));
370 * ntb_get_mw_vbase() - get virtual addr for the NTB memory window
371 * @ndev: pointer to ntb_device instance
372 * @mw: memory window number
374 * This function provides the base virtual address of the memory window
377 * RETURNS: pointer to virtual address, or NULL on error.
379 void __iomem *ntb_get_mw_vbase(struct ntb_device *ndev, unsigned int mw)
381 if (mw >= ntb_max_mw(ndev))
384 return ndev->mw[mw].vbase;
388 * ntb_get_mw_size() - return size of NTB memory window
389 * @ndev: pointer to ntb_device instance
390 * @mw: memory window number
392 * This function provides the physical size of the memory window specified
394 * RETURNS: the size of the memory window or zero on error
396 u64 ntb_get_mw_size(struct ntb_device *ndev, unsigned int mw)
398 if (mw >= ntb_max_mw(ndev))
401 return ndev->mw[mw].bar_sz;
405 * ntb_set_mw_addr - set the memory window address
406 * @ndev: pointer to ntb_device instance
407 * @mw: memory window number
408 * @addr: base address for data
410 * This function sets the base physical address of the memory window. This
411 * memory address is where data from the remote system will be transfered into
412 * or out of depending on how the transport is configured.
414 void ntb_set_mw_addr(struct ntb_device *ndev, unsigned int mw, u64 addr)
416 if (mw >= ntb_max_mw(ndev))
419 dev_dbg(&ndev->pdev->dev, "Writing addr %Lx to BAR %d\n", addr,
422 ndev->mw[mw].phys_addr = addr;
424 switch (MW_TO_BAR(mw)) {
426 writeq(addr, ndev->reg_ofs.sbar2_xlat);
429 writeq(addr, ndev->reg_ofs.sbar4_xlat);
435 * ntb_ring_sdb() - Set the doorbell on the secondary/external side
436 * @ndev: pointer to ntb_device instance
437 * @db: doorbell to ring
439 * This function allows triggering of a doorbell on the secondary/external
440 * side that will initiate an interrupt on the remote host
442 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
444 void ntb_ring_sdb(struct ntb_device *ndev, unsigned int db)
446 dev_dbg(&ndev->pdev->dev, "%s: ringing doorbell %d\n", __func__, db);
448 if (ndev->hw_type == BWD_HW)
449 writeq((u64) 1 << db, ndev->reg_ofs.sdb);
451 writew(((1 << ndev->bits_per_vector) - 1) <<
452 (db * ndev->bits_per_vector), ndev->reg_ofs.sdb);
455 static void bwd_recover_link(struct ntb_device *ndev)
459 /* Driver resets the NTB ModPhy lanes - magic! */
460 writeb(0xe0, ndev->reg_base + BWD_MODPHY_PCSREG6);
461 writeb(0x40, ndev->reg_base + BWD_MODPHY_PCSREG4);
462 writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG4);
463 writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG6);
465 /* Driver waits 100ms to allow the NTB ModPhy to settle */
468 /* Clear AER Errors, write to clear */
469 status = readl(ndev->reg_base + BWD_ERRCORSTS_OFFSET);
470 dev_dbg(&ndev->pdev->dev, "ERRCORSTS = %x\n", status);
471 status &= PCI_ERR_COR_REP_ROLL;
472 writel(status, ndev->reg_base + BWD_ERRCORSTS_OFFSET);
474 /* Clear unexpected electrical idle event in LTSSM, write to clear */
475 status = readl(ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET);
476 dev_dbg(&ndev->pdev->dev, "LTSSMERRSTS0 = %x\n", status);
477 status |= BWD_LTSSMERRSTS0_UNEXPECTEDEI;
478 writel(status, ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET);
480 /* Clear DeSkew Buffer error, write to clear */
481 status = readl(ndev->reg_base + BWD_DESKEWSTS_OFFSET);
482 dev_dbg(&ndev->pdev->dev, "DESKEWSTS = %x\n", status);
483 status |= BWD_DESKEWSTS_DBERR;
484 writel(status, ndev->reg_base + BWD_DESKEWSTS_OFFSET);
486 status = readl(ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
487 dev_dbg(&ndev->pdev->dev, "IBSTERRRCRVSTS0 = %x\n", status);
488 status &= BWD_IBIST_ERR_OFLOW;
489 writel(status, ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
491 /* Releases the NTB state machine to allow the link to retrain */
492 status = readl(ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
493 dev_dbg(&ndev->pdev->dev, "LTSSMSTATEJMP = %x\n", status);
494 status &= ~BWD_LTSSMSTATEJMP_FORCEDETECT;
495 writel(status, ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
498 static void ntb_link_event(struct ntb_device *ndev, int link_state)
502 if (ndev->link_status == link_state)
505 if (link_state == NTB_LINK_UP) {
508 dev_info(&ndev->pdev->dev, "Link Up\n");
509 ndev->link_status = NTB_LINK_UP;
510 event = NTB_EVENT_HW_LINK_UP;
512 if (ndev->hw_type == BWD_HW)
513 status = readw(ndev->reg_ofs.lnk_stat);
515 int rc = pci_read_config_word(ndev->pdev,
516 SNB_LINK_STATUS_OFFSET,
522 ndev->link_width = (status & NTB_LINK_WIDTH_MASK) >> 4;
523 ndev->link_speed = (status & NTB_LINK_SPEED_MASK);
524 dev_info(&ndev->pdev->dev, "Link Width %d, Link Speed %d\n",
525 ndev->link_width, ndev->link_speed);
527 dev_info(&ndev->pdev->dev, "Link Down\n");
528 ndev->link_status = NTB_LINK_DOWN;
529 event = NTB_EVENT_HW_LINK_DOWN;
530 /* Don't modify link width/speed, we need it in link recovery */
533 /* notify the upper layer if we have an event change */
535 ndev->event_cb(ndev->ntb_transport, event);
538 static int ntb_link_status(struct ntb_device *ndev)
542 if (ndev->hw_type == BWD_HW) {
545 ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
546 if (ntb_cntl & BWD_CNTL_LINK_DOWN)
547 link_state = NTB_LINK_DOWN;
549 link_state = NTB_LINK_UP;
554 rc = pci_read_config_word(ndev->pdev, SNB_LINK_STATUS_OFFSET,
559 if (status & NTB_LINK_STATUS_ACTIVE)
560 link_state = NTB_LINK_UP;
562 link_state = NTB_LINK_DOWN;
565 ntb_link_event(ndev, link_state);
570 static void bwd_link_recovery(struct work_struct *work)
572 struct ntb_device *ndev = container_of(work, struct ntb_device,
576 bwd_recover_link(ndev);
577 /* There is a potential race between the 2 NTB devices recovering at the
578 * same time. If the times are the same, the link will not recover and
579 * the driver will be stuck in this loop forever. Add a random interval
580 * to the recovery time to prevent this race.
582 msleep(BWD_LINK_RECOVERY_TIME + prandom_u32() % BWD_LINK_RECOVERY_TIME);
584 status32 = readl(ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
585 if (status32 & BWD_LTSSMSTATEJMP_FORCEDETECT)
588 status32 = readl(ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
589 if (status32 & BWD_IBIST_ERR_OFLOW)
592 status32 = readl(ndev->reg_ofs.lnk_cntl);
593 if (!(status32 & BWD_CNTL_LINK_DOWN)) {
594 unsigned char speed, width;
597 status16 = readw(ndev->reg_ofs.lnk_stat);
598 width = (status16 & NTB_LINK_WIDTH_MASK) >> 4;
599 speed = (status16 & NTB_LINK_SPEED_MASK);
600 if (ndev->link_width != width || ndev->link_speed != speed)
604 schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
608 schedule_delayed_work(&ndev->lr_timer, NTB_HB_TIMEOUT);
611 /* BWD doesn't have link status interrupt, poll on that platform */
612 static void bwd_link_poll(struct work_struct *work)
614 struct ntb_device *ndev = container_of(work, struct ntb_device,
616 unsigned long ts = jiffies;
618 /* If we haven't gotten an interrupt in a while, check the BWD link
621 if (ts > ndev->last_ts + NTB_HB_TIMEOUT) {
622 int rc = ntb_link_status(ndev);
624 dev_err(&ndev->pdev->dev,
625 "Error determining link status\n");
627 /* Check to see if a link error is the cause of the link down */
628 if (ndev->link_status == NTB_LINK_DOWN) {
629 u32 status32 = readl(ndev->reg_base +
630 BWD_LTSSMSTATEJMP_OFFSET);
631 if (status32 & BWD_LTSSMSTATEJMP_FORCEDETECT) {
632 schedule_delayed_work(&ndev->lr_timer, 0);
638 schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
641 static int ntb_xeon_setup(struct ntb_device *ndev)
646 ndev->hw_type = SNB_HW;
648 rc = pci_read_config_byte(ndev->pdev, NTB_PPD_OFFSET, &val);
652 switch (val & SNB_PPD_CONN_TYPE) {
654 ndev->conn_type = NTB_CONN_B2B;
656 case NTB_CONN_CLASSIC:
659 dev_err(&ndev->pdev->dev, "Only B2B supported at this time\n");
663 if (val & SNB_PPD_DEV_TYPE)
664 ndev->dev_type = NTB_DEV_USD;
666 ndev->dev_type = NTB_DEV_DSD;
668 ndev->reg_ofs.pdb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
669 ndev->reg_ofs.pdb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET;
670 ndev->reg_ofs.sbar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
671 ndev->reg_ofs.sbar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
672 ndev->reg_ofs.lnk_cntl = ndev->reg_base + SNB_NTBCNTL_OFFSET;
673 ndev->reg_ofs.lnk_stat = ndev->reg_base + SNB_LINK_STATUS_OFFSET;
674 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
675 ndev->reg_ofs.spci_cmd = ndev->reg_base + SNB_PCICMD_OFFSET;
677 /* There is a Xeon hardware errata related to writes to
678 * SDOORBELL or B2BDOORBELL in conjunction with inbound access
679 * to NTB MMIO Space, which may hang the system. To workaround
680 * this use the second memory window to access the interrupt and
681 * scratch pad registers on the remote system.
683 if (xeon_errata_workaround) {
684 if (!ndev->mw[1].bar_sz)
687 ndev->limits.max_mw = SNB_ERRATA_MAX_MW;
688 ndev->reg_ofs.spad_write = ndev->mw[1].vbase +
690 ndev->reg_ofs.sdb = ndev->mw[1].vbase +
691 SNB_PDOORBELL_OFFSET;
693 /* Set the Limit register to 4k, the minimum size, to
694 * prevent an illegal access
696 writeq(ndev->mw[1].bar_sz + 0x1000, ndev->reg_base +
697 SNB_PBAR4LMT_OFFSET);
699 ndev->limits.max_mw = SNB_MAX_MW;
700 ndev->reg_ofs.spad_write = ndev->reg_base +
702 ndev->reg_ofs.sdb = ndev->reg_base +
703 SNB_B2B_DOORBELL_OFFSET;
705 /* Disable the Limit register, just incase it is set to
708 writeq(0, ndev->reg_base + SNB_PBAR4LMT_OFFSET);
711 /* The Xeon errata workaround requires setting SBAR Base
712 * addresses to known values, so that the PBAR XLAT can be
713 * pointed at SBAR0 of the remote system.
715 if (ndev->dev_type == NTB_DEV_USD) {
716 writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
717 SNB_PBAR2XLAT_OFFSET);
718 if (xeon_errata_workaround)
719 writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
720 SNB_PBAR4XLAT_OFFSET);
722 writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
723 SNB_PBAR4XLAT_OFFSET);
724 /* B2B_XLAT_OFFSET is a 64bit register, but can
725 * only take 32bit writes
727 writel(SNB_MBAR01_USD_ADDR & 0xffffffff,
728 ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
729 writel(SNB_MBAR01_DSD_ADDR >> 32,
730 ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
733 writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
734 SNB_SBAR0BASE_OFFSET);
735 writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
736 SNB_SBAR2BASE_OFFSET);
737 writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
738 SNB_SBAR4BASE_OFFSET);
740 writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
741 SNB_PBAR2XLAT_OFFSET);
742 if (xeon_errata_workaround)
743 writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
744 SNB_PBAR4XLAT_OFFSET);
746 writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
747 SNB_PBAR4XLAT_OFFSET);
748 /* B2B_XLAT_OFFSET is a 64bit register, but can
749 * only take 32bit writes
751 writel(SNB_MBAR01_USD_ADDR & 0xffffffff,
752 ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
753 writel(SNB_MBAR01_USD_ADDR >> 32,
754 ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
756 writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
757 SNB_SBAR0BASE_OFFSET);
758 writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
759 SNB_SBAR2BASE_OFFSET);
760 writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
761 SNB_SBAR4BASE_OFFSET);
764 ndev->limits.max_spads = SNB_MAX_B2B_SPADS;
765 ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
766 ndev->limits.msix_cnt = SNB_MSIX_CNT;
767 ndev->bits_per_vector = SNB_DB_BITS_PER_VEC;
772 static int ntb_bwd_setup(struct ntb_device *ndev)
777 ndev->hw_type = BWD_HW;
779 rc = pci_read_config_dword(ndev->pdev, NTB_PPD_OFFSET, &val);
783 switch ((val & BWD_PPD_CONN_TYPE) >> 8) {
785 ndev->conn_type = NTB_CONN_B2B;
789 dev_err(&ndev->pdev->dev, "Only B2B supported at this time\n");
793 if (val & BWD_PPD_DEV_TYPE)
794 ndev->dev_type = NTB_DEV_DSD;
796 ndev->dev_type = NTB_DEV_USD;
798 /* Initiate PCI-E link training */
799 rc = pci_write_config_dword(ndev->pdev, NTB_PPD_OFFSET,
800 val | BWD_PPD_INIT_LINK);
804 ndev->reg_ofs.pdb = ndev->reg_base + BWD_PDOORBELL_OFFSET;
805 ndev->reg_ofs.pdb_mask = ndev->reg_base + BWD_PDBMSK_OFFSET;
806 ndev->reg_ofs.sbar2_xlat = ndev->reg_base + BWD_SBAR2XLAT_OFFSET;
807 ndev->reg_ofs.sbar4_xlat = ndev->reg_base + BWD_SBAR4XLAT_OFFSET;
808 ndev->reg_ofs.lnk_cntl = ndev->reg_base + BWD_NTBCNTL_OFFSET;
809 ndev->reg_ofs.lnk_stat = ndev->reg_base + BWD_LINK_STATUS_OFFSET;
810 ndev->reg_ofs.spad_read = ndev->reg_base + BWD_SPAD_OFFSET;
811 ndev->reg_ofs.spci_cmd = ndev->reg_base + BWD_PCICMD_OFFSET;
813 if (ndev->conn_type == NTB_CONN_B2B) {
814 ndev->reg_ofs.sdb = ndev->reg_base + BWD_B2B_DOORBELL_OFFSET;
815 ndev->reg_ofs.spad_write = ndev->reg_base + BWD_B2B_SPAD_OFFSET;
816 ndev->limits.max_spads = BWD_MAX_SPADS;
818 ndev->reg_ofs.sdb = ndev->reg_base + BWD_PDOORBELL_OFFSET;
819 ndev->reg_ofs.spad_write = ndev->reg_base + BWD_SPAD_OFFSET;
820 ndev->limits.max_spads = BWD_MAX_COMPAT_SPADS;
823 ndev->limits.max_mw = BWD_MAX_MW;
824 ndev->limits.max_db_bits = BWD_MAX_DB_BITS;
825 ndev->limits.msix_cnt = BWD_MSIX_CNT;
826 ndev->bits_per_vector = BWD_DB_BITS_PER_VEC;
828 /* Since bwd doesn't have a link interrupt, setup a poll timer */
829 INIT_DELAYED_WORK(&ndev->hb_timer, bwd_link_poll);
830 INIT_DELAYED_WORK(&ndev->lr_timer, bwd_link_recovery);
831 schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
836 static int ntb_device_setup(struct ntb_device *ndev)
840 switch (ndev->pdev->device) {
841 case PCI_DEVICE_ID_INTEL_NTB_SS_JSF:
842 case PCI_DEVICE_ID_INTEL_NTB_SS_SNB:
843 case PCI_DEVICE_ID_INTEL_NTB_SS_IVT:
844 case PCI_DEVICE_ID_INTEL_NTB_SS_HSX:
845 case PCI_DEVICE_ID_INTEL_NTB_PS_JSF:
846 case PCI_DEVICE_ID_INTEL_NTB_PS_SNB:
847 case PCI_DEVICE_ID_INTEL_NTB_PS_IVT:
848 case PCI_DEVICE_ID_INTEL_NTB_PS_HSX:
849 case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF:
850 case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB:
851 case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT:
852 case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX:
853 rc = ntb_xeon_setup(ndev);
855 case PCI_DEVICE_ID_INTEL_NTB_B2B_BWD:
856 rc = ntb_bwd_setup(ndev);
865 dev_info(&ndev->pdev->dev, "Device Type = %s\n",
866 ndev->dev_type == NTB_DEV_USD ? "USD/DSP" : "DSD/USP");
868 /* Enable Bus Master and Memory Space on the secondary side */
869 writew(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, ndev->reg_ofs.spci_cmd);
874 static void ntb_device_free(struct ntb_device *ndev)
876 if (ndev->hw_type == BWD_HW) {
877 cancel_delayed_work_sync(&ndev->hb_timer);
878 cancel_delayed_work_sync(&ndev->lr_timer);
882 static irqreturn_t bwd_callback_msix_irq(int irq, void *data)
884 struct ntb_db_cb *db_cb = data;
885 struct ntb_device *ndev = db_cb->ndev;
887 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq,
891 db_cb->callback(db_cb->data, db_cb->db_num);
893 /* No need to check for the specific HB irq, any interrupt means
896 ndev->last_ts = jiffies;
898 writeq((u64) 1 << db_cb->db_num, ndev->reg_ofs.pdb);
903 static irqreturn_t xeon_callback_msix_irq(int irq, void *data)
905 struct ntb_db_cb *db_cb = data;
906 struct ntb_device *ndev = db_cb->ndev;
908 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq,
912 db_cb->callback(db_cb->data, db_cb->db_num);
914 /* On Sandybridge, there are 16 bits in the interrupt register
915 * but only 4 vectors. So, 5 bits are assigned to the first 3
916 * vectors, with the 4th having a single bit for link
919 writew(((1 << ndev->bits_per_vector) - 1) <<
920 (db_cb->db_num * ndev->bits_per_vector), ndev->reg_ofs.pdb);
925 /* Since we do not have a HW doorbell in BWD, this is only used in JF/JT */
926 static irqreturn_t xeon_event_msix_irq(int irq, void *dev)
928 struct ntb_device *ndev = dev;
931 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for Events\n", irq);
933 rc = ntb_link_status(ndev);
935 dev_err(&ndev->pdev->dev, "Error determining link status\n");
937 /* bit 15 is always the link bit */
938 writew(1 << ndev->limits.max_db_bits, ndev->reg_ofs.pdb);
943 static irqreturn_t ntb_interrupt(int irq, void *dev)
945 struct ntb_device *ndev = dev;
948 if (ndev->hw_type == BWD_HW) {
949 u64 pdb = readq(ndev->reg_ofs.pdb);
951 dev_dbg(&ndev->pdev->dev, "irq %d - pdb = %Lx\n", irq, pdb);
956 bwd_callback_msix_irq(irq, &ndev->db_cb[i]);
959 u16 pdb = readw(ndev->reg_ofs.pdb);
961 dev_dbg(&ndev->pdev->dev, "irq %d - pdb = %x sdb %x\n", irq,
962 pdb, readw(ndev->reg_ofs.sdb));
964 if (pdb & SNB_DB_HW_LINK) {
965 xeon_event_msix_irq(irq, dev);
966 pdb &= ~SNB_DB_HW_LINK;
972 xeon_callback_msix_irq(irq, &ndev->db_cb[i]);
979 static int ntb_setup_msix(struct ntb_device *ndev)
981 struct pci_dev *pdev = ndev->pdev;
982 struct msix_entry *msix;
987 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
993 rc = pci_read_config_word(pdev, pos + PCI_MSIX_FLAGS, &val);
997 msix_entries = msix_table_size(val);
998 if (msix_entries > ndev->limits.msix_cnt) {
1003 ndev->msix_entries = kmalloc(sizeof(struct msix_entry) * msix_entries,
1005 if (!ndev->msix_entries) {
1010 for (i = 0; i < msix_entries; i++)
1011 ndev->msix_entries[i].entry = i;
1013 rc = pci_enable_msix(pdev, ndev->msix_entries, msix_entries);
1017 /* On SNB, the link interrupt is always tied to 4th vector. If
1018 * we can't get all 4, then we can't use MSI-X.
1020 if (ndev->hw_type != BWD_HW) {
1025 dev_warn(&pdev->dev,
1026 "Only %d MSI-X vectors. Limiting the number of queues to that number.\n",
1031 for (i = 0; i < msix_entries; i++) {
1032 msix = &ndev->msix_entries[i];
1033 WARN_ON(!msix->vector);
1035 /* Use the last MSI-X vector for Link status */
1036 if (ndev->hw_type == BWD_HW) {
1037 rc = request_irq(msix->vector, bwd_callback_msix_irq, 0,
1038 "ntb-callback-msix", &ndev->db_cb[i]);
1042 if (i == msix_entries - 1) {
1043 rc = request_irq(msix->vector,
1044 xeon_event_msix_irq, 0,
1045 "ntb-event-msix", ndev);
1049 rc = request_irq(msix->vector,
1050 xeon_callback_msix_irq, 0,
1051 "ntb-callback-msix",
1059 ndev->num_msix = msix_entries;
1060 if (ndev->hw_type == BWD_HW)
1061 ndev->max_cbs = msix_entries;
1063 ndev->max_cbs = msix_entries - 1;
1069 msix = &ndev->msix_entries[i];
1070 if (ndev->hw_type != BWD_HW && i == ndev->num_msix - 1)
1071 free_irq(msix->vector, ndev);
1073 free_irq(msix->vector, &ndev->db_cb[i]);
1075 pci_disable_msix(pdev);
1077 kfree(ndev->msix_entries);
1078 dev_err(&pdev->dev, "Error allocating MSI-X interrupt\n");
1084 static int ntb_setup_msi(struct ntb_device *ndev)
1086 struct pci_dev *pdev = ndev->pdev;
1089 rc = pci_enable_msi(pdev);
1093 rc = request_irq(pdev->irq, ntb_interrupt, 0, "ntb-msi", ndev);
1095 pci_disable_msi(pdev);
1096 dev_err(&pdev->dev, "Error allocating MSI interrupt\n");
1103 static int ntb_setup_intx(struct ntb_device *ndev)
1105 struct pci_dev *pdev = ndev->pdev;
1110 /* Verify intx is enabled */
1113 rc = request_irq(pdev->irq, ntb_interrupt, IRQF_SHARED, "ntb-intx",
1121 static int ntb_setup_interrupts(struct ntb_device *ndev)
1125 /* On BWD, disable all interrupts. On SNB, disable all but Link
1126 * Interrupt. The rest will be unmasked as callbacks are registered.
1128 if (ndev->hw_type == BWD_HW)
1129 writeq(~0, ndev->reg_ofs.pdb_mask);
1131 writew(~(1 << ndev->limits.max_db_bits),
1132 ndev->reg_ofs.pdb_mask);
1134 rc = ntb_setup_msix(ndev);
1138 ndev->bits_per_vector = 1;
1139 ndev->max_cbs = ndev->limits.max_db_bits;
1141 rc = ntb_setup_msi(ndev);
1145 rc = ntb_setup_intx(ndev);
1147 dev_err(&ndev->pdev->dev, "no usable interrupts\n");
1155 static void ntb_free_interrupts(struct ntb_device *ndev)
1157 struct pci_dev *pdev = ndev->pdev;
1159 /* mask interrupts */
1160 if (ndev->hw_type == BWD_HW)
1161 writeq(~0, ndev->reg_ofs.pdb_mask);
1163 writew(~0, ndev->reg_ofs.pdb_mask);
1165 if (ndev->num_msix) {
1166 struct msix_entry *msix;
1169 for (i = 0; i < ndev->num_msix; i++) {
1170 msix = &ndev->msix_entries[i];
1171 if (ndev->hw_type != BWD_HW && i == ndev->num_msix - 1)
1172 free_irq(msix->vector, ndev);
1174 free_irq(msix->vector, &ndev->db_cb[i]);
1176 pci_disable_msix(pdev);
1178 free_irq(pdev->irq, ndev);
1180 if (pci_dev_msi_enabled(pdev))
1181 pci_disable_msi(pdev);
1185 static int ntb_create_callbacks(struct ntb_device *ndev)
1189 /* Checken-egg issue. We won't know how many callbacks are necessary
1190 * until we see how many MSI-X vectors we get, but these pointers need
1191 * to be passed into the MSI-X register fucntion. So, we allocate the
1192 * max, knowing that they might not all be used, to work around this.
1194 ndev->db_cb = kcalloc(ndev->limits.max_db_bits,
1195 sizeof(struct ntb_db_cb),
1200 for (i = 0; i < ndev->limits.max_db_bits; i++) {
1201 ndev->db_cb[i].db_num = i;
1202 ndev->db_cb[i].ndev = ndev;
1208 static void ntb_free_callbacks(struct ntb_device *ndev)
1212 for (i = 0; i < ndev->limits.max_db_bits; i++)
1213 ntb_unregister_db_callback(ndev, i);
1218 static void ntb_setup_debugfs(struct ntb_device *ndev)
1220 if (!debugfs_initialized())
1224 debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL);
1226 ndev->debugfs_dir = debugfs_create_dir(pci_name(ndev->pdev),
1230 static void ntb_free_debugfs(struct ntb_device *ndev)
1232 debugfs_remove_recursive(ndev->debugfs_dir);
1234 if (debugfs_dir && simple_empty(debugfs_dir)) {
1235 debugfs_remove_recursive(debugfs_dir);
1240 static int ntb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1242 struct ntb_device *ndev;
1245 ndev = kzalloc(sizeof(struct ntb_device), GFP_KERNEL);
1250 ndev->link_status = NTB_LINK_DOWN;
1251 pci_set_drvdata(pdev, ndev);
1252 ntb_setup_debugfs(ndev);
1254 rc = pci_enable_device(pdev);
1258 pci_set_master(ndev->pdev);
1260 rc = pci_request_selected_regions(pdev, NTB_BAR_MASK, KBUILD_MODNAME);
1264 ndev->reg_base = pci_ioremap_bar(pdev, NTB_BAR_MMIO);
1265 if (!ndev->reg_base) {
1266 dev_warn(&pdev->dev, "Cannot remap BAR 0\n");
1271 for (i = 0; i < NTB_MAX_NUM_MW; i++) {
1272 ndev->mw[i].bar_sz = pci_resource_len(pdev, MW_TO_BAR(i));
1274 ioremap_wc(pci_resource_start(pdev, MW_TO_BAR(i)),
1275 ndev->mw[i].bar_sz);
1276 dev_info(&pdev->dev, "MW %d size %llu\n", i,
1277 (unsigned long long) ndev->mw[i].bar_sz);
1278 if (!ndev->mw[i].vbase) {
1279 dev_warn(&pdev->dev, "Cannot remap BAR %d\n",
1286 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1288 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1292 dev_warn(&pdev->dev, "Cannot DMA highmem\n");
1295 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1297 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1301 dev_warn(&pdev->dev, "Cannot DMA consistent highmem\n");
1304 rc = ntb_device_setup(ndev);
1308 rc = ntb_create_callbacks(ndev);
1312 rc = ntb_setup_interrupts(ndev);
1316 /* The scratchpad registers keep the values between rmmod/insmod,
1319 for (i = 0; i < ndev->limits.max_spads; i++) {
1320 ntb_write_local_spad(ndev, i, 0);
1321 ntb_write_remote_spad(ndev, i, 0);
1324 rc = ntb_transport_init(pdev);
1328 /* Let's bring the NTB link up */
1329 writel(NTB_CNTL_BAR23_SNOOP | NTB_CNTL_BAR45_SNOOP,
1330 ndev->reg_ofs.lnk_cntl);
1335 ntb_free_interrupts(ndev);
1337 ntb_free_callbacks(ndev);
1339 ntb_device_free(ndev);
1341 for (i--; i >= 0; i--)
1342 iounmap(ndev->mw[i].vbase);
1343 iounmap(ndev->reg_base);
1345 pci_release_selected_regions(pdev, NTB_BAR_MASK);
1347 pci_disable_device(pdev);
1349 ntb_free_debugfs(ndev);
1352 dev_err(&pdev->dev, "Error loading %s module\n", KBUILD_MODNAME);
1356 static void ntb_pci_remove(struct pci_dev *pdev)
1358 struct ntb_device *ndev = pci_get_drvdata(pdev);
1362 /* Bring NTB link down */
1363 ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
1364 ntb_cntl |= NTB_LINK_DISABLE;
1365 writel(ntb_cntl, ndev->reg_ofs.lnk_cntl);
1367 ntb_transport_free(ndev->ntb_transport);
1369 ntb_free_interrupts(ndev);
1370 ntb_free_callbacks(ndev);
1371 ntb_device_free(ndev);
1373 for (i = 0; i < NTB_MAX_NUM_MW; i++)
1374 iounmap(ndev->mw[i].vbase);
1376 iounmap(ndev->reg_base);
1377 pci_release_selected_regions(pdev, NTB_BAR_MASK);
1378 pci_disable_device(pdev);
1379 ntb_free_debugfs(ndev);
1383 static struct pci_driver ntb_pci_driver = {
1384 .name = KBUILD_MODNAME,
1385 .id_table = ntb_pci_tbl,
1386 .probe = ntb_pci_probe,
1387 .remove = ntb_pci_remove,
1389 module_pci_driver(ntb_pci_driver);