2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
7 * Copyright(c) 2012 Intel Corporation. All rights reserved.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
15 * Copyright(c) 2012 Intel Corporation. All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copy
24 * notice, this list of conditions and the following disclaimer in
25 * the documentation and/or other materials provided with the
27 * * Neither the name of Intel Corporation nor the names of its
28 * contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 * Intel PCIe NTB Linux driver
45 * Contact Information:
46 * Jon Mason <jon.mason@intel.com>
48 #include <linux/debugfs.h>
49 #include <linux/delay.h>
50 #include <linux/init.h>
51 #include <linux/interrupt.h>
52 #include <linux/module.h>
53 #include <linux/pci.h>
54 #include <linux/random.h>
55 #include <linux/slab.h>
59 #define NTB_NAME "Intel(R) PCI-E Non-Transparent Bridge Driver"
60 #define NTB_VER "0.25"
62 MODULE_DESCRIPTION(NTB_NAME);
63 MODULE_VERSION(NTB_VER);
64 MODULE_LICENSE("Dual BSD/GPL");
65 MODULE_AUTHOR("Intel Corporation");
67 static bool xeon_errata_workaround = true;
68 module_param(xeon_errata_workaround, bool, 0644);
69 MODULE_PARM_DESC(xeon_errata_workaround, "Workaround for the Xeon Errata");
72 NTB_CONN_TRANSPARENT = 0,
87 static struct dentry *debugfs_dir;
89 #define BWD_LINK_RECOVERY_TIME 500
91 /* Translate memory window 0,1 to BAR 2,4 */
92 #define MW_TO_BAR(mw) (mw * NTB_MAX_NUM_MW + 2)
94 static DEFINE_PCI_DEVICE_TABLE(ntb_pci_tbl) = {
95 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_BWD)},
96 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_JSF)},
97 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_SNB)},
98 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_IVT)},
99 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_HSX)},
100 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_JSF)},
101 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_SNB)},
102 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_IVT)},
103 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_HSX)},
104 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_JSF)},
105 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_SNB)},
106 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_IVT)},
107 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_HSX)},
110 MODULE_DEVICE_TABLE(pci, ntb_pci_tbl);
113 * ntb_register_event_callback() - register event callback
114 * @ndev: pointer to ntb_device instance
115 * @func: callback function to register
117 * This function registers a callback for any HW driver events such as link
118 * up/down, power management notices and etc.
120 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
122 int ntb_register_event_callback(struct ntb_device *ndev,
123 void (*func)(void *handle, enum ntb_hw_event event))
128 ndev->event_cb = func;
134 * ntb_unregister_event_callback() - unregisters the event callback
135 * @ndev: pointer to ntb_device instance
137 * This function unregisters the existing callback from transport
139 void ntb_unregister_event_callback(struct ntb_device *ndev)
141 ndev->event_cb = NULL;
145 * ntb_register_db_callback() - register a callback for doorbell interrupt
146 * @ndev: pointer to ntb_device instance
147 * @idx: doorbell index to register callback, zero based
148 * @func: callback function to register
150 * This function registers a callback function for the doorbell interrupt
151 * on the primary side. The function will unmask the doorbell as well to
154 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
156 int ntb_register_db_callback(struct ntb_device *ndev, unsigned int idx,
157 void *data, void (*func)(void *data, int db_num))
161 if (idx >= ndev->max_cbs || ndev->db_cb[idx].callback) {
162 dev_warn(&ndev->pdev->dev, "Invalid Index.\n");
166 ndev->db_cb[idx].callback = func;
167 ndev->db_cb[idx].data = data;
169 /* unmask interrupt */
170 mask = readw(ndev->reg_ofs.ldb_mask);
171 clear_bit(idx * ndev->bits_per_vector, &mask);
172 writew(mask, ndev->reg_ofs.ldb_mask);
178 * ntb_unregister_db_callback() - unregister a callback for doorbell interrupt
179 * @ndev: pointer to ntb_device instance
180 * @idx: doorbell index to register callback, zero based
182 * This function unregisters a callback function for the doorbell interrupt
183 * on the primary side. The function will also mask the said doorbell.
185 void ntb_unregister_db_callback(struct ntb_device *ndev, unsigned int idx)
189 if (idx >= ndev->max_cbs || !ndev->db_cb[idx].callback)
192 mask = readw(ndev->reg_ofs.ldb_mask);
193 set_bit(idx * ndev->bits_per_vector, &mask);
194 writew(mask, ndev->reg_ofs.ldb_mask);
196 ndev->db_cb[idx].callback = NULL;
200 * ntb_find_transport() - find the transport pointer
201 * @transport: pointer to pci device
203 * Given the pci device pointer, return the transport pointer passed in when
204 * the transport attached when it was inited.
206 * RETURNS: pointer to transport.
208 void *ntb_find_transport(struct pci_dev *pdev)
210 struct ntb_device *ndev = pci_get_drvdata(pdev);
211 return ndev->ntb_transport;
215 * ntb_register_transport() - Register NTB transport with NTB HW driver
216 * @transport: transport identifier
218 * This function allows a transport to reserve the hardware driver for
221 * RETURNS: pointer to ntb_device, NULL on error.
223 struct ntb_device *ntb_register_transport(struct pci_dev *pdev, void *transport)
225 struct ntb_device *ndev = pci_get_drvdata(pdev);
227 if (ndev->ntb_transport)
230 ndev->ntb_transport = transport;
235 * ntb_unregister_transport() - Unregister the transport with the NTB HW driver
236 * @ndev - ntb_device of the transport to be freed
238 * This function unregisters the transport from the HW driver and performs any
239 * necessary cleanups.
241 void ntb_unregister_transport(struct ntb_device *ndev)
245 if (!ndev->ntb_transport)
248 for (i = 0; i < ndev->max_cbs; i++)
249 ntb_unregister_db_callback(ndev, i);
251 ntb_unregister_event_callback(ndev);
252 ndev->ntb_transport = NULL;
256 * ntb_write_local_spad() - write to the secondary scratchpad register
257 * @ndev: pointer to ntb_device instance
258 * @idx: index to the scratchpad register, 0 based
259 * @val: the data value to put into the register
261 * This function allows writing of a 32bit value to the indexed scratchpad
262 * register. This writes over the data mirrored to the local scratchpad register
263 * by the remote system.
265 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
267 int ntb_write_local_spad(struct ntb_device *ndev, unsigned int idx, u32 val)
269 if (idx >= ndev->limits.max_spads)
272 dev_dbg(&ndev->pdev->dev, "Writing %x to local scratch pad index %d\n",
274 writel(val, ndev->reg_ofs.spad_read + idx * 4);
280 * ntb_read_local_spad() - read from the primary scratchpad register
281 * @ndev: pointer to ntb_device instance
282 * @idx: index to scratchpad register, 0 based
283 * @val: pointer to 32bit integer for storing the register value
285 * This function allows reading of the 32bit scratchpad register on
286 * the primary (internal) side. This allows the local system to read data
287 * written and mirrored to the scratchpad register by the remote system.
289 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
291 int ntb_read_local_spad(struct ntb_device *ndev, unsigned int idx, u32 *val)
293 if (idx >= ndev->limits.max_spads)
296 *val = readl(ndev->reg_ofs.spad_write + idx * 4);
297 dev_dbg(&ndev->pdev->dev,
298 "Reading %x from local scratch pad index %d\n", *val, idx);
304 * ntb_write_remote_spad() - write to the secondary scratchpad register
305 * @ndev: pointer to ntb_device instance
306 * @idx: index to the scratchpad register, 0 based
307 * @val: the data value to put into the register
309 * This function allows writing of a 32bit value to the indexed scratchpad
310 * register. The register resides on the secondary (external) side. This allows
311 * the local system to write data to be mirrored to the remote systems
312 * scratchpad register.
314 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
316 int ntb_write_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 val)
318 if (idx >= ndev->limits.max_spads)
321 dev_dbg(&ndev->pdev->dev, "Writing %x to remote scratch pad index %d\n",
323 writel(val, ndev->reg_ofs.spad_write + idx * 4);
329 * ntb_read_remote_spad() - read from the primary scratchpad register
330 * @ndev: pointer to ntb_device instance
331 * @idx: index to scratchpad register, 0 based
332 * @val: pointer to 32bit integer for storing the register value
334 * This function allows reading of the 32bit scratchpad register on
335 * the primary (internal) side. This alloows the local system to read the data
336 * it wrote to be mirrored on the remote system.
338 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
340 int ntb_read_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 *val)
342 if (idx >= ndev->limits.max_spads)
345 *val = readl(ndev->reg_ofs.spad_read + idx * 4);
346 dev_dbg(&ndev->pdev->dev,
347 "Reading %x from remote scratch pad index %d\n", *val, idx);
353 * ntb_get_mw_base() - get addr for the NTB memory window
354 * @ndev: pointer to ntb_device instance
355 * @mw: memory window number
357 * This function provides the base address of the memory window specified.
359 * RETURNS: address, or NULL on error.
361 resource_size_t ntb_get_mw_base(struct ntb_device *ndev, unsigned int mw)
363 if (mw >= ntb_max_mw(ndev))
366 return pci_resource_start(ndev->pdev, MW_TO_BAR(mw));
370 * ntb_get_mw_vbase() - get virtual addr for the NTB memory window
371 * @ndev: pointer to ntb_device instance
372 * @mw: memory window number
374 * This function provides the base virtual address of the memory window
377 * RETURNS: pointer to virtual address, or NULL on error.
379 void __iomem *ntb_get_mw_vbase(struct ntb_device *ndev, unsigned int mw)
381 if (mw >= ntb_max_mw(ndev))
384 return ndev->mw[mw].vbase;
388 * ntb_get_mw_size() - return size of NTB memory window
389 * @ndev: pointer to ntb_device instance
390 * @mw: memory window number
392 * This function provides the physical size of the memory window specified
394 * RETURNS: the size of the memory window or zero on error
396 u64 ntb_get_mw_size(struct ntb_device *ndev, unsigned int mw)
398 if (mw >= ntb_max_mw(ndev))
401 return ndev->mw[mw].bar_sz;
405 * ntb_set_mw_addr - set the memory window address
406 * @ndev: pointer to ntb_device instance
407 * @mw: memory window number
408 * @addr: base address for data
410 * This function sets the base physical address of the memory window. This
411 * memory address is where data from the remote system will be transfered into
412 * or out of depending on how the transport is configured.
414 void ntb_set_mw_addr(struct ntb_device *ndev, unsigned int mw, u64 addr)
416 if (mw >= ntb_max_mw(ndev))
419 dev_dbg(&ndev->pdev->dev, "Writing addr %Lx to BAR %d\n", addr,
422 ndev->mw[mw].phys_addr = addr;
424 switch (MW_TO_BAR(mw)) {
426 writeq(addr, ndev->reg_ofs.bar2_xlat);
429 writeq(addr, ndev->reg_ofs.bar4_xlat);
435 * ntb_ring_doorbell() - Set the doorbell on the secondary/external side
436 * @ndev: pointer to ntb_device instance
437 * @db: doorbell to ring
439 * This function allows triggering of a doorbell on the secondary/external
440 * side that will initiate an interrupt on the remote host
442 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
444 void ntb_ring_doorbell(struct ntb_device *ndev, unsigned int db)
446 dev_dbg(&ndev->pdev->dev, "%s: ringing doorbell %d\n", __func__, db);
448 if (ndev->hw_type == BWD_HW)
449 writeq((u64) 1 << db, ndev->reg_ofs.rdb);
451 writew(((1 << ndev->bits_per_vector) - 1) <<
452 (db * ndev->bits_per_vector), ndev->reg_ofs.rdb);
455 static void bwd_recover_link(struct ntb_device *ndev)
459 /* Driver resets the NTB ModPhy lanes - magic! */
460 writeb(0xe0, ndev->reg_base + BWD_MODPHY_PCSREG6);
461 writeb(0x40, ndev->reg_base + BWD_MODPHY_PCSREG4);
462 writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG4);
463 writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG6);
465 /* Driver waits 100ms to allow the NTB ModPhy to settle */
468 /* Clear AER Errors, write to clear */
469 status = readl(ndev->reg_base + BWD_ERRCORSTS_OFFSET);
470 dev_dbg(&ndev->pdev->dev, "ERRCORSTS = %x\n", status);
471 status &= PCI_ERR_COR_REP_ROLL;
472 writel(status, ndev->reg_base + BWD_ERRCORSTS_OFFSET);
474 /* Clear unexpected electrical idle event in LTSSM, write to clear */
475 status = readl(ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET);
476 dev_dbg(&ndev->pdev->dev, "LTSSMERRSTS0 = %x\n", status);
477 status |= BWD_LTSSMERRSTS0_UNEXPECTEDEI;
478 writel(status, ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET);
480 /* Clear DeSkew Buffer error, write to clear */
481 status = readl(ndev->reg_base + BWD_DESKEWSTS_OFFSET);
482 dev_dbg(&ndev->pdev->dev, "DESKEWSTS = %x\n", status);
483 status |= BWD_DESKEWSTS_DBERR;
484 writel(status, ndev->reg_base + BWD_DESKEWSTS_OFFSET);
486 status = readl(ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
487 dev_dbg(&ndev->pdev->dev, "IBSTERRRCRVSTS0 = %x\n", status);
488 status &= BWD_IBIST_ERR_OFLOW;
489 writel(status, ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
491 /* Releases the NTB state machine to allow the link to retrain */
492 status = readl(ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
493 dev_dbg(&ndev->pdev->dev, "LTSSMSTATEJMP = %x\n", status);
494 status &= ~BWD_LTSSMSTATEJMP_FORCEDETECT;
495 writel(status, ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
498 static void ntb_link_event(struct ntb_device *ndev, int link_state)
502 if (ndev->link_status == link_state)
505 if (link_state == NTB_LINK_UP) {
508 dev_info(&ndev->pdev->dev, "Link Up\n");
509 ndev->link_status = NTB_LINK_UP;
510 event = NTB_EVENT_HW_LINK_UP;
512 if (ndev->hw_type == BWD_HW ||
513 ndev->conn_type == NTB_CONN_TRANSPARENT)
514 status = readw(ndev->reg_ofs.lnk_stat);
516 int rc = pci_read_config_word(ndev->pdev,
517 SNB_LINK_STATUS_OFFSET,
523 ndev->link_width = (status & NTB_LINK_WIDTH_MASK) >> 4;
524 ndev->link_speed = (status & NTB_LINK_SPEED_MASK);
525 dev_info(&ndev->pdev->dev, "Link Width %d, Link Speed %d\n",
526 ndev->link_width, ndev->link_speed);
528 dev_info(&ndev->pdev->dev, "Link Down\n");
529 ndev->link_status = NTB_LINK_DOWN;
530 event = NTB_EVENT_HW_LINK_DOWN;
531 /* Don't modify link width/speed, we need it in link recovery */
534 /* notify the upper layer if we have an event change */
536 ndev->event_cb(ndev->ntb_transport, event);
539 static int ntb_link_status(struct ntb_device *ndev)
543 if (ndev->hw_type == BWD_HW) {
546 ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
547 if (ntb_cntl & BWD_CNTL_LINK_DOWN)
548 link_state = NTB_LINK_DOWN;
550 link_state = NTB_LINK_UP;
555 rc = pci_read_config_word(ndev->pdev, SNB_LINK_STATUS_OFFSET,
560 if (status & NTB_LINK_STATUS_ACTIVE)
561 link_state = NTB_LINK_UP;
563 link_state = NTB_LINK_DOWN;
566 ntb_link_event(ndev, link_state);
571 static void bwd_link_recovery(struct work_struct *work)
573 struct ntb_device *ndev = container_of(work, struct ntb_device,
577 bwd_recover_link(ndev);
578 /* There is a potential race between the 2 NTB devices recovering at the
579 * same time. If the times are the same, the link will not recover and
580 * the driver will be stuck in this loop forever. Add a random interval
581 * to the recovery time to prevent this race.
583 msleep(BWD_LINK_RECOVERY_TIME + prandom_u32() % BWD_LINK_RECOVERY_TIME);
585 status32 = readl(ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
586 if (status32 & BWD_LTSSMSTATEJMP_FORCEDETECT)
589 status32 = readl(ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
590 if (status32 & BWD_IBIST_ERR_OFLOW)
593 status32 = readl(ndev->reg_ofs.lnk_cntl);
594 if (!(status32 & BWD_CNTL_LINK_DOWN)) {
595 unsigned char speed, width;
598 status16 = readw(ndev->reg_ofs.lnk_stat);
599 width = (status16 & NTB_LINK_WIDTH_MASK) >> 4;
600 speed = (status16 & NTB_LINK_SPEED_MASK);
601 if (ndev->link_width != width || ndev->link_speed != speed)
605 schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
609 schedule_delayed_work(&ndev->lr_timer, NTB_HB_TIMEOUT);
612 /* BWD doesn't have link status interrupt, poll on that platform */
613 static void bwd_link_poll(struct work_struct *work)
615 struct ntb_device *ndev = container_of(work, struct ntb_device,
617 unsigned long ts = jiffies;
619 /* If we haven't gotten an interrupt in a while, check the BWD link
622 if (ts > ndev->last_ts + NTB_HB_TIMEOUT) {
623 int rc = ntb_link_status(ndev);
625 dev_err(&ndev->pdev->dev,
626 "Error determining link status\n");
628 /* Check to see if a link error is the cause of the link down */
629 if (ndev->link_status == NTB_LINK_DOWN) {
630 u32 status32 = readl(ndev->reg_base +
631 BWD_LTSSMSTATEJMP_OFFSET);
632 if (status32 & BWD_LTSSMSTATEJMP_FORCEDETECT) {
633 schedule_delayed_work(&ndev->lr_timer, 0);
639 schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
642 static int ntb_xeon_setup(struct ntb_device *ndev)
647 ndev->hw_type = SNB_HW;
649 rc = pci_read_config_byte(ndev->pdev, NTB_PPD_OFFSET, &val);
653 if (val & SNB_PPD_DEV_TYPE)
654 ndev->dev_type = NTB_DEV_USD;
656 ndev->dev_type = NTB_DEV_DSD;
658 switch (val & SNB_PPD_CONN_TYPE) {
660 dev_info(&ndev->pdev->dev, "Conn Type = B2B\n");
661 ndev->conn_type = NTB_CONN_B2B;
662 ndev->reg_ofs.ldb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
663 ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET;
664 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
665 ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
666 ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
667 ndev->limits.max_spads = SNB_MAX_B2B_SPADS;
669 /* There is a Xeon hardware errata related to writes to
670 * SDOORBELL or B2BDOORBELL in conjunction with inbound access
671 * to NTB MMIO Space, which may hang the system. To workaround
672 * this use the second memory window to access the interrupt and
673 * scratch pad registers on the remote system.
675 if (xeon_errata_workaround) {
676 if (!ndev->mw[1].bar_sz)
679 ndev->limits.max_mw = SNB_ERRATA_MAX_MW;
680 ndev->reg_ofs.spad_write = ndev->mw[1].vbase +
682 ndev->reg_ofs.rdb = ndev->mw[1].vbase +
683 SNB_PDOORBELL_OFFSET;
685 /* Set the Limit register to 4k, the minimum size, to
686 * prevent an illegal access
688 writeq(ndev->mw[1].bar_sz + 0x1000, ndev->reg_base +
689 SNB_PBAR4LMT_OFFSET);
691 ndev->limits.max_mw = SNB_MAX_MW;
692 ndev->reg_ofs.spad_write = ndev->reg_base +
694 ndev->reg_ofs.rdb = ndev->reg_base +
695 SNB_B2B_DOORBELL_OFFSET;
697 /* Disable the Limit register, just incase it is set to
700 writeq(0, ndev->reg_base + SNB_PBAR4LMT_OFFSET);
703 /* The Xeon errata workaround requires setting SBAR Base
704 * addresses to known values, so that the PBAR XLAT can be
705 * pointed at SBAR0 of the remote system.
707 if (ndev->dev_type == NTB_DEV_USD) {
708 writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
709 SNB_PBAR2XLAT_OFFSET);
710 if (xeon_errata_workaround)
711 writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
712 SNB_PBAR4XLAT_OFFSET);
714 writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
715 SNB_PBAR4XLAT_OFFSET);
716 /* B2B_XLAT_OFFSET is a 64bit register, but can
717 * only take 32bit writes
719 writel(SNB_MBAR01_DSD_ADDR & 0xffffffff,
720 ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
721 writel(SNB_MBAR01_DSD_ADDR >> 32,
722 ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
725 writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
726 SNB_SBAR0BASE_OFFSET);
727 writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
728 SNB_SBAR2BASE_OFFSET);
729 writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
730 SNB_SBAR4BASE_OFFSET);
732 writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
733 SNB_PBAR2XLAT_OFFSET);
734 if (xeon_errata_workaround)
735 writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
736 SNB_PBAR4XLAT_OFFSET);
738 writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
739 SNB_PBAR4XLAT_OFFSET);
740 /* B2B_XLAT_OFFSET is a 64bit register, but can
741 * only take 32bit writes
743 writel(SNB_MBAR01_DSD_ADDR & 0xffffffff,
744 ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
745 writel(SNB_MBAR01_USD_ADDR >> 32,
746 ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
748 writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
749 SNB_SBAR0BASE_OFFSET);
750 writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
751 SNB_SBAR2BASE_OFFSET);
752 writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
753 SNB_SBAR4BASE_OFFSET);
757 dev_info(&ndev->pdev->dev, "Conn Type = RP\n");
758 ndev->conn_type = NTB_CONN_RP;
760 if (xeon_errata_workaround) {
761 dev_err(&ndev->pdev->dev,
762 "NTB-RP disabled due to hardware errata. To disregard this warning and potentially lock-up the system, add the parameter 'xeon_errata_workaround=0'.\n");
766 /* Scratch pads need to have exclusive access from the primary
767 * or secondary side. Halve the num spads so that each side can
768 * have an equal amount.
770 ndev->limits.max_spads = SNB_MAX_COMPAT_SPADS / 2;
771 /* Note: The SDOORBELL is the cause of the errata. You REALLY
772 * don't want to touch it.
774 ndev->reg_ofs.rdb = ndev->reg_base + SNB_SDOORBELL_OFFSET;
775 ndev->reg_ofs.ldb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
776 ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET;
777 /* Offset the start of the spads to correspond to whether it is
778 * primary or secondary
780 ndev->reg_ofs.spad_write = ndev->reg_base + SNB_SPAD_OFFSET +
781 ndev->limits.max_spads * 4;
782 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
783 ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
784 ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
785 ndev->limits.max_mw = SNB_MAX_MW;
787 case NTB_CONN_TRANSPARENT:
788 dev_info(&ndev->pdev->dev, "Conn Type = TRANSPARENT\n");
789 ndev->conn_type = NTB_CONN_TRANSPARENT;
790 /* Scratch pads need to have exclusive access from the primary
791 * or secondary side. Halve the num spads so that each side can
792 * have an equal amount.
794 ndev->limits.max_spads = SNB_MAX_COMPAT_SPADS / 2;
795 ndev->reg_ofs.rdb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
796 ndev->reg_ofs.ldb = ndev->reg_base + SNB_SDOORBELL_OFFSET;
797 ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_SDBMSK_OFFSET;
798 ndev->reg_ofs.spad_write = ndev->reg_base + SNB_SPAD_OFFSET;
799 /* Offset the start of the spads to correspond to whether it is
800 * primary or secondary
802 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET +
803 ndev->limits.max_spads * 4;
804 ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_PBAR2XLAT_OFFSET;
805 ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_PBAR4XLAT_OFFSET;
807 ndev->limits.max_mw = SNB_MAX_MW;
810 /* Most likely caused by the remote NTB-RP device not being
813 dev_err(&ndev->pdev->dev, "Unknown PPD %x\n", val);
817 ndev->reg_ofs.lnk_cntl = ndev->reg_base + SNB_NTBCNTL_OFFSET;
818 ndev->reg_ofs.lnk_stat = ndev->reg_base + SNB_SLINK_STATUS_OFFSET;
819 ndev->reg_ofs.spci_cmd = ndev->reg_base + SNB_PCICMD_OFFSET;
821 ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
822 ndev->limits.msix_cnt = SNB_MSIX_CNT;
823 ndev->bits_per_vector = SNB_DB_BITS_PER_VEC;
828 static int ntb_bwd_setup(struct ntb_device *ndev)
833 ndev->hw_type = BWD_HW;
835 rc = pci_read_config_dword(ndev->pdev, NTB_PPD_OFFSET, &val);
839 switch ((val & BWD_PPD_CONN_TYPE) >> 8) {
841 ndev->conn_type = NTB_CONN_B2B;
845 dev_err(&ndev->pdev->dev, "Only B2B supported at this time\n");
849 if (val & BWD_PPD_DEV_TYPE)
850 ndev->dev_type = NTB_DEV_DSD;
852 ndev->dev_type = NTB_DEV_USD;
854 /* Initiate PCI-E link training */
855 rc = pci_write_config_dword(ndev->pdev, NTB_PPD_OFFSET,
856 val | BWD_PPD_INIT_LINK);
860 ndev->reg_ofs.ldb = ndev->reg_base + BWD_PDOORBELL_OFFSET;
861 ndev->reg_ofs.ldb_mask = ndev->reg_base + BWD_PDBMSK_OFFSET;
862 ndev->reg_ofs.bar2_xlat = ndev->reg_base + BWD_SBAR2XLAT_OFFSET;
863 ndev->reg_ofs.bar4_xlat = ndev->reg_base + BWD_SBAR4XLAT_OFFSET;
864 ndev->reg_ofs.lnk_cntl = ndev->reg_base + BWD_NTBCNTL_OFFSET;
865 ndev->reg_ofs.lnk_stat = ndev->reg_base + BWD_LINK_STATUS_OFFSET;
866 ndev->reg_ofs.spad_read = ndev->reg_base + BWD_SPAD_OFFSET;
867 ndev->reg_ofs.spci_cmd = ndev->reg_base + BWD_PCICMD_OFFSET;
869 if (ndev->conn_type == NTB_CONN_B2B) {
870 ndev->reg_ofs.rdb = ndev->reg_base + BWD_B2B_DOORBELL_OFFSET;
871 ndev->reg_ofs.spad_write = ndev->reg_base + BWD_B2B_SPAD_OFFSET;
872 ndev->limits.max_spads = BWD_MAX_SPADS;
874 ndev->reg_ofs.rdb = ndev->reg_base + BWD_PDOORBELL_OFFSET;
875 ndev->reg_ofs.spad_write = ndev->reg_base + BWD_SPAD_OFFSET;
876 ndev->limits.max_spads = BWD_MAX_COMPAT_SPADS;
879 ndev->limits.max_mw = BWD_MAX_MW;
880 ndev->limits.max_db_bits = BWD_MAX_DB_BITS;
881 ndev->limits.msix_cnt = BWD_MSIX_CNT;
882 ndev->bits_per_vector = BWD_DB_BITS_PER_VEC;
884 /* Since bwd doesn't have a link interrupt, setup a poll timer */
885 INIT_DELAYED_WORK(&ndev->hb_timer, bwd_link_poll);
886 INIT_DELAYED_WORK(&ndev->lr_timer, bwd_link_recovery);
887 schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
892 static int ntb_device_setup(struct ntb_device *ndev)
896 switch (ndev->pdev->device) {
897 case PCI_DEVICE_ID_INTEL_NTB_SS_JSF:
898 case PCI_DEVICE_ID_INTEL_NTB_SS_SNB:
899 case PCI_DEVICE_ID_INTEL_NTB_SS_IVT:
900 case PCI_DEVICE_ID_INTEL_NTB_SS_HSX:
901 case PCI_DEVICE_ID_INTEL_NTB_PS_JSF:
902 case PCI_DEVICE_ID_INTEL_NTB_PS_SNB:
903 case PCI_DEVICE_ID_INTEL_NTB_PS_IVT:
904 case PCI_DEVICE_ID_INTEL_NTB_PS_HSX:
905 case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF:
906 case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB:
907 case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT:
908 case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX:
909 rc = ntb_xeon_setup(ndev);
911 case PCI_DEVICE_ID_INTEL_NTB_B2B_BWD:
912 rc = ntb_bwd_setup(ndev);
921 dev_info(&ndev->pdev->dev, "Device Type = %s\n",
922 ndev->dev_type == NTB_DEV_USD ? "USD/DSP" : "DSD/USP");
924 if (ndev->conn_type == NTB_CONN_B2B)
925 /* Enable Bus Master and Memory Space on the secondary side */
926 writew(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
927 ndev->reg_ofs.spci_cmd);
932 static void ntb_device_free(struct ntb_device *ndev)
934 if (ndev->hw_type == BWD_HW) {
935 cancel_delayed_work_sync(&ndev->hb_timer);
936 cancel_delayed_work_sync(&ndev->lr_timer);
940 static irqreturn_t bwd_callback_msix_irq(int irq, void *data)
942 struct ntb_db_cb *db_cb = data;
943 struct ntb_device *ndev = db_cb->ndev;
945 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq,
949 db_cb->callback(db_cb->data, db_cb->db_num);
951 /* No need to check for the specific HB irq, any interrupt means
954 ndev->last_ts = jiffies;
956 writeq((u64) 1 << db_cb->db_num, ndev->reg_ofs.ldb);
961 static irqreturn_t xeon_callback_msix_irq(int irq, void *data)
963 struct ntb_db_cb *db_cb = data;
964 struct ntb_device *ndev = db_cb->ndev;
966 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq,
970 db_cb->callback(db_cb->data, db_cb->db_num);
972 /* On Sandybridge, there are 16 bits in the interrupt register
973 * but only 4 vectors. So, 5 bits are assigned to the first 3
974 * vectors, with the 4th having a single bit for link
977 writew(((1 << ndev->bits_per_vector) - 1) <<
978 (db_cb->db_num * ndev->bits_per_vector), ndev->reg_ofs.ldb);
983 /* Since we do not have a HW doorbell in BWD, this is only used in JF/JT */
984 static irqreturn_t xeon_event_msix_irq(int irq, void *dev)
986 struct ntb_device *ndev = dev;
989 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for Events\n", irq);
991 rc = ntb_link_status(ndev);
993 dev_err(&ndev->pdev->dev, "Error determining link status\n");
995 /* bit 15 is always the link bit */
996 writew(1 << ndev->limits.max_db_bits, ndev->reg_ofs.ldb);
1001 static irqreturn_t ntb_interrupt(int irq, void *dev)
1003 struct ntb_device *ndev = dev;
1006 if (ndev->hw_type == BWD_HW) {
1007 u64 ldb = readq(ndev->reg_ofs.ldb);
1009 dev_dbg(&ndev->pdev->dev, "irq %d - ldb = %Lx\n", irq, ldb);
1014 bwd_callback_msix_irq(irq, &ndev->db_cb[i]);
1017 u16 ldb = readw(ndev->reg_ofs.ldb);
1019 dev_dbg(&ndev->pdev->dev, "irq %d - ldb = %x\n", irq, ldb);
1021 if (ldb & SNB_DB_HW_LINK) {
1022 xeon_event_msix_irq(irq, dev);
1023 ldb &= ~SNB_DB_HW_LINK;
1029 xeon_callback_msix_irq(irq, &ndev->db_cb[i]);
1036 static int ntb_setup_msix(struct ntb_device *ndev)
1038 struct pci_dev *pdev = ndev->pdev;
1039 struct msix_entry *msix;
1044 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
1050 rc = pci_read_config_word(pdev, pos + PCI_MSIX_FLAGS, &val);
1054 msix_entries = msix_table_size(val);
1055 if (msix_entries > ndev->limits.msix_cnt) {
1060 ndev->msix_entries = kmalloc(sizeof(struct msix_entry) * msix_entries,
1062 if (!ndev->msix_entries) {
1067 for (i = 0; i < msix_entries; i++)
1068 ndev->msix_entries[i].entry = i;
1070 rc = pci_enable_msix(pdev, ndev->msix_entries, msix_entries);
1074 /* On SNB, the link interrupt is always tied to 4th vector. If
1075 * we can't get all 4, then we can't use MSI-X.
1077 if (ndev->hw_type != BWD_HW) {
1082 dev_warn(&pdev->dev,
1083 "Only %d MSI-X vectors. Limiting the number of queues to that number.\n",
1088 for (i = 0; i < msix_entries; i++) {
1089 msix = &ndev->msix_entries[i];
1090 WARN_ON(!msix->vector);
1092 /* Use the last MSI-X vector for Link status */
1093 if (ndev->hw_type == BWD_HW) {
1094 rc = request_irq(msix->vector, bwd_callback_msix_irq, 0,
1095 "ntb-callback-msix", &ndev->db_cb[i]);
1099 if (i == msix_entries - 1) {
1100 rc = request_irq(msix->vector,
1101 xeon_event_msix_irq, 0,
1102 "ntb-event-msix", ndev);
1106 rc = request_irq(msix->vector,
1107 xeon_callback_msix_irq, 0,
1108 "ntb-callback-msix",
1116 ndev->num_msix = msix_entries;
1117 if (ndev->hw_type == BWD_HW)
1118 ndev->max_cbs = msix_entries;
1120 ndev->max_cbs = msix_entries - 1;
1126 msix = &ndev->msix_entries[i];
1127 if (ndev->hw_type != BWD_HW && i == ndev->num_msix - 1)
1128 free_irq(msix->vector, ndev);
1130 free_irq(msix->vector, &ndev->db_cb[i]);
1132 pci_disable_msix(pdev);
1134 kfree(ndev->msix_entries);
1135 dev_err(&pdev->dev, "Error allocating MSI-X interrupt\n");
1141 static int ntb_setup_msi(struct ntb_device *ndev)
1143 struct pci_dev *pdev = ndev->pdev;
1146 rc = pci_enable_msi(pdev);
1150 rc = request_irq(pdev->irq, ntb_interrupt, 0, "ntb-msi", ndev);
1152 pci_disable_msi(pdev);
1153 dev_err(&pdev->dev, "Error allocating MSI interrupt\n");
1160 static int ntb_setup_intx(struct ntb_device *ndev)
1162 struct pci_dev *pdev = ndev->pdev;
1167 /* Verify intx is enabled */
1170 rc = request_irq(pdev->irq, ntb_interrupt, IRQF_SHARED, "ntb-intx",
1178 static int ntb_setup_interrupts(struct ntb_device *ndev)
1182 /* On BWD, disable all interrupts. On SNB, disable all but Link
1183 * Interrupt. The rest will be unmasked as callbacks are registered.
1185 if (ndev->hw_type == BWD_HW)
1186 writeq(~0, ndev->reg_ofs.ldb_mask);
1188 writew(~(1 << ndev->limits.max_db_bits),
1189 ndev->reg_ofs.ldb_mask);
1191 rc = ntb_setup_msix(ndev);
1195 ndev->bits_per_vector = 1;
1196 ndev->max_cbs = ndev->limits.max_db_bits;
1198 rc = ntb_setup_msi(ndev);
1202 rc = ntb_setup_intx(ndev);
1204 dev_err(&ndev->pdev->dev, "no usable interrupts\n");
1212 static void ntb_free_interrupts(struct ntb_device *ndev)
1214 struct pci_dev *pdev = ndev->pdev;
1216 /* mask interrupts */
1217 if (ndev->hw_type == BWD_HW)
1218 writeq(~0, ndev->reg_ofs.ldb_mask);
1220 writew(~0, ndev->reg_ofs.ldb_mask);
1222 if (ndev->num_msix) {
1223 struct msix_entry *msix;
1226 for (i = 0; i < ndev->num_msix; i++) {
1227 msix = &ndev->msix_entries[i];
1228 if (ndev->hw_type != BWD_HW && i == ndev->num_msix - 1)
1229 free_irq(msix->vector, ndev);
1231 free_irq(msix->vector, &ndev->db_cb[i]);
1233 pci_disable_msix(pdev);
1235 free_irq(pdev->irq, ndev);
1237 if (pci_dev_msi_enabled(pdev))
1238 pci_disable_msi(pdev);
1242 static int ntb_create_callbacks(struct ntb_device *ndev)
1246 /* Checken-egg issue. We won't know how many callbacks are necessary
1247 * until we see how many MSI-X vectors we get, but these pointers need
1248 * to be passed into the MSI-X register fucntion. So, we allocate the
1249 * max, knowing that they might not all be used, to work around this.
1251 ndev->db_cb = kcalloc(ndev->limits.max_db_bits,
1252 sizeof(struct ntb_db_cb),
1257 for (i = 0; i < ndev->limits.max_db_bits; i++) {
1258 ndev->db_cb[i].db_num = i;
1259 ndev->db_cb[i].ndev = ndev;
1265 static void ntb_free_callbacks(struct ntb_device *ndev)
1269 for (i = 0; i < ndev->limits.max_db_bits; i++)
1270 ntb_unregister_db_callback(ndev, i);
1275 static void ntb_setup_debugfs(struct ntb_device *ndev)
1277 if (!debugfs_initialized())
1281 debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL);
1283 ndev->debugfs_dir = debugfs_create_dir(pci_name(ndev->pdev),
1287 static void ntb_free_debugfs(struct ntb_device *ndev)
1289 debugfs_remove_recursive(ndev->debugfs_dir);
1291 if (debugfs_dir && simple_empty(debugfs_dir)) {
1292 debugfs_remove_recursive(debugfs_dir);
1297 static int ntb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1299 struct ntb_device *ndev;
1302 ndev = kzalloc(sizeof(struct ntb_device), GFP_KERNEL);
1307 ndev->link_status = NTB_LINK_DOWN;
1308 pci_set_drvdata(pdev, ndev);
1309 ntb_setup_debugfs(ndev);
1311 rc = pci_enable_device(pdev);
1315 pci_set_master(ndev->pdev);
1317 rc = pci_request_selected_regions(pdev, NTB_BAR_MASK, KBUILD_MODNAME);
1321 ndev->reg_base = pci_ioremap_bar(pdev, NTB_BAR_MMIO);
1322 if (!ndev->reg_base) {
1323 dev_warn(&pdev->dev, "Cannot remap BAR 0\n");
1328 for (i = 0; i < NTB_MAX_NUM_MW; i++) {
1329 ndev->mw[i].bar_sz = pci_resource_len(pdev, MW_TO_BAR(i));
1331 ioremap_wc(pci_resource_start(pdev, MW_TO_BAR(i)),
1332 ndev->mw[i].bar_sz);
1333 dev_info(&pdev->dev, "MW %d size %llu\n", i,
1334 (unsigned long long) ndev->mw[i].bar_sz);
1335 if (!ndev->mw[i].vbase) {
1336 dev_warn(&pdev->dev, "Cannot remap BAR %d\n",
1343 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1345 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1349 dev_warn(&pdev->dev, "Cannot DMA highmem\n");
1352 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1354 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1358 dev_warn(&pdev->dev, "Cannot DMA consistent highmem\n");
1361 rc = ntb_device_setup(ndev);
1365 rc = ntb_create_callbacks(ndev);
1369 rc = ntb_setup_interrupts(ndev);
1373 /* The scratchpad registers keep the values between rmmod/insmod,
1376 for (i = 0; i < ndev->limits.max_spads; i++) {
1377 ntb_write_local_spad(ndev, i, 0);
1378 ntb_write_remote_spad(ndev, i, 0);
1381 rc = ntb_transport_init(pdev);
1385 /* Let's bring the NTB link up */
1386 writel(NTB_CNTL_BAR23_SNOOP | NTB_CNTL_BAR45_SNOOP,
1387 ndev->reg_ofs.lnk_cntl);
1392 ntb_free_interrupts(ndev);
1394 ntb_free_callbacks(ndev);
1396 ntb_device_free(ndev);
1398 for (i--; i >= 0; i--)
1399 iounmap(ndev->mw[i].vbase);
1400 iounmap(ndev->reg_base);
1402 pci_release_selected_regions(pdev, NTB_BAR_MASK);
1404 pci_disable_device(pdev);
1406 ntb_free_debugfs(ndev);
1409 dev_err(&pdev->dev, "Error loading %s module\n", KBUILD_MODNAME);
1413 static void ntb_pci_remove(struct pci_dev *pdev)
1415 struct ntb_device *ndev = pci_get_drvdata(pdev);
1419 /* Bring NTB link down */
1420 ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
1421 ntb_cntl |= NTB_CNTL_LINK_DISABLE;
1422 writel(ntb_cntl, ndev->reg_ofs.lnk_cntl);
1424 ntb_transport_free(ndev->ntb_transport);
1426 ntb_free_interrupts(ndev);
1427 ntb_free_callbacks(ndev);
1428 ntb_device_free(ndev);
1430 for (i = 0; i < NTB_MAX_NUM_MW; i++)
1431 iounmap(ndev->mw[i].vbase);
1433 iounmap(ndev->reg_base);
1434 pci_release_selected_regions(pdev, NTB_BAR_MASK);
1435 pci_disable_device(pdev);
1436 ntb_free_debugfs(ndev);
1440 static struct pci_driver ntb_pci_driver = {
1441 .name = KBUILD_MODNAME,
1442 .id_table = ntb_pci_tbl,
1443 .probe = ntb_pci_probe,
1444 .remove = ntb_pci_remove,
1446 module_pci_driver(ntb_pci_driver);