drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/cpu.h>
  20 #include <linux/delay.h>
  21 #include <linux/errno.h>
  22 #include <linux/fs.h>
  23 #include <linux/genhd.h>
  24 #include <linux/hdreg.h>
  25 #include <linux/idr.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/kdev_t.h>
  30 #include <linux/kthread.h>
  31 #include <linux/kernel.h>
  32 #include <linux/mm.h>
  33 #include <linux/module.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/mutex.h>
  36 #include <linux/pci.h>
  37 #include <linux/poison.h>
  38 #include <linux/ptrace.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/t10-pi.h>
  42 #include <linux/types.h>
  43 #include <linux/io-64-nonatomic-lo-hi.h>
  44 #include <asm/unaligned.h>
  45
  46 #include "nvme.h"
  47
  48 #define NVME_Q_DEPTH            1024
  49 #define NVME_AQ_DEPTH           256
  50 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  51 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  52
  53 /*
  54  * We handle AEN commands ourselves and don't even let the
  55  * block layer know about them.
  56  */
  57 #define NVME_NR_AEN_COMMANDS    1
  58 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
  59
  60 unsigned char admin_timeout = 60;
  61 module_param(admin_timeout, byte, 0644);
  62 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
  63
  64 unsigned char nvme_io_timeout = 30;
  65 module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
  66 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
  67
  68 unsigned char shutdown_timeout = 5;
  69 module_param(shutdown_timeout, byte, 0644);
  70 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
  71
  72 static int use_threaded_interrupts;
  73 module_param(use_threaded_interrupts, int, 0);
  74
  75 static bool use_cmb_sqes = true;
  76 module_param(use_cmb_sqes, bool, 0644);
  77 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  78
  79 static LIST_HEAD(dev_list);
  80 static struct task_struct *nvme_thread;
  81 static struct workqueue_struct *nvme_workq;
  82 static wait_queue_head_t nvme_kthread_wait;
  83
  84 struct nvme_dev;
  85 struct nvme_queue;
  86
  87 static int nvme_reset(struct nvme_dev *dev);
  88 static void nvme_process_cq(struct nvme_queue *nvmeq);
  89 static void nvme_remove_dead_ctrl(struct nvme_dev *dev);
  90 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  91
  92 /*
  93  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  94  */
  95 struct nvme_dev {
  96         struct list_head node;
  97         struct nvme_queue **queues;
  98         struct blk_mq_tag_set tagset;
  99         struct blk_mq_tag_set admin_tagset;
 100         u32 __iomem *dbs;
 101         struct device *dev;
 102         struct dma_pool *prp_page_pool;
 103         struct dma_pool *prp_small_pool;
 104         unsigned queue_count;
 105         unsigned online_queues;
 106         unsigned max_qid;
 107         int q_depth;
 108         u32 db_stride;
 109         struct msix_entry *entry;
 110         void __iomem *bar;
 111         struct work_struct reset_work;
 112         struct work_struct scan_work;
 113         struct work_struct remove_work;
 114         struct mutex shutdown_lock;
 115         bool subsystem;
 116         void __iomem *cmb;
 117         dma_addr_t cmb_dma_addr;
 118         u64 cmb_size;
 119         u32 cmbsz;
 120         unsigned long flags;
 121
 122 #define NVME_CTRL_RESETTING    0
 123
 124         struct nvme_ctrl ctrl;
 125         struct completion ioq_wait;
 126 };
 127
 128 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 129 {
 130         return container_of(ctrl, struct nvme_dev, ctrl);
 131 }
 132
 133 /*
 134  * An NVM Express queue.  Each device has at least two (one for admin
 135  * commands and one for I/O commands).
 136  */
 137 struct nvme_queue {
 138         struct device *q_dmadev;
 139         struct nvme_dev *dev;
 140         char irqname[24];       /* nvme4294967295-65535\0 */
 141         spinlock_t q_lock;
 142         struct nvme_command *sq_cmds;
 143         struct nvme_command __iomem *sq_cmds_io;
 144         volatile struct nvme_completion *cqes;
 145         struct blk_mq_tags **tags;
 146         dma_addr_t sq_dma_addr;
 147         dma_addr_t cq_dma_addr;
 148         u32 __iomem *q_db;
 149         u16 q_depth;
 150         s16 cq_vector;
 151         u16 sq_head;
 152         u16 sq_tail;
 153         u16 cq_head;
 154         u16 qid;
 155         u8 cq_phase;
 156         u8 cqe_seen;
 157 };
 158
 159 /*
 160  * The nvme_iod describes the data in an I/O, including the list of PRP
 161  * entries.  You can't see it in this data structure because C doesn't let
 162  * me express that.  Use nvme_init_iod to ensure there's enough space
 163  * allocated to store the PRP list.
 164  */
 165 struct nvme_iod {
 166         struct nvme_queue *nvmeq;
 167         int aborted;
 168         int npages;             /* In the PRP list. 0 means small pool in use */
 169         int nents;              /* Used in scatterlist */
 170         int length;             /* Of data, in bytes */
 171         dma_addr_t first_dma;
 172         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 173         struct scatterlist *sg;
 174         struct scatterlist inline_sg[0];
 175 };
 176
 177 /*
 178  * Check we didin't inadvertently grow the command struct
 179  */
 180 static inline void _nvme_check_size(void)
 181 {
 182         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 183         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 184         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 185         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 186         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 187         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 188         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 189         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 190         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 191         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 192         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 193         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 194 }
 195
 196 /*
 197  * Max size of iod being embedded in the request payload
 198  */
 199 #define NVME_INT_PAGES          2
 200 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 201
 202 /*
 203  * Will slightly overestimate the number of pages needed.  This is OK
 204  * as it only leads to a small amount of wasted memory for the lifetime of
 205  * the I/O.
 206  */
 207 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 208 {
 209         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 210                                       dev->ctrl.page_size);
 211         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 212 }
 213
 214 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
 215                 unsigned int size, unsigned int nseg)
 216 {
 217         return sizeof(__le64 *) * nvme_npages(size, dev) +
 218                         sizeof(struct scatterlist) * nseg;
 219 }
 220
 221 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 222 {
 223         return sizeof(struct nvme_iod) +
 224                 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
 225 }
 226
 227 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 228                                 unsigned int hctx_idx)
 229 {
 230         struct nvme_dev *dev = data;
 231         struct nvme_queue *nvmeq = dev->queues[0];
 232
 233         WARN_ON(hctx_idx != 0);
 234         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 235         WARN_ON(nvmeq->tags);
 236
 237         hctx->driver_data = nvmeq;
 238         nvmeq->tags = &dev->admin_tagset.tags[0];
 239         return 0;
 240 }
 241
 242 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 243 {
 244         struct nvme_queue *nvmeq = hctx->driver_data;
 245
 246         nvmeq->tags = NULL;
 247 }
 248
 249 static int nvme_admin_init_request(void *data, struct request *req,
 250                                 unsigned int hctx_idx, unsigned int rq_idx,
 251                                 unsigned int numa_node)
 252 {
 253         struct nvme_dev *dev = data;
 254         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 255         struct nvme_queue *nvmeq = dev->queues[0];
 256
 257         BUG_ON(!nvmeq);
 258         iod->nvmeq = nvmeq;
 259         return 0;
 260 }
 261
 262 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 263                           unsigned int hctx_idx)
 264 {
 265         struct nvme_dev *dev = data;
 266         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 267
 268         if (!nvmeq->tags)
 269                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 270
 271         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 272         hctx->driver_data = nvmeq;
 273         return 0;
 274 }
 275
 276 static int nvme_init_request(void *data, struct request *req,
 277                                 unsigned int hctx_idx, unsigned int rq_idx,
 278                                 unsigned int numa_node)
 279 {
 280         struct nvme_dev *dev = data;
 281         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 282         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 283
 284         BUG_ON(!nvmeq);
 285         iod->nvmeq = nvmeq;
 286         return 0;
 287 }
 288
 289 static void nvme_complete_async_event(struct nvme_dev *dev,
 290                 struct nvme_completion *cqe)
 291 {
 292         u16 status = le16_to_cpu(cqe->status) >> 1;
 293         u32 result = le32_to_cpu(cqe->result);
 294
 295         if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
 296                 ++dev->ctrl.event_limit;
 297         if (status != NVME_SC_SUCCESS)
 298                 return;
 299
 300         switch (result & 0xff07) {
 301         case NVME_AER_NOTICE_NS_CHANGED:
 302                 dev_info(dev->dev, "rescanning\n");
 303                 queue_work(nvme_workq, &dev->scan_work);
 304         default:
 305                 dev_warn(dev->dev, "async event result %08x\n", result);
 306         }
 307 }
 308
 309 /**
 310  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 311  * @nvmeq: The queue to use
 312  * @cmd: The command to send
 313  *
 314  * Safe to use from interrupt context
 315  */
 316 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 317                                                 struct nvme_command *cmd)
 318 {
 319         u16 tail = nvmeq->sq_tail;
 320
 321         if (nvmeq->sq_cmds_io)
 322                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 323         else
 324                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 325
 326         if (++tail == nvmeq->q_depth)
 327                 tail = 0;
 328         writel(tail, nvmeq->q_db);
 329         nvmeq->sq_tail = tail;
 330 }
 331
 332 static __le64 **iod_list(struct request *req)
 333 {
 334         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 335         return (__le64 **)(iod->sg + req->nr_phys_segments);
 336 }
 337
 338 static int nvme_init_iod(struct request *rq, struct nvme_dev *dev)
 339 {
 340         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 341         int nseg = rq->nr_phys_segments;
 342         unsigned size;
 343
 344         if (rq->cmd_flags & REQ_DISCARD)
 345                 size = sizeof(struct nvme_dsm_range);
 346         else
 347                 size = blk_rq_bytes(rq);
 348
 349         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 350                 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
 351                 if (!iod->sg)
 352                         return BLK_MQ_RQ_QUEUE_BUSY;
 353         } else {
 354                 iod->sg = iod->inline_sg;
 355         }
 356
 357         iod->aborted = 0;
 358         iod->npages = -1;
 359         iod->nents = 0;
 360         iod->length = size;
 361         return 0;
 362 }
 363
 364 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 365 {
 366         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 367         const int last_prp = dev->ctrl.page_size / 8 - 1;
 368         int i;
 369         __le64 **list = iod_list(req);
 370         dma_addr_t prp_dma = iod->first_dma;
 371
 372         if (iod->npages == 0)
 373                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 374         for (i = 0; i < iod->npages; i++) {
 375                 __le64 *prp_list = list[i];
 376                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 377                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 378                 prp_dma = next_prp_dma;
 379         }
 380
 381         if (iod->sg != iod->inline_sg)
 382                 kfree(iod->sg);
 383 }
 384
 385 #ifdef CONFIG_BLK_DEV_INTEGRITY
 386 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 387 {
 388         if (be32_to_cpu(pi->ref_tag) == v)
 389                 pi->ref_tag = cpu_to_be32(p);
 390 }
 391
 392 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 393 {
 394         if (be32_to_cpu(pi->ref_tag) == p)
 395                 pi->ref_tag = cpu_to_be32(v);
 396 }
 397
 398 /**
 399  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 400  *
 401  * The virtual start sector is the one that was originally submitted by the
 402  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 403  * start sector may be different. Remap protection information to match the
 404  * physical LBA on writes, and back to the original seed on reads.
 405  *
 406  * Type 0 and 3 do not have a ref tag, so no remapping required.
 407  */
 408 static void nvme_dif_remap(struct request *req,
 409                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 410 {
 411         struct nvme_ns *ns = req->rq_disk->private_data;
 412         struct bio_integrity_payload *bip;
 413         struct t10_pi_tuple *pi;
 414         void *p, *pmap;
 415         u32 i, nlb, ts, phys, virt;
 416
 417         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 418                 return;
 419
 420         bip = bio_integrity(req->bio);
 421         if (!bip)
 422                 return;
 423
 424         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 425
 426         p = pmap;
 427         virt = bip_get_seed(bip);
 428         phys = nvme_block_nr(ns, blk_rq_pos(req));
 429         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 430         ts = ns->disk->queue->integrity.tuple_size;
 431
 432         for (i = 0; i < nlb; i++, virt++, phys++) {
 433                 pi = (struct t10_pi_tuple *)p;
 434                 dif_swap(phys, virt, pi);
 435                 p += ts;
 436         }
 437         kunmap_atomic(pmap);
 438 }
 439 #else /* CONFIG_BLK_DEV_INTEGRITY */
 440 static void nvme_dif_remap(struct request *req,
 441                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 442 {
 443 }
 444 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 445 {
 446 }
 447 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 448 {
 449 }
 450 #endif
 451
 452 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req,
 453                 int total_len)
 454 {
 455         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 456         struct dma_pool *pool;
 457         int length = total_len;
 458         struct scatterlist *sg = iod->sg;
 459         int dma_len = sg_dma_len(sg);
 460         u64 dma_addr = sg_dma_address(sg);
 461         u32 page_size = dev->ctrl.page_size;
 462         int offset = dma_addr & (page_size - 1);
 463         __le64 *prp_list;
 464         __le64 **list = iod_list(req);
 465         dma_addr_t prp_dma;
 466         int nprps, i;
 467
 468         length -= (page_size - offset);
 469         if (length <= 0)
 470                 return true;
 471
 472         dma_len -= (page_size - offset);
 473         if (dma_len) {
 474                 dma_addr += (page_size - offset);
 475         } else {
 476                 sg = sg_next(sg);
 477                 dma_addr = sg_dma_address(sg);
 478                 dma_len = sg_dma_len(sg);
 479         }
 480
 481         if (length <= page_size) {
 482                 iod->first_dma = dma_addr;
 483                 return true;
 484         }
 485
 486         nprps = DIV_ROUND_UP(length, page_size);
 487         if (nprps <= (256 / 8)) {
 488                 pool = dev->prp_small_pool;
 489                 iod->npages = 0;
 490         } else {
 491                 pool = dev->prp_page_pool;
 492                 iod->npages = 1;
 493         }
 494
 495         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 496         if (!prp_list) {
 497                 iod->first_dma = dma_addr;
 498                 iod->npages = -1;
 499                 return false;
 500         }
 501         list[0] = prp_list;
 502         iod->first_dma = prp_dma;
 503         i = 0;
 504         for (;;) {
 505                 if (i == page_size >> 3) {
 506                         __le64 *old_prp_list = prp_list;
 507                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 508                         if (!prp_list)
 509                                 return false;
 510                         list[iod->npages++] = prp_list;
 511                         prp_list[0] = old_prp_list[i - 1];
 512                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 513                         i = 1;
 514                 }
 515                 prp_list[i++] = cpu_to_le64(dma_addr);
 516                 dma_len -= page_size;
 517                 dma_addr += page_size;
 518                 length -= page_size;
 519                 if (length <= 0)
 520                         break;
 521                 if (dma_len > 0)
 522                         continue;
 523                 BUG_ON(dma_len < 0);
 524                 sg = sg_next(sg);
 525                 dma_addr = sg_dma_address(sg);
 526                 dma_len = sg_dma_len(sg);
 527         }
 528
 529         return true;
 530 }
 531
 532 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
 533                 struct nvme_command *cmnd)
 534 {
 535         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 536         struct request_queue *q = req->q;
 537         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 538                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 539         int ret = BLK_MQ_RQ_QUEUE_ERROR;
 540
 541         sg_init_table(iod->sg, req->nr_phys_segments);
 542         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 543         if (!iod->nents)
 544                 goto out;
 545
 546         ret = BLK_MQ_RQ_QUEUE_BUSY;
 547         if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir))
 548                 goto out;
 549
 550         if (!nvme_setup_prps(dev, req, blk_rq_bytes(req)))
 551                 goto out_unmap;
 552
 553         ret = BLK_MQ_RQ_QUEUE_ERROR;
 554         if (blk_integrity_rq(req)) {
 555                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 556                         goto out_unmap;
 557
 558                 sg_init_table(&iod->meta_sg, 1);
 559                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 560                         goto out_unmap;
 561
 562                 if (rq_data_dir(req))
 563                         nvme_dif_remap(req, nvme_dif_prep);
 564
 565                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 566                         goto out_unmap;
 567         }
 568
 569         cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 570         cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
 571         if (blk_integrity_rq(req))
 572                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 573         return BLK_MQ_RQ_QUEUE_OK;
 574
 575 out_unmap:
 576         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 577 out:
 578         return ret;
 579 }
 580
 581 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 582 {
 583         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 584         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 585                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 586
 587         if (iod->nents) {
 588                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 589                 if (blk_integrity_rq(req)) {
 590                         if (!rq_data_dir(req))
 591                                 nvme_dif_remap(req, nvme_dif_complete);
 592                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 593                 }
 594         }
 595
 596         nvme_free_iod(dev, req);
 597 }
 598
 599 /*
 600  * We reuse the small pool to allocate the 16-byte range here as it is not
 601  * worth having a special pool for these or additional cases to handle freeing
 602  * the iod.
 603  */
 604 static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 605                 struct request *req, struct nvme_command *cmnd)
 606 {
 607         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 608         struct nvme_dsm_range *range;
 609
 610         range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
 611                                                 &iod->first_dma);
 612         if (!range)
 613                 return BLK_MQ_RQ_QUEUE_BUSY;
 614         iod_list(req)[0] = (__le64 *)range;
 615         iod->npages = 0;
 616
 617         range->cattr = cpu_to_le32(0);
 618         range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
 619         range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
 620
 621         memset(cmnd, 0, sizeof(*cmnd));
 622         cmnd->dsm.opcode = nvme_cmd_dsm;
 623         cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
 624         cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
 625         cmnd->dsm.nr = 0;
 626         cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
 627         return BLK_MQ_RQ_QUEUE_OK;
 628 }
 629
 630 /*
 631  * NOTE: ns is NULL when called on the admin queue.
 632  */
 633 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 634                          const struct blk_mq_queue_data *bd)
 635 {
 636         struct nvme_ns *ns = hctx->queue->queuedata;
 637         struct nvme_queue *nvmeq = hctx->driver_data;
 638         struct nvme_dev *dev = nvmeq->dev;
 639         struct request *req = bd->rq;
 640         struct nvme_command cmnd;
 641         int ret = BLK_MQ_RQ_QUEUE_OK;
 642
 643         /*
 644          * If formated with metadata, require the block layer provide a buffer
 645          * unless this namespace is formated such that the metadata can be
 646          * stripped/generated by the controller with PRACT=1.
 647          */
 648         if (ns && ns->ms && !blk_integrity_rq(req)) {
 649                 if (!(ns->pi_type && ns->ms == 8) &&
 650                                         req->cmd_type != REQ_TYPE_DRV_PRIV) {
 651                         blk_mq_end_request(req, -EFAULT);
 652                         return BLK_MQ_RQ_QUEUE_OK;
 653                 }
 654         }
 655
 656         ret = nvme_init_iod(req, dev);
 657         if (ret)
 658                 return ret;
 659
 660         if (req->cmd_flags & REQ_DISCARD) {
 661                 ret = nvme_setup_discard(nvmeq, ns, req, &cmnd);
 662         } else {
 663                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 664                         memcpy(&cmnd, req->cmd, sizeof(cmnd));
 665                 else if (req->cmd_flags & REQ_FLUSH)
 666                         nvme_setup_flush(ns, &cmnd);
 667                 else
 668                         nvme_setup_rw(ns, req, &cmnd);
 669
 670                 if (req->nr_phys_segments)
 671                         ret = nvme_map_data(dev, req, &cmnd);
 672         }
 673
 674         if (ret)
 675                 goto out;
 676
 677         cmnd.common.command_id = req->tag;
 678         blk_mq_start_request(req);
 679
 680         spin_lock_irq(&nvmeq->q_lock);
 681         __nvme_submit_cmd(nvmeq, &cmnd);
 682         nvme_process_cq(nvmeq);
 683         spin_unlock_irq(&nvmeq->q_lock);
 684         return BLK_MQ_RQ_QUEUE_OK;
 685 out:
 686         nvme_free_iod(dev, req);
 687         return ret;
 688 }
 689
 690 static void nvme_complete_rq(struct request *req)
 691 {
 692         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 693         struct nvme_dev *dev = iod->nvmeq->dev;
 694         int error = 0;
 695
 696         nvme_unmap_data(dev, req);
 697
 698         if (unlikely(req->errors)) {
 699                 if (nvme_req_needs_retry(req, req->errors)) {
 700                         nvme_requeue_req(req);
 701                         return;
 702                 }
 703
 704                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 705                         error = req->errors;
 706                 else
 707                         error = nvme_error_status(req->errors);
 708         }
 709
 710         if (unlikely(iod->aborted)) {
 711                 dev_warn(dev->dev,
 712                         "completing aborted command with status: %04x\n",
 713                         req->errors);
 714         }
 715
 716         blk_mq_end_request(req, error);
 717 }
 718
 719 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 720 {
 721         u16 head, phase;
 722
 723         head = nvmeq->cq_head;
 724         phase = nvmeq->cq_phase;
 725
 726         for (;;) {
 727                 struct nvme_completion cqe = nvmeq->cqes[head];
 728                 u16 status = le16_to_cpu(cqe.status);
 729                 struct request *req;
 730
 731                 if ((status & 1) != phase)
 732                         break;
 733                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 734                 if (++head == nvmeq->q_depth) {
 735                         head = 0;
 736                         phase = !phase;
 737                 }
 738
 739                 if (tag && *tag == cqe.command_id)
 740                         *tag = -1;
 741
 742                 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
 743                         dev_warn(nvmeq->q_dmadev,
 744                                 "invalid id %d completed on queue %d\n",
 745                                 cqe.command_id, le16_to_cpu(cqe.sq_id));
 746                         continue;
 747                 }
 748
 749                 /*
 750                  * AEN requests are special as they don't time out and can
 751                  * survive any kind of queue freeze and often don't respond to
 752                  * aborts.  We don't even bother to allocate a struct request
 753                  * for them but rather special case them here.
 754                  */
 755                 if (unlikely(nvmeq->qid == 0 &&
 756                                 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 757                         nvme_complete_async_event(nvmeq->dev, &cqe);
 758                         continue;
 759                 }
 760
 761                 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
 762                 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
 763                         u32 result = le32_to_cpu(cqe.result);
 764                         req->special = (void *)(uintptr_t)result;
 765                 }
 766                 blk_mq_complete_request(req, status >> 1);
 767
 768         }
 769
 770         /* If the controller ignores the cq head doorbell and continuously
 771          * writes to the queue, it is theoretically possible to wrap around
 772          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 773          * requires that 0.1% of your interrupts are handled, so this isn't
 774          * a big problem.
 775          */
 776         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 777                 return;
 778
 779         if (likely(nvmeq->cq_vector >= 0))
 780                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 781         nvmeq->cq_head = head;
 782         nvmeq->cq_phase = phase;
 783
 784         nvmeq->cqe_seen = 1;
 785 }
 786
 787 static void nvme_process_cq(struct nvme_queue *nvmeq)
 788 {
 789         __nvme_process_cq(nvmeq, NULL);
 790 }
 791
 792 static irqreturn_t nvme_irq(int irq, void *data)
 793 {
 794         irqreturn_t result;
 795         struct nvme_queue *nvmeq = data;
 796         spin_lock(&nvmeq->q_lock);
 797         nvme_process_cq(nvmeq);
 798         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 799         nvmeq->cqe_seen = 0;
 800         spin_unlock(&nvmeq->q_lock);
 801         return result;
 802 }
 803
 804 static irqreturn_t nvme_irq_check(int irq, void *data)
 805 {
 806         struct nvme_queue *nvmeq = data;
 807         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 808         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 809                 return IRQ_NONE;
 810         return IRQ_WAKE_THREAD;
 811 }
 812
 813 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 814 {
 815         struct nvme_queue *nvmeq = hctx->driver_data;
 816
 817         if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
 818             nvmeq->cq_phase) {
 819                 spin_lock_irq(&nvmeq->q_lock);
 820                 __nvme_process_cq(nvmeq, &tag);
 821                 spin_unlock_irq(&nvmeq->q_lock);
 822
 823                 if (tag == -1)
 824                         return 1;
 825         }
 826
 827         return 0;
 828 }
 829
 830 static void nvme_submit_async_event(struct nvme_dev *dev)
 831 {
 832         struct nvme_command c;
 833
 834         memset(&c, 0, sizeof(c));
 835         c.common.opcode = nvme_admin_async_event;
 836         c.common.command_id = NVME_AQ_BLKMQ_DEPTH + --dev->ctrl.event_limit;
 837
 838         __nvme_submit_cmd(dev->queues[0], &c);
 839 }
 840
 841 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 842 {
 843         struct nvme_command c;
 844
 845         memset(&c, 0, sizeof(c));
 846         c.delete_queue.opcode = opcode;
 847         c.delete_queue.qid = cpu_to_le16(id);
 848
 849         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 850 }
 851
 852 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 853                                                 struct nvme_queue *nvmeq)
 854 {
 855         struct nvme_command c;
 856         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 857
 858         /*
 859          * Note: we (ab)use the fact the the prp fields survive if no data
 860          * is attached to the request.
 861          */
 862         memset(&c, 0, sizeof(c));
 863         c.create_cq.opcode = nvme_admin_create_cq;
 864         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 865         c.create_cq.cqid = cpu_to_le16(qid);
 866         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 867         c.create_cq.cq_flags = cpu_to_le16(flags);
 868         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 869
 870         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 871 }
 872
 873 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 874                                                 struct nvme_queue *nvmeq)
 875 {
 876         struct nvme_command c;
 877         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 878
 879         /*
 880          * Note: we (ab)use the fact the the prp fields survive if no data
 881          * is attached to the request.
 882          */
 883         memset(&c, 0, sizeof(c));
 884         c.create_sq.opcode = nvme_admin_create_sq;
 885         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 886         c.create_sq.sqid = cpu_to_le16(qid);
 887         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 888         c.create_sq.sq_flags = cpu_to_le16(flags);
 889         c.create_sq.cqid = cpu_to_le16(qid);
 890
 891         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 892 }
 893
 894 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 895 {
 896         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 897 }
 898
 899 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 900 {
 901         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 902 }
 903
 904 static void abort_endio(struct request *req, int error)
 905 {
 906         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 907         struct nvme_queue *nvmeq = iod->nvmeq;
 908         u32 result = (u32)(uintptr_t)req->special;
 909         u16 status = req->errors;
 910
 911         dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
 912         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 913
 914         blk_mq_free_request(req);
 915 }
 916
 917 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 918 {
 919         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 920         struct nvme_queue *nvmeq = iod->nvmeq;
 921         struct nvme_dev *dev = nvmeq->dev;
 922         struct request *abort_req;
 923         struct nvme_command cmd;
 924
 925         /*
 926          * Shutdown immediately if controller times out while starting. The
 927          * reset work will see the pci device disabled when it gets the forced
 928          * cancellation error. All outstanding requests are completed on
 929          * shutdown, so we return BLK_EH_HANDLED.
 930          */
 931         if (test_bit(NVME_CTRL_RESETTING, &dev->flags)) {
 932                 dev_warn(dev->dev,
 933                          "I/O %d QID %d timeout, disable controller\n",
 934                          req->tag, nvmeq->qid);
 935                 nvme_dev_disable(dev, false);
 936                 req->errors = NVME_SC_CANCELLED;
 937                 return BLK_EH_HANDLED;
 938         }
 939
 940         /*
 941          * Shutdown the controller immediately and schedule a reset if the
 942          * command was already aborted once before and still hasn't been
 943          * returned to the driver, or if this is the admin queue.
 944          */
 945         if (!nvmeq->qid || iod->aborted) {
 946                 dev_warn(dev->dev,
 947                          "I/O %d QID %d timeout, reset controller\n",
 948                          req->tag, nvmeq->qid);
 949                 nvme_dev_disable(dev, false);
 950                 queue_work(nvme_workq, &dev->reset_work);
 951
 952                 /*
 953                  * Mark the request as handled, since the inline shutdown
 954                  * forces all outstanding requests to complete.
 955                  */
 956                 req->errors = NVME_SC_CANCELLED;
 957                 return BLK_EH_HANDLED;
 958         }
 959
 960         iod->aborted = 1;
 961
 962         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
 963                 atomic_inc(&dev->ctrl.abort_limit);
 964                 return BLK_EH_RESET_TIMER;
 965         }
 966
 967         memset(&cmd, 0, sizeof(cmd));
 968         cmd.abort.opcode = nvme_admin_abort_cmd;
 969         cmd.abort.cid = req->tag;
 970         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
 971
 972         dev_warn(nvmeq->q_dmadev, "I/O %d QID %d timeout, aborting\n",
 973                                  req->tag, nvmeq->qid);
 974
 975         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
 976                         BLK_MQ_REQ_NOWAIT);
 977         if (IS_ERR(abort_req)) {
 978                 atomic_inc(&dev->ctrl.abort_limit);
 979                 return BLK_EH_RESET_TIMER;
 980         }
 981
 982         abort_req->timeout = ADMIN_TIMEOUT;
 983         abort_req->end_io_data = NULL;
 984         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
 985
 986         /*
 987          * The aborted req will be completed on receiving the abort req.
 988          * We enable the timer again. If hit twice, it'll cause a device reset,
 989          * as the device then is in a faulty state.
 990          */
 991         return BLK_EH_RESET_TIMER;
 992 }
 993
 994 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
 995 {
 996         struct nvme_queue *nvmeq = data;
 997         int status;
 998
 999         if (!blk_mq_request_started(req))
1000                 return;
1001
1002         dev_warn(nvmeq->q_dmadev,
1003                  "Cancelling I/O %d QID %d\n", req->tag, nvmeq->qid);
1004
1005         status = NVME_SC_ABORT_REQ;
1006         if (blk_queue_dying(req->q))
1007                 status |= NVME_SC_DNR;
1008         blk_mq_complete_request(req, status);
1009 }
1010
1011 static void nvme_free_queue(struct nvme_queue *nvmeq)
1012 {
1013         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1014                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1015         if (nvmeq->sq_cmds)
1016                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1017                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1018         kfree(nvmeq);
1019 }
1020
1021 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1022 {
1023         int i;
1024
1025         for (i = dev->queue_count - 1; i >= lowest; i--) {
1026                 struct nvme_queue *nvmeq = dev->queues[i];
1027                 dev->queue_count--;
1028                 dev->queues[i] = NULL;
1029                 nvme_free_queue(nvmeq);
1030         }
1031 }
1032
1033 /**
1034  * nvme_suspend_queue - put queue into suspended state
1035  * @nvmeq - queue to suspend
1036  */
1037 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1038 {
1039         int vector;
1040
1041         spin_lock_irq(&nvmeq->q_lock);
1042         if (nvmeq->cq_vector == -1) {
1043                 spin_unlock_irq(&nvmeq->q_lock);
1044                 return 1;
1045         }
1046         vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1047         nvmeq->dev->online_queues--;
1048         nvmeq->cq_vector = -1;
1049         spin_unlock_irq(&nvmeq->q_lock);
1050
1051         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1052                 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
1053
1054         irq_set_affinity_hint(vector, NULL);
1055         free_irq(vector, nvmeq);
1056
1057         return 0;
1058 }
1059
1060 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1061 {
1062         spin_lock_irq(&nvmeq->q_lock);
1063         if (nvmeq->tags && *nvmeq->tags)
1064                 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
1065         spin_unlock_irq(&nvmeq->q_lock);
1066 }
1067
1068 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1069 {
1070         struct nvme_queue *nvmeq = dev->queues[0];
1071
1072         if (!nvmeq)
1073                 return;
1074         if (nvme_suspend_queue(nvmeq))
1075                 return;
1076
1077         if (shutdown)
1078                 nvme_shutdown_ctrl(&dev->ctrl);
1079         else
1080                 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1081                                                 dev->bar + NVME_REG_CAP));
1082
1083         spin_lock_irq(&nvmeq->q_lock);
1084         nvme_process_cq(nvmeq);
1085         spin_unlock_irq(&nvmeq->q_lock);
1086 }
1087
1088 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1089                                 int entry_size)
1090 {
1091         int q_depth = dev->q_depth;
1092         unsigned q_size_aligned = roundup(q_depth * entry_size,
1093                                           dev->ctrl.page_size);
1094
1095         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1096                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1097                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1098                 q_depth = div_u64(mem_per_q, entry_size);
1099
1100                 /*
1101                  * Ensure the reduced q_depth is above some threshold where it
1102                  * would be better to map queues in system memory with the
1103                  * original depth
1104                  */
1105                 if (q_depth < 64)
1106                         return -ENOMEM;
1107         }
1108
1109         return q_depth;
1110 }
1111
1112 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1113                                 int qid, int depth)
1114 {
1115         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1116                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1117                                                       dev->ctrl.page_size);
1118                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1119                 nvmeq->sq_cmds_io = dev->cmb + offset;
1120         } else {
1121                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1122                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1123                 if (!nvmeq->sq_cmds)
1124                         return -ENOMEM;
1125         }
1126
1127         return 0;
1128 }
1129
1130 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1131                                                         int depth)
1132 {
1133         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1134         if (!nvmeq)
1135                 return NULL;
1136
1137         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1138                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1139         if (!nvmeq->cqes)
1140                 goto free_nvmeq;
1141
1142         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1143                 goto free_cqdma;
1144
1145         nvmeq->q_dmadev = dev->dev;
1146         nvmeq->dev = dev;
1147         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1148                         dev->ctrl.instance, qid);
1149         spin_lock_init(&nvmeq->q_lock);
1150         nvmeq->cq_head = 0;
1151         nvmeq->cq_phase = 1;
1152         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1153         nvmeq->q_depth = depth;
1154         nvmeq->qid = qid;
1155         nvmeq->cq_vector = -1;
1156         dev->queues[qid] = nvmeq;
1157
1158         /* make sure queue descriptor is set before queue count, for kthread */
1159         mb();
1160         dev->queue_count++;
1161
1162         return nvmeq;
1163
1164  free_cqdma:
1165         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1166                                                         nvmeq->cq_dma_addr);
1167  free_nvmeq:
1168         kfree(nvmeq);
1169         return NULL;
1170 }
1171
1172 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1173                                                         const char *name)
1174 {
1175         if (use_threaded_interrupts)
1176                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1177                                         nvme_irq_check, nvme_irq, IRQF_SHARED,
1178                                         name, nvmeq);
1179         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1180                                 IRQF_SHARED, name, nvmeq);
1181 }
1182
1183 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1184 {
1185         struct nvme_dev *dev = nvmeq->dev;
1186
1187         spin_lock_irq(&nvmeq->q_lock);
1188         nvmeq->sq_tail = 0;
1189         nvmeq->cq_head = 0;
1190         nvmeq->cq_phase = 1;
1191         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1192         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1193         dev->online_queues++;
1194         spin_unlock_irq(&nvmeq->q_lock);
1195 }
1196
1197 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1198 {
1199         struct nvme_dev *dev = nvmeq->dev;
1200         int result;
1201
1202         nvmeq->cq_vector = qid - 1;
1203         result = adapter_alloc_cq(dev, qid, nvmeq);
1204         if (result < 0)
1205                 return result;
1206
1207         result = adapter_alloc_sq(dev, qid, nvmeq);
1208         if (result < 0)
1209                 goto release_cq;
1210
1211         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1212         if (result < 0)
1213                 goto release_sq;
1214
1215         nvme_init_queue(nvmeq, qid);
1216         return result;
1217
1218  release_sq:
1219         adapter_delete_sq(dev, qid);
1220  release_cq:
1221         adapter_delete_cq(dev, qid);
1222         return result;
1223 }
1224
1225 static struct blk_mq_ops nvme_mq_admin_ops = {
1226         .queue_rq       = nvme_queue_rq,
1227         .complete       = nvme_complete_rq,
1228         .map_queue      = blk_mq_map_queue,
1229         .init_hctx      = nvme_admin_init_hctx,
1230         .exit_hctx      = nvme_admin_exit_hctx,
1231         .init_request   = nvme_admin_init_request,
1232         .timeout        = nvme_timeout,
1233 };
1234
1235 static struct blk_mq_ops nvme_mq_ops = {
1236         .queue_rq       = nvme_queue_rq,
1237         .complete       = nvme_complete_rq,
1238         .map_queue      = blk_mq_map_queue,
1239         .init_hctx      = nvme_init_hctx,
1240         .init_request   = nvme_init_request,
1241         .timeout        = nvme_timeout,
1242         .poll           = nvme_poll,
1243 };
1244
1245 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1246 {
1247         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1248                 blk_cleanup_queue(dev->ctrl.admin_q);
1249                 blk_mq_free_tag_set(&dev->admin_tagset);
1250         }
1251 }
1252
1253 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1254 {
1255         if (!dev->ctrl.admin_q) {
1256                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1257                 dev->admin_tagset.nr_hw_queues = 1;
1258
1259                 /*
1260                  * Subtract one to leave an empty queue entry for 'Full Queue'
1261                  * condition. See NVM-Express 1.2 specification, section 4.1.2.
1262                  */
1263                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1264                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1265                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1266                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1267                 dev->admin_tagset.driver_data = dev;
1268
1269                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1270                         return -ENOMEM;
1271
1272                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1273                 if (IS_ERR(dev->ctrl.admin_q)) {
1274                         blk_mq_free_tag_set(&dev->admin_tagset);
1275                         return -ENOMEM;
1276                 }
1277                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1278                         nvme_dev_remove_admin(dev);
1279                         dev->ctrl.admin_q = NULL;
1280                         return -ENODEV;
1281                 }
1282         } else
1283                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1284
1285         return 0;
1286 }
1287
1288 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1289 {
1290         int result;
1291         u32 aqa;
1292         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1293         struct nvme_queue *nvmeq;
1294
1295         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ?
1296                                                 NVME_CAP_NSSRC(cap) : 0;
1297
1298         if (dev->subsystem &&
1299             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1300                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1301
1302         result = nvme_disable_ctrl(&dev->ctrl, cap);
1303         if (result < 0)
1304                 return result;
1305
1306         nvmeq = dev->queues[0];
1307         if (!nvmeq) {
1308                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1309                 if (!nvmeq)
1310                         return -ENOMEM;
1311         }
1312
1313         aqa = nvmeq->q_depth - 1;
1314         aqa |= aqa << 16;
1315
1316         writel(aqa, dev->bar + NVME_REG_AQA);
1317         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1318         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1319
1320         result = nvme_enable_ctrl(&dev->ctrl, cap);
1321         if (result)
1322                 goto free_nvmeq;
1323
1324         nvmeq->cq_vector = 0;
1325         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1326         if (result) {
1327                 nvmeq->cq_vector = -1;
1328                 goto free_nvmeq;
1329         }
1330
1331         return result;
1332
1333  free_nvmeq:
1334         nvme_free_queues(dev, 0);
1335         return result;
1336 }
1337
1338 static int nvme_kthread(void *data)
1339 {
1340         struct nvme_dev *dev, *next;
1341
1342         while (!kthread_should_stop()) {
1343                 set_current_state(TASK_INTERRUPTIBLE);
1344                 spin_lock(&dev_list_lock);
1345                 list_for_each_entry_safe(dev, next, &dev_list, node) {
1346                         int i;
1347                         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1348
1349                         /*
1350                          * Skip controllers currently under reset.
1351                          */
1352                         if (work_pending(&dev->reset_work) || work_busy(&dev->reset_work))
1353                                 continue;
1354
1355                         if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
1356                                                         csts & NVME_CSTS_CFS) {
1357                                 if (queue_work(nvme_workq, &dev->reset_work)) {
1358                                         dev_warn(dev->dev,
1359                                                 "Failed status: %x, reset controller\n",
1360                                                 readl(dev->bar + NVME_REG_CSTS));
1361                                 }
1362                                 continue;
1363                         }
1364                         for (i = 0; i < dev->queue_count; i++) {
1365                                 struct nvme_queue *nvmeq = dev->queues[i];
1366                                 if (!nvmeq)
1367                                         continue;
1368                                 spin_lock_irq(&nvmeq->q_lock);
1369                                 nvme_process_cq(nvmeq);
1370
1371                                 while (i == 0 && dev->ctrl.event_limit > 0)
1372                                         nvme_submit_async_event(dev);
1373                                 spin_unlock_irq(&nvmeq->q_lock);
1374                         }
1375                 }
1376                 spin_unlock(&dev_list_lock);
1377                 schedule_timeout(round_jiffies_relative(HZ));
1378         }
1379         return 0;
1380 }
1381
1382 static int nvme_create_io_queues(struct nvme_dev *dev)
1383 {
1384         unsigned i;
1385         int ret = 0;
1386
1387         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1388                 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1389                         ret = -ENOMEM;
1390                         break;
1391                 }
1392         }
1393
1394         for (i = dev->online_queues; i <= dev->queue_count - 1; i++) {
1395                 ret = nvme_create_queue(dev->queues[i], i);
1396                 if (ret) {
1397                         nvme_free_queues(dev, i);
1398                         break;
1399                 }
1400         }
1401
1402         /*
1403          * Ignore failing Create SQ/CQ commands, we can continue with less
1404          * than the desired aount of queues, and even a controller without
1405          * I/O queues an still be used to issue admin commands.  This might
1406          * be useful to upgrade a buggy firmware for example.
1407          */
1408         return ret >= 0 ? 0 : ret;
1409 }
1410
1411 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1412 {
1413         u64 szu, size, offset;
1414         u32 cmbloc;
1415         resource_size_t bar_size;
1416         struct pci_dev *pdev = to_pci_dev(dev->dev);
1417         void __iomem *cmb;
1418         dma_addr_t dma_addr;
1419
1420         if (!use_cmb_sqes)
1421                 return NULL;
1422
1423         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1424         if (!(NVME_CMB_SZ(dev->cmbsz)))
1425                 return NULL;
1426
1427         cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1428
1429         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1430         size = szu * NVME_CMB_SZ(dev->cmbsz);
1431         offset = szu * NVME_CMB_OFST(cmbloc);
1432         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
1433
1434         if (offset > bar_size)
1435                 return NULL;
1436
1437         /*
1438          * Controllers may support a CMB size larger than their BAR,
1439          * for example, due to being behind a bridge. Reduce the CMB to
1440          * the reported size of the BAR
1441          */
1442         if (size > bar_size - offset)
1443                 size = bar_size - offset;
1444
1445         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
1446         cmb = ioremap_wc(dma_addr, size);
1447         if (!cmb)
1448                 return NULL;
1449
1450         dev->cmb_dma_addr = dma_addr;
1451         dev->cmb_size = size;
1452         return cmb;
1453 }
1454
1455 static inline void nvme_release_cmb(struct nvme_dev *dev)
1456 {
1457         if (dev->cmb) {
1458                 iounmap(dev->cmb);
1459                 dev->cmb = NULL;
1460         }
1461 }
1462
1463 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1464 {
1465         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1466 }
1467
1468 static int nvme_setup_io_queues(struct nvme_dev *dev)
1469 {
1470         struct nvme_queue *adminq = dev->queues[0];
1471         struct pci_dev *pdev = to_pci_dev(dev->dev);
1472         int result, i, vecs, nr_io_queues, size;
1473
1474         nr_io_queues = num_possible_cpus();
1475         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1476         if (result < 0)
1477                 return result;
1478
1479         /*
1480          * Degraded controllers might return an error when setting the queue
1481          * count.  We still want to be able to bring them online and offer
1482          * access to the admin queue, as that might be only way to fix them up.
1483          */
1484         if (result > 0) {
1485                 dev_err(dev->dev, "Could not set queue count (%d)\n", result);
1486                 nr_io_queues = 0;
1487                 result = 0;
1488         }
1489
1490         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1491                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1492                                 sizeof(struct nvme_command));
1493                 if (result > 0)
1494                         dev->q_depth = result;
1495                 else
1496                         nvme_release_cmb(dev);
1497         }
1498
1499         size = db_bar_size(dev, nr_io_queues);
1500         if (size > 8192) {
1501                 iounmap(dev->bar);
1502                 do {
1503                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1504                         if (dev->bar)
1505                                 break;
1506                         if (!--nr_io_queues)
1507                                 return -ENOMEM;
1508                         size = db_bar_size(dev, nr_io_queues);
1509                 } while (1);
1510                 dev->dbs = dev->bar + 4096;
1511                 adminq->q_db = dev->dbs;
1512         }
1513
1514         /* Deregister the admin queue's interrupt */
1515         free_irq(dev->entry[0].vector, adminq);
1516
1517         /*
1518          * If we enable msix early due to not intx, disable it again before
1519          * setting up the full range we need.
1520          */
1521         if (!pdev->irq)
1522                 pci_disable_msix(pdev);
1523
1524         for (i = 0; i < nr_io_queues; i++)
1525                 dev->entry[i].entry = i;
1526         vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
1527         if (vecs < 0) {
1528                 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
1529                 if (vecs < 0) {
1530                         vecs = 1;
1531                 } else {
1532                         for (i = 0; i < vecs; i++)
1533                                 dev->entry[i].vector = i + pdev->irq;
1534                 }
1535         }
1536
1537         /*
1538          * Should investigate if there's a performance win from allocating
1539          * more queues than interrupt vectors; it might allow the submission
1540          * path to scale better, even if the receive path is limited by the
1541          * number of interrupts.
1542          */
1543         nr_io_queues = vecs;
1544         dev->max_qid = nr_io_queues;
1545
1546         result = queue_request_irq(dev, adminq, adminq->irqname);
1547         if (result) {
1548                 adminq->cq_vector = -1;
1549                 goto free_queues;
1550         }
1551
1552         /* Free previously allocated queues that are no longer usable */
1553         nvme_free_queues(dev, nr_io_queues + 1);
1554         return nvme_create_io_queues(dev);
1555
1556  free_queues:
1557         nvme_free_queues(dev, 1);
1558         return result;
1559 }
1560
1561 static void nvme_set_irq_hints(struct nvme_dev *dev)
1562 {
1563         struct nvme_queue *nvmeq;
1564         int i;
1565
1566         for (i = 0; i < dev->online_queues; i++) {
1567                 nvmeq = dev->queues[i];
1568
1569                 if (!nvmeq->tags || !(*nvmeq->tags))
1570                         continue;
1571
1572                 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
1573                                         blk_mq_tags_cpumask(*nvmeq->tags));
1574         }
1575 }
1576
1577 static void nvme_dev_scan(struct work_struct *work)
1578 {
1579         struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
1580
1581         if (!dev->tagset.tags)
1582                 return;
1583         nvme_scan_namespaces(&dev->ctrl);
1584         nvme_set_irq_hints(dev);
1585 }
1586
1587 static void nvme_del_queue_end(struct request *req, int error)
1588 {
1589         struct nvme_queue *nvmeq = req->end_io_data;
1590
1591         blk_mq_free_request(req);
1592         complete(&nvmeq->dev->ioq_wait);
1593 }
1594
1595 static void nvme_del_cq_end(struct request *req, int error)
1596 {
1597         struct nvme_queue *nvmeq = req->end_io_data;
1598
1599         if (!error) {
1600                 unsigned long flags;
1601
1602                 spin_lock_irqsave(&nvmeq->q_lock, flags);
1603                 nvme_process_cq(nvmeq);
1604                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1605         }
1606
1607         nvme_del_queue_end(req, error);
1608 }
1609
1610 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1611 {
1612         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1613         struct request *req;
1614         struct nvme_command cmd;
1615
1616         memset(&cmd, 0, sizeof(cmd));
1617         cmd.delete_queue.opcode = opcode;
1618         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1619
1620         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
1621         if (IS_ERR(req))
1622                 return PTR_ERR(req);
1623
1624         req->timeout = ADMIN_TIMEOUT;
1625         req->end_io_data = nvmeq;
1626
1627         blk_execute_rq_nowait(q, NULL, req, false,
1628                         opcode == nvme_admin_delete_cq ?
1629                                 nvme_del_cq_end : nvme_del_queue_end);
1630         return 0;
1631 }
1632
1633 static void nvme_disable_io_queues(struct nvme_dev *dev)
1634 {
1635         int pass;
1636         unsigned long timeout;
1637         u8 opcode = nvme_admin_delete_sq;
1638
1639         for (pass = 0; pass < 2; pass++) {
1640                 int sent = 0, i = dev->queue_count - 1;
1641
1642                 reinit_completion(&dev->ioq_wait);
1643  retry:
1644                 timeout = ADMIN_TIMEOUT;
1645                 for (; i > 0; i--) {
1646                         struct nvme_queue *nvmeq = dev->queues[i];
1647
1648                         if (!pass)
1649                                 nvme_suspend_queue(nvmeq);
1650                         if (nvme_delete_queue(nvmeq, opcode))
1651                                 break;
1652                         ++sent;
1653                 }
1654                 while (sent--) {
1655                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1656                         if (timeout == 0)
1657                                 return;
1658                         if (i)
1659                                 goto retry;
1660                 }
1661                 opcode = nvme_admin_delete_cq;
1662         }
1663 }
1664
1665 /*
1666  * Return: error value if an error occurred setting up the queues or calling
1667  * Identify Device.  0 if these succeeded, even if adding some of the
1668  * namespaces failed.  At the moment, these failures are silent.  TBD which
1669  * failures should be reported.
1670  */
1671 static int nvme_dev_add(struct nvme_dev *dev)
1672 {
1673         if (!dev->ctrl.tagset) {
1674                 dev->tagset.ops = &nvme_mq_ops;
1675                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1676                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1677                 dev->tagset.numa_node = dev_to_node(dev->dev);
1678                 dev->tagset.queue_depth =
1679                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1680                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1681                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1682                 dev->tagset.driver_data = dev;
1683
1684                 if (blk_mq_alloc_tag_set(&dev->tagset))
1685                         return 0;
1686                 dev->ctrl.tagset = &dev->tagset;
1687         }
1688         queue_work(nvme_workq, &dev->scan_work);
1689         return 0;
1690 }
1691
1692 static int nvme_dev_map(struct nvme_dev *dev)
1693 {
1694         u64 cap;
1695         int bars, result = -ENOMEM;
1696         struct pci_dev *pdev = to_pci_dev(dev->dev);
1697
1698         if (pci_enable_device_mem(pdev))
1699                 return result;
1700
1701         dev->entry[0].vector = pdev->irq;
1702         pci_set_master(pdev);
1703         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1704         if (!bars)
1705                 goto disable_pci;
1706
1707         if (pci_request_selected_regions(pdev, bars, "nvme"))
1708                 goto disable_pci;
1709
1710         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1711             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1712                 goto disable;
1713
1714         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1715         if (!dev->bar)
1716                 goto disable;
1717
1718         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1719                 result = -ENODEV;
1720                 goto unmap;
1721         }
1722
1723         /*
1724          * Some devices don't advertse INTx interrupts, pre-enable a single
1725          * MSIX vec for setup. We'll adjust this later.
1726          */
1727         if (!pdev->irq) {
1728                 result = pci_enable_msix(pdev, dev->entry, 1);
1729                 if (result < 0)
1730                         goto unmap;
1731         }
1732
1733         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1734
1735         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1736         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1737         dev->dbs = dev->bar + 4096;
1738
1739         /*
1740          * Temporary fix for the Apple controller found in the MacBook8,1 and
1741          * some MacBook7,1 to avoid controller resets and data loss.
1742          */
1743         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1744                 dev->q_depth = 2;
1745                 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1746                         "queue depth=%u to work around controller resets\n",
1747                         dev->q_depth);
1748         }
1749
1750         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2))
1751                 dev->cmb = nvme_map_cmb(dev);
1752
1753         pci_enable_pcie_error_reporting(pdev);
1754         pci_save_state(pdev);
1755         return 0;
1756
1757  unmap:
1758         iounmap(dev->bar);
1759         dev->bar = NULL;
1760  disable:
1761         pci_release_regions(pdev);
1762  disable_pci:
1763         pci_disable_device(pdev);
1764         return result;
1765 }
1766
1767 static void nvme_dev_unmap(struct nvme_dev *dev)
1768 {
1769         struct pci_dev *pdev = to_pci_dev(dev->dev);
1770
1771         if (pdev->msi_enabled)
1772                 pci_disable_msi(pdev);
1773         else if (pdev->msix_enabled)
1774                 pci_disable_msix(pdev);
1775
1776         if (dev->bar) {
1777                 iounmap(dev->bar);
1778                 dev->bar = NULL;
1779                 pci_release_regions(pdev);
1780         }
1781
1782         if (pci_is_enabled(pdev)) {
1783                 pci_disable_pcie_error_reporting(pdev);
1784                 pci_disable_device(pdev);
1785         }
1786 }
1787
1788 static int nvme_dev_list_add(struct nvme_dev *dev)
1789 {
1790         bool start_thread = false;
1791
1792         spin_lock(&dev_list_lock);
1793         if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
1794                 start_thread = true;
1795                 nvme_thread = NULL;
1796         }
1797         list_add(&dev->node, &dev_list);
1798         spin_unlock(&dev_list_lock);
1799
1800         if (start_thread) {
1801                 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1802                 wake_up_all(&nvme_kthread_wait);
1803         } else
1804                 wait_event_killable(nvme_kthread_wait, nvme_thread);
1805
1806         if (IS_ERR_OR_NULL(nvme_thread))
1807                 return nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
1808
1809         return 0;
1810 }
1811
1812 /*
1813 * Remove the node from the device list and check
1814 * for whether or not we need to stop the nvme_thread.
1815 */
1816 static void nvme_dev_list_remove(struct nvme_dev *dev)
1817 {
1818         struct task_struct *tmp = NULL;
1819
1820         spin_lock(&dev_list_lock);
1821         list_del_init(&dev->node);
1822         if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
1823                 tmp = nvme_thread;
1824                 nvme_thread = NULL;
1825         }
1826         spin_unlock(&dev_list_lock);
1827
1828         if (tmp)
1829                 kthread_stop(tmp);
1830 }
1831
1832 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1833 {
1834         int i;
1835         u32 csts = -1;
1836
1837         nvme_dev_list_remove(dev);
1838
1839         mutex_lock(&dev->shutdown_lock);
1840         if (dev->bar) {
1841                 nvme_stop_queues(&dev->ctrl);
1842                 csts = readl(dev->bar + NVME_REG_CSTS);
1843         }
1844         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
1845                 for (i = dev->queue_count - 1; i >= 0; i--) {
1846                         struct nvme_queue *nvmeq = dev->queues[i];
1847                         nvme_suspend_queue(nvmeq);
1848                 }
1849         } else {
1850                 nvme_disable_io_queues(dev);
1851                 nvme_disable_admin_queue(dev, shutdown);
1852         }
1853         nvme_dev_unmap(dev);
1854
1855         for (i = dev->queue_count - 1; i >= 0; i--)
1856                 nvme_clear_queue(dev->queues[i]);
1857         mutex_unlock(&dev->shutdown_lock);
1858 }
1859
1860 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1861 {
1862         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1863                                                 PAGE_SIZE, PAGE_SIZE, 0);
1864         if (!dev->prp_page_pool)
1865                 return -ENOMEM;
1866
1867         /* Optimisation for I/Os between 4k and 128k */
1868         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1869                                                 256, 256, 0);
1870         if (!dev->prp_small_pool) {
1871                 dma_pool_destroy(dev->prp_page_pool);
1872                 return -ENOMEM;
1873         }
1874         return 0;
1875 }
1876
1877 static void nvme_release_prp_pools(struct nvme_dev *dev)
1878 {
1879         dma_pool_destroy(dev->prp_page_pool);
1880         dma_pool_destroy(dev->prp_small_pool);
1881 }
1882
1883 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1884 {
1885         struct nvme_dev *dev = to_nvme_dev(ctrl);
1886
1887         put_device(dev->dev);
1888         if (dev->tagset.tags)
1889                 blk_mq_free_tag_set(&dev->tagset);
1890         if (dev->ctrl.admin_q)
1891                 blk_put_queue(dev->ctrl.admin_q);
1892         kfree(dev->queues);
1893         kfree(dev->entry);
1894         kfree(dev);
1895 }
1896
1897 static void nvme_reset_work(struct work_struct *work)
1898 {
1899         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1900         int result;
1901
1902         if (WARN_ON(test_bit(NVME_CTRL_RESETTING, &dev->flags)))
1903                 goto out;
1904
1905         /*
1906          * If we're called to reset a live controller first shut it down before
1907          * moving on.
1908          */
1909         if (dev->bar)
1910                 nvme_dev_disable(dev, false);
1911
1912         set_bit(NVME_CTRL_RESETTING, &dev->flags);
1913
1914         result = nvme_dev_map(dev);
1915         if (result)
1916                 goto out;
1917
1918         result = nvme_configure_admin_queue(dev);
1919         if (result)
1920                 goto unmap;
1921
1922         nvme_init_queue(dev->queues[0], 0);
1923         result = nvme_alloc_admin_tags(dev);
1924         if (result)
1925                 goto disable;
1926
1927         result = nvme_init_identify(&dev->ctrl);
1928         if (result)
1929                 goto free_tags;
1930
1931         result = nvme_setup_io_queues(dev);
1932         if (result)
1933                 goto free_tags;
1934
1935         dev->ctrl.event_limit = NVME_NR_AEN_COMMANDS;
1936
1937         result = nvme_dev_list_add(dev);
1938         if (result)
1939                 goto remove;
1940
1941         /*
1942          * Keep the controller around but remove all namespaces if we don't have
1943          * any working I/O queue.
1944          */
1945         if (dev->online_queues < 2) {
1946                 dev_warn(dev->dev, "IO queues not created\n");
1947                 nvme_remove_namespaces(&dev->ctrl);
1948         } else {
1949                 nvme_start_queues(&dev->ctrl);
1950                 nvme_dev_add(dev);
1951         }
1952
1953         clear_bit(NVME_CTRL_RESETTING, &dev->flags);
1954         return;
1955
1956  remove:
1957         nvme_dev_list_remove(dev);
1958  free_tags:
1959         nvme_dev_remove_admin(dev);
1960         blk_put_queue(dev->ctrl.admin_q);
1961         dev->ctrl.admin_q = NULL;
1962         dev->queues[0]->tags = NULL;
1963  disable:
1964         nvme_disable_admin_queue(dev, false);
1965  unmap:
1966         nvme_dev_unmap(dev);
1967  out:
1968         nvme_remove_dead_ctrl(dev);
1969 }
1970
1971 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1972 {
1973         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1974         struct pci_dev *pdev = to_pci_dev(dev->dev);
1975
1976         if (pci_get_drvdata(pdev))
1977                 pci_stop_and_remove_bus_device_locked(pdev);
1978         nvme_put_ctrl(&dev->ctrl);
1979 }
1980
1981 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
1982 {
1983         dev_warn(dev->dev, "Removing after probe failure\n");
1984         kref_get(&dev->ctrl.kref);
1985         if (!schedule_work(&dev->remove_work))
1986                 nvme_put_ctrl(&dev->ctrl);
1987 }
1988
1989 static int nvme_reset(struct nvme_dev *dev)
1990 {
1991         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1992                 return -ENODEV;
1993
1994         if (!queue_work(nvme_workq, &dev->reset_work))
1995                 return -EBUSY;
1996
1997         flush_work(&dev->reset_work);
1998         return 0;
1999 }
2000
2001 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2002 {
2003         *val = readl(to_nvme_dev(ctrl)->bar + off);
2004         return 0;
2005 }
2006
2007 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2008 {
2009         writel(val, to_nvme_dev(ctrl)->bar + off);
2010         return 0;
2011 }
2012
2013 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2014 {
2015         *val = readq(to_nvme_dev(ctrl)->bar + off);
2016         return 0;
2017 }
2018
2019 static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl)
2020 {
2021         struct nvme_dev *dev = to_nvme_dev(ctrl);
2022
2023         return !dev->bar || dev->online_queues < 2;
2024 }
2025
2026 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
2027 {
2028         return nvme_reset(to_nvme_dev(ctrl));
2029 }
2030
2031 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2032         .reg_read32             = nvme_pci_reg_read32,
2033         .reg_write32            = nvme_pci_reg_write32,
2034         .reg_read64             = nvme_pci_reg_read64,
2035         .io_incapable           = nvme_pci_io_incapable,
2036         .reset_ctrl             = nvme_pci_reset_ctrl,
2037         .free_ctrl              = nvme_pci_free_ctrl,
2038 };
2039
2040 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2041 {
2042         int node, result = -ENOMEM;
2043         struct nvme_dev *dev;
2044
2045         node = dev_to_node(&pdev->dev);
2046         if (node == NUMA_NO_NODE)
2047                 set_dev_node(&pdev->dev, 0);
2048
2049         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2050         if (!dev)
2051                 return -ENOMEM;
2052         dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2053                                                         GFP_KERNEL, node);
2054         if (!dev->entry)
2055                 goto free;
2056         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2057                                                         GFP_KERNEL, node);
2058         if (!dev->queues)
2059                 goto free;
2060
2061         dev->dev = get_device(&pdev->dev);
2062         pci_set_drvdata(pdev, dev);
2063
2064         INIT_LIST_HEAD(&dev->node);
2065         INIT_WORK(&dev->scan_work, nvme_dev_scan);
2066         INIT_WORK(&dev->reset_work, nvme_reset_work);
2067         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2068         mutex_init(&dev->shutdown_lock);
2069         init_completion(&dev->ioq_wait);
2070
2071         result = nvme_setup_prp_pools(dev);
2072         if (result)
2073                 goto put_pci;
2074
2075         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2076                         id->driver_data);
2077         if (result)
2078                 goto release_pools;
2079
2080         queue_work(nvme_workq, &dev->reset_work);
2081         return 0;
2082
2083  release_pools:
2084         nvme_release_prp_pools(dev);
2085  put_pci:
2086         put_device(dev->dev);
2087  free:
2088         kfree(dev->queues);
2089         kfree(dev->entry);
2090         kfree(dev);
2091         return result;
2092 }
2093
2094 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2095 {
2096         struct nvme_dev *dev = pci_get_drvdata(pdev);
2097
2098         if (prepare)
2099                 nvme_dev_disable(dev, false);
2100         else
2101                 queue_work(nvme_workq, &dev->reset_work);
2102 }
2103
2104 static void nvme_shutdown(struct pci_dev *pdev)
2105 {
2106         struct nvme_dev *dev = pci_get_drvdata(pdev);
2107         nvme_dev_disable(dev, true);
2108 }
2109
2110 static void nvme_remove(struct pci_dev *pdev)
2111 {
2112         struct nvme_dev *dev = pci_get_drvdata(pdev);
2113
2114         spin_lock(&dev_list_lock);
2115         list_del_init(&dev->node);
2116         spin_unlock(&dev_list_lock);
2117
2118         pci_set_drvdata(pdev, NULL);
2119         flush_work(&dev->reset_work);
2120         flush_work(&dev->scan_work);
2121         nvme_remove_namespaces(&dev->ctrl);
2122         nvme_uninit_ctrl(&dev->ctrl);
2123         nvme_dev_disable(dev, true);
2124         nvme_dev_remove_admin(dev);
2125         nvme_free_queues(dev, 0);
2126         nvme_release_cmb(dev);
2127         nvme_release_prp_pools(dev);
2128         nvme_put_ctrl(&dev->ctrl);
2129 }
2130
2131 #ifdef CONFIG_PM_SLEEP
2132 static int nvme_suspend(struct device *dev)
2133 {
2134         struct pci_dev *pdev = to_pci_dev(dev);
2135         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2136
2137         nvme_dev_disable(ndev, true);
2138         return 0;
2139 }
2140
2141 static int nvme_resume(struct device *dev)
2142 {
2143         struct pci_dev *pdev = to_pci_dev(dev);
2144         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2145
2146         queue_work(nvme_workq, &ndev->reset_work);
2147         return 0;
2148 }
2149 #endif
2150
2151 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2152
2153 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2154                                                 pci_channel_state_t state)
2155 {
2156         struct nvme_dev *dev = pci_get_drvdata(pdev);
2157
2158         /*
2159          * A frozen channel requires a reset. When detected, this method will
2160          * shutdown the controller to quiesce. The controller will be restarted
2161          * after the slot reset through driver's slot_reset callback.
2162          */
2163         dev_warn(&pdev->dev, "error detected: state:%d\n", state);
2164         switch (state) {
2165         case pci_channel_io_normal:
2166                 return PCI_ERS_RESULT_CAN_RECOVER;
2167         case pci_channel_io_frozen:
2168                 nvme_dev_disable(dev, false);
2169                 return PCI_ERS_RESULT_NEED_RESET;
2170         case pci_channel_io_perm_failure:
2171                 return PCI_ERS_RESULT_DISCONNECT;
2172         }
2173         return PCI_ERS_RESULT_NEED_RESET;
2174 }
2175
2176 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2177 {
2178         struct nvme_dev *dev = pci_get_drvdata(pdev);
2179
2180         dev_info(&pdev->dev, "restart after slot reset\n");
2181         pci_restore_state(pdev);
2182         queue_work(nvme_workq, &dev->reset_work);
2183         return PCI_ERS_RESULT_RECOVERED;
2184 }
2185
2186 static void nvme_error_resume(struct pci_dev *pdev)
2187 {
2188         pci_cleanup_aer_uncorrect_error_status(pdev);
2189 }
2190
2191 static const struct pci_error_handlers nvme_err_handler = {
2192         .error_detected = nvme_error_detected,
2193         .slot_reset     = nvme_slot_reset,
2194         .resume         = nvme_error_resume,
2195         .reset_notify   = nvme_reset_notify,
2196 };
2197
2198 /* Move to pci_ids.h later */
2199 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
2200
2201 static const struct pci_device_id nvme_id_table[] = {
2202         { PCI_VDEVICE(INTEL, 0x0953),
2203                 .driver_data = NVME_QUIRK_STRIPE_SIZE, },
2204         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2205                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2206         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2207         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2208         { 0, }
2209 };
2210 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2211
2212 static struct pci_driver nvme_driver = {
2213         .name           = "nvme",
2214         .id_table       = nvme_id_table,
2215         .probe          = nvme_probe,
2216         .remove         = nvme_remove,
2217         .shutdown       = nvme_shutdown,
2218         .driver         = {
2219                 .pm     = &nvme_dev_pm_ops,
2220         },
2221         .err_handler    = &nvme_err_handler,
2222 };
2223
2224 static int __init nvme_init(void)
2225 {
2226         int result;
2227
2228         init_waitqueue_head(&nvme_kthread_wait);
2229
2230         nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2231         if (!nvme_workq)
2232                 return -ENOMEM;
2233
2234         result = nvme_core_init();
2235         if (result < 0)
2236                 goto kill_workq;
2237
2238         result = pci_register_driver(&nvme_driver);
2239         if (result)
2240                 goto core_exit;
2241         return 0;
2242
2243  core_exit:
2244         nvme_core_exit();
2245  kill_workq:
2246         destroy_workqueue(nvme_workq);
2247         return result;
2248 }
2249
2250 static void __exit nvme_exit(void)
2251 {
2252         pci_unregister_driver(&nvme_driver);
2253         nvme_core_exit();
2254         destroy_workqueue(nvme_workq);
2255         BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
2256         _nvme_check_size();
2257 }
2258
2259 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2260 MODULE_LICENSE("GPL");
2261 MODULE_VERSION("1.0");
2262 module_init(nvme_init);
2263 module_exit(nvme_exit);