drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/cpu.h>
  20 #include <linux/delay.h>
  21 #include <linux/errno.h>
  22 #include <linux/fs.h>
  23 #include <linux/genhd.h>
  24 #include <linux/hdreg.h>
  25 #include <linux/idr.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/kdev_t.h>
  30 #include <linux/kthread.h>
  31 #include <linux/kernel.h>
  32 #include <linux/mm.h>
  33 #include <linux/module.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/mutex.h>
  36 #include <linux/pci.h>
  37 #include <linux/poison.h>
  38 #include <linux/ptrace.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/t10-pi.h>
  42 #include <linux/types.h>
  43 #include <linux/io-64-nonatomic-lo-hi.h>
  44 #include <asm/unaligned.h>
  45
  46 #include "nvme.h"
  47
  48 #define NVME_Q_DEPTH            1024
  49 #define NVME_AQ_DEPTH           256
  50 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  51 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  52
  53 /*
  54  * We handle AEN commands ourselves and don't even let the
  55  * block layer know about them.
  56  */
  57 #define NVME_NR_AEN_COMMANDS    1
  58 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
  59
  60 static int use_threaded_interrupts;
  61 module_param(use_threaded_interrupts, int, 0);
  62
  63 static bool use_cmb_sqes = true;
  64 module_param(use_cmb_sqes, bool, 0644);
  65 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  66
  67 static LIST_HEAD(dev_list);
  68 static DEFINE_SPINLOCK(dev_list_lock);
  69 static struct task_struct *nvme_thread;
  70 static struct workqueue_struct *nvme_workq;
  71 static wait_queue_head_t nvme_kthread_wait;
  72
  73 struct nvme_dev;
  74 struct nvme_queue;
  75
  76 static int nvme_reset(struct nvme_dev *dev);
  77 static void nvme_process_cq(struct nvme_queue *nvmeq);
  78 static void nvme_remove_dead_ctrl(struct nvme_dev *dev);
  79 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  80
  81 /*
  82  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  83  */
  84 struct nvme_dev {
  85         struct list_head node;
  86         struct nvme_queue **queues;
  87         struct blk_mq_tag_set tagset;
  88         struct blk_mq_tag_set admin_tagset;
  89         u32 __iomem *dbs;
  90         struct device *dev;
  91         struct dma_pool *prp_page_pool;
  92         struct dma_pool *prp_small_pool;
  93         unsigned queue_count;
  94         unsigned online_queues;
  95         unsigned max_qid;
  96         int q_depth;
  97         u32 db_stride;
  98         struct msix_entry *entry;
  99         void __iomem *bar;
 100         struct work_struct reset_work;
 101         struct work_struct scan_work;
 102         struct work_struct remove_work;
 103         struct mutex shutdown_lock;
 104         bool subsystem;
 105         void __iomem *cmb;
 106         dma_addr_t cmb_dma_addr;
 107         u64 cmb_size;
 108         u32 cmbsz;
 109         unsigned long flags;
 110
 111 #define NVME_CTRL_RESETTING    0
 112
 113         struct nvme_ctrl ctrl;
 114         struct completion ioq_wait;
 115 };
 116
 117 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 118 {
 119         return container_of(ctrl, struct nvme_dev, ctrl);
 120 }
 121
 122 /*
 123  * An NVM Express queue.  Each device has at least two (one for admin
 124  * commands and one for I/O commands).
 125  */
 126 struct nvme_queue {
 127         struct device *q_dmadev;
 128         struct nvme_dev *dev;
 129         char irqname[24];       /* nvme4294967295-65535\0 */
 130         spinlock_t q_lock;
 131         struct nvme_command *sq_cmds;
 132         struct nvme_command __iomem *sq_cmds_io;
 133         volatile struct nvme_completion *cqes;
 134         struct blk_mq_tags **tags;
 135         dma_addr_t sq_dma_addr;
 136         dma_addr_t cq_dma_addr;
 137         u32 __iomem *q_db;
 138         u16 q_depth;
 139         s16 cq_vector;
 140         u16 sq_head;
 141         u16 sq_tail;
 142         u16 cq_head;
 143         u16 qid;
 144         u8 cq_phase;
 145         u8 cqe_seen;
 146 };
 147
 148 /*
 149  * The nvme_iod describes the data in an I/O, including the list of PRP
 150  * entries.  You can't see it in this data structure because C doesn't let
 151  * me express that.  Use nvme_init_iod to ensure there's enough space
 152  * allocated to store the PRP list.
 153  */
 154 struct nvme_iod {
 155         struct nvme_queue *nvmeq;
 156         int aborted;
 157         int npages;             /* In the PRP list. 0 means small pool in use */
 158         int nents;              /* Used in scatterlist */
 159         int length;             /* Of data, in bytes */
 160         dma_addr_t first_dma;
 161         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 162         struct scatterlist *sg;
 163         struct scatterlist inline_sg[0];
 164 };
 165
 166 /*
 167  * Check we didin't inadvertently grow the command struct
 168  */
 169 static inline void _nvme_check_size(void)
 170 {
 171         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 172         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 173         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 174         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 175         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 176         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 177         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 178         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 179         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 180         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 181         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 182         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 183 }
 184
 185 /*
 186  * Max size of iod being embedded in the request payload
 187  */
 188 #define NVME_INT_PAGES          2
 189 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 190
 191 /*
 192  * Will slightly overestimate the number of pages needed.  This is OK
 193  * as it only leads to a small amount of wasted memory for the lifetime of
 194  * the I/O.
 195  */
 196 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 197 {
 198         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 199                                       dev->ctrl.page_size);
 200         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 201 }
 202
 203 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
 204                 unsigned int size, unsigned int nseg)
 205 {
 206         return sizeof(__le64 *) * nvme_npages(size, dev) +
 207                         sizeof(struct scatterlist) * nseg;
 208 }
 209
 210 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 211 {
 212         return sizeof(struct nvme_iod) +
 213                 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
 214 }
 215
 216 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 217                                 unsigned int hctx_idx)
 218 {
 219         struct nvme_dev *dev = data;
 220         struct nvme_queue *nvmeq = dev->queues[0];
 221
 222         WARN_ON(hctx_idx != 0);
 223         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 224         WARN_ON(nvmeq->tags);
 225
 226         hctx->driver_data = nvmeq;
 227         nvmeq->tags = &dev->admin_tagset.tags[0];
 228         return 0;
 229 }
 230
 231 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 232 {
 233         struct nvme_queue *nvmeq = hctx->driver_data;
 234
 235         nvmeq->tags = NULL;
 236 }
 237
 238 static int nvme_admin_init_request(void *data, struct request *req,
 239                                 unsigned int hctx_idx, unsigned int rq_idx,
 240                                 unsigned int numa_node)
 241 {
 242         struct nvme_dev *dev = data;
 243         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 244         struct nvme_queue *nvmeq = dev->queues[0];
 245
 246         BUG_ON(!nvmeq);
 247         iod->nvmeq = nvmeq;
 248         return 0;
 249 }
 250
 251 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 252                           unsigned int hctx_idx)
 253 {
 254         struct nvme_dev *dev = data;
 255         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 256
 257         if (!nvmeq->tags)
 258                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 259
 260         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 261         hctx->driver_data = nvmeq;
 262         return 0;
 263 }
 264
 265 static int nvme_init_request(void *data, struct request *req,
 266                                 unsigned int hctx_idx, unsigned int rq_idx,
 267                                 unsigned int numa_node)
 268 {
 269         struct nvme_dev *dev = data;
 270         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 271         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 272
 273         BUG_ON(!nvmeq);
 274         iod->nvmeq = nvmeq;
 275         return 0;
 276 }
 277
 278 static void nvme_complete_async_event(struct nvme_dev *dev,
 279                 struct nvme_completion *cqe)
 280 {
 281         u16 status = le16_to_cpu(cqe->status) >> 1;
 282         u32 result = le32_to_cpu(cqe->result);
 283
 284         if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
 285                 ++dev->ctrl.event_limit;
 286         if (status != NVME_SC_SUCCESS)
 287                 return;
 288
 289         switch (result & 0xff07) {
 290         case NVME_AER_NOTICE_NS_CHANGED:
 291                 dev_info(dev->ctrl.device, "rescanning\n");
 292                 queue_work(nvme_workq, &dev->scan_work);
 293         default:
 294                 dev_warn(dev->ctrl.device, "async event result %08x\n", result);
 295         }
 296 }
 297
 298 /**
 299  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 300  * @nvmeq: The queue to use
 301  * @cmd: The command to send
 302  *
 303  * Safe to use from interrupt context
 304  */
 305 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 306                                                 struct nvme_command *cmd)
 307 {
 308         u16 tail = nvmeq->sq_tail;
 309
 310         if (nvmeq->sq_cmds_io)
 311                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 312         else
 313                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 314
 315         if (++tail == nvmeq->q_depth)
 316                 tail = 0;
 317         writel(tail, nvmeq->q_db);
 318         nvmeq->sq_tail = tail;
 319 }
 320
 321 static __le64 **iod_list(struct request *req)
 322 {
 323         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 324         return (__le64 **)(iod->sg + req->nr_phys_segments);
 325 }
 326
 327 static int nvme_init_iod(struct request *rq, struct nvme_dev *dev)
 328 {
 329         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 330         int nseg = rq->nr_phys_segments;
 331         unsigned size;
 332
 333         if (rq->cmd_flags & REQ_DISCARD)
 334                 size = sizeof(struct nvme_dsm_range);
 335         else
 336                 size = blk_rq_bytes(rq);
 337
 338         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 339                 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
 340                 if (!iod->sg)
 341                         return BLK_MQ_RQ_QUEUE_BUSY;
 342         } else {
 343                 iod->sg = iod->inline_sg;
 344         }
 345
 346         iod->aborted = 0;
 347         iod->npages = -1;
 348         iod->nents = 0;
 349         iod->length = size;
 350         return 0;
 351 }
 352
 353 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 354 {
 355         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 356         const int last_prp = dev->ctrl.page_size / 8 - 1;
 357         int i;
 358         __le64 **list = iod_list(req);
 359         dma_addr_t prp_dma = iod->first_dma;
 360
 361         if (iod->npages == 0)
 362                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 363         for (i = 0; i < iod->npages; i++) {
 364                 __le64 *prp_list = list[i];
 365                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 366                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 367                 prp_dma = next_prp_dma;
 368         }
 369
 370         if (iod->sg != iod->inline_sg)
 371                 kfree(iod->sg);
 372 }
 373
 374 #ifdef CONFIG_BLK_DEV_INTEGRITY
 375 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 376 {
 377         if (be32_to_cpu(pi->ref_tag) == v)
 378                 pi->ref_tag = cpu_to_be32(p);
 379 }
 380
 381 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 382 {
 383         if (be32_to_cpu(pi->ref_tag) == p)
 384                 pi->ref_tag = cpu_to_be32(v);
 385 }
 386
 387 /**
 388  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 389  *
 390  * The virtual start sector is the one that was originally submitted by the
 391  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 392  * start sector may be different. Remap protection information to match the
 393  * physical LBA on writes, and back to the original seed on reads.
 394  *
 395  * Type 0 and 3 do not have a ref tag, so no remapping required.
 396  */
 397 static void nvme_dif_remap(struct request *req,
 398                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 399 {
 400         struct nvme_ns *ns = req->rq_disk->private_data;
 401         struct bio_integrity_payload *bip;
 402         struct t10_pi_tuple *pi;
 403         void *p, *pmap;
 404         u32 i, nlb, ts, phys, virt;
 405
 406         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 407                 return;
 408
 409         bip = bio_integrity(req->bio);
 410         if (!bip)
 411                 return;
 412
 413         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 414
 415         p = pmap;
 416         virt = bip_get_seed(bip);
 417         phys = nvme_block_nr(ns, blk_rq_pos(req));
 418         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 419         ts = ns->disk->queue->integrity.tuple_size;
 420
 421         for (i = 0; i < nlb; i++, virt++, phys++) {
 422                 pi = (struct t10_pi_tuple *)p;
 423                 dif_swap(phys, virt, pi);
 424                 p += ts;
 425         }
 426         kunmap_atomic(pmap);
 427 }
 428 #else /* CONFIG_BLK_DEV_INTEGRITY */
 429 static void nvme_dif_remap(struct request *req,
 430                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 431 {
 432 }
 433 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 434 {
 435 }
 436 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 437 {
 438 }
 439 #endif
 440
 441 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req,
 442                 int total_len)
 443 {
 444         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 445         struct dma_pool *pool;
 446         int length = total_len;
 447         struct scatterlist *sg = iod->sg;
 448         int dma_len = sg_dma_len(sg);
 449         u64 dma_addr = sg_dma_address(sg);
 450         u32 page_size = dev->ctrl.page_size;
 451         int offset = dma_addr & (page_size - 1);
 452         __le64 *prp_list;
 453         __le64 **list = iod_list(req);
 454         dma_addr_t prp_dma;
 455         int nprps, i;
 456
 457         length -= (page_size - offset);
 458         if (length <= 0)
 459                 return true;
 460
 461         dma_len -= (page_size - offset);
 462         if (dma_len) {
 463                 dma_addr += (page_size - offset);
 464         } else {
 465                 sg = sg_next(sg);
 466                 dma_addr = sg_dma_address(sg);
 467                 dma_len = sg_dma_len(sg);
 468         }
 469
 470         if (length <= page_size) {
 471                 iod->first_dma = dma_addr;
 472                 return true;
 473         }
 474
 475         nprps = DIV_ROUND_UP(length, page_size);
 476         if (nprps <= (256 / 8)) {
 477                 pool = dev->prp_small_pool;
 478                 iod->npages = 0;
 479         } else {
 480                 pool = dev->prp_page_pool;
 481                 iod->npages = 1;
 482         }
 483
 484         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 485         if (!prp_list) {
 486                 iod->first_dma = dma_addr;
 487                 iod->npages = -1;
 488                 return false;
 489         }
 490         list[0] = prp_list;
 491         iod->first_dma = prp_dma;
 492         i = 0;
 493         for (;;) {
 494                 if (i == page_size >> 3) {
 495                         __le64 *old_prp_list = prp_list;
 496                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 497                         if (!prp_list)
 498                                 return false;
 499                         list[iod->npages++] = prp_list;
 500                         prp_list[0] = old_prp_list[i - 1];
 501                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 502                         i = 1;
 503                 }
 504                 prp_list[i++] = cpu_to_le64(dma_addr);
 505                 dma_len -= page_size;
 506                 dma_addr += page_size;
 507                 length -= page_size;
 508                 if (length <= 0)
 509                         break;
 510                 if (dma_len > 0)
 511                         continue;
 512                 BUG_ON(dma_len < 0);
 513                 sg = sg_next(sg);
 514                 dma_addr = sg_dma_address(sg);
 515                 dma_len = sg_dma_len(sg);
 516         }
 517
 518         return true;
 519 }
 520
 521 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
 522                 struct nvme_command *cmnd)
 523 {
 524         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 525         struct request_queue *q = req->q;
 526         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 527                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 528         int ret = BLK_MQ_RQ_QUEUE_ERROR;
 529
 530         sg_init_table(iod->sg, req->nr_phys_segments);
 531         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 532         if (!iod->nents)
 533                 goto out;
 534
 535         ret = BLK_MQ_RQ_QUEUE_BUSY;
 536         if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir))
 537                 goto out;
 538
 539         if (!nvme_setup_prps(dev, req, blk_rq_bytes(req)))
 540                 goto out_unmap;
 541
 542         ret = BLK_MQ_RQ_QUEUE_ERROR;
 543         if (blk_integrity_rq(req)) {
 544                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 545                         goto out_unmap;
 546
 547                 sg_init_table(&iod->meta_sg, 1);
 548                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 549                         goto out_unmap;
 550
 551                 if (rq_data_dir(req))
 552                         nvme_dif_remap(req, nvme_dif_prep);
 553
 554                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 555                         goto out_unmap;
 556         }
 557
 558         cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 559         cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
 560         if (blk_integrity_rq(req))
 561                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 562         return BLK_MQ_RQ_QUEUE_OK;
 563
 564 out_unmap:
 565         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 566 out:
 567         return ret;
 568 }
 569
 570 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 571 {
 572         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 573         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 574                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 575
 576         if (iod->nents) {
 577                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 578                 if (blk_integrity_rq(req)) {
 579                         if (!rq_data_dir(req))
 580                                 nvme_dif_remap(req, nvme_dif_complete);
 581                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 582                 }
 583         }
 584
 585         nvme_free_iod(dev, req);
 586 }
 587
 588 /*
 589  * We reuse the small pool to allocate the 16-byte range here as it is not
 590  * worth having a special pool for these or additional cases to handle freeing
 591  * the iod.
 592  */
 593 static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 594                 struct request *req, struct nvme_command *cmnd)
 595 {
 596         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 597         struct nvme_dsm_range *range;
 598
 599         range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
 600                                                 &iod->first_dma);
 601         if (!range)
 602                 return BLK_MQ_RQ_QUEUE_BUSY;
 603         iod_list(req)[0] = (__le64 *)range;
 604         iod->npages = 0;
 605
 606         range->cattr = cpu_to_le32(0);
 607         range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
 608         range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
 609
 610         memset(cmnd, 0, sizeof(*cmnd));
 611         cmnd->dsm.opcode = nvme_cmd_dsm;
 612         cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
 613         cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
 614         cmnd->dsm.nr = 0;
 615         cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
 616         return BLK_MQ_RQ_QUEUE_OK;
 617 }
 618
 619 /*
 620  * NOTE: ns is NULL when called on the admin queue.
 621  */
 622 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 623                          const struct blk_mq_queue_data *bd)
 624 {
 625         struct nvme_ns *ns = hctx->queue->queuedata;
 626         struct nvme_queue *nvmeq = hctx->driver_data;
 627         struct nvme_dev *dev = nvmeq->dev;
 628         struct request *req = bd->rq;
 629         struct nvme_command cmnd;
 630         int ret = BLK_MQ_RQ_QUEUE_OK;
 631
 632         /*
 633          * If formated with metadata, require the block layer provide a buffer
 634          * unless this namespace is formated such that the metadata can be
 635          * stripped/generated by the controller with PRACT=1.
 636          */
 637         if (ns && ns->ms && !blk_integrity_rq(req)) {
 638                 if (!(ns->pi_type && ns->ms == 8) &&
 639                                         req->cmd_type != REQ_TYPE_DRV_PRIV) {
 640                         blk_mq_end_request(req, -EFAULT);
 641                         return BLK_MQ_RQ_QUEUE_OK;
 642                 }
 643         }
 644
 645         ret = nvme_init_iod(req, dev);
 646         if (ret)
 647                 return ret;
 648
 649         if (req->cmd_flags & REQ_DISCARD) {
 650                 ret = nvme_setup_discard(nvmeq, ns, req, &cmnd);
 651         } else {
 652                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 653                         memcpy(&cmnd, req->cmd, sizeof(cmnd));
 654                 else if (req->cmd_flags & REQ_FLUSH)
 655                         nvme_setup_flush(ns, &cmnd);
 656                 else
 657                         nvme_setup_rw(ns, req, &cmnd);
 658
 659                 if (req->nr_phys_segments)
 660                         ret = nvme_map_data(dev, req, &cmnd);
 661         }
 662
 663         if (ret)
 664                 goto out;
 665
 666         cmnd.common.command_id = req->tag;
 667         blk_mq_start_request(req);
 668
 669         spin_lock_irq(&nvmeq->q_lock);
 670         __nvme_submit_cmd(nvmeq, &cmnd);
 671         nvme_process_cq(nvmeq);
 672         spin_unlock_irq(&nvmeq->q_lock);
 673         return BLK_MQ_RQ_QUEUE_OK;
 674 out:
 675         nvme_free_iod(dev, req);
 676         return ret;
 677 }
 678
 679 static void nvme_complete_rq(struct request *req)
 680 {
 681         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 682         struct nvme_dev *dev = iod->nvmeq->dev;
 683         int error = 0;
 684
 685         nvme_unmap_data(dev, req);
 686
 687         if (unlikely(req->errors)) {
 688                 if (nvme_req_needs_retry(req, req->errors)) {
 689                         nvme_requeue_req(req);
 690                         return;
 691                 }
 692
 693                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 694                         error = req->errors;
 695                 else
 696                         error = nvme_error_status(req->errors);
 697         }
 698
 699         if (unlikely(iod->aborted)) {
 700                 dev_warn(dev->ctrl.device,
 701                         "completing aborted command with status: %04x\n",
 702                         req->errors);
 703         }
 704
 705         blk_mq_end_request(req, error);
 706 }
 707
 708 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 709 {
 710         u16 head, phase;
 711
 712         head = nvmeq->cq_head;
 713         phase = nvmeq->cq_phase;
 714
 715         for (;;) {
 716                 struct nvme_completion cqe = nvmeq->cqes[head];
 717                 u16 status = le16_to_cpu(cqe.status);
 718                 struct request *req;
 719
 720                 if ((status & 1) != phase)
 721                         break;
 722                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 723                 if (++head == nvmeq->q_depth) {
 724                         head = 0;
 725                         phase = !phase;
 726                 }
 727
 728                 if (tag && *tag == cqe.command_id)
 729                         *tag = -1;
 730
 731                 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
 732                         dev_warn(nvmeq->dev->ctrl.device,
 733                                 "invalid id %d completed on queue %d\n",
 734                                 cqe.command_id, le16_to_cpu(cqe.sq_id));
 735                         continue;
 736                 }
 737
 738                 /*
 739                  * AEN requests are special as they don't time out and can
 740                  * survive any kind of queue freeze and often don't respond to
 741                  * aborts.  We don't even bother to allocate a struct request
 742                  * for them but rather special case them here.
 743                  */
 744                 if (unlikely(nvmeq->qid == 0 &&
 745                                 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 746                         nvme_complete_async_event(nvmeq->dev, &cqe);
 747                         continue;
 748                 }
 749
 750                 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
 751                 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
 752                         u32 result = le32_to_cpu(cqe.result);
 753                         req->special = (void *)(uintptr_t)result;
 754                 }
 755                 blk_mq_complete_request(req, status >> 1);
 756
 757         }
 758
 759         /* If the controller ignores the cq head doorbell and continuously
 760          * writes to the queue, it is theoretically possible to wrap around
 761          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 762          * requires that 0.1% of your interrupts are handled, so this isn't
 763          * a big problem.
 764          */
 765         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 766                 return;
 767
 768         if (likely(nvmeq->cq_vector >= 0))
 769                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 770         nvmeq->cq_head = head;
 771         nvmeq->cq_phase = phase;
 772
 773         nvmeq->cqe_seen = 1;
 774 }
 775
 776 static void nvme_process_cq(struct nvme_queue *nvmeq)
 777 {
 778         __nvme_process_cq(nvmeq, NULL);
 779 }
 780
 781 static irqreturn_t nvme_irq(int irq, void *data)
 782 {
 783         irqreturn_t result;
 784         struct nvme_queue *nvmeq = data;
 785         spin_lock(&nvmeq->q_lock);
 786         nvme_process_cq(nvmeq);
 787         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 788         nvmeq->cqe_seen = 0;
 789         spin_unlock(&nvmeq->q_lock);
 790         return result;
 791 }
 792
 793 static irqreturn_t nvme_irq_check(int irq, void *data)
 794 {
 795         struct nvme_queue *nvmeq = data;
 796         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 797         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 798                 return IRQ_NONE;
 799         return IRQ_WAKE_THREAD;
 800 }
 801
 802 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 803 {
 804         struct nvme_queue *nvmeq = hctx->driver_data;
 805
 806         if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
 807             nvmeq->cq_phase) {
 808                 spin_lock_irq(&nvmeq->q_lock);
 809                 __nvme_process_cq(nvmeq, &tag);
 810                 spin_unlock_irq(&nvmeq->q_lock);
 811
 812                 if (tag == -1)
 813                         return 1;
 814         }
 815
 816         return 0;
 817 }
 818
 819 static void nvme_submit_async_event(struct nvme_dev *dev)
 820 {
 821         struct nvme_command c;
 822
 823         memset(&c, 0, sizeof(c));
 824         c.common.opcode = nvme_admin_async_event;
 825         c.common.command_id = NVME_AQ_BLKMQ_DEPTH + --dev->ctrl.event_limit;
 826
 827         __nvme_submit_cmd(dev->queues[0], &c);
 828 }
 829
 830 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 831 {
 832         struct nvme_command c;
 833
 834         memset(&c, 0, sizeof(c));
 835         c.delete_queue.opcode = opcode;
 836         c.delete_queue.qid = cpu_to_le16(id);
 837
 838         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 839 }
 840
 841 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 842                                                 struct nvme_queue *nvmeq)
 843 {
 844         struct nvme_command c;
 845         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 846
 847         /*
 848          * Note: we (ab)use the fact the the prp fields survive if no data
 849          * is attached to the request.
 850          */
 851         memset(&c, 0, sizeof(c));
 852         c.create_cq.opcode = nvme_admin_create_cq;
 853         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 854         c.create_cq.cqid = cpu_to_le16(qid);
 855         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 856         c.create_cq.cq_flags = cpu_to_le16(flags);
 857         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 858
 859         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 860 }
 861
 862 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 863                                                 struct nvme_queue *nvmeq)
 864 {
 865         struct nvme_command c;
 866         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 867
 868         /*
 869          * Note: we (ab)use the fact the the prp fields survive if no data
 870          * is attached to the request.
 871          */
 872         memset(&c, 0, sizeof(c));
 873         c.create_sq.opcode = nvme_admin_create_sq;
 874         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 875         c.create_sq.sqid = cpu_to_le16(qid);
 876         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 877         c.create_sq.sq_flags = cpu_to_le16(flags);
 878         c.create_sq.cqid = cpu_to_le16(qid);
 879
 880         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 881 }
 882
 883 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 884 {
 885         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 886 }
 887
 888 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 889 {
 890         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 891 }
 892
 893 static void abort_endio(struct request *req, int error)
 894 {
 895         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 896         struct nvme_queue *nvmeq = iod->nvmeq;
 897         u32 result = (u32)(uintptr_t)req->special;
 898         u16 status = req->errors;
 899
 900         dev_warn(nvmeq->dev->ctrl.device,
 901                 "Abort status:%x result:%x", status, result);
 902         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 903
 904         blk_mq_free_request(req);
 905 }
 906
 907 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 908 {
 909         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 910         struct nvme_queue *nvmeq = iod->nvmeq;
 911         struct nvme_dev *dev = nvmeq->dev;
 912         struct request *abort_req;
 913         struct nvme_command cmd;
 914
 915         /*
 916          * Shutdown immediately if controller times out while starting. The
 917          * reset work will see the pci device disabled when it gets the forced
 918          * cancellation error. All outstanding requests are completed on
 919          * shutdown, so we return BLK_EH_HANDLED.
 920          */
 921         if (test_bit(NVME_CTRL_RESETTING, &dev->flags)) {
 922                 dev_warn(dev->ctrl.device,
 923                          "I/O %d QID %d timeout, disable controller\n",
 924                          req->tag, nvmeq->qid);
 925                 nvme_dev_disable(dev, false);
 926                 req->errors = NVME_SC_CANCELLED;
 927                 return BLK_EH_HANDLED;
 928         }
 929
 930         /*
 931          * Shutdown the controller immediately and schedule a reset if the
 932          * command was already aborted once before and still hasn't been
 933          * returned to the driver, or if this is the admin queue.
 934          */
 935         if (!nvmeq->qid || iod->aborted) {
 936                 dev_warn(dev->ctrl.device,
 937                          "I/O %d QID %d timeout, reset controller\n",
 938                          req->tag, nvmeq->qid);
 939                 nvme_dev_disable(dev, false);
 940                 queue_work(nvme_workq, &dev->reset_work);
 941
 942                 /*
 943                  * Mark the request as handled, since the inline shutdown
 944                  * forces all outstanding requests to complete.
 945                  */
 946                 req->errors = NVME_SC_CANCELLED;
 947                 return BLK_EH_HANDLED;
 948         }
 949
 950         iod->aborted = 1;
 951
 952         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
 953                 atomic_inc(&dev->ctrl.abort_limit);
 954                 return BLK_EH_RESET_TIMER;
 955         }
 956
 957         memset(&cmd, 0, sizeof(cmd));
 958         cmd.abort.opcode = nvme_admin_abort_cmd;
 959         cmd.abort.cid = req->tag;
 960         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
 961
 962         dev_warn(nvmeq->dev->ctrl.device,
 963                 "I/O %d QID %d timeout, aborting\n",
 964                  req->tag, nvmeq->qid);
 965
 966         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
 967                         BLK_MQ_REQ_NOWAIT);
 968         if (IS_ERR(abort_req)) {
 969                 atomic_inc(&dev->ctrl.abort_limit);
 970                 return BLK_EH_RESET_TIMER;
 971         }
 972
 973         abort_req->timeout = ADMIN_TIMEOUT;
 974         abort_req->end_io_data = NULL;
 975         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
 976
 977         /*
 978          * The aborted req will be completed on receiving the abort req.
 979          * We enable the timer again. If hit twice, it'll cause a device reset,
 980          * as the device then is in a faulty state.
 981          */
 982         return BLK_EH_RESET_TIMER;
 983 }
 984
 985 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
 986 {
 987         struct nvme_queue *nvmeq = data;
 988         int status;
 989
 990         if (!blk_mq_request_started(req))
 991                 return;
 992
 993         dev_warn(nvmeq->dev->ctrl.device,
 994                  "Cancelling I/O %d QID %d\n", req->tag, nvmeq->qid);
 995
 996         status = NVME_SC_ABORT_REQ;
 997         if (blk_queue_dying(req->q))
 998                 status |= NVME_SC_DNR;
 999         blk_mq_complete_request(req, status);
1000 }
1001
1002 static void nvme_free_queue(struct nvme_queue *nvmeq)
1003 {
1004         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1005                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1006         if (nvmeq->sq_cmds)
1007                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1008                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1009         kfree(nvmeq);
1010 }
1011
1012 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1013 {
1014         int i;
1015
1016         for (i = dev->queue_count - 1; i >= lowest; i--) {
1017                 struct nvme_queue *nvmeq = dev->queues[i];
1018                 dev->queue_count--;
1019                 dev->queues[i] = NULL;
1020                 nvme_free_queue(nvmeq);
1021         }
1022 }
1023
1024 /**
1025  * nvme_suspend_queue - put queue into suspended state
1026  * @nvmeq - queue to suspend
1027  */
1028 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1029 {
1030         int vector;
1031
1032         spin_lock_irq(&nvmeq->q_lock);
1033         if (nvmeq->cq_vector == -1) {
1034                 spin_unlock_irq(&nvmeq->q_lock);
1035                 return 1;
1036         }
1037         vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1038         nvmeq->dev->online_queues--;
1039         nvmeq->cq_vector = -1;
1040         spin_unlock_irq(&nvmeq->q_lock);
1041
1042         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1043                 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
1044
1045         irq_set_affinity_hint(vector, NULL);
1046         free_irq(vector, nvmeq);
1047
1048         return 0;
1049 }
1050
1051 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1052 {
1053         spin_lock_irq(&nvmeq->q_lock);
1054         if (nvmeq->tags && *nvmeq->tags)
1055                 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
1056         spin_unlock_irq(&nvmeq->q_lock);
1057 }
1058
1059 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1060 {
1061         struct nvme_queue *nvmeq = dev->queues[0];
1062
1063         if (!nvmeq)
1064                 return;
1065         if (nvme_suspend_queue(nvmeq))
1066                 return;
1067
1068         if (shutdown)
1069                 nvme_shutdown_ctrl(&dev->ctrl);
1070         else
1071                 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1072                                                 dev->bar + NVME_REG_CAP));
1073
1074         spin_lock_irq(&nvmeq->q_lock);
1075         nvme_process_cq(nvmeq);
1076         spin_unlock_irq(&nvmeq->q_lock);
1077 }
1078
1079 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1080                                 int entry_size)
1081 {
1082         int q_depth = dev->q_depth;
1083         unsigned q_size_aligned = roundup(q_depth * entry_size,
1084                                           dev->ctrl.page_size);
1085
1086         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1087                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1088                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1089                 q_depth = div_u64(mem_per_q, entry_size);
1090
1091                 /*
1092                  * Ensure the reduced q_depth is above some threshold where it
1093                  * would be better to map queues in system memory with the
1094                  * original depth
1095                  */
1096                 if (q_depth < 64)
1097                         return -ENOMEM;
1098         }
1099
1100         return q_depth;
1101 }
1102
1103 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1104                                 int qid, int depth)
1105 {
1106         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1107                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1108                                                       dev->ctrl.page_size);
1109                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1110                 nvmeq->sq_cmds_io = dev->cmb + offset;
1111         } else {
1112                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1113                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1114                 if (!nvmeq->sq_cmds)
1115                         return -ENOMEM;
1116         }
1117
1118         return 0;
1119 }
1120
1121 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1122                                                         int depth)
1123 {
1124         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1125         if (!nvmeq)
1126                 return NULL;
1127
1128         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1129                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1130         if (!nvmeq->cqes)
1131                 goto free_nvmeq;
1132
1133         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1134                 goto free_cqdma;
1135
1136         nvmeq->q_dmadev = dev->dev;
1137         nvmeq->dev = dev;
1138         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1139                         dev->ctrl.instance, qid);
1140         spin_lock_init(&nvmeq->q_lock);
1141         nvmeq->cq_head = 0;
1142         nvmeq->cq_phase = 1;
1143         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1144         nvmeq->q_depth = depth;
1145         nvmeq->qid = qid;
1146         nvmeq->cq_vector = -1;
1147         dev->queues[qid] = nvmeq;
1148
1149         /* make sure queue descriptor is set before queue count, for kthread */
1150         mb();
1151         dev->queue_count++;
1152
1153         return nvmeq;
1154
1155  free_cqdma:
1156         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1157                                                         nvmeq->cq_dma_addr);
1158  free_nvmeq:
1159         kfree(nvmeq);
1160         return NULL;
1161 }
1162
1163 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1164                                                         const char *name)
1165 {
1166         if (use_threaded_interrupts)
1167                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1168                                         nvme_irq_check, nvme_irq, IRQF_SHARED,
1169                                         name, nvmeq);
1170         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1171                                 IRQF_SHARED, name, nvmeq);
1172 }
1173
1174 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1175 {
1176         struct nvme_dev *dev = nvmeq->dev;
1177
1178         spin_lock_irq(&nvmeq->q_lock);
1179         nvmeq->sq_tail = 0;
1180         nvmeq->cq_head = 0;
1181         nvmeq->cq_phase = 1;
1182         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1183         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1184         dev->online_queues++;
1185         spin_unlock_irq(&nvmeq->q_lock);
1186 }
1187
1188 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1189 {
1190         struct nvme_dev *dev = nvmeq->dev;
1191         int result;
1192
1193         nvmeq->cq_vector = qid - 1;
1194         result = adapter_alloc_cq(dev, qid, nvmeq);
1195         if (result < 0)
1196                 return result;
1197
1198         result = adapter_alloc_sq(dev, qid, nvmeq);
1199         if (result < 0)
1200                 goto release_cq;
1201
1202         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1203         if (result < 0)
1204                 goto release_sq;
1205
1206         nvme_init_queue(nvmeq, qid);
1207         return result;
1208
1209  release_sq:
1210         adapter_delete_sq(dev, qid);
1211  release_cq:
1212         adapter_delete_cq(dev, qid);
1213         return result;
1214 }
1215
1216 static struct blk_mq_ops nvme_mq_admin_ops = {
1217         .queue_rq       = nvme_queue_rq,
1218         .complete       = nvme_complete_rq,
1219         .map_queue      = blk_mq_map_queue,
1220         .init_hctx      = nvme_admin_init_hctx,
1221         .exit_hctx      = nvme_admin_exit_hctx,
1222         .init_request   = nvme_admin_init_request,
1223         .timeout        = nvme_timeout,
1224 };
1225
1226 static struct blk_mq_ops nvme_mq_ops = {
1227         .queue_rq       = nvme_queue_rq,
1228         .complete       = nvme_complete_rq,
1229         .map_queue      = blk_mq_map_queue,
1230         .init_hctx      = nvme_init_hctx,
1231         .init_request   = nvme_init_request,
1232         .timeout        = nvme_timeout,
1233         .poll           = nvme_poll,
1234 };
1235
1236 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1237 {
1238         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1239                 blk_cleanup_queue(dev->ctrl.admin_q);
1240                 blk_mq_free_tag_set(&dev->admin_tagset);
1241         }
1242 }
1243
1244 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1245 {
1246         if (!dev->ctrl.admin_q) {
1247                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1248                 dev->admin_tagset.nr_hw_queues = 1;
1249
1250                 /*
1251                  * Subtract one to leave an empty queue entry for 'Full Queue'
1252                  * condition. See NVM-Express 1.2 specification, section 4.1.2.
1253                  */
1254                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1255                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1256                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1257                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1258                 dev->admin_tagset.driver_data = dev;
1259
1260                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1261                         return -ENOMEM;
1262
1263                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1264                 if (IS_ERR(dev->ctrl.admin_q)) {
1265                         blk_mq_free_tag_set(&dev->admin_tagset);
1266                         return -ENOMEM;
1267                 }
1268                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1269                         nvme_dev_remove_admin(dev);
1270                         dev->ctrl.admin_q = NULL;
1271                         return -ENODEV;
1272                 }
1273         } else
1274                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1275
1276         return 0;
1277 }
1278
1279 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1280 {
1281         int result;
1282         u32 aqa;
1283         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1284         struct nvme_queue *nvmeq;
1285
1286         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ?
1287                                                 NVME_CAP_NSSRC(cap) : 0;
1288
1289         if (dev->subsystem &&
1290             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1291                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1292
1293         result = nvme_disable_ctrl(&dev->ctrl, cap);
1294         if (result < 0)
1295                 return result;
1296
1297         nvmeq = dev->queues[0];
1298         if (!nvmeq) {
1299                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1300                 if (!nvmeq)
1301                         return -ENOMEM;
1302         }
1303
1304         aqa = nvmeq->q_depth - 1;
1305         aqa |= aqa << 16;
1306
1307         writel(aqa, dev->bar + NVME_REG_AQA);
1308         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1309         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1310
1311         result = nvme_enable_ctrl(&dev->ctrl, cap);
1312         if (result)
1313                 goto free_nvmeq;
1314
1315         nvmeq->cq_vector = 0;
1316         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1317         if (result) {
1318                 nvmeq->cq_vector = -1;
1319                 goto free_nvmeq;
1320         }
1321
1322         return result;
1323
1324  free_nvmeq:
1325         nvme_free_queues(dev, 0);
1326         return result;
1327 }
1328
1329 static int nvme_kthread(void *data)
1330 {
1331         struct nvme_dev *dev, *next;
1332
1333         while (!kthread_should_stop()) {
1334                 set_current_state(TASK_INTERRUPTIBLE);
1335                 spin_lock(&dev_list_lock);
1336                 list_for_each_entry_safe(dev, next, &dev_list, node) {
1337                         int i;
1338                         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1339
1340                         /*
1341                          * Skip controllers currently under reset.
1342                          */
1343                         if (work_pending(&dev->reset_work) || work_busy(&dev->reset_work))
1344                                 continue;
1345
1346                         if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
1347                                                         csts & NVME_CSTS_CFS) {
1348                                 if (queue_work(nvme_workq, &dev->reset_work)) {
1349                                         dev_warn(dev->ctrl.device,
1350                                                 "Failed status: %x, reset controller\n",
1351                                                 readl(dev->bar + NVME_REG_CSTS));
1352                                 }
1353                                 continue;
1354                         }
1355                         for (i = 0; i < dev->queue_count; i++) {
1356                                 struct nvme_queue *nvmeq = dev->queues[i];
1357                                 if (!nvmeq)
1358                                         continue;
1359                                 spin_lock_irq(&nvmeq->q_lock);
1360                                 nvme_process_cq(nvmeq);
1361
1362                                 while (i == 0 && dev->ctrl.event_limit > 0)
1363                                         nvme_submit_async_event(dev);
1364                                 spin_unlock_irq(&nvmeq->q_lock);
1365                         }
1366                 }
1367                 spin_unlock(&dev_list_lock);
1368                 schedule_timeout(round_jiffies_relative(HZ));
1369         }
1370         return 0;
1371 }
1372
1373 static int nvme_create_io_queues(struct nvme_dev *dev)
1374 {
1375         unsigned i, max;
1376         int ret = 0;
1377
1378         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1379                 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1380                         ret = -ENOMEM;
1381                         break;
1382                 }
1383         }
1384
1385         max = min(dev->max_qid, dev->queue_count - 1);
1386         for (i = dev->online_queues; i <= max; i++) {
1387                 ret = nvme_create_queue(dev->queues[i], i);
1388                 if (ret) {
1389                         nvme_free_queues(dev, i);
1390                         break;
1391                 }
1392         }
1393
1394         /*
1395          * Ignore failing Create SQ/CQ commands, we can continue with less
1396          * than the desired aount of queues, and even a controller without
1397          * I/O queues an still be used to issue admin commands.  This might
1398          * be useful to upgrade a buggy firmware for example.
1399          */
1400         return ret >= 0 ? 0 : ret;
1401 }
1402
1403 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1404 {
1405         u64 szu, size, offset;
1406         u32 cmbloc;
1407         resource_size_t bar_size;
1408         struct pci_dev *pdev = to_pci_dev(dev->dev);
1409         void __iomem *cmb;
1410         dma_addr_t dma_addr;
1411
1412         if (!use_cmb_sqes)
1413                 return NULL;
1414
1415         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1416         if (!(NVME_CMB_SZ(dev->cmbsz)))
1417                 return NULL;
1418
1419         cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1420
1421         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1422         size = szu * NVME_CMB_SZ(dev->cmbsz);
1423         offset = szu * NVME_CMB_OFST(cmbloc);
1424         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
1425
1426         if (offset > bar_size)
1427                 return NULL;
1428
1429         /*
1430          * Controllers may support a CMB size larger than their BAR,
1431          * for example, due to being behind a bridge. Reduce the CMB to
1432          * the reported size of the BAR
1433          */
1434         if (size > bar_size - offset)
1435                 size = bar_size - offset;
1436
1437         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
1438         cmb = ioremap_wc(dma_addr, size);
1439         if (!cmb)
1440                 return NULL;
1441
1442         dev->cmb_dma_addr = dma_addr;
1443         dev->cmb_size = size;
1444         return cmb;
1445 }
1446
1447 static inline void nvme_release_cmb(struct nvme_dev *dev)
1448 {
1449         if (dev->cmb) {
1450                 iounmap(dev->cmb);
1451                 dev->cmb = NULL;
1452         }
1453 }
1454
1455 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1456 {
1457         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1458 }
1459
1460 static int nvme_setup_io_queues(struct nvme_dev *dev)
1461 {
1462         struct nvme_queue *adminq = dev->queues[0];
1463         struct pci_dev *pdev = to_pci_dev(dev->dev);
1464         int result, i, vecs, nr_io_queues, size;
1465
1466         nr_io_queues = num_possible_cpus();
1467         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1468         if (result < 0)
1469                 return result;
1470
1471         /*
1472          * Degraded controllers might return an error when setting the queue
1473          * count.  We still want to be able to bring them online and offer
1474          * access to the admin queue, as that might be only way to fix them up.
1475          */
1476         if (result > 0) {
1477                 dev_err(dev->ctrl.device,
1478                         "Could not set queue count (%d)\n", result);
1479                 nr_io_queues = 0;
1480                 result = 0;
1481         }
1482
1483         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1484                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1485                                 sizeof(struct nvme_command));
1486                 if (result > 0)
1487                         dev->q_depth = result;
1488                 else
1489                         nvme_release_cmb(dev);
1490         }
1491
1492         size = db_bar_size(dev, nr_io_queues);
1493         if (size > 8192) {
1494                 iounmap(dev->bar);
1495                 do {
1496                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1497                         if (dev->bar)
1498                                 break;
1499                         if (!--nr_io_queues)
1500                                 return -ENOMEM;
1501                         size = db_bar_size(dev, nr_io_queues);
1502                 } while (1);
1503                 dev->dbs = dev->bar + 4096;
1504                 adminq->q_db = dev->dbs;
1505         }
1506
1507         /* Deregister the admin queue's interrupt */
1508         free_irq(dev->entry[0].vector, adminq);
1509
1510         /*
1511          * If we enable msix early due to not intx, disable it again before
1512          * setting up the full range we need.
1513          */
1514         if (!pdev->irq)
1515                 pci_disable_msix(pdev);
1516
1517         for (i = 0; i < nr_io_queues; i++)
1518                 dev->entry[i].entry = i;
1519         vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
1520         if (vecs < 0) {
1521                 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
1522                 if (vecs < 0) {
1523                         vecs = 1;
1524                 } else {
1525                         for (i = 0; i < vecs; i++)
1526                                 dev->entry[i].vector = i + pdev->irq;
1527                 }
1528         }
1529
1530         /*
1531          * Should investigate if there's a performance win from allocating
1532          * more queues than interrupt vectors; it might allow the submission
1533          * path to scale better, even if the receive path is limited by the
1534          * number of interrupts.
1535          */
1536         nr_io_queues = vecs;
1537         dev->max_qid = nr_io_queues;
1538
1539         result = queue_request_irq(dev, adminq, adminq->irqname);
1540         if (result) {
1541                 adminq->cq_vector = -1;
1542                 goto free_queues;
1543         }
1544         return nvme_create_io_queues(dev);
1545
1546  free_queues:
1547         nvme_free_queues(dev, 1);
1548         return result;
1549 }
1550
1551 static void nvme_set_irq_hints(struct nvme_dev *dev)
1552 {
1553         struct nvme_queue *nvmeq;
1554         int i;
1555
1556         for (i = 0; i < dev->online_queues; i++) {
1557                 nvmeq = dev->queues[i];
1558
1559                 if (!nvmeq->tags || !(*nvmeq->tags))
1560                         continue;
1561
1562                 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
1563                                         blk_mq_tags_cpumask(*nvmeq->tags));
1564         }
1565 }
1566
1567 static void nvme_dev_scan(struct work_struct *work)
1568 {
1569         struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
1570
1571         if (!dev->tagset.tags)
1572                 return;
1573         nvme_scan_namespaces(&dev->ctrl);
1574         nvme_set_irq_hints(dev);
1575 }
1576
1577 static void nvme_del_queue_end(struct request *req, int error)
1578 {
1579         struct nvme_queue *nvmeq = req->end_io_data;
1580
1581         blk_mq_free_request(req);
1582         complete(&nvmeq->dev->ioq_wait);
1583 }
1584
1585 static void nvme_del_cq_end(struct request *req, int error)
1586 {
1587         struct nvme_queue *nvmeq = req->end_io_data;
1588
1589         if (!error) {
1590                 unsigned long flags;
1591
1592                 spin_lock_irqsave(&nvmeq->q_lock, flags);
1593                 nvme_process_cq(nvmeq);
1594                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1595         }
1596
1597         nvme_del_queue_end(req, error);
1598 }
1599
1600 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1601 {
1602         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1603         struct request *req;
1604         struct nvme_command cmd;
1605
1606         memset(&cmd, 0, sizeof(cmd));
1607         cmd.delete_queue.opcode = opcode;
1608         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1609
1610         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
1611         if (IS_ERR(req))
1612                 return PTR_ERR(req);
1613
1614         req->timeout = ADMIN_TIMEOUT;
1615         req->end_io_data = nvmeq;
1616
1617         blk_execute_rq_nowait(q, NULL, req, false,
1618                         opcode == nvme_admin_delete_cq ?
1619                                 nvme_del_cq_end : nvme_del_queue_end);
1620         return 0;
1621 }
1622
1623 static void nvme_disable_io_queues(struct nvme_dev *dev)
1624 {
1625         int pass;
1626         unsigned long timeout;
1627         u8 opcode = nvme_admin_delete_sq;
1628
1629         for (pass = 0; pass < 2; pass++) {
1630                 int sent = 0, i = dev->queue_count - 1;
1631
1632                 reinit_completion(&dev->ioq_wait);
1633  retry:
1634                 timeout = ADMIN_TIMEOUT;
1635                 for (; i > 0; i--) {
1636                         struct nvme_queue *nvmeq = dev->queues[i];
1637
1638                         if (!pass)
1639                                 nvme_suspend_queue(nvmeq);
1640                         if (nvme_delete_queue(nvmeq, opcode))
1641                                 break;
1642                         ++sent;
1643                 }
1644                 while (sent--) {
1645                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1646                         if (timeout == 0)
1647                                 return;
1648                         if (i)
1649                                 goto retry;
1650                 }
1651                 opcode = nvme_admin_delete_cq;
1652         }
1653 }
1654
1655 /*
1656  * Return: error value if an error occurred setting up the queues or calling
1657  * Identify Device.  0 if these succeeded, even if adding some of the
1658  * namespaces failed.  At the moment, these failures are silent.  TBD which
1659  * failures should be reported.
1660  */
1661 static int nvme_dev_add(struct nvme_dev *dev)
1662 {
1663         if (!dev->ctrl.tagset) {
1664                 dev->tagset.ops = &nvme_mq_ops;
1665                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1666                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1667                 dev->tagset.numa_node = dev_to_node(dev->dev);
1668                 dev->tagset.queue_depth =
1669                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1670                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1671                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1672                 dev->tagset.driver_data = dev;
1673
1674                 if (blk_mq_alloc_tag_set(&dev->tagset))
1675                         return 0;
1676                 dev->ctrl.tagset = &dev->tagset;
1677         } else {
1678                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1679
1680                 /* Free previously allocated queues that are no longer usable */
1681                 nvme_free_queues(dev, dev->online_queues);
1682         }
1683
1684         queue_work(nvme_workq, &dev->scan_work);
1685         return 0;
1686 }
1687
1688 static int nvme_dev_map(struct nvme_dev *dev)
1689 {
1690         u64 cap;
1691         int bars, result = -ENOMEM;
1692         struct pci_dev *pdev = to_pci_dev(dev->dev);
1693
1694         if (pci_enable_device_mem(pdev))
1695                 return result;
1696
1697         dev->entry[0].vector = pdev->irq;
1698         pci_set_master(pdev);
1699         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1700         if (!bars)
1701                 goto disable_pci;
1702
1703         if (pci_request_selected_regions(pdev, bars, "nvme"))
1704                 goto disable_pci;
1705
1706         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1707             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1708                 goto disable;
1709
1710         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1711         if (!dev->bar)
1712                 goto disable;
1713
1714         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1715                 result = -ENODEV;
1716                 goto unmap;
1717         }
1718
1719         /*
1720          * Some devices don't advertse INTx interrupts, pre-enable a single
1721          * MSIX vec for setup. We'll adjust this later.
1722          */
1723         if (!pdev->irq) {
1724                 result = pci_enable_msix(pdev, dev->entry, 1);
1725                 if (result < 0)
1726                         goto unmap;
1727         }
1728
1729         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1730
1731         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1732         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1733         dev->dbs = dev->bar + 4096;
1734
1735         /*
1736          * Temporary fix for the Apple controller found in the MacBook8,1 and
1737          * some MacBook7,1 to avoid controller resets and data loss.
1738          */
1739         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1740                 dev->q_depth = 2;
1741                 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1742                         "queue depth=%u to work around controller resets\n",
1743                         dev->q_depth);
1744         }
1745
1746         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2))
1747                 dev->cmb = nvme_map_cmb(dev);
1748
1749         pci_enable_pcie_error_reporting(pdev);
1750         pci_save_state(pdev);
1751         return 0;
1752
1753  unmap:
1754         iounmap(dev->bar);
1755         dev->bar = NULL;
1756  disable:
1757         pci_release_regions(pdev);
1758  disable_pci:
1759         pci_disable_device(pdev);
1760         return result;
1761 }
1762
1763 static void nvme_dev_unmap(struct nvme_dev *dev)
1764 {
1765         struct pci_dev *pdev = to_pci_dev(dev->dev);
1766
1767         if (pdev->msi_enabled)
1768                 pci_disable_msi(pdev);
1769         else if (pdev->msix_enabled)
1770                 pci_disable_msix(pdev);
1771
1772         if (dev->bar) {
1773                 iounmap(dev->bar);
1774                 dev->bar = NULL;
1775                 pci_release_regions(pdev);
1776         }
1777
1778         if (pci_is_enabled(pdev)) {
1779                 pci_disable_pcie_error_reporting(pdev);
1780                 pci_disable_device(pdev);
1781         }
1782 }
1783
1784 static int nvme_dev_list_add(struct nvme_dev *dev)
1785 {
1786         bool start_thread = false;
1787
1788         spin_lock(&dev_list_lock);
1789         if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
1790                 start_thread = true;
1791                 nvme_thread = NULL;
1792         }
1793         list_add(&dev->node, &dev_list);
1794         spin_unlock(&dev_list_lock);
1795
1796         if (start_thread) {
1797                 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1798                 wake_up_all(&nvme_kthread_wait);
1799         } else
1800                 wait_event_killable(nvme_kthread_wait, nvme_thread);
1801
1802         if (IS_ERR_OR_NULL(nvme_thread))
1803                 return nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
1804
1805         return 0;
1806 }
1807
1808 /*
1809 * Remove the node from the device list and check
1810 * for whether or not we need to stop the nvme_thread.
1811 */
1812 static void nvme_dev_list_remove(struct nvme_dev *dev)
1813 {
1814         struct task_struct *tmp = NULL;
1815
1816         spin_lock(&dev_list_lock);
1817         list_del_init(&dev->node);
1818         if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
1819                 tmp = nvme_thread;
1820                 nvme_thread = NULL;
1821         }
1822         spin_unlock(&dev_list_lock);
1823
1824         if (tmp)
1825                 kthread_stop(tmp);
1826 }
1827
1828 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1829 {
1830         int i;
1831         u32 csts = -1;
1832
1833         nvme_dev_list_remove(dev);
1834
1835         mutex_lock(&dev->shutdown_lock);
1836         if (dev->bar) {
1837                 nvme_stop_queues(&dev->ctrl);
1838                 csts = readl(dev->bar + NVME_REG_CSTS);
1839         }
1840         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
1841                 for (i = dev->queue_count - 1; i >= 0; i--) {
1842                         struct nvme_queue *nvmeq = dev->queues[i];
1843                         nvme_suspend_queue(nvmeq);
1844                 }
1845         } else {
1846                 nvme_disable_io_queues(dev);
1847                 nvme_disable_admin_queue(dev, shutdown);
1848         }
1849         nvme_dev_unmap(dev);
1850
1851         for (i = dev->queue_count - 1; i >= 0; i--)
1852                 nvme_clear_queue(dev->queues[i]);
1853         mutex_unlock(&dev->shutdown_lock);
1854 }
1855
1856 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1857 {
1858         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1859                                                 PAGE_SIZE, PAGE_SIZE, 0);
1860         if (!dev->prp_page_pool)
1861                 return -ENOMEM;
1862
1863         /* Optimisation for I/Os between 4k and 128k */
1864         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1865                                                 256, 256, 0);
1866         if (!dev->prp_small_pool) {
1867                 dma_pool_destroy(dev->prp_page_pool);
1868                 return -ENOMEM;
1869         }
1870         return 0;
1871 }
1872
1873 static void nvme_release_prp_pools(struct nvme_dev *dev)
1874 {
1875         dma_pool_destroy(dev->prp_page_pool);
1876         dma_pool_destroy(dev->prp_small_pool);
1877 }
1878
1879 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1880 {
1881         struct nvme_dev *dev = to_nvme_dev(ctrl);
1882
1883         put_device(dev->dev);
1884         if (dev->tagset.tags)
1885                 blk_mq_free_tag_set(&dev->tagset);
1886         if (dev->ctrl.admin_q)
1887                 blk_put_queue(dev->ctrl.admin_q);
1888         kfree(dev->queues);
1889         kfree(dev->entry);
1890         kfree(dev);
1891 }
1892
1893 static void nvme_reset_work(struct work_struct *work)
1894 {
1895         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1896         int result;
1897
1898         if (WARN_ON(test_bit(NVME_CTRL_RESETTING, &dev->flags)))
1899                 goto out;
1900
1901         /*
1902          * If we're called to reset a live controller first shut it down before
1903          * moving on.
1904          */
1905         if (dev->bar)
1906                 nvme_dev_disable(dev, false);
1907
1908         set_bit(NVME_CTRL_RESETTING, &dev->flags);
1909
1910         result = nvme_dev_map(dev);
1911         if (result)
1912                 goto out;
1913
1914         result = nvme_configure_admin_queue(dev);
1915         if (result)
1916                 goto unmap;
1917
1918         nvme_init_queue(dev->queues[0], 0);
1919         result = nvme_alloc_admin_tags(dev);
1920         if (result)
1921                 goto disable;
1922
1923         result = nvme_init_identify(&dev->ctrl);
1924         if (result)
1925                 goto free_tags;
1926
1927         result = nvme_setup_io_queues(dev);
1928         if (result)
1929                 goto free_tags;
1930
1931         dev->ctrl.event_limit = NVME_NR_AEN_COMMANDS;
1932
1933         result = nvme_dev_list_add(dev);
1934         if (result)
1935                 goto remove;
1936
1937         /*
1938          * Keep the controller around but remove all namespaces if we don't have
1939          * any working I/O queue.
1940          */
1941         if (dev->online_queues < 2) {
1942                 dev_warn(dev->ctrl.device, "IO queues not created\n");
1943                 nvme_remove_namespaces(&dev->ctrl);
1944         } else {
1945                 nvme_start_queues(&dev->ctrl);
1946                 nvme_dev_add(dev);
1947         }
1948
1949         clear_bit(NVME_CTRL_RESETTING, &dev->flags);
1950         return;
1951
1952  remove:
1953         nvme_dev_list_remove(dev);
1954  free_tags:
1955         nvme_dev_remove_admin(dev);
1956         blk_put_queue(dev->ctrl.admin_q);
1957         dev->ctrl.admin_q = NULL;
1958         dev->queues[0]->tags = NULL;
1959  disable:
1960         nvme_disable_admin_queue(dev, false);
1961  unmap:
1962         nvme_dev_unmap(dev);
1963  out:
1964         nvme_remove_dead_ctrl(dev);
1965 }
1966
1967 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1968 {
1969         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1970         struct pci_dev *pdev = to_pci_dev(dev->dev);
1971
1972         if (pci_get_drvdata(pdev))
1973                 pci_stop_and_remove_bus_device_locked(pdev);
1974         nvme_put_ctrl(&dev->ctrl);
1975 }
1976
1977 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
1978 {
1979         dev_warn(dev->ctrl.device, "Removing after probe failure\n");
1980         kref_get(&dev->ctrl.kref);
1981         if (!schedule_work(&dev->remove_work))
1982                 nvme_put_ctrl(&dev->ctrl);
1983 }
1984
1985 static int nvme_reset(struct nvme_dev *dev)
1986 {
1987         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1988                 return -ENODEV;
1989
1990         if (!queue_work(nvme_workq, &dev->reset_work))
1991                 return -EBUSY;
1992
1993         flush_work(&dev->reset_work);
1994         return 0;
1995 }
1996
1997 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
1998 {
1999         *val = readl(to_nvme_dev(ctrl)->bar + off);
2000         return 0;
2001 }
2002
2003 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2004 {
2005         writel(val, to_nvme_dev(ctrl)->bar + off);
2006         return 0;
2007 }
2008
2009 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2010 {
2011         *val = readq(to_nvme_dev(ctrl)->bar + off);
2012         return 0;
2013 }
2014
2015 static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl)
2016 {
2017         struct nvme_dev *dev = to_nvme_dev(ctrl);
2018
2019         return !dev->bar || dev->online_queues < 2;
2020 }
2021
2022 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
2023 {
2024         return nvme_reset(to_nvme_dev(ctrl));
2025 }
2026
2027 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2028         .module                 = THIS_MODULE,
2029         .reg_read32             = nvme_pci_reg_read32,
2030         .reg_write32            = nvme_pci_reg_write32,
2031         .reg_read64             = nvme_pci_reg_read64,
2032         .io_incapable           = nvme_pci_io_incapable,
2033         .reset_ctrl             = nvme_pci_reset_ctrl,
2034         .free_ctrl              = nvme_pci_free_ctrl,
2035 };
2036
2037 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2038 {
2039         int node, result = -ENOMEM;
2040         struct nvme_dev *dev;
2041
2042         node = dev_to_node(&pdev->dev);
2043         if (node == NUMA_NO_NODE)
2044                 set_dev_node(&pdev->dev, 0);
2045
2046         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2047         if (!dev)
2048                 return -ENOMEM;
2049         dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2050                                                         GFP_KERNEL, node);
2051         if (!dev->entry)
2052                 goto free;
2053         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2054                                                         GFP_KERNEL, node);
2055         if (!dev->queues)
2056                 goto free;
2057
2058         dev->dev = get_device(&pdev->dev);
2059         pci_set_drvdata(pdev, dev);
2060
2061         INIT_LIST_HEAD(&dev->node);
2062         INIT_WORK(&dev->scan_work, nvme_dev_scan);
2063         INIT_WORK(&dev->reset_work, nvme_reset_work);
2064         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2065         mutex_init(&dev->shutdown_lock);
2066         init_completion(&dev->ioq_wait);
2067
2068         result = nvme_setup_prp_pools(dev);
2069         if (result)
2070                 goto put_pci;
2071
2072         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2073                         id->driver_data);
2074         if (result)
2075                 goto release_pools;
2076
2077         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2078
2079         queue_work(nvme_workq, &dev->reset_work);
2080         return 0;
2081
2082  release_pools:
2083         nvme_release_prp_pools(dev);
2084  put_pci:
2085         put_device(dev->dev);
2086  free:
2087         kfree(dev->queues);
2088         kfree(dev->entry);
2089         kfree(dev);
2090         return result;
2091 }
2092
2093 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2094 {
2095         struct nvme_dev *dev = pci_get_drvdata(pdev);
2096
2097         if (prepare)
2098                 nvme_dev_disable(dev, false);
2099         else
2100                 queue_work(nvme_workq, &dev->reset_work);
2101 }
2102
2103 static void nvme_shutdown(struct pci_dev *pdev)
2104 {
2105         struct nvme_dev *dev = pci_get_drvdata(pdev);
2106         nvme_dev_disable(dev, true);
2107 }
2108
2109 static void nvme_remove(struct pci_dev *pdev)
2110 {
2111         struct nvme_dev *dev = pci_get_drvdata(pdev);
2112
2113         spin_lock(&dev_list_lock);
2114         list_del_init(&dev->node);
2115         spin_unlock(&dev_list_lock);
2116
2117         pci_set_drvdata(pdev, NULL);
2118         flush_work(&dev->reset_work);
2119         flush_work(&dev->scan_work);
2120         nvme_remove_namespaces(&dev->ctrl);
2121         nvme_uninit_ctrl(&dev->ctrl);
2122         nvme_dev_disable(dev, true);
2123         nvme_dev_remove_admin(dev);
2124         nvme_free_queues(dev, 0);
2125         nvme_release_cmb(dev);
2126         nvme_release_prp_pools(dev);
2127         nvme_put_ctrl(&dev->ctrl);
2128 }
2129
2130 #ifdef CONFIG_PM_SLEEP
2131 static int nvme_suspend(struct device *dev)
2132 {
2133         struct pci_dev *pdev = to_pci_dev(dev);
2134         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2135
2136         nvme_dev_disable(ndev, true);
2137         return 0;
2138 }
2139
2140 static int nvme_resume(struct device *dev)
2141 {
2142         struct pci_dev *pdev = to_pci_dev(dev);
2143         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2144
2145         queue_work(nvme_workq, &ndev->reset_work);
2146         return 0;
2147 }
2148 #endif
2149
2150 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2151
2152 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2153                                                 pci_channel_state_t state)
2154 {
2155         struct nvme_dev *dev = pci_get_drvdata(pdev);
2156
2157         /*
2158          * A frozen channel requires a reset. When detected, this method will
2159          * shutdown the controller to quiesce. The controller will be restarted
2160          * after the slot reset through driver's slot_reset callback.
2161          */
2162         dev_warn(dev->ctrl.device, "error detected: state:%d\n", state);
2163         switch (state) {
2164         case pci_channel_io_normal:
2165                 return PCI_ERS_RESULT_CAN_RECOVER;
2166         case pci_channel_io_frozen:
2167                 nvme_dev_disable(dev, false);
2168                 return PCI_ERS_RESULT_NEED_RESET;
2169         case pci_channel_io_perm_failure:
2170                 return PCI_ERS_RESULT_DISCONNECT;
2171         }
2172         return PCI_ERS_RESULT_NEED_RESET;
2173 }
2174
2175 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2176 {
2177         struct nvme_dev *dev = pci_get_drvdata(pdev);
2178
2179         dev_info(dev->ctrl.device, "restart after slot reset\n");
2180         pci_restore_state(pdev);
2181         queue_work(nvme_workq, &dev->reset_work);
2182         return PCI_ERS_RESULT_RECOVERED;
2183 }
2184
2185 static void nvme_error_resume(struct pci_dev *pdev)
2186 {
2187         pci_cleanup_aer_uncorrect_error_status(pdev);
2188 }
2189
2190 static const struct pci_error_handlers nvme_err_handler = {
2191         .error_detected = nvme_error_detected,
2192         .slot_reset     = nvme_slot_reset,
2193         .resume         = nvme_error_resume,
2194         .reset_notify   = nvme_reset_notify,
2195 };
2196
2197 /* Move to pci_ids.h later */
2198 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
2199
2200 static const struct pci_device_id nvme_id_table[] = {
2201         { PCI_VDEVICE(INTEL, 0x0953),
2202                 .driver_data = NVME_QUIRK_STRIPE_SIZE, },
2203         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2204                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2205         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2206         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2207         { 0, }
2208 };
2209 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2210
2211 static struct pci_driver nvme_driver = {
2212         .name           = "nvme",
2213         .id_table       = nvme_id_table,
2214         .probe          = nvme_probe,
2215         .remove         = nvme_remove,
2216         .shutdown       = nvme_shutdown,
2217         .driver         = {
2218                 .pm     = &nvme_dev_pm_ops,
2219         },
2220         .err_handler    = &nvme_err_handler,
2221 };
2222
2223 static int __init nvme_init(void)
2224 {
2225         int result;
2226
2227         init_waitqueue_head(&nvme_kthread_wait);
2228
2229         nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2230         if (!nvme_workq)
2231                 return -ENOMEM;
2232
2233         result = pci_register_driver(&nvme_driver);
2234         if (result)
2235                 destroy_workqueue(nvme_workq);
2236         return result;
2237 }
2238
2239 static void __exit nvme_exit(void)
2240 {
2241         pci_unregister_driver(&nvme_driver);
2242         destroy_workqueue(nvme_workq);
2243         BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
2244         _nvme_check_size();
2245 }
2246
2247 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2248 MODULE_LICENSE("GPL");
2249 MODULE_VERSION("1.0");
2250 module_init(nvme_init);
2251 module_exit(nvme_exit);