2 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/gpio.h>
14 #include <linux/module.h>
15 #include <linux/mbus.h>
16 #include <linux/msi.h>
17 #include <linux/slab.h>
18 #include <linux/platform_device.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_pci.h>
23 #include <linux/of_platform.h>
26 * PCIe unit register offsets.
28 #define PCIE_DEV_ID_OFF 0x0000
29 #define PCIE_CMD_OFF 0x0004
30 #define PCIE_DEV_REV_OFF 0x0008
31 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
32 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
33 #define PCIE_HEADER_LOG_4_OFF 0x0128
34 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
35 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
36 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
37 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
38 #define PCIE_WIN5_CTRL_OFF 0x1880
39 #define PCIE_WIN5_BASE_OFF 0x1884
40 #define PCIE_WIN5_REMAP_OFF 0x188c
41 #define PCIE_CONF_ADDR_OFF 0x18f8
42 #define PCIE_CONF_ADDR_EN 0x80000000
43 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
44 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
45 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
46 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
47 #define PCIE_CONF_ADDR(bus, devfn, where) \
48 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
49 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
51 #define PCIE_CONF_DATA_OFF 0x18fc
52 #define PCIE_MASK_OFF 0x1910
53 #define PCIE_MASK_ENABLE_INTS 0x0f000000
54 #define PCIE_CTRL_OFF 0x1a00
55 #define PCIE_CTRL_X1_MODE 0x0001
56 #define PCIE_STAT_OFF 0x1a04
57 #define PCIE_STAT_BUS 0xff00
58 #define PCIE_STAT_DEV 0x1f0000
59 #define PCIE_STAT_LINK_DOWN BIT(0)
60 #define PCIE_DEBUG_CTRL 0x1a60
61 #define PCIE_DEBUG_SOFT_RESET BIT(20)
64 * This product ID is registered by Marvell, and used when the Marvell
65 * SoC is not the root complex, but an endpoint on the PCIe bus. It is
66 * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
69 #define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
71 /* PCI configuration space of a PCI-to-PCI bridge */
72 struct mvebu_sw_pci_bridge {
87 u8 secondary_latency_timer;
104 struct mvebu_pcie_port;
106 /* Structure representing all PCIe interfaces */
108 struct platform_device *pdev;
109 struct mvebu_pcie_port *ports;
110 struct msi_chip *msi;
112 struct resource realio;
114 struct resource busn;
118 /* Structure representing one PCIe interface */
119 struct mvebu_pcie_port {
122 spinlock_t conf_lock;
126 unsigned int mem_target;
127 unsigned int mem_attr;
128 unsigned int io_target;
129 unsigned int io_attr;
132 int reset_active_low;
134 struct mvebu_sw_pci_bridge bridge;
135 struct device_node *dn;
136 struct mvebu_pcie *pcie;
137 phys_addr_t memwin_base;
139 phys_addr_t iowin_base;
143 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
145 writel(val, port->base + reg);
148 static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
150 return readl(port->base + reg);
153 static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
155 return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
158 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
162 stat = mvebu_readl(port, PCIE_STAT_OFF);
163 stat &= ~PCIE_STAT_BUS;
165 mvebu_writel(port, stat, PCIE_STAT_OFF);
168 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
172 stat = mvebu_readl(port, PCIE_STAT_OFF);
173 stat &= ~PCIE_STAT_DEV;
175 mvebu_writel(port, stat, PCIE_STAT_OFF);
179 * Setup PCIE BARs and Address Decode Wins:
180 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
181 * WIN[0-3] -> DRAM bank[0-3]
183 static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
185 const struct mbus_dram_target_info *dram;
189 dram = mv_mbus_dram_info();
191 /* First, disable and clear BARs and windows. */
192 for (i = 1; i < 3; i++) {
193 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
194 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
195 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
198 for (i = 0; i < 5; i++) {
199 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
200 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
201 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
204 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
205 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
206 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
208 /* Setup windows for DDR banks. Count total DDR size on the fly. */
210 for (i = 0; i < dram->num_cs; i++) {
211 const struct mbus_dram_window *cs = dram->cs + i;
213 mvebu_writel(port, cs->base & 0xffff0000,
214 PCIE_WIN04_BASE_OFF(i));
215 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
217 ((cs->size - 1) & 0xffff0000) |
218 (cs->mbus_attr << 8) |
219 (dram->mbus_dram_target_id << 4) | 1,
220 PCIE_WIN04_CTRL_OFF(i));
225 /* Round up 'size' to the nearest power of two. */
226 if ((size & (size - 1)) != 0)
227 size = 1 << fls(size);
229 /* Setup BAR[1] to all DRAM banks. */
230 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
231 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
232 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
233 PCIE_BAR_CTRL_OFF(1));
236 static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
240 /* Point PCIe unit MBUS decode windows to DRAM space. */
241 mvebu_pcie_setup_wins(port);
243 /* Master + slave enable. */
244 cmd = mvebu_readl(port, PCIE_CMD_OFF);
245 cmd |= PCI_COMMAND_IO;
246 cmd |= PCI_COMMAND_MEMORY;
247 cmd |= PCI_COMMAND_MASTER;
248 mvebu_writel(port, cmd, PCIE_CMD_OFF);
250 /* Enable interrupt lines A-D. */
251 mask = mvebu_readl(port, PCIE_MASK_OFF);
252 mask |= PCIE_MASK_ENABLE_INTS;
253 mvebu_writel(port, mask, PCIE_MASK_OFF);
256 static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
258 u32 devfn, int where, int size, u32 *val)
260 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
263 *val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
266 *val = (*val >> (8 * (where & 3))) & 0xff;
268 *val = (*val >> (8 * (where & 3))) & 0xffff;
270 return PCIBIOS_SUCCESSFUL;
273 static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
275 u32 devfn, int where, int size, u32 val)
277 u32 _val, shift = 8 * (where & 3);
279 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
281 _val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
286 _val = (_val & ~(0xffff << shift)) | ((val & 0xffff) << shift);
288 _val = (_val & ~(0xff << shift)) | ((val & 0xff) << shift);
290 return PCIBIOS_BAD_REGISTER_NUMBER;
292 mvebu_writel(port, _val, PCIE_CONF_DATA_OFF);
294 return PCIBIOS_SUCCESSFUL;
297 static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
301 /* Are the new iobase/iolimit values invalid? */
302 if (port->bridge.iolimit < port->bridge.iobase ||
303 port->bridge.iolimitupper < port->bridge.iobaseupper ||
304 !(port->bridge.command & PCI_COMMAND_IO)) {
306 /* If a window was configured, remove it */
307 if (port->iowin_base) {
308 mvebu_mbus_del_window(port->iowin_base,
310 port->iowin_base = 0;
311 port->iowin_size = 0;
318 * We read the PCI-to-PCI bridge emulated registers, and
319 * calculate the base address and size of the address decoding
320 * window to setup, according to the PCI-to-PCI bridge
321 * specifications. iobase is the bus address, port->iowin_base
322 * is the CPU address.
324 iobase = ((port->bridge.iobase & 0xF0) << 8) |
325 (port->bridge.iobaseupper << 16);
326 port->iowin_base = port->pcie->io.start + iobase;
327 port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
328 (port->bridge.iolimitupper << 16)) -
331 mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr,
332 port->iowin_base, port->iowin_size,
335 pci_ioremap_io(iobase, port->iowin_base);
338 static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
340 /* Are the new membase/memlimit values invalid? */
341 if (port->bridge.memlimit < port->bridge.membase ||
342 !(port->bridge.command & PCI_COMMAND_MEMORY)) {
344 /* If a window was configured, remove it */
345 if (port->memwin_base) {
346 mvebu_mbus_del_window(port->memwin_base,
348 port->memwin_base = 0;
349 port->memwin_size = 0;
356 * We read the PCI-to-PCI bridge emulated registers, and
357 * calculate the base address and size of the address decoding
358 * window to setup, according to the PCI-to-PCI bridge
361 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
363 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
366 mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr,
367 port->memwin_base, port->memwin_size);
371 * Initialize the configuration space of the PCI-to-PCI bridge
372 * associated with the given PCIe interface.
374 static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
376 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
378 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
380 bridge->class = PCI_CLASS_BRIDGE_PCI;
381 bridge->vendor = PCI_VENDOR_ID_MARVELL;
382 bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
383 bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
384 bridge->cache_line_size = 0x10;
386 /* We support 32 bits I/O addressing */
387 bridge->iobase = PCI_IO_RANGE_TYPE_32;
388 bridge->iolimit = PCI_IO_RANGE_TYPE_32;
392 * Read the configuration space of the PCI-to-PCI bridge associated to
393 * the given PCIe interface.
395 static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
396 unsigned int where, int size, u32 *value)
398 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
400 switch (where & ~3) {
402 *value = bridge->device << 16 | bridge->vendor;
406 *value = bridge->command;
409 case PCI_CLASS_REVISION:
410 *value = bridge->class << 16 | bridge->interface << 8 |
414 case PCI_CACHE_LINE_SIZE:
415 *value = bridge->bist << 24 | bridge->header_type << 16 |
416 bridge->latency_timer << 8 | bridge->cache_line_size;
419 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
420 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
423 case PCI_PRIMARY_BUS:
424 *value = (bridge->secondary_latency_timer << 24 |
425 bridge->subordinate_bus << 16 |
426 bridge->secondary_bus << 8 |
427 bridge->primary_bus);
431 *value = (bridge->secondary_status << 16 |
432 bridge->iolimit << 8 |
436 case PCI_MEMORY_BASE:
437 *value = (bridge->memlimit << 16 | bridge->membase);
440 case PCI_PREF_MEMORY_BASE:
444 case PCI_IO_BASE_UPPER16:
445 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
448 case PCI_ROM_ADDRESS1:
454 return PCIBIOS_BAD_REGISTER_NUMBER;
458 *value = (*value >> (8 * (where & 3))) & 0xffff;
460 *value = (*value >> (8 * (where & 3))) & 0xff;
462 return PCIBIOS_SUCCESSFUL;
465 /* Write to the PCI-to-PCI bridge configuration space */
466 static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
467 unsigned int where, int size, u32 value)
469 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
476 mask = ~(0xffff << ((where & 3) * 8));
478 mask = ~(0xff << ((where & 3) * 8));
480 return PCIBIOS_BAD_REGISTER_NUMBER;
482 err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®);
486 value = (reg & mask) | value << ((where & 3) * 8);
488 switch (where & ~3) {
491 u32 old = bridge->command;
493 bridge->command = value & 0xffff;
494 if ((old ^ bridge->command) & PCI_COMMAND_IO)
495 mvebu_pcie_handle_iobase_change(port);
496 if ((old ^ bridge->command) & PCI_COMMAND_MEMORY)
497 mvebu_pcie_handle_membase_change(port);
501 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
502 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
507 * We also keep bit 1 set, it is a read-only bit that
508 * indicates we support 32 bits addressing for the
511 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
512 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
513 mvebu_pcie_handle_iobase_change(port);
516 case PCI_MEMORY_BASE:
517 bridge->membase = value & 0xffff;
518 bridge->memlimit = value >> 16;
519 mvebu_pcie_handle_membase_change(port);
522 case PCI_IO_BASE_UPPER16:
523 bridge->iobaseupper = value & 0xffff;
524 bridge->iolimitupper = value >> 16;
525 mvebu_pcie_handle_iobase_change(port);
528 case PCI_PRIMARY_BUS:
529 bridge->primary_bus = value & 0xff;
530 bridge->secondary_bus = (value >> 8) & 0xff;
531 bridge->subordinate_bus = (value >> 16) & 0xff;
532 bridge->secondary_latency_timer = (value >> 24) & 0xff;
533 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
540 return PCIBIOS_SUCCESSFUL;
543 static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
545 return sys->private_data;
548 static struct mvebu_pcie_port *
549 mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
554 for (i = 0; i < pcie->nports; i++) {
555 struct mvebu_pcie_port *port = &pcie->ports[i];
556 if (bus->number == 0 && port->devfn == devfn)
558 if (bus->number != 0 &&
559 bus->number >= port->bridge.secondary_bus &&
560 bus->number <= port->bridge.subordinate_bus)
567 /* PCI configuration space write function */
568 static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
569 int where, int size, u32 val)
571 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
572 struct mvebu_pcie_port *port;
576 port = mvebu_pcie_find_port(pcie, bus, devfn);
578 return PCIBIOS_DEVICE_NOT_FOUND;
580 /* Access the emulated PCI-to-PCI bridge */
581 if (bus->number == 0)
582 return mvebu_sw_pci_bridge_write(port, where, size, val);
584 if (!mvebu_pcie_link_up(port))
585 return PCIBIOS_DEVICE_NOT_FOUND;
588 * On the secondary bus, we don't want to expose any other
589 * device than the device physically connected in the PCIe
590 * slot, visible in slot 0. In slot 1, there's a special
591 * Marvell device that only makes sense when the Armada is
592 * used as a PCIe endpoint.
594 if (bus->number == port->bridge.secondary_bus &&
595 PCI_SLOT(devfn) != 0)
596 return PCIBIOS_DEVICE_NOT_FOUND;
598 /* Access the real PCIe interface */
599 spin_lock_irqsave(&port->conf_lock, flags);
600 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
602 spin_unlock_irqrestore(&port->conf_lock, flags);
607 /* PCI configuration space read function */
608 static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
611 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
612 struct mvebu_pcie_port *port;
616 port = mvebu_pcie_find_port(pcie, bus, devfn);
619 return PCIBIOS_DEVICE_NOT_FOUND;
622 /* Access the emulated PCI-to-PCI bridge */
623 if (bus->number == 0)
624 return mvebu_sw_pci_bridge_read(port, where, size, val);
626 if (!mvebu_pcie_link_up(port)) {
628 return PCIBIOS_DEVICE_NOT_FOUND;
632 * On the secondary bus, we don't want to expose any other
633 * device than the device physically connected in the PCIe
634 * slot, visible in slot 0. In slot 1, there's a special
635 * Marvell device that only makes sense when the Armada is
636 * used as a PCIe endpoint.
638 if (bus->number == port->bridge.secondary_bus &&
639 PCI_SLOT(devfn) != 0) {
641 return PCIBIOS_DEVICE_NOT_FOUND;
644 /* Access the real PCIe interface */
645 spin_lock_irqsave(&port->conf_lock, flags);
646 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
648 spin_unlock_irqrestore(&port->conf_lock, flags);
653 static struct pci_ops mvebu_pcie_ops = {
654 .read = mvebu_pcie_rd_conf,
655 .write = mvebu_pcie_wr_conf,
658 static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
660 struct mvebu_pcie *pcie = sys_to_pcie(sys);
663 pci_add_resource_offset(&sys->resources, &pcie->realio, sys->io_offset);
664 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
665 pci_add_resource(&sys->resources, &pcie->busn);
667 for (i = 0; i < pcie->nports; i++) {
668 struct mvebu_pcie_port *port = &pcie->ports[i];
671 mvebu_pcie_setup_hw(port);
677 static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
679 struct mvebu_pcie *pcie = sys_to_pcie(sys);
682 bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
683 &mvebu_pcie_ops, sys, &sys->resources);
687 pci_scan_child_bus(bus);
692 static void mvebu_pcie_add_bus(struct pci_bus *bus)
694 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
695 bus->msi = pcie->msi;
698 static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
699 const struct resource *res,
700 resource_size_t start,
701 resource_size_t size,
702 resource_size_t align)
704 if (dev->bus->number != 0)
708 * On the PCI-to-PCI bridge side, the I/O windows must have at
709 * least a 64 KB size and be aligned on their size, and the
710 * memory windows must have at least a 1 MB size and be
711 * aligned on their size
713 if (res->flags & IORESOURCE_IO)
714 return round_up(start, max((resource_size_t)SZ_64K, size));
715 else if (res->flags & IORESOURCE_MEM)
716 return round_up(start, max((resource_size_t)SZ_1M, size));
721 static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
725 memset(&hw, 0, sizeof(hw));
727 hw.nr_controllers = 1;
728 hw.private_data = (void **)&pcie;
729 hw.setup = mvebu_pcie_setup;
730 hw.scan = mvebu_pcie_scan_bus;
731 hw.map_irq = of_irq_parse_and_map_pci;
732 hw.ops = &mvebu_pcie_ops;
733 hw.align_resource = mvebu_pcie_align_resource;
734 hw.add_bus = mvebu_pcie_add_bus;
736 pci_common_init(&hw);
740 * Looks up the list of register addresses encoded into the reg =
741 * <...> property for one that matches the given port/lane. Once
744 static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
745 struct device_node *np, struct mvebu_pcie_port *port)
747 struct resource regs;
750 ret = of_address_to_resource(np, 0, ®s);
754 return devm_ioremap_resource(&pdev->dev, ®s);
757 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
758 #define DT_TYPE_IO 0x1
759 #define DT_TYPE_MEM32 0x2
760 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
761 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
763 static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
764 unsigned long type, int *tgt, int *attr)
766 const int na = 3, ns = 2;
768 int rlen, nranges, rangesz, pna, i;
770 range = of_get_property(np, "ranges", &rlen);
774 pna = of_n_addr_cells(np);
775 rangesz = pna + na + ns;
776 nranges = rlen / sizeof(__be32) / rangesz;
778 for (i = 0; i < nranges; i++) {
779 u32 flags = of_read_number(range, 1);
780 u32 slot = of_read_number(range, 2);
781 u64 cpuaddr = of_read_number(range + na, pna);
784 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
785 rtype = IORESOURCE_IO;
786 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
787 rtype = IORESOURCE_MEM;
789 if (slot == PCI_SLOT(devfn) && type == rtype) {
790 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
791 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
801 static void mvebu_pcie_msi_enable(struct mvebu_pcie *pcie)
803 struct device_node *msi_node;
805 msi_node = of_parse_phandle(pcie->pdev->dev.of_node,
810 pcie->msi = of_pci_find_msi_chip_by_node(msi_node);
813 pcie->msi->dev = &pcie->pdev->dev;
816 static int mvebu_pcie_probe(struct platform_device *pdev)
818 struct mvebu_pcie *pcie;
819 struct device_node *np = pdev->dev.of_node;
820 struct device_node *child;
823 pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
829 platform_set_drvdata(pdev, pcie);
831 /* Get the PCIe memory and I/O aperture */
832 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
833 if (resource_size(&pcie->mem) == 0) {
834 dev_err(&pdev->dev, "invalid memory aperture size\n");
838 mvebu_mbus_get_pcie_io_aperture(&pcie->io);
839 if (resource_size(&pcie->io) == 0) {
840 dev_err(&pdev->dev, "invalid I/O aperture size\n");
844 pcie->realio.flags = pcie->io.flags;
845 pcie->realio.start = PCIBIOS_MIN_IO;
846 pcie->realio.end = min_t(resource_size_t,
848 resource_size(&pcie->io));
850 /* Get the bus range */
851 ret = of_pci_parse_bus_range(np, &pcie->busn);
853 dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
859 for_each_child_of_node(pdev->dev.of_node, child) {
860 if (!of_device_is_available(child))
865 pcie->ports = devm_kzalloc(&pdev->dev, i *
866 sizeof(struct mvebu_pcie_port),
872 for_each_child_of_node(pdev->dev.of_node, child) {
873 struct mvebu_pcie_port *port = &pcie->ports[i];
874 enum of_gpio_flags flags;
876 if (!of_device_is_available(child))
881 if (of_property_read_u32(child, "marvell,pcie-port",
884 "ignoring PCIe DT node, missing pcie-port property\n");
888 if (of_property_read_u32(child, "marvell,pcie-lane",
892 port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
893 port->port, port->lane);
895 port->devfn = of_pci_get_devfn(child);
899 ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM,
900 &port->mem_target, &port->mem_attr);
902 dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n",
903 port->port, port->lane);
907 ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO,
908 &port->io_target, &port->io_attr);
910 dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for io window\n",
911 port->port, port->lane);
915 port->reset_gpio = of_get_named_gpio_flags(child,
916 "reset-gpios", 0, &flags);
917 if (gpio_is_valid(port->reset_gpio)) {
918 u32 reset_udelay = 20000;
920 port->reset_active_low = flags & OF_GPIO_ACTIVE_LOW;
921 port->reset_name = kasprintf(GFP_KERNEL,
922 "pcie%d.%d-reset", port->port, port->lane);
923 of_property_read_u32(child, "reset-delay-us",
926 ret = devm_gpio_request_one(&pdev->dev,
927 port->reset_gpio, GPIOF_DIR_OUT, port->reset_name);
929 if (ret == -EPROBE_DEFER)
934 gpio_set_value(port->reset_gpio,
935 (port->reset_active_low) ? 1 : 0);
936 msleep(reset_udelay/1000);
939 port->clk = of_clk_get_by_name(child, NULL);
940 if (IS_ERR(port->clk)) {
941 dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
942 port->port, port->lane);
946 ret = clk_prepare_enable(port->clk);
950 port->base = mvebu_pcie_map_registers(pdev, child, port);
951 if (IS_ERR(port->base)) {
952 dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
953 port->port, port->lane);
955 clk_disable_unprepare(port->clk);
959 mvebu_pcie_set_local_dev_nr(port, 1);
961 port->clk = of_clk_get_by_name(child, NULL);
962 if (IS_ERR(port->clk)) {
963 dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
964 port->port, port->lane);
970 spin_lock_init(&port->conf_lock);
971 mvebu_sw_pci_bridge_init(port);
976 mvebu_pcie_msi_enable(pcie);
977 mvebu_pcie_enable(pcie);
982 static const struct of_device_id mvebu_pcie_of_match_table[] = {
983 { .compatible = "marvell,armada-xp-pcie", },
984 { .compatible = "marvell,armada-370-pcie", },
985 { .compatible = "marvell,dove-pcie", },
986 { .compatible = "marvell,kirkwood-pcie", },
989 MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
991 static struct platform_driver mvebu_pcie_driver = {
993 .owner = THIS_MODULE,
994 .name = "mvebu-pcie",
996 of_match_ptr(mvebu_pcie_of_match_table),
997 /* driver unloading/unbinding currently not supported */
998 .suppress_bind_attrs = true,
1000 .probe = mvebu_pcie_probe,
1002 module_platform_driver(mvebu_pcie_driver);
1004 MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
1005 MODULE_DESCRIPTION("Marvell EBU PCIe driver");
1006 MODULE_LICENSE("GPLv2");