3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 * Copyright (C) 2016 Christoph Hellwig.
10 #include <linux/err.h>
12 #include <linux/irq.h>
13 #include <linux/interrupt.h>
14 #include <linux/export.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18 #include <linux/msi.h>
19 #include <linux/smp.h>
20 #include <linux/errno.h>
22 #include <linux/slab.h>
23 #include <linux/irqdomain.h>
24 #include <linux/of_irq.h>
28 static int pci_msi_enable = 1;
29 int pci_msi_ignore_mask;
31 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
33 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
34 static struct irq_domain *pci_msi_default_domain;
35 static DEFINE_MUTEX(pci_msi_domain_lock);
37 struct irq_domain * __weak arch_get_pci_msi_domain(struct pci_dev *dev)
39 return pci_msi_default_domain;
42 static struct irq_domain *pci_msi_get_domain(struct pci_dev *dev)
44 struct irq_domain *domain;
46 domain = dev_get_msi_domain(&dev->dev);
50 return arch_get_pci_msi_domain(dev);
53 static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
55 struct irq_domain *domain;
57 domain = pci_msi_get_domain(dev);
58 if (domain && irq_domain_is_hierarchy(domain))
59 return pci_msi_domain_alloc_irqs(domain, dev, nvec, type);
61 return arch_setup_msi_irqs(dev, nvec, type);
64 static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
66 struct irq_domain *domain;
68 domain = pci_msi_get_domain(dev);
69 if (domain && irq_domain_is_hierarchy(domain))
70 pci_msi_domain_free_irqs(domain, dev);
72 arch_teardown_msi_irqs(dev);
75 #define pci_msi_setup_msi_irqs arch_setup_msi_irqs
76 #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
81 int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
83 struct msi_controller *chip = dev->bus->msi;
86 if (!chip || !chip->setup_irq)
89 err = chip->setup_irq(chip, dev, desc);
93 irq_set_chip_data(desc->irq, chip);
98 void __weak arch_teardown_msi_irq(unsigned int irq)
100 struct msi_controller *chip = irq_get_chip_data(irq);
102 if (!chip || !chip->teardown_irq)
105 chip->teardown_irq(chip, irq);
108 int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
110 struct msi_controller *chip = dev->bus->msi;
111 struct msi_desc *entry;
114 if (chip && chip->setup_irqs)
115 return chip->setup_irqs(chip, dev, nvec, type);
117 * If an architecture wants to support multiple MSI, it needs to
118 * override arch_setup_msi_irqs()
120 if (type == PCI_CAP_ID_MSI && nvec > 1)
123 for_each_pci_msi_entry(entry, dev) {
124 ret = arch_setup_msi_irq(dev, entry);
135 * We have a default implementation available as a separate non-weak
136 * function, as it is used by the Xen x86 PCI code
138 void default_teardown_msi_irqs(struct pci_dev *dev)
141 struct msi_desc *entry;
143 for_each_pci_msi_entry(entry, dev)
145 for (i = 0; i < entry->nvec_used; i++)
146 arch_teardown_msi_irq(entry->irq + i);
149 void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
151 return default_teardown_msi_irqs(dev);
154 static void default_restore_msi_irq(struct pci_dev *dev, int irq)
156 struct msi_desc *entry;
159 if (dev->msix_enabled) {
160 for_each_pci_msi_entry(entry, dev) {
161 if (irq == entry->irq)
164 } else if (dev->msi_enabled) {
165 entry = irq_get_msi_desc(irq);
169 __pci_write_msi_msg(entry, &entry->msg);
172 void __weak arch_restore_msi_irqs(struct pci_dev *dev)
174 return default_restore_msi_irqs(dev);
177 static inline __attribute_const__ u32 msi_mask(unsigned x)
179 /* Don't shift by >= width of type */
182 return (1 << (1 << x)) - 1;
186 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
187 * mask all MSI interrupts by clearing the MSI enable bit does not work
188 * reliably as devices without an INTx disable bit will then generate a
189 * level IRQ which will never be cleared.
191 u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
193 u32 mask_bits = desc->masked;
195 if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
200 pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos,
206 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
208 desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag);
211 static void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
213 return desc->mask_base +
214 desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
218 * This internal function does not flush PCI writes to the device.
219 * All users must ensure that they read from the device before either
220 * assuming that the device state is up to date, or returning out of this
221 * file. This saves a few milliseconds when initialising devices with lots
222 * of MSI-X interrupts.
224 u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
226 u32 mask_bits = desc->masked;
228 if (pci_msi_ignore_mask)
231 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
233 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
234 writel(mask_bits, pci_msix_desc_addr(desc) + PCI_MSIX_ENTRY_VECTOR_CTRL);
239 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
241 desc->masked = __pci_msix_desc_mask_irq(desc, flag);
244 static void msi_set_mask_bit(struct irq_data *data, u32 flag)
246 struct msi_desc *desc = irq_data_get_msi_desc(data);
248 if (desc->msi_attrib.is_msix) {
249 msix_mask_irq(desc, flag);
250 readl(desc->mask_base); /* Flush write to device */
252 unsigned offset = data->irq - desc->irq;
253 msi_mask_irq(desc, 1 << offset, flag << offset);
258 * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts
259 * @data: pointer to irqdata associated to that interrupt
261 void pci_msi_mask_irq(struct irq_data *data)
263 msi_set_mask_bit(data, 1);
265 EXPORT_SYMBOL_GPL(pci_msi_mask_irq);
268 * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts
269 * @data: pointer to irqdata associated to that interrupt
271 void pci_msi_unmask_irq(struct irq_data *data)
273 msi_set_mask_bit(data, 0);
275 EXPORT_SYMBOL_GPL(pci_msi_unmask_irq);
277 void default_restore_msi_irqs(struct pci_dev *dev)
279 struct msi_desc *entry;
281 for_each_pci_msi_entry(entry, dev)
282 default_restore_msi_irq(dev, entry->irq);
285 void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
287 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
289 BUG_ON(dev->current_state != PCI_D0);
291 if (entry->msi_attrib.is_msix) {
292 void __iomem *base = pci_msix_desc_addr(entry);
294 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
295 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
296 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
298 int pos = dev->msi_cap;
301 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
303 if (entry->msi_attrib.is_64) {
304 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
306 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
309 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
315 void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
317 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
319 if (dev->current_state != PCI_D0) {
320 /* Don't touch the hardware now */
321 } else if (entry->msi_attrib.is_msix) {
322 void __iomem *base = pci_msix_desc_addr(entry);
324 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
325 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
326 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
328 int pos = dev->msi_cap;
331 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
332 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
333 msgctl |= entry->msi_attrib.multiple << 4;
334 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
336 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
338 if (entry->msi_attrib.is_64) {
339 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
341 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
344 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
351 void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
353 struct msi_desc *entry = irq_get_msi_desc(irq);
355 __pci_write_msi_msg(entry, msg);
357 EXPORT_SYMBOL_GPL(pci_write_msi_msg);
359 static void free_msi_irqs(struct pci_dev *dev)
361 struct list_head *msi_list = dev_to_msi_list(&dev->dev);
362 struct msi_desc *entry, *tmp;
363 struct attribute **msi_attrs;
364 struct device_attribute *dev_attr;
367 for_each_pci_msi_entry(entry, dev)
369 for (i = 0; i < entry->nvec_used; i++)
370 BUG_ON(irq_has_action(entry->irq + i));
372 pci_msi_teardown_msi_irqs(dev);
374 list_for_each_entry_safe(entry, tmp, msi_list, list) {
375 if (entry->msi_attrib.is_msix) {
376 if (list_is_last(&entry->list, msi_list))
377 iounmap(entry->mask_base);
380 list_del(&entry->list);
384 if (dev->msi_irq_groups) {
385 sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
386 msi_attrs = dev->msi_irq_groups[0]->attrs;
387 while (msi_attrs[count]) {
388 dev_attr = container_of(msi_attrs[count],
389 struct device_attribute, attr);
390 kfree(dev_attr->attr.name);
395 kfree(dev->msi_irq_groups[0]);
396 kfree(dev->msi_irq_groups);
397 dev->msi_irq_groups = NULL;
401 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
403 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
404 pci_intx(dev, enable);
407 static void __pci_restore_msi_state(struct pci_dev *dev)
410 struct msi_desc *entry;
412 if (!dev->msi_enabled)
415 entry = irq_get_msi_desc(dev->irq);
417 pci_intx_for_msi(dev, 0);
418 pci_msi_set_enable(dev, 0);
419 arch_restore_msi_irqs(dev);
421 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
422 msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
424 control &= ~PCI_MSI_FLAGS_QSIZE;
425 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
426 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
429 static void __pci_restore_msix_state(struct pci_dev *dev)
431 struct msi_desc *entry;
433 if (!dev->msix_enabled)
435 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
437 /* route the table */
438 pci_intx_for_msi(dev, 0);
439 pci_msix_clear_and_set_ctrl(dev, 0,
440 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
442 arch_restore_msi_irqs(dev);
443 for_each_pci_msi_entry(entry, dev)
444 msix_mask_irq(entry, entry->masked);
446 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
449 void pci_restore_msi_state(struct pci_dev *dev)
451 __pci_restore_msi_state(dev);
452 __pci_restore_msix_state(dev);
454 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
456 static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
459 struct msi_desc *entry;
463 retval = kstrtoul(attr->attr.name, 10, &irq);
467 entry = irq_get_msi_desc(irq);
469 return sprintf(buf, "%s\n",
470 entry->msi_attrib.is_msix ? "msix" : "msi");
475 static int populate_msi_sysfs(struct pci_dev *pdev)
477 struct attribute **msi_attrs;
478 struct attribute *msi_attr;
479 struct device_attribute *msi_dev_attr;
480 struct attribute_group *msi_irq_group;
481 const struct attribute_group **msi_irq_groups;
482 struct msi_desc *entry;
488 /* Determine how many msi entries we have */
489 for_each_pci_msi_entry(entry, pdev)
490 num_msi += entry->nvec_used;
494 /* Dynamically create the MSI attributes for the PCI device */
495 msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL);
498 for_each_pci_msi_entry(entry, pdev) {
499 for (i = 0; i < entry->nvec_used; i++) {
500 msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
503 msi_attrs[count] = &msi_dev_attr->attr;
505 sysfs_attr_init(&msi_dev_attr->attr);
506 msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
508 if (!msi_dev_attr->attr.name)
510 msi_dev_attr->attr.mode = S_IRUGO;
511 msi_dev_attr->show = msi_mode_show;
516 msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
519 msi_irq_group->name = "msi_irqs";
520 msi_irq_group->attrs = msi_attrs;
522 msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL);
524 goto error_irq_group;
525 msi_irq_groups[0] = msi_irq_group;
527 ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
529 goto error_irq_groups;
530 pdev->msi_irq_groups = msi_irq_groups;
535 kfree(msi_irq_groups);
537 kfree(msi_irq_group);
540 msi_attr = msi_attrs[count];
542 msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
543 kfree(msi_attr->name);
546 msi_attr = msi_attrs[count];
552 static struct msi_desc *msi_setup_entry(struct pci_dev *dev, int nvec)
555 struct msi_desc *entry;
557 /* MSI Entry Initialization */
558 entry = alloc_msi_entry(&dev->dev, nvec, NULL);
562 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
564 entry->msi_attrib.is_msix = 0;
565 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
566 entry->msi_attrib.entry_nr = 0;
567 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
568 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
569 entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
570 entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
571 entry->affinity = dev->irq_affinity;
573 if (control & PCI_MSI_FLAGS_64BIT)
574 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
576 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
578 /* Save the initial mask status */
579 if (entry->msi_attrib.maskbit)
580 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
585 static int msi_verify_entries(struct pci_dev *dev)
587 struct msi_desc *entry;
589 for_each_pci_msi_entry(entry, dev) {
590 if (!dev->no_64bit_msi || !entry->msg.address_hi)
592 dev_err(&dev->dev, "Device has broken 64-bit MSI but arch"
593 " tried to assign one above 4G\n");
600 * msi_capability_init - configure device's MSI capability structure
601 * @dev: pointer to the pci_dev data structure of MSI device function
602 * @nvec: number of interrupts to allocate
604 * Setup the MSI capability structure of the device with the requested
605 * number of interrupts. A return value of zero indicates the successful
606 * setup of an entry with the new MSI irq. A negative return value indicates
607 * an error, and a positive return value indicates the number of interrupts
608 * which could have been allocated.
610 static int msi_capability_init(struct pci_dev *dev, int nvec)
612 struct msi_desc *entry;
616 pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
618 entry = msi_setup_entry(dev, nvec);
622 /* All MSIs are unmasked by default, Mask them all */
623 mask = msi_mask(entry->msi_attrib.multi_cap);
624 msi_mask_irq(entry, mask, mask);
626 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
628 /* Configure MSI capability structure */
629 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
631 msi_mask_irq(entry, mask, ~mask);
636 ret = msi_verify_entries(dev);
638 msi_mask_irq(entry, mask, ~mask);
643 ret = populate_msi_sysfs(dev);
645 msi_mask_irq(entry, mask, ~mask);
650 /* Set MSI enabled bits */
651 pci_intx_for_msi(dev, 0);
652 pci_msi_set_enable(dev, 1);
653 dev->msi_enabled = 1;
655 pcibios_free_irq(dev);
656 dev->irq = entry->irq;
660 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
662 resource_size_t phys_addr;
667 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
669 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
670 flags = pci_resource_flags(dev, bir);
671 if (!flags || (flags & IORESOURCE_UNSET))
674 table_offset &= PCI_MSIX_TABLE_OFFSET;
675 phys_addr = pci_resource_start(dev, bir) + table_offset;
677 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
680 static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
681 struct msix_entry *entries, int nvec)
683 const struct cpumask *mask = NULL;
684 struct msi_desc *entry;
687 for (i = 0; i < nvec; i++) {
688 if (dev->irq_affinity) {
689 cpu = cpumask_next(cpu, dev->irq_affinity);
690 if (cpu >= nr_cpu_ids)
691 cpu = cpumask_first(dev->irq_affinity);
692 mask = cpumask_of(cpu);
695 entry = alloc_msi_entry(&dev->dev, 1, NULL);
701 /* No enough memory. Don't try again */
705 entry->msi_attrib.is_msix = 1;
706 entry->msi_attrib.is_64 = 1;
708 entry->msi_attrib.entry_nr = entries[i].entry;
710 entry->msi_attrib.entry_nr = i;
711 entry->msi_attrib.default_irq = dev->irq;
712 entry->mask_base = base;
713 entry->affinity = mask;
715 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
721 static void msix_program_entries(struct pci_dev *dev,
722 struct msix_entry *entries)
724 struct msi_desc *entry;
727 for_each_pci_msi_entry(entry, dev) {
729 entries[i++].vector = entry->irq;
730 entry->masked = readl(pci_msix_desc_addr(entry) +
731 PCI_MSIX_ENTRY_VECTOR_CTRL);
732 msix_mask_irq(entry, 1);
737 * msix_capability_init - configure device's MSI-X capability
738 * @dev: pointer to the pci_dev data structure of MSI-X device function
739 * @entries: pointer to an array of struct msix_entry entries
740 * @nvec: number of @entries
742 * Setup the MSI-X capability structure of device function with a
743 * single MSI-X irq. A return of zero indicates the successful setup of
744 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
746 static int msix_capability_init(struct pci_dev *dev,
747 struct msix_entry *entries, int nvec)
753 /* Ensure MSI-X is disabled while it is set up */
754 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
756 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
757 /* Request & Map MSI-X table region */
758 base = msix_map_region(dev, msix_table_size(control));
762 ret = msix_setup_entries(dev, base, entries, nvec);
766 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
770 /* Check if all MSI entries honor device restrictions */
771 ret = msi_verify_entries(dev);
776 * Some devices require MSI-X to be enabled before we can touch the
777 * MSI-X registers. We need to mask all the vectors to prevent
778 * interrupts coming in before they're fully set up.
780 pci_msix_clear_and_set_ctrl(dev, 0,
781 PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE);
783 msix_program_entries(dev, entries);
785 ret = populate_msi_sysfs(dev);
789 /* Set MSI-X enabled bits and unmask the function */
790 pci_intx_for_msi(dev, 0);
791 dev->msix_enabled = 1;
792 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
794 pcibios_free_irq(dev);
800 * If we had some success, report the number of irqs
801 * we succeeded in setting up.
803 struct msi_desc *entry;
806 for_each_pci_msi_entry(entry, dev) {
821 * pci_msi_supported - check whether MSI may be enabled on a device
822 * @dev: pointer to the pci_dev data structure of MSI device function
823 * @nvec: how many MSIs have been requested ?
825 * Look at global flags, the device itself, and its parent buses
826 * to determine if MSI/-X are supported for the device. If MSI/-X is
827 * supported return 1, else return 0.
829 static int pci_msi_supported(struct pci_dev *dev, int nvec)
833 /* MSI must be globally enabled and supported by the device */
837 if (!dev || dev->no_msi || dev->current_state != PCI_D0)
841 * You can't ask to have 0 or less MSIs configured.
843 * b) the list manipulation code assumes nvec >= 1.
849 * Any bridge which does NOT route MSI transactions from its
850 * secondary bus to its primary bus must set NO_MSI flag on
851 * the secondary pci_bus.
852 * We expect only arch-specific PCI host bus controller driver
853 * or quirks for specific PCI bridges to be setting NO_MSI.
855 for (bus = dev->bus; bus; bus = bus->parent)
856 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
863 * pci_msi_vec_count - Return the number of MSI vectors a device can send
864 * @dev: device to report about
866 * This function returns the number of MSI vectors a device requested via
867 * Multiple Message Capable register. It returns a negative errno if the
868 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
869 * and returns a power of two, up to a maximum of 2^5 (32), according to the
872 int pci_msi_vec_count(struct pci_dev *dev)
880 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
881 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
885 EXPORT_SYMBOL(pci_msi_vec_count);
887 void pci_msi_shutdown(struct pci_dev *dev)
889 struct msi_desc *desc;
892 if (!pci_msi_enable || !dev || !dev->msi_enabled)
895 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
896 desc = first_pci_msi_entry(dev);
898 pci_msi_set_enable(dev, 0);
899 pci_intx_for_msi(dev, 1);
900 dev->msi_enabled = 0;
902 /* Return the device with MSI unmasked as initial states */
903 mask = msi_mask(desc->msi_attrib.multi_cap);
904 /* Keep cached state to be restored */
905 __pci_msi_desc_mask_irq(desc, mask, ~mask);
907 /* Restore dev->irq to its default pin-assertion irq */
908 dev->irq = desc->msi_attrib.default_irq;
909 pcibios_alloc_irq(dev);
912 void pci_disable_msi(struct pci_dev *dev)
914 if (!pci_msi_enable || !dev || !dev->msi_enabled)
917 pci_msi_shutdown(dev);
920 EXPORT_SYMBOL(pci_disable_msi);
923 * pci_msix_vec_count - return the number of device's MSI-X table entries
924 * @dev: pointer to the pci_dev data structure of MSI-X device function
925 * This function returns the number of device's MSI-X table entries and
926 * therefore the number of MSI-X vectors device is capable of sending.
927 * It returns a negative errno if the device is not capable of sending MSI-X
930 int pci_msix_vec_count(struct pci_dev *dev)
937 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
938 return msix_table_size(control);
940 EXPORT_SYMBOL(pci_msix_vec_count);
943 * pci_enable_msix - configure device's MSI-X capability structure
944 * @dev: pointer to the pci_dev data structure of MSI-X device function
945 * @entries: pointer to an array of MSI-X entries (optional)
946 * @nvec: number of MSI-X irqs requested for allocation by device driver
948 * Setup the MSI-X capability structure of device function with the number
949 * of requested irqs upon its software driver call to request for
950 * MSI-X mode enabled on its hardware device function. A return of zero
951 * indicates the successful configuration of MSI-X capability structure
952 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
953 * Or a return of > 0 indicates that driver request is exceeding the number
954 * of irqs or MSI-X vectors available. Driver should use the returned value to
955 * re-send its request.
957 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
962 if (!pci_msi_supported(dev, nvec))
965 nr_entries = pci_msix_vec_count(dev);
968 if (nvec > nr_entries)
972 /* Check for any invalid entries */
973 for (i = 0; i < nvec; i++) {
974 if (entries[i].entry >= nr_entries)
975 return -EINVAL; /* invalid entry */
976 for (j = i + 1; j < nvec; j++) {
977 if (entries[i].entry == entries[j].entry)
978 return -EINVAL; /* duplicate entry */
982 WARN_ON(!!dev->msix_enabled);
984 /* Check whether driver already requested for MSI irq */
985 if (dev->msi_enabled) {
986 dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
989 return msix_capability_init(dev, entries, nvec);
991 EXPORT_SYMBOL(pci_enable_msix);
993 void pci_msix_shutdown(struct pci_dev *dev)
995 struct msi_desc *entry;
997 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1000 /* Return the device with MSI-X masked as initial states */
1001 for_each_pci_msi_entry(entry, dev) {
1002 /* Keep cached states to be restored */
1003 __pci_msix_desc_mask_irq(entry, 1);
1006 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1007 pci_intx_for_msi(dev, 1);
1008 dev->msix_enabled = 0;
1009 pcibios_alloc_irq(dev);
1012 void pci_disable_msix(struct pci_dev *dev)
1014 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1017 pci_msix_shutdown(dev);
1020 EXPORT_SYMBOL(pci_disable_msix);
1022 void pci_no_msi(void)
1028 * pci_msi_enabled - is MSI enabled?
1030 * Returns true if MSI has not been disabled by the command-line option
1033 int pci_msi_enabled(void)
1035 return pci_msi_enable;
1037 EXPORT_SYMBOL(pci_msi_enabled);
1039 static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
1045 if (!pci_msi_supported(dev, minvec))
1048 WARN_ON(!!dev->msi_enabled);
1050 /* Check whether driver already requested MSI-X irqs */
1051 if (dev->msix_enabled) {
1053 "can't enable MSI (MSI-X already enabled)\n");
1057 if (maxvec < minvec)
1060 nvec = pci_msi_vec_count(dev);
1070 if (flags & PCI_IRQ_AFFINITY) {
1071 dev->irq_affinity = irq_create_affinity_mask(&nvec);
1076 rc = msi_capability_init(dev, nvec);
1080 kfree(dev->irq_affinity);
1081 dev->irq_affinity = NULL;
1093 * pci_enable_msi_range - configure device's MSI capability structure
1094 * @dev: device to configure
1095 * @minvec: minimal number of interrupts to configure
1096 * @maxvec: maximum number of interrupts to configure
1098 * This function tries to allocate a maximum possible number of interrupts in a
1099 * range between @minvec and @maxvec. It returns a negative errno if an error
1100 * occurs. If it succeeds, it returns the actual number of interrupts allocated
1101 * and updates the @dev's irq member to the lowest new interrupt number;
1102 * the other interrupt numbers allocated to this device are consecutive.
1104 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec)
1106 return __pci_enable_msi_range(dev, minvec, maxvec, 0);
1108 EXPORT_SYMBOL(pci_enable_msi_range);
1110 static int __pci_enable_msix_range(struct pci_dev *dev,
1111 struct msix_entry *entries, int minvec, int maxvec,
1117 if (maxvec < minvec)
1121 if (flags & PCI_IRQ_AFFINITY) {
1122 dev->irq_affinity = irq_create_affinity_mask(&nvec);
1127 rc = pci_enable_msix(dev, entries, nvec);
1131 kfree(dev->irq_affinity);
1132 dev->irq_affinity = NULL;
1144 * pci_enable_msix_range - configure device's MSI-X capability structure
1145 * @dev: pointer to the pci_dev data structure of MSI-X device function
1146 * @entries: pointer to an array of MSI-X entries
1147 * @minvec: minimum number of MSI-X irqs requested
1148 * @maxvec: maximum number of MSI-X irqs requested
1150 * Setup the MSI-X capability structure of device function with a maximum
1151 * possible number of interrupts in the range between @minvec and @maxvec
1152 * upon its software driver call to request for MSI-X mode enabled on its
1153 * hardware device function. It returns a negative errno if an error occurs.
1154 * If it succeeds, it returns the actual number of interrupts allocated and
1155 * indicates the successful configuration of MSI-X capability structure
1156 * with new allocated MSI-X interrupts.
1158 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1159 int minvec, int maxvec)
1161 return __pci_enable_msix_range(dev, entries, minvec, maxvec, 0);
1163 EXPORT_SYMBOL(pci_enable_msix_range);
1166 * pci_alloc_irq_vectors - allocate multiple IRQs for a device
1167 * @dev: PCI device to operate on
1168 * @min_vecs: minimum number of vectors required (must be >= 1)
1169 * @max_vecs: maximum (desired) number of vectors
1170 * @flags: flags or quirks for the allocation
1172 * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI
1173 * vectors if available, and fall back to a single legacy vector
1174 * if neither is available. Return the number of vectors allocated,
1175 * (which might be smaller than @max_vecs) if successful, or a negative
1176 * error code on error. If less than @min_vecs interrupt vectors are
1177 * available for @dev the function will fail with -ENOSPC.
1179 * To get the Linux IRQ number used for a vector that can be passed to
1180 * request_irq() use the pci_irq_vector() helper.
1182 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1183 unsigned int max_vecs, unsigned int flags)
1187 if (flags & PCI_IRQ_MSIX) {
1188 vecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs,
1194 if (flags & PCI_IRQ_MSI) {
1195 vecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, flags);
1200 /* use legacy irq if allowed */
1201 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1) {
1208 EXPORT_SYMBOL(pci_alloc_irq_vectors);
1211 * pci_free_irq_vectors - free previously allocated IRQs for a device
1212 * @dev: PCI device to operate on
1214 * Undoes the allocations and enabling in pci_alloc_irq_vectors().
1216 void pci_free_irq_vectors(struct pci_dev *dev)
1218 pci_disable_msix(dev);
1219 pci_disable_msi(dev);
1221 EXPORT_SYMBOL(pci_free_irq_vectors);
1224 * pci_irq_vector - return Linux IRQ number of a device vector
1225 * @dev: PCI device to operate on
1226 * @nr: device-relative interrupt vector index (0-based).
1228 int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1230 if (dev->msix_enabled) {
1231 struct msi_desc *entry;
1234 for_each_pci_msi_entry(entry, dev) {
1243 if (dev->msi_enabled) {
1244 struct msi_desc *entry = first_pci_msi_entry(dev);
1246 if (WARN_ON_ONCE(nr >= entry->nvec_used))
1249 if (WARN_ON_ONCE(nr > 0))
1253 return dev->irq + nr;
1255 EXPORT_SYMBOL(pci_irq_vector);
1257 struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
1259 return to_pci_dev(desc->dev);
1261 EXPORT_SYMBOL(msi_desc_to_pci_dev);
1263 void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
1265 struct pci_dev *dev = msi_desc_to_pci_dev(desc);
1267 return dev->bus->sysdata;
1269 EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata);
1271 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1273 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1274 * @irq_data: Pointer to interrupt data of the MSI interrupt
1275 * @msg: Pointer to the message
1277 void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg)
1279 struct msi_desc *desc = irq_data_get_msi_desc(irq_data);
1282 * For MSI-X desc->irq is always equal to irq_data->irq. For
1283 * MSI only the first interrupt of MULTI MSI passes the test.
1285 if (desc->irq == irq_data->irq)
1286 __pci_write_msi_msg(desc, msg);
1290 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1291 * @dev: Pointer to the PCI device
1292 * @desc: Pointer to the msi descriptor
1294 * The ID number is only used within the irqdomain.
1296 irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
1297 struct msi_desc *desc)
1299 return (irq_hw_number_t)desc->msi_attrib.entry_nr |
1300 PCI_DEVID(dev->bus->number, dev->devfn) << 11 |
1301 (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
1304 static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
1306 return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
1310 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev
1311 * @domain: The interrupt domain to check
1312 * @info: The domain info for verification
1313 * @dev: The device to check
1316 * 0 if the functionality is supported
1317 * 1 if Multi MSI is requested, but the domain does not support it
1318 * -ENOTSUPP otherwise
1320 int pci_msi_domain_check_cap(struct irq_domain *domain,
1321 struct msi_domain_info *info, struct device *dev)
1323 struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev));
1325 /* Special handling to support pci_enable_msi_range() */
1326 if (pci_msi_desc_is_multi_msi(desc) &&
1327 !(info->flags & MSI_FLAG_MULTI_PCI_MSI))
1329 else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
1335 static int pci_msi_domain_handle_error(struct irq_domain *domain,
1336 struct msi_desc *desc, int error)
1338 /* Special handling to support pci_enable_msi_range() */
1339 if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC)
1345 #ifdef GENERIC_MSI_DOMAIN_OPS
1346 static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
1347 struct msi_desc *desc)
1350 arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc),
1354 #define pci_msi_domain_set_desc NULL
1357 static struct msi_domain_ops pci_msi_domain_ops_default = {
1358 .set_desc = pci_msi_domain_set_desc,
1359 .msi_check = pci_msi_domain_check_cap,
1360 .handle_error = pci_msi_domain_handle_error,
1363 static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info)
1365 struct msi_domain_ops *ops = info->ops;
1368 info->ops = &pci_msi_domain_ops_default;
1370 if (ops->set_desc == NULL)
1371 ops->set_desc = pci_msi_domain_set_desc;
1372 if (ops->msi_check == NULL)
1373 ops->msi_check = pci_msi_domain_check_cap;
1374 if (ops->handle_error == NULL)
1375 ops->handle_error = pci_msi_domain_handle_error;
1379 static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info)
1381 struct irq_chip *chip = info->chip;
1384 if (!chip->irq_write_msi_msg)
1385 chip->irq_write_msi_msg = pci_msi_domain_write_msg;
1386 if (!chip->irq_mask)
1387 chip->irq_mask = pci_msi_mask_irq;
1388 if (!chip->irq_unmask)
1389 chip->irq_unmask = pci_msi_unmask_irq;
1393 * pci_msi_create_irq_domain - Create a MSI interrupt domain
1394 * @fwnode: Optional fwnode of the interrupt controller
1395 * @info: MSI domain info
1396 * @parent: Parent irq domain
1398 * Updates the domain and chip ops and creates a MSI interrupt domain.
1401 * A domain pointer or NULL in case of failure.
1403 struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
1404 struct msi_domain_info *info,
1405 struct irq_domain *parent)
1407 struct irq_domain *domain;
1409 if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
1410 pci_msi_domain_update_dom_ops(info);
1411 if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
1412 pci_msi_domain_update_chip_ops(info);
1414 info->flags |= MSI_FLAG_ACTIVATE_EARLY;
1416 domain = msi_create_irq_domain(fwnode, info, parent);
1420 domain->bus_token = DOMAIN_BUS_PCI_MSI;
1423 EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain);
1426 * pci_msi_domain_alloc_irqs - Allocate interrupts for @dev in @domain
1427 * @domain: The interrupt domain to allocate from
1428 * @dev: The device for which to allocate
1429 * @nvec: The number of interrupts to allocate
1430 * @type: Unused to allow simpler migration from the arch_XXX interfaces
1433 * A virtual interrupt number or an error code in case of failure
1435 int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev,
1438 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
1442 * pci_msi_domain_free_irqs - Free interrupts for @dev in @domain
1443 * @domain: The interrupt domain
1444 * @dev: The device for which to free interrupts
1446 void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev)
1448 msi_domain_free_irqs(domain, &dev->dev);
1452 * pci_msi_create_default_irq_domain - Create a default MSI interrupt domain
1453 * @fwnode: Optional fwnode of the interrupt controller
1454 * @info: MSI domain info
1455 * @parent: Parent irq domain
1457 * Returns: A domain pointer or NULL in case of failure. If successful
1458 * the default PCI/MSI irqdomain pointer is updated.
1460 struct irq_domain *pci_msi_create_default_irq_domain(struct fwnode_handle *fwnode,
1461 struct msi_domain_info *info, struct irq_domain *parent)
1463 struct irq_domain *domain;
1465 mutex_lock(&pci_msi_domain_lock);
1466 if (pci_msi_default_domain) {
1467 pr_err("PCI: default irq domain for PCI MSI has already been created.\n");
1470 domain = pci_msi_create_irq_domain(fwnode, info, parent);
1471 pci_msi_default_domain = domain;
1473 mutex_unlock(&pci_msi_domain_lock);
1478 static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data)
1486 * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID)
1487 * @domain: The interrupt domain
1488 * @pdev: The PCI device.
1490 * The RID for a device is formed from the alias, with a firmware
1491 * supplied mapping applied
1495 u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev)
1497 struct device_node *of_node;
1500 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1502 of_node = irq_domain_get_of_node(domain);
1504 rid = of_msi_map_rid(&pdev->dev, of_node, rid);
1510 * pci_msi_get_device_domain - Get the MSI domain for a given PCI device
1511 * @pdev: The PCI device
1513 * Use the firmware data to find a device-specific MSI domain
1514 * (i.e. not one that is ste as a default).
1516 * Returns: The coresponding MSI domain or NULL if none has been found.
1518 struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
1522 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1523 return of_msi_map_get_device_domain(&pdev->dev, rid);
1525 #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */