drivers/perf/arm_pmu.c

   1 #undef DEBUG
   2
   3 /*
   4  * ARM performance counter support.
   5  *
   6  * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
   7  * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
   8  *
   9  * This code is based on the sparc64 perf event code, which is in turn based
  10  * on the x86 code.
  11  */
  12 #define pr_fmt(fmt) "hw perfevents: " fmt
  13
  14 #include <linux/bitmap.h>
  15 #include <linux/cpumask.h>
  16 #include <linux/cpu_pm.h>
  17 #include <linux/export.h>
  18 #include <linux/kernel.h>
  19 #include <linux/of_device.h>
  20 #include <linux/perf/arm_pmu.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/slab.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/irq.h>
  25 #include <linux/irqdesc.h>
  26
  27 #include <asm/cputype.h>
  28 #include <asm/irq_regs.h>
  29
  30 static int
  31 armpmu_map_cache_event(const unsigned (*cache_map)
  32                                       [PERF_COUNT_HW_CACHE_MAX]
  33                                       [PERF_COUNT_HW_CACHE_OP_MAX]
  34                                       [PERF_COUNT_HW_CACHE_RESULT_MAX],
  35                        u64 config)
  36 {
  37         unsigned int cache_type, cache_op, cache_result, ret;
  38
  39         cache_type = (config >>  0) & 0xff;
  40         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
  41                 return -EINVAL;
  42
  43         cache_op = (config >>  8) & 0xff;
  44         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
  45                 return -EINVAL;
  46
  47         cache_result = (config >> 16) & 0xff;
  48         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
  49                 return -EINVAL;
  50
  51         ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
  52
  53         if (ret == CACHE_OP_UNSUPPORTED)
  54                 return -ENOENT;
  55
  56         return ret;
  57 }
  58
  59 static int
  60 armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
  61 {
  62         int mapping;
  63
  64         if (config >= PERF_COUNT_HW_MAX)
  65                 return -EINVAL;
  66
  67         mapping = (*event_map)[config];
  68         return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
  69 }
  70
  71 static int
  72 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
  73 {
  74         return (int)(config & raw_event_mask);
  75 }
  76
  77 int
  78 armpmu_map_event(struct perf_event *event,
  79                  const unsigned (*event_map)[PERF_COUNT_HW_MAX],
  80                  const unsigned (*cache_map)
  81                                 [PERF_COUNT_HW_CACHE_MAX]
  82                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  83                                 [PERF_COUNT_HW_CACHE_RESULT_MAX],
  84                  u32 raw_event_mask)
  85 {
  86         u64 config = event->attr.config;
  87         int type = event->attr.type;
  88
  89         if (type == event->pmu->type)
  90                 return armpmu_map_raw_event(raw_event_mask, config);
  91
  92         switch (type) {
  93         case PERF_TYPE_HARDWARE:
  94                 return armpmu_map_hw_event(event_map, config);
  95         case PERF_TYPE_HW_CACHE:
  96                 return armpmu_map_cache_event(cache_map, config);
  97         case PERF_TYPE_RAW:
  98                 return armpmu_map_raw_event(raw_event_mask, config);
  99         }
 100
 101         return -ENOENT;
 102 }
 103
 104 int armpmu_event_set_period(struct perf_event *event)
 105 {
 106         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 107         struct hw_perf_event *hwc = &event->hw;
 108         s64 left = local64_read(&hwc->period_left);
 109         s64 period = hwc->sample_period;
 110         int ret = 0;
 111
 112         if (unlikely(left <= -period)) {
 113                 left = period;
 114                 local64_set(&hwc->period_left, left);
 115                 hwc->last_period = period;
 116                 ret = 1;
 117         }
 118
 119         if (unlikely(left <= 0)) {
 120                 left += period;
 121                 local64_set(&hwc->period_left, left);
 122                 hwc->last_period = period;
 123                 ret = 1;
 124         }
 125
 126         /*
 127          * Limit the maximum period to prevent the counter value
 128          * from overtaking the one we are about to program. In
 129          * effect we are reducing max_period to account for
 130          * interrupt latency (and we are being very conservative).
 131          */
 132         if (left > (armpmu->max_period >> 1))
 133                 left = armpmu->max_period >> 1;
 134
 135         local64_set(&hwc->prev_count, (u64)-left);
 136
 137         armpmu->write_counter(event, (u64)(-left) & 0xffffffff);
 138
 139         perf_event_update_userpage(event);
 140
 141         return ret;
 142 }
 143
 144 u64 armpmu_event_update(struct perf_event *event)
 145 {
 146         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 147         struct hw_perf_event *hwc = &event->hw;
 148         u64 delta, prev_raw_count, new_raw_count;
 149
 150 again:
 151         prev_raw_count = local64_read(&hwc->prev_count);
 152         new_raw_count = armpmu->read_counter(event);
 153
 154         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 155                              new_raw_count) != prev_raw_count)
 156                 goto again;
 157
 158         delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
 159
 160         local64_add(delta, &event->count);
 161         local64_sub(delta, &hwc->period_left);
 162
 163         return new_raw_count;
 164 }
 165
 166 static void
 167 armpmu_read(struct perf_event *event)
 168 {
 169         armpmu_event_update(event);
 170 }
 171
 172 static void
 173 armpmu_stop(struct perf_event *event, int flags)
 174 {
 175         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 176         struct hw_perf_event *hwc = &event->hw;
 177
 178         /*
 179          * ARM pmu always has to update the counter, so ignore
 180          * PERF_EF_UPDATE, see comments in armpmu_start().
 181          */
 182         if (!(hwc->state & PERF_HES_STOPPED)) {
 183                 armpmu->disable(event);
 184                 armpmu_event_update(event);
 185                 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 186         }
 187 }
 188
 189 static void armpmu_start(struct perf_event *event, int flags)
 190 {
 191         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 192         struct hw_perf_event *hwc = &event->hw;
 193
 194         /*
 195          * ARM pmu always has to reprogram the period, so ignore
 196          * PERF_EF_RELOAD, see the comment below.
 197          */
 198         if (flags & PERF_EF_RELOAD)
 199                 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
 200
 201         hwc->state = 0;
 202         /*
 203          * Set the period again. Some counters can't be stopped, so when we
 204          * were stopped we simply disabled the IRQ source and the counter
 205          * may have been left counting. If we don't do this step then we may
 206          * get an interrupt too soon or *way* too late if the overflow has
 207          * happened since disabling.
 208          */
 209         armpmu_event_set_period(event);
 210         armpmu->enable(event);
 211 }
 212
 213 static void
 214 armpmu_del(struct perf_event *event, int flags)
 215 {
 216         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 217         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 218         struct hw_perf_event *hwc = &event->hw;
 219         int idx = hwc->idx;
 220
 221         armpmu_stop(event, PERF_EF_UPDATE);
 222         hw_events->events[idx] = NULL;
 223         clear_bit(idx, hw_events->used_mask);
 224         if (armpmu->clear_event_idx)
 225                 armpmu->clear_event_idx(hw_events, event);
 226
 227         perf_event_update_userpage(event);
 228 }
 229
 230 static int
 231 armpmu_add(struct perf_event *event, int flags)
 232 {
 233         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 234         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 235         struct hw_perf_event *hwc = &event->hw;
 236         int idx;
 237         int err = 0;
 238
 239         /* An event following a process won't be stopped earlier */
 240         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
 241                 return -ENOENT;
 242
 243         perf_pmu_disable(event->pmu);
 244
 245         /* If we don't have a space for the counter then finish early. */
 246         idx = armpmu->get_event_idx(hw_events, event);
 247         if (idx < 0) {
 248                 err = idx;
 249                 goto out;
 250         }
 251
 252         /*
 253          * If there is an event in the counter we are going to use then make
 254          * sure it is disabled.
 255          */
 256         event->hw.idx = idx;
 257         armpmu->disable(event);
 258         hw_events->events[idx] = event;
 259
 260         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 261         if (flags & PERF_EF_START)
 262                 armpmu_start(event, PERF_EF_RELOAD);
 263
 264         /* Propagate our changes to the userspace mapping. */
 265         perf_event_update_userpage(event);
 266
 267 out:
 268         perf_pmu_enable(event->pmu);
 269         return err;
 270 }
 271
 272 static int
 273 validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
 274                                struct perf_event *event)
 275 {
 276         struct arm_pmu *armpmu;
 277
 278         if (is_software_event(event))
 279                 return 1;
 280
 281         /*
 282          * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
 283          * core perf code won't check that the pmu->ctx == leader->ctx
 284          * until after pmu->event_init(event).
 285          */
 286         if (event->pmu != pmu)
 287                 return 0;
 288
 289         if (event->state < PERF_EVENT_STATE_OFF)
 290                 return 1;
 291
 292         if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
 293                 return 1;
 294
 295         armpmu = to_arm_pmu(event->pmu);
 296         return armpmu->get_event_idx(hw_events, event) >= 0;
 297 }
 298
 299 static int
 300 validate_group(struct perf_event *event)
 301 {
 302         struct perf_event *sibling, *leader = event->group_leader;
 303         struct pmu_hw_events fake_pmu;
 304
 305         /*
 306          * Initialise the fake PMU. We only need to populate the
 307          * used_mask for the purposes of validation.
 308          */
 309         memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
 310
 311         if (!validate_event(event->pmu, &fake_pmu, leader))
 312                 return -EINVAL;
 313
 314         list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
 315                 if (!validate_event(event->pmu, &fake_pmu, sibling))
 316                         return -EINVAL;
 317         }
 318
 319         if (!validate_event(event->pmu, &fake_pmu, event))
 320                 return -EINVAL;
 321
 322         return 0;
 323 }
 324
 325 static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
 326 {
 327         struct arm_pmu *armpmu;
 328         struct platform_device *plat_device;
 329         struct arm_pmu_platdata *plat;
 330         int ret;
 331         u64 start_clock, finish_clock;
 332
 333         /*
 334          * we request the IRQ with a (possibly percpu) struct arm_pmu**, but
 335          * the handlers expect a struct arm_pmu*. The percpu_irq framework will
 336          * do any necessary shifting, we just need to perform the first
 337          * dereference.
 338          */
 339         armpmu = *(void **)dev;
 340         plat_device = armpmu->plat_device;
 341         plat = dev_get_platdata(&plat_device->dev);
 342
 343         start_clock = sched_clock();
 344         if (plat && plat->handle_irq)
 345                 ret = plat->handle_irq(irq, armpmu, armpmu->handle_irq);
 346         else
 347                 ret = armpmu->handle_irq(irq, armpmu);
 348         finish_clock = sched_clock();
 349
 350         perf_sample_event_took(finish_clock - start_clock);
 351         return ret;
 352 }
 353
 354 static void
 355 armpmu_release_hardware(struct arm_pmu *armpmu)
 356 {
 357         armpmu->free_irq(armpmu);
 358 }
 359
 360 static int
 361 armpmu_reserve_hardware(struct arm_pmu *armpmu)
 362 {
 363         int err = armpmu->request_irq(armpmu, armpmu_dispatch_irq);
 364         if (err) {
 365                 armpmu_release_hardware(armpmu);
 366                 return err;
 367         }
 368
 369         return 0;
 370 }
 371
 372 static void
 373 hw_perf_event_destroy(struct perf_event *event)
 374 {
 375         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 376         atomic_t *active_events  = &armpmu->active_events;
 377         struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
 378
 379         if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
 380                 armpmu_release_hardware(armpmu);
 381                 mutex_unlock(pmu_reserve_mutex);
 382         }
 383 }
 384
 385 static int
 386 event_requires_mode_exclusion(struct perf_event_attr *attr)
 387 {
 388         return attr->exclude_idle || attr->exclude_user ||
 389                attr->exclude_kernel || attr->exclude_hv;
 390 }
 391
 392 static int
 393 __hw_perf_event_init(struct perf_event *event)
 394 {
 395         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 396         struct hw_perf_event *hwc = &event->hw;
 397         int mapping;
 398
 399         mapping = armpmu->map_event(event);
 400
 401         if (mapping < 0) {
 402                 pr_debug("event %x:%llx not supported\n", event->attr.type,
 403                          event->attr.config);
 404                 return mapping;
 405         }
 406
 407         /*
 408          * We don't assign an index until we actually place the event onto
 409          * hardware. Use -1 to signify that we haven't decided where to put it
 410          * yet. For SMP systems, each core has it's own PMU so we can't do any
 411          * clever allocation or constraints checking at this point.
 412          */
 413         hwc->idx                = -1;
 414         hwc->config_base        = 0;
 415         hwc->config             = 0;
 416         hwc->event_base         = 0;
 417
 418         /*
 419          * Check whether we need to exclude the counter from certain modes.
 420          */
 421         if ((!armpmu->set_event_filter ||
 422              armpmu->set_event_filter(hwc, &event->attr)) &&
 423              event_requires_mode_exclusion(&event->attr)) {
 424                 pr_debug("ARM performance counters do not support "
 425                          "mode exclusion\n");
 426                 return -EOPNOTSUPP;
 427         }
 428
 429         /*
 430          * Store the event encoding into the config_base field.
 431          */
 432         hwc->config_base            |= (unsigned long)mapping;
 433
 434         if (!is_sampling_event(event)) {
 435                 /*
 436                  * For non-sampling runs, limit the sample_period to half
 437                  * of the counter width. That way, the new counter value
 438                  * is far less likely to overtake the previous one unless
 439                  * you have some serious IRQ latency issues.
 440                  */
 441                 hwc->sample_period  = armpmu->max_period >> 1;
 442                 hwc->last_period    = hwc->sample_period;
 443                 local64_set(&hwc->period_left, hwc->sample_period);
 444         }
 445
 446         if (event->group_leader != event) {
 447                 if (validate_group(event) != 0)
 448                         return -EINVAL;
 449         }
 450
 451         return 0;
 452 }
 453
 454 static int armpmu_event_init(struct perf_event *event)
 455 {
 456         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 457         int err = 0;
 458         atomic_t *active_events = &armpmu->active_events;
 459
 460         /*
 461          * Reject CPU-affine events for CPUs that are of a different class to
 462          * that which this PMU handles. Process-following events (where
 463          * event->cpu == -1) can be migrated between CPUs, and thus we have to
 464          * reject them later (in armpmu_add) if they're scheduled on a
 465          * different class of CPU.
 466          */
 467         if (event->cpu != -1 &&
 468                 !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))
 469                 return -ENOENT;
 470
 471         /* does not support taken branch sampling */
 472         if (has_branch_stack(event))
 473                 return -EOPNOTSUPP;
 474
 475         if (armpmu->map_event(event) == -ENOENT)
 476                 return -ENOENT;
 477
 478         event->destroy = hw_perf_event_destroy;
 479
 480         if (!atomic_inc_not_zero(active_events)) {
 481                 mutex_lock(&armpmu->reserve_mutex);
 482                 if (atomic_read(active_events) == 0)
 483                         err = armpmu_reserve_hardware(armpmu);
 484
 485                 if (!err)
 486                         atomic_inc(active_events);
 487                 mutex_unlock(&armpmu->reserve_mutex);
 488         }
 489
 490         if (err)
 491                 return err;
 492
 493         err = __hw_perf_event_init(event);
 494         if (err)
 495                 hw_perf_event_destroy(event);
 496
 497         return err;
 498 }
 499
 500 static void armpmu_enable(struct pmu *pmu)
 501 {
 502         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 503         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 504         int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
 505
 506         /* For task-bound events we may be called on other CPUs */
 507         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
 508                 return;
 509
 510         if (enabled)
 511                 armpmu->start(armpmu);
 512 }
 513
 514 static void armpmu_disable(struct pmu *pmu)
 515 {
 516         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 517
 518         /* For task-bound events we may be called on other CPUs */
 519         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
 520                 return;
 521
 522         armpmu->stop(armpmu);
 523 }
 524
 525 /*
 526  * In heterogeneous systems, events are specific to a particular
 527  * microarchitecture, and aren't suitable for another. Thus, only match CPUs of
 528  * the same microarchitecture.
 529  */
 530 static int armpmu_filter_match(struct perf_event *event)
 531 {
 532         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 533         unsigned int cpu = smp_processor_id();
 534         return cpumask_test_cpu(cpu, &armpmu->supported_cpus);
 535 }
 536
 537 static void armpmu_init(struct arm_pmu *armpmu)
 538 {
 539         atomic_set(&armpmu->active_events, 0);
 540         mutex_init(&armpmu->reserve_mutex);
 541
 542         armpmu->pmu = (struct pmu) {
 543                 .pmu_enable     = armpmu_enable,
 544                 .pmu_disable    = armpmu_disable,
 545                 .event_init     = armpmu_event_init,
 546                 .add            = armpmu_add,
 547                 .del            = armpmu_del,
 548                 .start          = armpmu_start,
 549                 .stop           = armpmu_stop,
 550                 .read           = armpmu_read,
 551                 .filter_match   = armpmu_filter_match,
 552         };
 553 }
 554
 555 /* Set at runtime when we know what CPU type we are. */
 556 static struct arm_pmu *__oprofile_cpu_pmu;
 557
 558 /*
 559  * Despite the names, these two functions are CPU-specific and are used
 560  * by the OProfile/perf code.
 561  */
 562 const char *perf_pmu_name(void)
 563 {
 564         if (!__oprofile_cpu_pmu)
 565                 return NULL;
 566
 567         return __oprofile_cpu_pmu->name;
 568 }
 569 EXPORT_SYMBOL_GPL(perf_pmu_name);
 570
 571 int perf_num_counters(void)
 572 {
 573         int max_events = 0;
 574
 575         if (__oprofile_cpu_pmu != NULL)
 576                 max_events = __oprofile_cpu_pmu->num_events;
 577
 578         return max_events;
 579 }
 580 EXPORT_SYMBOL_GPL(perf_num_counters);
 581
 582 static void cpu_pmu_enable_percpu_irq(void *data)
 583 {
 584         int irq = *(int *)data;
 585
 586         enable_percpu_irq(irq, IRQ_TYPE_NONE);
 587 }
 588
 589 static void cpu_pmu_disable_percpu_irq(void *data)
 590 {
 591         int irq = *(int *)data;
 592
 593         disable_percpu_irq(irq);
 594 }
 595
 596 static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu)
 597 {
 598         int i, irq, irqs;
 599         struct platform_device *pmu_device = cpu_pmu->plat_device;
 600         struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events;
 601
 602         irqs = min(pmu_device->num_resources, num_possible_cpus());
 603
 604         irq = platform_get_irq(pmu_device, 0);
 605         if (irq >= 0 && irq_is_percpu(irq)) {
 606                 on_each_cpu_mask(&cpu_pmu->supported_cpus,
 607                                  cpu_pmu_disable_percpu_irq, &irq, 1);
 608                 free_percpu_irq(irq, &hw_events->percpu_pmu);
 609         } else {
 610                 for (i = 0; i < irqs; ++i) {
 611                         int cpu = i;
 612
 613                         if (cpu_pmu->irq_affinity)
 614                                 cpu = cpu_pmu->irq_affinity[i];
 615
 616                         if (!cpumask_test_and_clear_cpu(cpu, &cpu_pmu->active_irqs))
 617                                 continue;
 618                         irq = platform_get_irq(pmu_device, i);
 619                         if (irq >= 0)
 620                                 free_irq(irq, per_cpu_ptr(&hw_events->percpu_pmu, cpu));
 621                 }
 622         }
 623 }
 624
 625 static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
 626 {
 627         int i, err, irq, irqs;
 628         struct platform_device *pmu_device = cpu_pmu->plat_device;
 629         struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events;
 630
 631         if (!pmu_device)
 632                 return -ENODEV;
 633
 634         irqs = min(pmu_device->num_resources, num_possible_cpus());
 635         if (irqs < 1) {
 636                 pr_warn_once("perf/ARM: No irqs for PMU defined, sampling events not supported\n");
 637                 return 0;
 638         }
 639
 640         irq = platform_get_irq(pmu_device, 0);
 641         if (irq >= 0 && irq_is_percpu(irq)) {
 642                 err = request_percpu_irq(irq, handler, "arm-pmu",
 643                                          &hw_events->percpu_pmu);
 644                 if (err) {
 645                         pr_err("unable to request IRQ%d for ARM PMU counters\n",
 646                                 irq);
 647                         return err;
 648                 }
 649
 650                 on_each_cpu_mask(&cpu_pmu->supported_cpus,
 651                                  cpu_pmu_enable_percpu_irq, &irq, 1);
 652         } else {
 653                 for (i = 0; i < irqs; ++i) {
 654                         int cpu = i;
 655
 656                         err = 0;
 657                         irq = platform_get_irq(pmu_device, i);
 658                         if (irq < 0)
 659                                 continue;
 660
 661                         if (cpu_pmu->irq_affinity)
 662                                 cpu = cpu_pmu->irq_affinity[i];
 663
 664                         /*
 665                          * If we have a single PMU interrupt that we can't shift,
 666                          * assume that we're running on a uniprocessor machine and
 667                          * continue. Otherwise, continue without this interrupt.
 668                          */
 669                         if (irq_set_affinity(irq, cpumask_of(cpu)) && irqs > 1) {
 670                                 pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
 671                                         irq, cpu);
 672                                 continue;
 673                         }
 674
 675                         err = request_irq(irq, handler,
 676                                           IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu",
 677                                           per_cpu_ptr(&hw_events->percpu_pmu, cpu));
 678                         if (err) {
 679                                 pr_err("unable to request IRQ%d for ARM PMU counters\n",
 680                                         irq);
 681                                 return err;
 682                         }
 683
 684                         cpumask_set_cpu(cpu, &cpu_pmu->active_irqs);
 685                 }
 686         }
 687
 688         return 0;
 689 }
 690
 691 static DEFINE_SPINLOCK(arm_pmu_lock);
 692 static LIST_HEAD(arm_pmu_list);
 693
 694 /*
 695  * PMU hardware loses all context when a CPU goes offline.
 696  * When a CPU is hotplugged back in, since some hardware registers are
 697  * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
 698  * junk values out of them.
 699  */
 700 static int arm_perf_starting_cpu(unsigned int cpu)
 701 {
 702         struct arm_pmu *pmu;
 703
 704         spin_lock(&arm_pmu_lock);
 705         list_for_each_entry(pmu, &arm_pmu_list, entry) {
 706
 707                 if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
 708                         continue;
 709                 if (pmu->reset)
 710                         pmu->reset(pmu);
 711         }
 712         spin_unlock(&arm_pmu_lock);
 713         return 0;
 714 }
 715
 716 #ifdef CONFIG_CPU_PM
 717 static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd)
 718 {
 719         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 720         struct perf_event *event;
 721         int idx;
 722
 723         for (idx = 0; idx < armpmu->num_events; idx++) {
 724                 /*
 725                  * If the counter is not used skip it, there is no
 726                  * need of stopping/restarting it.
 727                  */
 728                 if (!test_bit(idx, hw_events->used_mask))
 729                         continue;
 730
 731                 event = hw_events->events[idx];
 732
 733                 switch (cmd) {
 734                 case CPU_PM_ENTER:
 735                         /*
 736                          * Stop and update the counter
 737                          */
 738                         armpmu_stop(event, PERF_EF_UPDATE);
 739                         break;
 740                 case CPU_PM_EXIT:
 741                 case CPU_PM_ENTER_FAILED:
 742                          /*
 743                           * Restore and enable the counter.
 744                           * armpmu_start() indirectly calls
 745                           *
 746                           * perf_event_update_userpage()
 747                           *
 748                           * that requires RCU read locking to be functional,
 749                           * wrap the call within RCU_NONIDLE to make the
 750                           * RCU subsystem aware this cpu is not idle from
 751                           * an RCU perspective for the armpmu_start() call
 752                           * duration.
 753                           */
 754                         RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD));
 755                         break;
 756                 default:
 757                         break;
 758                 }
 759         }
 760 }
 761
 762 static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
 763                              void *v)
 764 {
 765         struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb);
 766         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 767         int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
 768
 769         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
 770                 return NOTIFY_DONE;
 771
 772         /*
 773          * Always reset the PMU registers on power-up even if
 774          * there are no events running.
 775          */
 776         if (cmd == CPU_PM_EXIT && armpmu->reset)
 777                 armpmu->reset(armpmu);
 778
 779         if (!enabled)
 780                 return NOTIFY_OK;
 781
 782         switch (cmd) {
 783         case CPU_PM_ENTER:
 784                 armpmu->stop(armpmu);
 785                 cpu_pm_pmu_setup(armpmu, cmd);
 786                 break;
 787         case CPU_PM_EXIT:
 788                 cpu_pm_pmu_setup(armpmu, cmd);
 789         case CPU_PM_ENTER_FAILED:
 790                 armpmu->start(armpmu);
 791                 break;
 792         default:
 793                 return NOTIFY_DONE;
 794         }
 795
 796         return NOTIFY_OK;
 797 }
 798
 799 static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu)
 800 {
 801         cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify;
 802         return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb);
 803 }
 804
 805 static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu)
 806 {
 807         cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb);
 808 }
 809 #else
 810 static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; }
 811 static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { }
 812 #endif
 813
 814 static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
 815 {
 816         int err;
 817         int cpu;
 818         struct pmu_hw_events __percpu *cpu_hw_events;
 819
 820         cpu_hw_events = alloc_percpu(struct pmu_hw_events);
 821         if (!cpu_hw_events)
 822                 return -ENOMEM;
 823
 824         spin_lock(&arm_pmu_lock);
 825         list_add_tail(&cpu_pmu->entry, &arm_pmu_list);
 826         spin_unlock(&arm_pmu_lock);
 827
 828         err = cpu_pm_pmu_register(cpu_pmu);
 829         if (err)
 830                 goto out_unregister;
 831
 832         for_each_possible_cpu(cpu) {
 833                 struct pmu_hw_events *events = per_cpu_ptr(cpu_hw_events, cpu);
 834                 raw_spin_lock_init(&events->pmu_lock);
 835                 events->percpu_pmu = cpu_pmu;
 836         }
 837
 838         cpu_pmu->hw_events      = cpu_hw_events;
 839         cpu_pmu->request_irq    = cpu_pmu_request_irq;
 840         cpu_pmu->free_irq       = cpu_pmu_free_irq;
 841
 842         /* Ensure the PMU has sane values out of reset. */
 843         if (cpu_pmu->reset)
 844                 on_each_cpu_mask(&cpu_pmu->supported_cpus, cpu_pmu->reset,
 845                          cpu_pmu, 1);
 846
 847         /* If no interrupts available, set the corresponding capability flag */
 848         if (!platform_get_irq(cpu_pmu->plat_device, 0))
 849                 cpu_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
 850
 851         /*
 852          * This is a CPU PMU potentially in a heterogeneous configuration (e.g.
 853          * big.LITTLE). This is not an uncore PMU, and we have taken ctx
 854          * sharing into account (e.g. with our pmu::filter_match callback and
 855          * pmu::event_init group validation).
 856          */
 857         cpu_pmu->pmu.capabilities |= PERF_PMU_CAP_HETEROGENEOUS_CPUS;
 858
 859         return 0;
 860
 861 out_unregister:
 862         spin_lock(&arm_pmu_lock);
 863         list_del(&cpu_pmu->entry);
 864         spin_unlock(&arm_pmu_lock);
 865         free_percpu(cpu_hw_events);
 866         return err;
 867 }
 868
 869 static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
 870 {
 871         cpu_pm_pmu_unregister(cpu_pmu);
 872         spin_lock(&arm_pmu_lock);
 873         list_del(&cpu_pmu->entry);
 874         spin_unlock(&arm_pmu_lock);
 875         free_percpu(cpu_pmu->hw_events);
 876 }
 877
 878 /*
 879  * CPU PMU identification and probing.
 880  */
 881 static int probe_current_pmu(struct arm_pmu *pmu,
 882                              const struct pmu_probe_info *info)
 883 {
 884         int cpu = get_cpu();
 885         unsigned int cpuid = read_cpuid_id();
 886         int ret = -ENODEV;
 887
 888         pr_info("probing PMU on CPU %d\n", cpu);
 889
 890         for (; info->init != NULL; info++) {
 891                 if ((cpuid & info->mask) != info->cpuid)
 892                         continue;
 893                 ret = info->init(pmu);
 894                 break;
 895         }
 896
 897         put_cpu();
 898         return ret;
 899 }
 900
 901 static int of_pmu_irq_cfg(struct arm_pmu *pmu)
 902 {
 903         int *irqs, i = 0;
 904         bool using_spi = false;
 905         struct platform_device *pdev = pmu->plat_device;
 906
 907         irqs = kcalloc(pdev->num_resources, sizeof(*irqs), GFP_KERNEL);
 908         if (!irqs)
 909                 return -ENOMEM;
 910
 911         do {
 912                 struct device_node *dn;
 913                 int cpu, irq;
 914
 915                 /* See if we have an affinity entry */
 916                 dn = of_parse_phandle(pdev->dev.of_node, "interrupt-affinity", i);
 917                 if (!dn)
 918                         break;
 919
 920                 /* Check the IRQ type and prohibit a mix of PPIs and SPIs */
 921                 irq = platform_get_irq(pdev, i);
 922                 if (irq >= 0) {
 923                         bool spi = !irq_is_percpu(irq);
 924
 925                         if (i > 0 && spi != using_spi) {
 926                                 pr_err("PPI/SPI IRQ type mismatch for %s!\n",
 927                                         dn->name);
 928                                 of_node_put(dn);
 929                                 kfree(irqs);
 930                                 return -EINVAL;
 931                         }
 932
 933                         using_spi = spi;
 934                 }
 935
 936                 /* Now look up the logical CPU number */
 937                 for_each_possible_cpu(cpu) {
 938                         struct device_node *cpu_dn;
 939
 940                         cpu_dn = of_cpu_device_node_get(cpu);
 941                         of_node_put(cpu_dn);
 942
 943                         if (dn == cpu_dn)
 944                                 break;
 945                 }
 946
 947                 if (cpu >= nr_cpu_ids) {
 948                         pr_warn("Failed to find logical CPU for %s\n",
 949                                 dn->name);
 950                         of_node_put(dn);
 951                         cpumask_setall(&pmu->supported_cpus);
 952                         break;
 953                 }
 954                 of_node_put(dn);
 955
 956                 /* For SPIs, we need to track the affinity per IRQ */
 957                 if (using_spi) {
 958                         if (i >= pdev->num_resources)
 959                                 break;
 960
 961                         irqs[i] = cpu;
 962                 }
 963
 964                 /* Keep track of the CPUs containing this PMU type */
 965                 cpumask_set_cpu(cpu, &pmu->supported_cpus);
 966                 i++;
 967         } while (1);
 968
 969         /* If we didn't manage to parse anything, try the interrupt affinity */
 970         if (cpumask_weight(&pmu->supported_cpus) == 0) {
 971                 int irq = platform_get_irq(pdev, 0);
 972
 973                 if (irq >= 0 && irq_is_percpu(irq)) {
 974                         /* If using PPIs, check the affinity of the partition */
 975                         int ret;
 976
 977                         ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus);
 978                         if (ret) {
 979                                 kfree(irqs);
 980                                 return ret;
 981                         }
 982                 } else {
 983                         /* Otherwise default to all CPUs */
 984                         cpumask_setall(&pmu->supported_cpus);
 985                 }
 986         }
 987
 988         /* If we matched up the IRQ affinities, use them to route the SPIs */
 989         if (using_spi && i == pdev->num_resources)
 990                 pmu->irq_affinity = irqs;
 991         else
 992                 kfree(irqs);
 993
 994         return 0;
 995 }
 996
 997 int arm_pmu_device_probe(struct platform_device *pdev,
 998                          const struct of_device_id *of_table,
 999                          const struct pmu_probe_info *probe_table)
1000 {
1001         const struct of_device_id *of_id;
1002         const int (*init_fn)(struct arm_pmu *);
1003         struct device_node *node = pdev->dev.of_node;
1004         struct arm_pmu *pmu;
1005         int ret = -ENODEV;
1006
1007         pmu = kzalloc(sizeof(struct arm_pmu), GFP_KERNEL);
1008         if (!pmu) {
1009                 pr_info("failed to allocate PMU device!\n");
1010                 return -ENOMEM;
1011         }
1012
1013         armpmu_init(pmu);
1014
1015         pmu->plat_device = pdev;
1016
1017         if (node && (of_id = of_match_node(of_table, pdev->dev.of_node))) {
1018                 init_fn = of_id->data;
1019
1020                 pmu->secure_access = of_property_read_bool(pdev->dev.of_node,
1021                                                            "secure-reg-access");
1022
1023                 /* arm64 systems boot only as non-secure */
1024                 if (IS_ENABLED(CONFIG_ARM64) && pmu->secure_access) {
1025                         pr_warn("ignoring \"secure-reg-access\" property for arm64\n");
1026                         pmu->secure_access = false;
1027                 }
1028
1029                 ret = of_pmu_irq_cfg(pmu);
1030                 if (!ret)
1031                         ret = init_fn(pmu);
1032         } else {
1033                 cpumask_setall(&pmu->supported_cpus);
1034                 ret = probe_current_pmu(pmu, probe_table);
1035         }
1036
1037         if (ret) {
1038                 pr_info("%s: failed to probe PMU!\n", of_node_full_name(node));
1039                 goto out_free;
1040         }
1041
1042         ret = cpu_pmu_init(pmu);
1043         if (ret)
1044                 goto out_free;
1045
1046         ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
1047         if (ret)
1048                 goto out_destroy;
1049
1050         if (!__oprofile_cpu_pmu)
1051                 __oprofile_cpu_pmu = pmu;
1052
1053         pr_info("enabled with %s PMU driver, %d counters available\n",
1054                         pmu->name, pmu->num_events);
1055
1056         return 0;
1057
1058 out_destroy:
1059         cpu_pmu_destroy(pmu);
1060 out_free:
1061         pr_info("%s: failed to register PMU devices!\n",
1062                 of_node_full_name(node));
1063         kfree(pmu->irq_affinity);
1064         kfree(pmu);
1065         return ret;
1066 }
1067
1068 static int arm_pmu_hp_init(void)
1069 {
1070         int ret;
1071
1072         ret = cpuhp_setup_state_nocalls(CPUHP_AP_PERF_ARM_STARTING,
1073                                         "AP_PERF_ARM_STARTING",
1074                                         arm_perf_starting_cpu, NULL);
1075         if (ret)
1076                 pr_err("CPU hotplug notifier for ARM PMU could not be registered: %d\n",
1077                        ret);
1078         return ret;
1079 }
1080 subsys_initcall(arm_pmu_hp_init);