drivers/phy/phy-rockchip-usb.c

   1 /*
   2  * Rockchip usb PHY driver
   3  *
   4  * Copyright (C) 2014 Yunzhi Li <lyz@rock-chips.com>
   5  * Copyright (C) 2014 ROCKCHIP, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/io.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/mutex.h>
  23 #include <linux/of.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/phy/phy.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/regulator/consumer.h>
  29 #include <linux/reset.h>
  30 #include <linux/regmap.h>
  31 #include <linux/mfd/syscon.h>
  32
  33 static int enable_usb_uart;
  34
  35 #define HIWORD_UPDATE(val, mask) \
  36                 ((val) | (mask) << 16)
  37
  38 #define UOC_CON0_SIDDQ BIT(13)
  39
  40 struct rockchip_usb_phys {
  41         int reg;
  42         const char *pll_name;
  43 };
  44
  45 struct rockchip_usb_phy_base;
  46 struct rockchip_usb_phy_pdata {
  47         struct rockchip_usb_phys *phys;
  48         int (*init_usb_uart)(struct regmap *grf);
  49         int usb_uart_phy;
  50 };
  51
  52 struct rockchip_usb_phy_base {
  53         struct device *dev;
  54         struct regmap *reg_base;
  55         const struct rockchip_usb_phy_pdata *pdata;
  56 };
  57
  58 struct rockchip_usb_phy {
  59         struct rockchip_usb_phy_base *base;
  60         struct device_node *np;
  61         unsigned int    reg_offset;
  62         struct clk      *clk;
  63         struct clk      *clk480m;
  64         struct clk_hw   clk480m_hw;
  65         struct phy      *phy;
  66         bool            uart_enabled;
  67 };
  68
  69 static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
  70                                            bool siddq)
  71 {
  72         u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ);
  73
  74         return regmap_write(phy->base->reg_base, phy->reg_offset, val);
  75 }
  76
  77 static unsigned long rockchip_usb_phy480m_recalc_rate(struct clk_hw *hw,
  78                                                 unsigned long parent_rate)
  79 {
  80         return 480000000;
  81 }
  82
  83 static void rockchip_usb_phy480m_disable(struct clk_hw *hw)
  84 {
  85         struct rockchip_usb_phy *phy = container_of(hw,
  86                                                     struct rockchip_usb_phy,
  87                                                     clk480m_hw);
  88
  89         /* Power down usb phy analog blocks by set siddq 1 */
  90         rockchip_usb_phy_power(phy, 1);
  91 }
  92
  93 static int rockchip_usb_phy480m_enable(struct clk_hw *hw)
  94 {
  95         struct rockchip_usb_phy *phy = container_of(hw,
  96                                                     struct rockchip_usb_phy,
  97                                                     clk480m_hw);
  98
  99         /* Power up usb phy analog blocks by set siddq 0 */
 100         return rockchip_usb_phy_power(phy, 0);
 101 }
 102
 103 static int rockchip_usb_phy480m_is_enabled(struct clk_hw *hw)
 104 {
 105         struct rockchip_usb_phy *phy = container_of(hw,
 106                                                     struct rockchip_usb_phy,
 107                                                     clk480m_hw);
 108         int ret;
 109         u32 val;
 110
 111         ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val);
 112         if (ret < 0)
 113                 return ret;
 114
 115         return (val & UOC_CON0_SIDDQ) ? 0 : 1;
 116 }
 117
 118 static const struct clk_ops rockchip_usb_phy480m_ops = {
 119         .enable = rockchip_usb_phy480m_enable,
 120         .disable = rockchip_usb_phy480m_disable,
 121         .is_enabled = rockchip_usb_phy480m_is_enabled,
 122         .recalc_rate = rockchip_usb_phy480m_recalc_rate,
 123 };
 124
 125 static int rockchip_usb_phy_power_off(struct phy *_phy)
 126 {
 127         struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
 128
 129         if (phy->uart_enabled)
 130                 return -EBUSY;
 131
 132         clk_disable_unprepare(phy->clk480m);
 133
 134         return 0;
 135 }
 136
 137 static int rockchip_usb_phy_power_on(struct phy *_phy)
 138 {
 139         struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
 140
 141         if (phy->uart_enabled)
 142                 return -EBUSY;
 143
 144         return clk_prepare_enable(phy->clk480m);
 145 }
 146
 147 static const struct phy_ops ops = {
 148         .power_on       = rockchip_usb_phy_power_on,
 149         .power_off      = rockchip_usb_phy_power_off,
 150         .owner          = THIS_MODULE,
 151 };
 152
 153 static void rockchip_usb_phy_action(void *data)
 154 {
 155         struct rockchip_usb_phy *rk_phy = data;
 156
 157         if (!rk_phy->uart_enabled) {
 158                 of_clk_del_provider(rk_phy->np);
 159                 clk_unregister(rk_phy->clk480m);
 160         }
 161
 162         if (rk_phy->clk)
 163                 clk_put(rk_phy->clk);
 164 }
 165
 166 static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
 167                                  struct device_node *child)
 168 {
 169         struct rockchip_usb_phy *rk_phy;
 170         unsigned int reg_offset;
 171         const char *clk_name;
 172         struct clk_init_data init;
 173         int err, i;
 174
 175         rk_phy = devm_kzalloc(base->dev, sizeof(*rk_phy), GFP_KERNEL);
 176         if (!rk_phy)
 177                 return -ENOMEM;
 178
 179         rk_phy->base = base;
 180         rk_phy->np = child;
 181
 182         if (of_property_read_u32(child, "reg", &reg_offset)) {
 183                 dev_err(base->dev, "missing reg property in node %s\n",
 184                         child->name);
 185                 return -EINVAL;
 186         }
 187
 188         rk_phy->reg_offset = reg_offset;
 189
 190         rk_phy->clk = of_clk_get_by_name(child, "phyclk");
 191         if (IS_ERR(rk_phy->clk))
 192                 rk_phy->clk = NULL;
 193
 194         i = 0;
 195         init.name = NULL;
 196         while (base->pdata->phys[i].reg) {
 197                 if (base->pdata->phys[i].reg == reg_offset) {
 198                         init.name = base->pdata->phys[i].pll_name;
 199                         break;
 200                 }
 201                 i++;
 202         }
 203
 204         if (!init.name) {
 205                 dev_err(base->dev, "phy data not found\n");
 206                 return -EINVAL;
 207         }
 208
 209         if (enable_usb_uart && base->pdata->usb_uart_phy == i) {
 210                 dev_dbg(base->dev, "phy%d used as uart output\n", i);
 211                 rk_phy->uart_enabled = true;
 212         } else {
 213                 if (rk_phy->clk) {
 214                         clk_name = __clk_get_name(rk_phy->clk);
 215                         init.flags = 0;
 216                         init.parent_names = &clk_name;
 217                         init.num_parents = 1;
 218                 } else {
 219                         init.flags = 0;
 220                         init.parent_names = NULL;
 221                         init.num_parents = 0;
 222                 }
 223
 224                 init.ops = &rockchip_usb_phy480m_ops;
 225                 rk_phy->clk480m_hw.init = &init;
 226
 227                 rk_phy->clk480m = clk_register(base->dev, &rk_phy->clk480m_hw);
 228                 if (IS_ERR(rk_phy->clk480m)) {
 229                         err = PTR_ERR(rk_phy->clk480m);
 230                         goto err_clk;
 231                 }
 232
 233                 err = of_clk_add_provider(child, of_clk_src_simple_get,
 234                                         rk_phy->clk480m);
 235                 if (err < 0)
 236                         goto err_clk_prov;
 237         }
 238
 239         err = devm_add_action_or_reset(base->dev, rockchip_usb_phy_action,
 240                                        rk_phy);
 241         if (err)
 242                 return err;
 243
 244         rk_phy->phy = devm_phy_create(base->dev, child, &ops);
 245         if (IS_ERR(rk_phy->phy)) {
 246                 dev_err(base->dev, "failed to create PHY\n");
 247                 return PTR_ERR(rk_phy->phy);
 248         }
 249         phy_set_drvdata(rk_phy->phy, rk_phy);
 250
 251         /*
 252          * When acting as uart-pipe, just keep clock on otherwise
 253          * only power up usb phy when it use, so disable it when init
 254          */
 255         if (rk_phy->uart_enabled)
 256                 return clk_prepare_enable(rk_phy->clk);
 257         else
 258                 return rockchip_usb_phy_power(rk_phy, 1);
 259
 260 err_clk_prov:
 261         if (!rk_phy->uart_enabled)
 262                 clk_unregister(rk_phy->clk480m);
 263 err_clk:
 264         if (rk_phy->clk)
 265                 clk_put(rk_phy->clk);
 266         return err;
 267 }
 268
 269 static const struct rockchip_usb_phy_pdata rk3066a_pdata = {
 270         .phys = (struct rockchip_usb_phys[]){
 271                 { .reg = 0x17c, .pll_name = "sclk_otgphy0_480m" },
 272                 { .reg = 0x188, .pll_name = "sclk_otgphy1_480m" },
 273                 { /* sentinel */ }
 274         },
 275 };
 276
 277 static const struct rockchip_usb_phy_pdata rk3188_pdata = {
 278         .phys = (struct rockchip_usb_phys[]){
 279                 { .reg = 0x10c, .pll_name = "sclk_otgphy0_480m" },
 280                 { .reg = 0x11c, .pll_name = "sclk_otgphy1_480m" },
 281                 { /* sentinel */ }
 282         },
 283 };
 284
 285 #define RK3288_UOC0_CON0                                0x320
 286 #define RK3288_UOC0_CON0_COMMON_ON_N                    BIT(0)
 287 #define RK3288_UOC0_CON0_DISABLE                        BIT(4)
 288
 289 #define RK3288_UOC0_CON2                                0x328
 290 #define RK3288_UOC0_CON2_SOFT_CON_SEL                   BIT(2)
 291
 292 #define RK3288_UOC0_CON3                                0x32c
 293 #define RK3288_UOC0_CON3_UTMI_SUSPENDN                  BIT(0)
 294 #define RK3288_UOC0_CON3_UTMI_OPMODE_NODRIVING          (1 << 1)
 295 #define RK3288_UOC0_CON3_UTMI_OPMODE_MASK               (3 << 1)
 296 #define RK3288_UOC0_CON3_UTMI_XCVRSEELCT_FSTRANSC       (1 << 3)
 297 #define RK3288_UOC0_CON3_UTMI_XCVRSEELCT_MASK           (3 << 3)
 298 #define RK3288_UOC0_CON3_UTMI_TERMSEL_FULLSPEED         BIT(5)
 299 #define RK3288_UOC0_CON3_BYPASSDMEN                     BIT(6)
 300 #define RK3288_UOC0_CON3_BYPASSSEL                      BIT(7)
 301
 302 /*
 303  * Enable the bypass of uart2 data through the otg usb phy.
 304  * Original description in the TRM.
 305  * 1. Disable the OTG block by setting OTGDISABLE0 to 1’b1.
 306  * 2. Disable the pull-up resistance on the D+ line by setting
 307  *    OPMODE0[1:0] to 2’b01.
 308  * 3. To ensure that the XO, Bias, and PLL blocks are powered down in Suspend
 309  *    mode, set COMMONONN to 1’b1.
 310  * 4. Place the USB PHY in Suspend mode by setting SUSPENDM0 to 1’b0.
 311  * 5. Set BYPASSSEL0 to 1’b1.
 312  * 6. To transmit data, controls BYPASSDMEN0, and BYPASSDMDATA0.
 313  * To receive data, monitor FSVPLUS0.
 314  *
 315  * The actual code in the vendor kernel does some things differently.
 316  */
 317 static int __init rk3288_init_usb_uart(struct regmap *grf)
 318 {
 319         u32 val;
 320         int ret;
 321
 322         /*
 323          * COMMON_ON and DISABLE settings are described in the TRM,
 324          * but were not present in the original code.
 325          * Also disable the analog phy components to save power.
 326          */
 327         val = HIWORD_UPDATE(RK3288_UOC0_CON0_COMMON_ON_N
 328                                 | RK3288_UOC0_CON0_DISABLE
 329                                 | UOC_CON0_SIDDQ,
 330                             RK3288_UOC0_CON0_COMMON_ON_N
 331                                 | RK3288_UOC0_CON0_DISABLE
 332                                 | UOC_CON0_SIDDQ);
 333         ret = regmap_write(grf, RK3288_UOC0_CON0, val);
 334         if (ret)
 335                 return ret;
 336
 337         val = HIWORD_UPDATE(RK3288_UOC0_CON2_SOFT_CON_SEL,
 338                             RK3288_UOC0_CON2_SOFT_CON_SEL);
 339         ret = regmap_write(grf, RK3288_UOC0_CON2, val);
 340         if (ret)
 341                 return ret;
 342
 343         val = HIWORD_UPDATE(RK3288_UOC0_CON3_UTMI_OPMODE_NODRIVING
 344                                 | RK3288_UOC0_CON3_UTMI_XCVRSEELCT_FSTRANSC
 345                                 | RK3288_UOC0_CON3_UTMI_TERMSEL_FULLSPEED,
 346                             RK3288_UOC0_CON3_UTMI_SUSPENDN
 347                                 | RK3288_UOC0_CON3_UTMI_OPMODE_MASK
 348                                 | RK3288_UOC0_CON3_UTMI_XCVRSEELCT_MASK
 349                                 | RK3288_UOC0_CON3_UTMI_TERMSEL_FULLSPEED);
 350         ret = regmap_write(grf, RK3288_UOC0_CON3, val);
 351         if (ret)
 352                 return ret;
 353
 354         val = HIWORD_UPDATE(RK3288_UOC0_CON3_BYPASSSEL
 355                                 | RK3288_UOC0_CON3_BYPASSDMEN,
 356                             RK3288_UOC0_CON3_BYPASSSEL
 357                                 | RK3288_UOC0_CON3_BYPASSDMEN);
 358         ret = regmap_write(grf, RK3288_UOC0_CON3, val);
 359         if (ret)
 360                 return ret;
 361
 362         return 0;
 363 }
 364
 365 static const struct rockchip_usb_phy_pdata rk3288_pdata = {
 366         .phys = (struct rockchip_usb_phys[]){
 367                 { .reg = 0x320, .pll_name = "sclk_otgphy0_480m" },
 368                 { .reg = 0x334, .pll_name = "sclk_otgphy1_480m" },
 369                 { .reg = 0x348, .pll_name = "sclk_otgphy2_480m" },
 370                 { /* sentinel */ }
 371         },
 372         .init_usb_uart = rk3288_init_usb_uart,
 373         .usb_uart_phy = 0,
 374 };
 375
 376 static int rockchip_usb_phy_probe(struct platform_device *pdev)
 377 {
 378         struct device *dev = &pdev->dev;
 379         struct rockchip_usb_phy_base *phy_base;
 380         struct phy_provider *phy_provider;
 381         const struct of_device_id *match;
 382         struct device_node *child;
 383         int err;
 384
 385         phy_base = devm_kzalloc(dev, sizeof(*phy_base), GFP_KERNEL);
 386         if (!phy_base)
 387                 return -ENOMEM;
 388
 389         match = of_match_device(dev->driver->of_match_table, dev);
 390         if (!match || !match->data) {
 391                 dev_err(dev, "missing phy data\n");
 392                 return -EINVAL;
 393         }
 394
 395         phy_base->pdata = match->data;
 396
 397         phy_base->dev = dev;
 398         phy_base->reg_base = ERR_PTR(-ENODEV);
 399         if (dev->parent && dev->parent->of_node)
 400                 phy_base->reg_base = syscon_node_to_regmap(
 401                                                 dev->parent->of_node);
 402         if (IS_ERR(phy_base->reg_base))
 403                 phy_base->reg_base = syscon_regmap_lookup_by_phandle(
 404                                                 dev->of_node, "rockchip,grf");
 405         if (IS_ERR(phy_base->reg_base)) {
 406                 dev_err(&pdev->dev, "Missing rockchip,grf property\n");
 407                 return PTR_ERR(phy_base->reg_base);
 408         }
 409
 410         for_each_available_child_of_node(dev->of_node, child) {
 411                 err = rockchip_usb_phy_init(phy_base, child);
 412                 if (err) {
 413                         of_node_put(child);
 414                         return err;
 415                 }
 416         }
 417
 418         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 419         return PTR_ERR_OR_ZERO(phy_provider);
 420 }
 421
 422 static const struct of_device_id rockchip_usb_phy_dt_ids[] = {
 423         { .compatible = "rockchip,rk3066a-usb-phy", .data = &rk3066a_pdata },
 424         { .compatible = "rockchip,rk3188-usb-phy", .data = &rk3188_pdata },
 425         { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
 426         {}
 427 };
 428
 429 MODULE_DEVICE_TABLE(of, rockchip_usb_phy_dt_ids);
 430
 431 static struct platform_driver rockchip_usb_driver = {
 432         .probe          = rockchip_usb_phy_probe,
 433         .driver         = {
 434                 .name   = "rockchip-usb-phy",
 435                 .of_match_table = rockchip_usb_phy_dt_ids,
 436         },
 437 };
 438
 439 module_platform_driver(rockchip_usb_driver);
 440
 441 #ifndef MODULE
 442 static int __init rockchip_init_usb_uart(void)
 443 {
 444         const struct of_device_id *match;
 445         const struct rockchip_usb_phy_pdata *data;
 446         struct device_node *np;
 447         struct regmap *grf;
 448         int ret;
 449
 450         if (!enable_usb_uart)
 451                 return 0;
 452
 453         np = of_find_matching_node_and_match(NULL, rockchip_usb_phy_dt_ids,
 454                                              &match);
 455         if (!np) {
 456                 pr_err("%s: failed to find usbphy node\n", __func__);
 457                 return -ENOTSUPP;
 458         }
 459
 460         pr_debug("%s: using settings for %s\n", __func__, match->compatible);
 461         data = match->data;
 462
 463         if (!data->init_usb_uart) {
 464                 pr_err("%s: usb-uart not available on %s\n",
 465                        __func__, match->compatible);
 466                 return -ENOTSUPP;
 467         }
 468
 469         grf = ERR_PTR(-ENODEV);
 470         if (np->parent)
 471                 grf = syscon_node_to_regmap(np->parent);
 472         if (IS_ERR(grf))
 473                 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
 474         if (IS_ERR(grf)) {
 475                 pr_err("%s: Missing rockchip,grf property, %lu\n",
 476                        __func__, PTR_ERR(grf));
 477                 return PTR_ERR(grf);
 478         }
 479
 480         ret = data->init_usb_uart(grf);
 481         if (ret) {
 482                 pr_err("%s: could not init usb_uart, %d\n", __func__, ret);
 483                 enable_usb_uart = 0;
 484                 return ret;
 485         }
 486
 487         return 0;
 488 }
 489 early_initcall(rockchip_init_usb_uart);
 490
 491 static int __init rockchip_usb_uart(char *buf)
 492 {
 493         enable_usb_uart = true;
 494         return 0;
 495 }
 496 early_param("rockchip.usb_uart", rockchip_usb_uart);
 497 #endif
 498
 499 MODULE_AUTHOR("Yunzhi Li <lyz@rock-chips.com>");
 500 MODULE_DESCRIPTION("Rockchip USB 2.0 PHY driver");
 501 MODULE_LICENSE("GPL v2");