drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

   1 /*
   2  * Copyright (C) 2016 IBM Corp.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9 #include <linux/bitops.h>
  10 #include <linux/init.h>
  11 #include <linux/io.h>
  12 #include <linux/kernel.h>
  13 #include <linux/mutex.h>
  14 #include <linux/of.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pinctrl/pinctrl.h>
  17 #include <linux/pinctrl/pinmux.h>
  18 #include <linux/pinctrl/pinconf.h>
  19 #include <linux/pinctrl/pinconf-generic.h>
  20 #include <linux/string.h>
  21 #include <linux/types.h>
  22
  23 #include "../core.h"
  24 #include "../pinctrl-utils.h"
  25 #include "pinctrl-aspeed.h"
  26
  27 #define ASPEED_G5_NR_PINS 228
  28
  29 #define COND1           SIG_DESC_BIT(SCU90, 6, 0)
  30 #define COND2           { SCU94, GENMASK(1, 0), 0, 0 }
  31
  32 #define B14 0
  33 SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
  34
  35 #define E13 3
  36 SSSF_PIN_DECL(E13, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3));
  37
  38 #define I2C9_DESC       SIG_DESC_SET(SCU90, 22)
  39
  40 #define C14 4
  41 SIG_EXPR_LIST_DECL_SINGLE(SCL9, I2C9, I2C9_DESC, COND1);
  42 SIG_EXPR_LIST_DECL_SINGLE(TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4), COND1);
  43 MS_PIN_DECL(C14, GPIOA4, SCL9, TIMER5);
  44
  45 FUNC_GROUP_DECL(TIMER5, C14);
  46
  47 #define A13 5
  48 SIG_EXPR_LIST_DECL_SINGLE(SDA9, I2C9, I2C9_DESC, COND1);
  49 SIG_EXPR_LIST_DECL_SINGLE(TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5), COND1);
  50 MS_PIN_DECL(A13, GPIOA5, SDA9, TIMER6);
  51
  52 FUNC_GROUP_DECL(TIMER6, A13);
  53
  54 FUNC_GROUP_DECL(I2C9, C14, A13);
  55
  56 #define MDIO2_DESC      SIG_DESC_SET(SCU90, 2)
  57
  58 #define C13 6
  59 SIG_EXPR_LIST_DECL_SINGLE(MDC2, MDIO2, MDIO2_DESC, COND1);
  60 SIG_EXPR_LIST_DECL_SINGLE(TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6), COND1);
  61 MS_PIN_DECL(C13, GPIOA6, MDC2, TIMER7);
  62
  63 FUNC_GROUP_DECL(TIMER7, C13);
  64
  65 #define B13 7
  66 SIG_EXPR_LIST_DECL_SINGLE(MDIO2, MDIO2, MDIO2_DESC, COND1);
  67 SIG_EXPR_LIST_DECL_SINGLE(TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7), COND1);
  68 MS_PIN_DECL(B13, GPIOA7, MDIO2, TIMER8);
  69
  70 FUNC_GROUP_DECL(TIMER8, B13);
  71
  72 FUNC_GROUP_DECL(MDIO2, C13, B13);
  73
  74 #define H20 15
  75 GPIO_PIN_DECL(H20, GPIOB7);
  76
  77 #define SD1_DESC        SIG_DESC_SET(SCU90, 0)
  78
  79 #define C12 16
  80 #define I2C10_DESC      SIG_DESC_SET(SCU90, 23)
  81 SIG_EXPR_LIST_DECL_SINGLE(SD1CLK, SD1, SD1_DESC);
  82 SIG_EXPR_LIST_DECL_SINGLE(SCL10, I2C10, I2C10_DESC);
  83 MS_PIN_DECL(C12, GPIOC0, SD1CLK, SCL10);
  84
  85 #define A12 17
  86 SIG_EXPR_LIST_DECL_SINGLE(SD1CMD, SD1, SD1_DESC);
  87 SIG_EXPR_LIST_DECL_SINGLE(SDA10, I2C10, I2C10_DESC);
  88 MS_PIN_DECL(A12, GPIOC1, SD1CMD, SDA10);
  89
  90 FUNC_GROUP_DECL(I2C10, C12, A12);
  91
  92 #define B12 18
  93 #define I2C11_DESC      SIG_DESC_SET(SCU90, 24)
  94 SIG_EXPR_LIST_DECL_SINGLE(SD1DAT0, SD1, SD1_DESC);
  95 SIG_EXPR_LIST_DECL_SINGLE(SCL11, I2C11, I2C11_DESC);
  96 MS_PIN_DECL(B12, GPIOC2, SD1DAT0, SCL11);
  97
  98 #define D9  19
  99 SIG_EXPR_LIST_DECL_SINGLE(SD1DAT1, SD1, SD1_DESC);
 100 SIG_EXPR_LIST_DECL_SINGLE(SDA11, I2C11, I2C11_DESC);
 101 MS_PIN_DECL(D9, GPIOC3, SD1DAT1, SDA11);
 102
 103 FUNC_GROUP_DECL(I2C11, B12, D9);
 104
 105 #define D10 20
 106 #define I2C12_DESC      SIG_DESC_SET(SCU90, 25)
 107 SIG_EXPR_LIST_DECL_SINGLE(SD1DAT2, SD1, SD1_DESC);
 108 SIG_EXPR_LIST_DECL_SINGLE(SCL12, I2C12, I2C12_DESC);
 109 MS_PIN_DECL(D10, GPIOC4, SD1DAT2, SCL12);
 110
 111 #define E12 21
 112 SIG_EXPR_LIST_DECL_SINGLE(SD1DAT3, SD1, SD1_DESC);
 113 SIG_EXPR_LIST_DECL_SINGLE(SDA12, I2C12, I2C12_DESC);
 114 MS_PIN_DECL(E12, GPIOC5, SD1DAT3, SDA12);
 115
 116 FUNC_GROUP_DECL(I2C12, D10, E12);
 117
 118 #define C11 22
 119 #define I2C13_DESC      SIG_DESC_SET(SCU90, 26)
 120 SIG_EXPR_LIST_DECL_SINGLE(SD1CD, SD1, SD1_DESC);
 121 SIG_EXPR_LIST_DECL_SINGLE(SCL13, I2C13, I2C13_DESC);
 122 MS_PIN_DECL(C11, GPIOC6, SD1CD, SCL13);
 123
 124 #define B11 23
 125 SIG_EXPR_LIST_DECL_SINGLE(SD1WP, SD1, SD1_DESC);
 126 SIG_EXPR_LIST_DECL_SINGLE(SDA13, I2C13, I2C13_DESC);
 127 MS_PIN_DECL(B11, GPIOC7, SD1WP, SDA13);
 128
 129 FUNC_GROUP_DECL(I2C13, C11, B11);
 130 FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11);
 131
 132 #define SD2_DESC        SIG_DESC_SET(SCU90, 1)
 133 #define GPID0_DESC      SIG_DESC_SET(SCU8C, 8)
 134 #define GPID_DESC       SIG_DESC_SET(HW_STRAP1, 21)
 135
 136 #define F19 24
 137 SIG_EXPR_LIST_DECL_SINGLE(SD2CLK, SD2, SD2_DESC);
 138 SIG_EXPR_DECL(GPID0IN, GPID0, GPID0_DESC);
 139 SIG_EXPR_DECL(GPID0IN, GPID, GPID_DESC);
 140 SIG_EXPR_LIST_DECL_DUAL(GPID0IN, GPID0, GPID);
 141 MS_PIN_DECL(F19, GPIOD0, SD2CLK, GPID0IN);
 142
 143 #define E21 25
 144 SIG_EXPR_LIST_DECL_SINGLE(SD2CMD, SD2, SD2_DESC);
 145 SIG_EXPR_DECL(GPID0OUT, GPID0, GPID0_DESC);
 146 SIG_EXPR_DECL(GPID0OUT, GPID, GPID_DESC);
 147 SIG_EXPR_LIST_DECL_DUAL(GPID0OUT, GPID0, GPID);
 148 MS_PIN_DECL(E21, GPIOD1, SD2CMD, GPID0OUT);
 149
 150 FUNC_GROUP_DECL(GPID0, F19, E21);
 151
 152 #define GPID2_DESC      SIG_DESC_SET(SCU8C, 9)
 153
 154 #define D20 26
 155 SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC);
 156 SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC);
 157 SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC);
 158 SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID);
 159 MS_PIN_DECL(D20, GPIOD2, SD2DAT0, GPID2IN);
 160
 161 #define D21 27
 162 SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC);
 163 SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC);
 164 SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC);
 165 SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID);
 166 MS_PIN_DECL(D21, GPIOD3, SD2DAT1, GPID2OUT);
 167
 168 FUNC_GROUP_DECL(GPID2, D20, D21);
 169
 170 #define GPIE_DESC       SIG_DESC_SET(HW_STRAP1, 21)
 171 #define GPIE0_DESC      SIG_DESC_SET(SCU8C, 12)
 172
 173 #define B20 32
 174 SIG_EXPR_LIST_DECL_SINGLE(NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16));
 175 SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC);
 176 SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC);
 177 SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE);
 178 MS_PIN_DECL(B20, GPIOE0, NCTS3, GPIE0IN);
 179
 180 #define C20 33
 181 SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17));
 182 SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC);
 183 SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC);
 184 SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE);
 185 MS_PIN_DECL(C20, GPIE0, NDCD3, GPIE0OUT);
 186
 187 FUNC_GROUP_DECL(GPIE0, B20, C20);
 188
 189 #define SPI1_DESC       SIG_DESC_SET(HW_STRAP1, 13)
 190 #define C18 64
 191 SIG_EXPR_LIST_DECL_SINGLE(SYSCS, SPI1, COND1, SPI1_DESC);
 192 SS_PIN_DECL(C18, GPIOI0, SYSCS);
 193
 194 #define E15 65
 195 SIG_EXPR_LIST_DECL_SINGLE(SYSCK, SPI1, COND1, SPI1_DESC);
 196 SS_PIN_DECL(E15, GPIOI1, SYSCK);
 197
 198 #define A14 66
 199 SIG_EXPR_LIST_DECL_SINGLE(SYSMOSI, SPI1, COND1, SPI1_DESC);
 200 SS_PIN_DECL(A14, GPIOI2, SYSMOSI);
 201
 202 #define C16 67
 203 SIG_EXPR_LIST_DECL_SINGLE(SYSMISO, SPI1, COND1, SPI1_DESC);
 204 SS_PIN_DECL(C16, GPIOI3, SYSMISO);
 205
 206 FUNC_GROUP_DECL(SPI1, C18, E15, A14, C16);
 207
 208 #define L2 73
 209 SIG_EXPR_LIST_DECL_SINGLE(SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9));
 210 SS_PIN_DECL(L2, GPIOJ1, SGPMLD);
 211
 212 #define N3 74
 213 SIG_EXPR_LIST_DECL_SINGLE(SGPMO, SGPM, SIG_DESC_SET(SCU84, 10));
 214 SS_PIN_DECL(N3, GPIOJ2, SGPMO);
 215
 216 #define N4 75
 217 SIG_EXPR_LIST_DECL_SINGLE(SGPMI, SGPM, SIG_DESC_SET(SCU84, 11));
 218 SS_PIN_DECL(N4, GPIOJ3, SGPMI);
 219
 220 #define I2C5_DESC       SIG_DESC_SET(SCU90, 18)
 221
 222 #define L3 80
 223 SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
 224 SS_PIN_DECL(L3, GPIOK0, SCL5);
 225
 226 #define L4 81
 227 SIG_EXPR_LIST_DECL_SINGLE(SDA5, I2C5, I2C5_DESC);
 228 SS_PIN_DECL(L4, GPIOK1, SDA5);
 229
 230 FUNC_GROUP_DECL(I2C5, L3, L4);
 231
 232 #define I2C6_DESC       SIG_DESC_SET(SCU90, 19)
 233
 234 #define L1 82
 235 SIG_EXPR_LIST_DECL_SINGLE(SCL6, I2C6, I2C6_DESC);
 236 SS_PIN_DECL(L1, GPIOK2, SCL6);
 237
 238 #define N2 83
 239 SIG_EXPR_LIST_DECL_SINGLE(SDA6, I2C6, I2C6_DESC);
 240 SS_PIN_DECL(N2, GPIOK3, SDA6);
 241
 242 FUNC_GROUP_DECL(I2C6, L1, N2);
 243
 244 #define I2C7_DESC       SIG_DESC_SET(SCU90, 20)
 245
 246 #define N1 84
 247 SIG_EXPR_LIST_DECL_SINGLE(SCL7, I2C7, I2C7_DESC);
 248 SS_PIN_DECL(N1, GPIOK4, SCL7);
 249
 250 #define P1 85
 251 SIG_EXPR_LIST_DECL_SINGLE(SDA7, I2C7, I2C7_DESC);
 252 SS_PIN_DECL(P1, GPIOK5, SDA7);
 253
 254 FUNC_GROUP_DECL(I2C7, N1, P1);
 255
 256 #define I2C8_DESC       SIG_DESC_SET(SCU90, 21)
 257
 258 #define P2 86
 259 SIG_EXPR_LIST_DECL_SINGLE(SCL8, I2C8, I2C8_DESC);
 260 SS_PIN_DECL(P2, GPIOK6, SCL8);
 261
 262 #define R1 87
 263 SIG_EXPR_LIST_DECL_SINGLE(SDA8, I2C8, I2C8_DESC);
 264 SS_PIN_DECL(R1, GPIOK7, SDA8);
 265
 266 FUNC_GROUP_DECL(I2C8, P2, R1);
 267
 268 #define VPIOFF0_DESC    { SCU90, GENMASK(5, 4), 0, 0 }
 269 #define VPIOFF1_DESC    { SCU90, GENMASK(5, 4), 1, 0 }
 270 #define VPI24_DESC      { SCU90, GENMASK(5, 4), 2, 0 }
 271 #define VPIRSVD_DESC    { SCU90, GENMASK(5, 4), 3, 0 }
 272
 273 #define V2 104
 274 #define V2_DESC         SIG_DESC_SET(SCU88, 0)
 275 SIG_EXPR_LIST_DECL_SINGLE(DASHN0, DASHN0, VPIRSVD_DESC, V2_DESC);
 276 SIG_EXPR_LIST_DECL_SINGLE(PWM0, PWM0, V2_DESC, COND2);
 277 MS_PIN_DECL(V2, GPION0, DASHN0, PWM0);
 278 FUNC_GROUP_DECL(PWM0, V2);
 279
 280 #define W2 105
 281 #define W2_DESC         SIG_DESC_SET(SCU88, 1)
 282 SIG_EXPR_LIST_DECL_SINGLE(DASHN1, DASHN1, VPIRSVD_DESC, W2_DESC);
 283 SIG_EXPR_LIST_DECL_SINGLE(PWM1, PWM1, W2_DESC, COND2);
 284 MS_PIN_DECL(W2, GPION1, DASHN1, PWM1);
 285 FUNC_GROUP_DECL(PWM1, W2);
 286
 287 #define V3 106
 288 #define V3_DESC         SIG_DESC_SET(SCU88, 2)
 289 SIG_EXPR_DECL(VPIG2, VPI24, VPI24_DESC, V3_DESC, COND2);
 290 SIG_EXPR_DECL(VPIG2, VPIRSVD, VPIRSVD_DESC, V3_DESC, COND2);
 291 SIG_EXPR_LIST_DECL_DUAL(VPIG2, VPI24, VPIRSVD);
 292 SIG_EXPR_LIST_DECL_SINGLE(PWM2, PWM2, V3_DESC, COND2);
 293 MS_PIN_DECL(V3, GPION2, VPIG2, PWM2);
 294 FUNC_GROUP_DECL(PWM2, V3);
 295
 296 #define U3 107
 297 #define U3_DESC         SIG_DESC_SET(SCU88, 3)
 298 SIG_EXPR_DECL(VPIG3, VPI24, VPI24_DESC, U3_DESC, COND2);
 299 SIG_EXPR_DECL(VPIG3, VPIRSVD, VPIRSVD_DESC, U3_DESC, COND2);
 300 SIG_EXPR_LIST_DECL_DUAL(VPIG3, VPI24, VPIRSVD);
 301 SIG_EXPR_LIST_DECL_SINGLE(PWM3, PWM3, U3_DESC, COND2);
 302 MS_PIN_DECL(U3, GPION3, VPIG3, PWM3);
 303 FUNC_GROUP_DECL(PWM3, U3);
 304
 305 #define W3 108
 306 #define W3_DESC         SIG_DESC_SET(SCU88, 4)
 307 SIG_EXPR_DECL(VPIG4, VPI24, VPI24_DESC, W3_DESC, COND2);
 308 SIG_EXPR_DECL(VPIG4, VPIRSVD, VPIRSVD_DESC, W3_DESC, COND2);
 309 SIG_EXPR_LIST_DECL_DUAL(VPIG4, VPI24, VPIRSVD);
 310 SIG_EXPR_LIST_DECL_SINGLE(PWM4, PWM4, W3_DESC, COND2);
 311 MS_PIN_DECL(W3, GPION4, VPIG4, PWM4);
 312 FUNC_GROUP_DECL(PWM4, W3);
 313
 314 #define AA3 109
 315 #define AA3_DESC        SIG_DESC_SET(SCU88, 5)
 316 SIG_EXPR_DECL(VPIG5, VPI24, VPI24_DESC, AA3_DESC, COND2);
 317 SIG_EXPR_DECL(VPIG5, VPIRSVD, VPIRSVD_DESC, AA3_DESC, COND2);
 318 SIG_EXPR_LIST_DECL_DUAL(VPIG5, VPI24, VPIRSVD);
 319 SIG_EXPR_LIST_DECL_SINGLE(PWM5, PWM5, AA3_DESC, COND2);
 320 MS_PIN_DECL(AA3, GPION5, VPIG5, PWM5);
 321 FUNC_GROUP_DECL(PWM5, AA3);
 322
 323 #define Y3 110
 324 #define Y3_DESC         SIG_DESC_SET(SCU88, 6)
 325 SIG_EXPR_LIST_DECL_SINGLE(VPIG6, VPI24, VPI24_DESC, Y3_DESC);
 326 SIG_EXPR_LIST_DECL_SINGLE(PWM6, PWM6, Y3_DESC, COND2);
 327 MS_PIN_DECL(Y3, GPION6, VPIG6, PWM6);
 328 FUNC_GROUP_DECL(PWM6, Y3);
 329
 330 #define T4 111
 331 #define T4_DESC         SIG_DESC_SET(SCU88, 7)
 332 SIG_EXPR_LIST_DECL_SINGLE(VPIG7, VPI24, VPI24_DESC, T4_DESC);
 333 SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, T4_DESC, COND2);
 334 MS_PIN_DECL(T4, GPION7, VPIG7, PWM7);
 335 FUNC_GROUP_DECL(PWM7, T4);
 336
 337 #define V6 127
 338 SIG_EXPR_LIST_DECL_SINGLE(DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28),
 339                 SIG_DESC_SET(SCU88, 23));
 340 SS_PIN_DECL(V6, GPIOP7, DASHV6);
 341
 342 #define I2C3_DESC       SIG_DESC_SET(SCU90, 16)
 343
 344 #define A11 128
 345 SIG_EXPR_LIST_DECL_SINGLE(SCL3, I2C3, I2C3_DESC);
 346 SS_PIN_DECL(A11, GPIOQ0, SCL3);
 347
 348 #define A10 129
 349 SIG_EXPR_LIST_DECL_SINGLE(SDA3, I2C3, I2C3_DESC);
 350 SS_PIN_DECL(A10, GPIOQ1, SDA3);
 351
 352 FUNC_GROUP_DECL(I2C3, A11, A10);
 353
 354 #define I2C4_DESC       SIG_DESC_SET(SCU90, 17)
 355
 356 #define A9 130
 357 SIG_EXPR_LIST_DECL_SINGLE(SCL4, I2C4, I2C4_DESC);
 358 SS_PIN_DECL(A9, GPIOQ2, SCL4);
 359
 360 #define B9 131
 361 SIG_EXPR_LIST_DECL_SINGLE(SDA4, I2C4, I2C4_DESC);
 362 SS_PIN_DECL(B9, GPIOQ3, SDA4);
 363
 364 FUNC_GROUP_DECL(I2C4, A9, B9);
 365
 366 #define I2C14_DESC      SIG_DESC_SET(SCU90, 27)
 367
 368 #define N21 132
 369 SIG_EXPR_LIST_DECL_SINGLE(SCL14, I2C14, I2C14_DESC);
 370 SS_PIN_DECL(N21, GPIOQ4, SCL14);
 371
 372 #define N22 133
 373 SIG_EXPR_LIST_DECL_SINGLE(SDA14, I2C14, I2C14_DESC);
 374 SS_PIN_DECL(N22, GPIOQ5, SDA14);
 375
 376 FUNC_GROUP_DECL(I2C14, N21, N22);
 377
 378 #define B10 134
 379 SSSF_PIN_DECL(B10, GPIOQ6, OSCCLK, SIG_DESC_SET(SCU2C, 1));
 380
 381 #define N20 135
 382 SSSF_PIN_DECL(N20, GPIOQ7, PEWAKE, SIG_DESC_SET(SCU2C, 29));
 383
 384 #define D8 142
 385 SIG_EXPR_LIST_DECL_SINGLE(MDC1, MDIO1, SIG_DESC_SET(SCU88, 30));
 386 SS_PIN_DECL(D8, GPIOR6, MDC1);
 387
 388 #define E10 143
 389 SIG_EXPR_LIST_DECL_SINGLE(MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31));
 390 SS_PIN_DECL(E10, GPIOR7, MDIO1);
 391
 392 FUNC_GROUP_DECL(MDIO1, D8, E10);
 393
 394 /* RGMII1/RMII1 */
 395
 396 #define RMII1_DESC      SIG_DESC_BIT(HW_STRAP1, 6, 0)
 397 #define RMII2_DESC      SIG_DESC_BIT(HW_STRAP1, 7, 0)
 398
 399 #define B5 152
 400 SIG_EXPR_LIST_DECL_SINGLE(GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0));
 401 SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKO, RMII1, RMII1_DESC,
 402                 SIG_DESC_SET(SCU48, 29));
 403 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCK, RGMII1);
 404 MS_PIN_DECL_(B5, SIG_EXPR_LIST_PTR(GPIOT0), SIG_EXPR_LIST_PTR(RMII1RCLKO),
 405                 SIG_EXPR_LIST_PTR(RGMII1TXCK));
 406
 407 #define E9 153
 408 SIG_EXPR_LIST_DECL_SINGLE(GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1));
 409 SIG_EXPR_LIST_DECL_SINGLE(RMII1TXEN, RMII1, RMII1_DESC);
 410 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCTL, RGMII1);
 411 MS_PIN_DECL_(E9, SIG_EXPR_LIST_PTR(GPIOT1), SIG_EXPR_LIST_PTR(RMII1TXEN),
 412                 SIG_EXPR_LIST_PTR(RGMII1TXCTL));
 413
 414 #define F9 154
 415 SIG_EXPR_LIST_DECL_SINGLE(GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2));
 416 SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD0, RMII1, RMII1_DESC);
 417 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD0, RGMII1);
 418 MS_PIN_DECL_(F9, SIG_EXPR_LIST_PTR(GPIOT2), SIG_EXPR_LIST_PTR(RMII1TXD0),
 419                 SIG_EXPR_LIST_PTR(RGMII1TXD0));
 420
 421 #define A5 155
 422 SIG_EXPR_LIST_DECL_SINGLE(GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3));
 423 SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD1, RMII1, RMII1_DESC);
 424 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD1, RGMII1);
 425 MS_PIN_DECL_(A5, SIG_EXPR_LIST_PTR(GPIOT3), SIG_EXPR_LIST_PTR(RMII1TXD1),
 426                 SIG_EXPR_LIST_PTR(RGMII1TXD1));
 427
 428 #define E7 156
 429 SIG_EXPR_LIST_DECL_SINGLE(GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4));
 430 SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH0, RMII1, RMII1_DESC);
 431 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD2, RGMII1);
 432 MS_PIN_DECL_(E7, SIG_EXPR_LIST_PTR(GPIOT4), SIG_EXPR_LIST_PTR(RMII1DASH0),
 433                 SIG_EXPR_LIST_PTR(RGMII1TXD2));
 434
 435 #define D7 157
 436 SIG_EXPR_LIST_DECL_SINGLE(GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5));
 437 SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH1, RMII1, RMII1_DESC);
 438 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD3, RGMII1);
 439 MS_PIN_DECL_(D7, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(RMII1DASH1),
 440                 SIG_EXPR_LIST_PTR(RGMII1TXD3));
 441
 442 #define B2 158
 443 SIG_EXPR_LIST_DECL_SINGLE(GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6));
 444 SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLKO, RMII2, RMII2_DESC,
 445                 SIG_DESC_SET(SCU48, 30));
 446 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCK, RGMII2);
 447 MS_PIN_DECL_(B2, SIG_EXPR_LIST_PTR(GPIOT6), SIG_EXPR_LIST_PTR(RMII2RCLKO),
 448                 SIG_EXPR_LIST_PTR(RGMII2TXCK));
 449
 450 #define B1 159
 451 SIG_EXPR_LIST_DECL_SINGLE(GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7));
 452 SIG_EXPR_LIST_DECL_SINGLE(RMII2TXEN, RMII2, RMII2_DESC);
 453 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCTL, RGMII2);
 454 MS_PIN_DECL_(B1, SIG_EXPR_LIST_PTR(GPIOT7), SIG_EXPR_LIST_PTR(RMII2TXEN),
 455                 SIG_EXPR_LIST_PTR(RGMII2TXCTL));
 456
 457 #define A2 160
 458 SIG_EXPR_LIST_DECL_SINGLE(GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8));
 459 SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD0, RMII2, RMII2_DESC);
 460 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD0, RGMII2);
 461 MS_PIN_DECL_(A2, SIG_EXPR_LIST_PTR(GPIOU0), SIG_EXPR_LIST_PTR(RMII2TXD0),
 462                 SIG_EXPR_LIST_PTR(RGMII2TXD0));
 463
 464 #define B3 161
 465 SIG_EXPR_LIST_DECL_SINGLE(GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9));
 466 SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD1, RMII2, RMII2_DESC);
 467 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD1, RGMII2);
 468 MS_PIN_DECL_(B3, SIG_EXPR_LIST_PTR(GPIOU1), SIG_EXPR_LIST_PTR(RMII2TXD1),
 469                 SIG_EXPR_LIST_PTR(RGMII2TXD1));
 470
 471 #define D5 162
 472 SIG_EXPR_LIST_DECL_SINGLE(GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10));
 473 SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH0, RMII2, RMII2_DESC);
 474 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD2, RGMII2);
 475 MS_PIN_DECL_(D5, SIG_EXPR_LIST_PTR(GPIOU2), SIG_EXPR_LIST_PTR(RMII2DASH0),
 476                 SIG_EXPR_LIST_PTR(RGMII2TXD2));
 477
 478 #define D4 163
 479 SIG_EXPR_LIST_DECL_SINGLE(GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11));
 480 SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH1, RMII2, RMII2_DESC);
 481 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD3, RGMII2);
 482 MS_PIN_DECL_(D4, SIG_EXPR_LIST_PTR(GPIOU3), SIG_EXPR_LIST_PTR(RMII2DASH1),
 483                 SIG_EXPR_LIST_PTR(RGMII2TXD3));
 484
 485 #define B4 164
 486 SIG_EXPR_LIST_DECL_SINGLE(GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12));
 487 SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKI, RMII1, RMII1_DESC);
 488 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCK, RGMII1);
 489 MS_PIN_DECL_(B4, SIG_EXPR_LIST_PTR(GPIOU4), SIG_EXPR_LIST_PTR(RMII1RCLKI),
 490                 SIG_EXPR_LIST_PTR(RGMII1RXCK));
 491
 492 #define A4 165
 493 SIG_EXPR_LIST_DECL_SINGLE(GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13));
 494 SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH2, RMII1, RMII1_DESC);
 495 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCTL, RGMII1);
 496 MS_PIN_DECL_(A4, SIG_EXPR_LIST_PTR(GPIOU5), SIG_EXPR_LIST_PTR(RMII1DASH2),
 497                 SIG_EXPR_LIST_PTR(RGMII1RXCTL));
 498
 499 #define A3 166
 500 SIG_EXPR_LIST_DECL_SINGLE(GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14));
 501 SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD0, RMII1, RMII1_DESC);
 502 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD0, RGMII1);
 503 MS_PIN_DECL_(A3, SIG_EXPR_LIST_PTR(GPIOU6), SIG_EXPR_LIST_PTR(RMII1RXD0),
 504                 SIG_EXPR_LIST_PTR(RGMII1RXD0));
 505
 506 #define D6 167
 507 SIG_EXPR_LIST_DECL_SINGLE(GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15));
 508 SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD1, RMII1, RMII1_DESC);
 509 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD1, RGMII1);
 510 MS_PIN_DECL_(D6, SIG_EXPR_LIST_PTR(GPIOU7), SIG_EXPR_LIST_PTR(RMII1RXD1),
 511                 SIG_EXPR_LIST_PTR(RGMII1RXD1));
 512
 513 #define C5 168
 514 SIG_EXPR_LIST_DECL_SINGLE(GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16));
 515 SIG_EXPR_LIST_DECL_SINGLE(RMII1CRSDV, RMII1, RMII1_DESC);
 516 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD2, RGMII1);
 517 MS_PIN_DECL_(C5, SIG_EXPR_LIST_PTR(GPIOV0), SIG_EXPR_LIST_PTR(RMII1CRSDV),
 518                 SIG_EXPR_LIST_PTR(RGMII1RXD2));
 519
 520 #define C4 169
 521 SIG_EXPR_LIST_DECL_SINGLE(GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17));
 522 SIG_EXPR_LIST_DECL_SINGLE(RMII1RXER, RMII1, RMII1_DESC);
 523 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD3, RGMII1);
 524 MS_PIN_DECL_(C4, SIG_EXPR_LIST_PTR(GPIOV1), SIG_EXPR_LIST_PTR(RMII1RXER),
 525                 SIG_EXPR_LIST_PTR(RGMII1RXD3));
 526
 527 FUNC_GROUP_DECL(RGMII1, B4, A4, A3, D6, C5, C4, B5, E9, F9, A5, E7, D7);
 528 FUNC_GROUP_DECL(RMII1, B4, A3, D6, C5, C4, B5, E9, F9, A5);
 529
 530 #define C2 170
 531 SIG_EXPR_LIST_DECL_SINGLE(GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18));
 532 SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLKI, RMII2, RMII2_DESC);
 533 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCK, RGMII2);
 534 MS_PIN_DECL_(C2, SIG_EXPR_LIST_PTR(GPIOV2), SIG_EXPR_LIST_PTR(RMII2RCLKI),
 535                 SIG_EXPR_LIST_PTR(RGMII2RXCK));
 536
 537 #define C1 171
 538 SIG_EXPR_LIST_DECL_SINGLE(GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19));
 539 SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH2, RMII2, RMII2_DESC);
 540 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCTL, RGMII2);
 541 MS_PIN_DECL_(C1, SIG_EXPR_LIST_PTR(GPIOV3), SIG_EXPR_LIST_PTR(RMII2DASH2),
 542                 SIG_EXPR_LIST_PTR(RGMII2RXCTL));
 543
 544 #define C3 172
 545 SIG_EXPR_LIST_DECL_SINGLE(GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20));
 546 SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD0, RMII2, RMII2_DESC);
 547 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD0, RGMII2);
 548 MS_PIN_DECL_(C3, SIG_EXPR_LIST_PTR(GPIOV4), SIG_EXPR_LIST_PTR(RMII2RXD0),
 549                 SIG_EXPR_LIST_PTR(RGMII2RXD0));
 550
 551 #define D1 173
 552 SIG_EXPR_LIST_DECL_SINGLE(GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21));
 553 SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD1, RMII2, RMII2_DESC);
 554 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD1, RGMII2);
 555 MS_PIN_DECL_(D1, SIG_EXPR_LIST_PTR(GPIOV5), SIG_EXPR_LIST_PTR(RMII2RXD1),
 556                 SIG_EXPR_LIST_PTR(RGMII2RXD1));
 557
 558 #define D2 174
 559 SIG_EXPR_LIST_DECL_SINGLE(GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22));
 560 SIG_EXPR_LIST_DECL_SINGLE(RMII2CRSDV, RMII2, RMII2_DESC);
 561 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD2, RGMII2);
 562 MS_PIN_DECL_(D2, SIG_EXPR_LIST_PTR(GPIOV6), SIG_EXPR_LIST_PTR(RMII2CRSDV),
 563                 SIG_EXPR_LIST_PTR(RGMII2RXD2));
 564
 565 #define E6 175
 566 SIG_EXPR_LIST_DECL_SINGLE(GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23));
 567 SIG_EXPR_LIST_DECL_SINGLE(RMII2RXER, RMII2, RMII2_DESC);
 568 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD3, RGMII2);
 569 MS_PIN_DECL_(E6, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER),
 570                 SIG_EXPR_LIST_PTR(RGMII2RXD3));
 571
 572 FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6);
 573 FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6);
 574
 575 /* Pins, groups and functions are sort(1):ed alphabetically for sanity */
 576
 577 static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
 578         ASPEED_PINCTRL_PIN(A10),
 579         ASPEED_PINCTRL_PIN(A11),
 580         ASPEED_PINCTRL_PIN(A12),
 581         ASPEED_PINCTRL_PIN(A13),
 582         ASPEED_PINCTRL_PIN(A14),
 583         ASPEED_PINCTRL_PIN(A2),
 584         ASPEED_PINCTRL_PIN(A3),
 585         ASPEED_PINCTRL_PIN(A4),
 586         ASPEED_PINCTRL_PIN(A5),
 587         ASPEED_PINCTRL_PIN(A9),
 588         ASPEED_PINCTRL_PIN(AA3),
 589         ASPEED_PINCTRL_PIN(B1),
 590         ASPEED_PINCTRL_PIN(B10),
 591         ASPEED_PINCTRL_PIN(B11),
 592         ASPEED_PINCTRL_PIN(B12),
 593         ASPEED_PINCTRL_PIN(B13),
 594         ASPEED_PINCTRL_PIN(B14),
 595         ASPEED_PINCTRL_PIN(B2),
 596         ASPEED_PINCTRL_PIN(B20),
 597         ASPEED_PINCTRL_PIN(B3),
 598         ASPEED_PINCTRL_PIN(B4),
 599         ASPEED_PINCTRL_PIN(B5),
 600         ASPEED_PINCTRL_PIN(B9),
 601         ASPEED_PINCTRL_PIN(C1),
 602         ASPEED_PINCTRL_PIN(C11),
 603         ASPEED_PINCTRL_PIN(C12),
 604         ASPEED_PINCTRL_PIN(C13),
 605         ASPEED_PINCTRL_PIN(C14),
 606         ASPEED_PINCTRL_PIN(C16),
 607         ASPEED_PINCTRL_PIN(C18),
 608         ASPEED_PINCTRL_PIN(C2),
 609         ASPEED_PINCTRL_PIN(C20),
 610         ASPEED_PINCTRL_PIN(C3),
 611         ASPEED_PINCTRL_PIN(C4),
 612         ASPEED_PINCTRL_PIN(C5),
 613         ASPEED_PINCTRL_PIN(D1),
 614         ASPEED_PINCTRL_PIN(D10),
 615         ASPEED_PINCTRL_PIN(D2),
 616         ASPEED_PINCTRL_PIN(D20),
 617         ASPEED_PINCTRL_PIN(D21),
 618         ASPEED_PINCTRL_PIN(D4),
 619         ASPEED_PINCTRL_PIN(D5),
 620         ASPEED_PINCTRL_PIN(D6),
 621         ASPEED_PINCTRL_PIN(D7),
 622         ASPEED_PINCTRL_PIN(D8),
 623         ASPEED_PINCTRL_PIN(D9),
 624         ASPEED_PINCTRL_PIN(E10),
 625         ASPEED_PINCTRL_PIN(E12),
 626         ASPEED_PINCTRL_PIN(E13),
 627         ASPEED_PINCTRL_PIN(E15),
 628         ASPEED_PINCTRL_PIN(E21),
 629         ASPEED_PINCTRL_PIN(E6),
 630         ASPEED_PINCTRL_PIN(E7),
 631         ASPEED_PINCTRL_PIN(E9),
 632         ASPEED_PINCTRL_PIN(F19),
 633         ASPEED_PINCTRL_PIN(F9),
 634         ASPEED_PINCTRL_PIN(H20),
 635         ASPEED_PINCTRL_PIN(L1),
 636         ASPEED_PINCTRL_PIN(L2),
 637         ASPEED_PINCTRL_PIN(L3),
 638         ASPEED_PINCTRL_PIN(L4),
 639         ASPEED_PINCTRL_PIN(N1),
 640         ASPEED_PINCTRL_PIN(N2),
 641         ASPEED_PINCTRL_PIN(N20),
 642         ASPEED_PINCTRL_PIN(N21),
 643         ASPEED_PINCTRL_PIN(N22),
 644         ASPEED_PINCTRL_PIN(N3),
 645         ASPEED_PINCTRL_PIN(N4),
 646         ASPEED_PINCTRL_PIN(P1),
 647         ASPEED_PINCTRL_PIN(P2),
 648         ASPEED_PINCTRL_PIN(R1),
 649         ASPEED_PINCTRL_PIN(T4),
 650         ASPEED_PINCTRL_PIN(U3),
 651         ASPEED_PINCTRL_PIN(V2),
 652         ASPEED_PINCTRL_PIN(V3),
 653         ASPEED_PINCTRL_PIN(V6),
 654         ASPEED_PINCTRL_PIN(W2),
 655         ASPEED_PINCTRL_PIN(W3),
 656         ASPEED_PINCTRL_PIN(Y3),
 657 };
 658
 659 static const struct aspeed_pin_group aspeed_g5_groups[] = {
 660         ASPEED_PINCTRL_GROUP(GPID0),
 661         ASPEED_PINCTRL_GROUP(GPID2),
 662         ASPEED_PINCTRL_GROUP(GPIE0),
 663         ASPEED_PINCTRL_GROUP(I2C10),
 664         ASPEED_PINCTRL_GROUP(I2C11),
 665         ASPEED_PINCTRL_GROUP(I2C12),
 666         ASPEED_PINCTRL_GROUP(I2C13),
 667         ASPEED_PINCTRL_GROUP(I2C14),
 668         ASPEED_PINCTRL_GROUP(I2C3),
 669         ASPEED_PINCTRL_GROUP(I2C4),
 670         ASPEED_PINCTRL_GROUP(I2C5),
 671         ASPEED_PINCTRL_GROUP(I2C6),
 672         ASPEED_PINCTRL_GROUP(I2C7),
 673         ASPEED_PINCTRL_GROUP(I2C8),
 674         ASPEED_PINCTRL_GROUP(I2C9),
 675         ASPEED_PINCTRL_GROUP(MAC1LINK),
 676         ASPEED_PINCTRL_GROUP(MDIO1),
 677         ASPEED_PINCTRL_GROUP(MDIO2),
 678         ASPEED_PINCTRL_GROUP(OSCCLK),
 679         ASPEED_PINCTRL_GROUP(PEWAKE),
 680         ASPEED_PINCTRL_GROUP(PWM0),
 681         ASPEED_PINCTRL_GROUP(PWM1),
 682         ASPEED_PINCTRL_GROUP(PWM2),
 683         ASPEED_PINCTRL_GROUP(PWM3),
 684         ASPEED_PINCTRL_GROUP(PWM4),
 685         ASPEED_PINCTRL_GROUP(PWM5),
 686         ASPEED_PINCTRL_GROUP(PWM6),
 687         ASPEED_PINCTRL_GROUP(PWM7),
 688         ASPEED_PINCTRL_GROUP(RGMII1),
 689         ASPEED_PINCTRL_GROUP(RGMII2),
 690         ASPEED_PINCTRL_GROUP(RMII1),
 691         ASPEED_PINCTRL_GROUP(RMII2),
 692         ASPEED_PINCTRL_GROUP(SD1),
 693         ASPEED_PINCTRL_GROUP(SPI1),
 694         ASPEED_PINCTRL_GROUP(TIMER4),
 695         ASPEED_PINCTRL_GROUP(TIMER5),
 696         ASPEED_PINCTRL_GROUP(TIMER6),
 697         ASPEED_PINCTRL_GROUP(TIMER7),
 698         ASPEED_PINCTRL_GROUP(TIMER8),
 699 };
 700
 701 static const struct aspeed_pin_function aspeed_g5_functions[] = {
 702         ASPEED_PINCTRL_FUNC(GPID0),
 703         ASPEED_PINCTRL_FUNC(GPID2),
 704         ASPEED_PINCTRL_FUNC(GPIE0),
 705         ASPEED_PINCTRL_FUNC(I2C10),
 706         ASPEED_PINCTRL_FUNC(I2C11),
 707         ASPEED_PINCTRL_FUNC(I2C12),
 708         ASPEED_PINCTRL_FUNC(I2C13),
 709         ASPEED_PINCTRL_FUNC(I2C14),
 710         ASPEED_PINCTRL_FUNC(I2C3),
 711         ASPEED_PINCTRL_FUNC(I2C4),
 712         ASPEED_PINCTRL_FUNC(I2C5),
 713         ASPEED_PINCTRL_FUNC(I2C6),
 714         ASPEED_PINCTRL_FUNC(I2C7),
 715         ASPEED_PINCTRL_FUNC(I2C8),
 716         ASPEED_PINCTRL_FUNC(I2C9),
 717         ASPEED_PINCTRL_FUNC(MAC1LINK),
 718         ASPEED_PINCTRL_FUNC(MDIO1),
 719         ASPEED_PINCTRL_FUNC(MDIO2),
 720         ASPEED_PINCTRL_FUNC(OSCCLK),
 721         ASPEED_PINCTRL_FUNC(PEWAKE),
 722         ASPEED_PINCTRL_FUNC(PWM0),
 723         ASPEED_PINCTRL_FUNC(PWM1),
 724         ASPEED_PINCTRL_FUNC(PWM2),
 725         ASPEED_PINCTRL_FUNC(PWM3),
 726         ASPEED_PINCTRL_FUNC(PWM4),
 727         ASPEED_PINCTRL_FUNC(PWM5),
 728         ASPEED_PINCTRL_FUNC(PWM6),
 729         ASPEED_PINCTRL_FUNC(PWM7),
 730         ASPEED_PINCTRL_FUNC(RGMII1),
 731         ASPEED_PINCTRL_FUNC(RGMII2),
 732         ASPEED_PINCTRL_FUNC(RMII1),
 733         ASPEED_PINCTRL_FUNC(RMII2),
 734         ASPEED_PINCTRL_FUNC(SD1),
 735         ASPEED_PINCTRL_FUNC(SPI1),
 736         ASPEED_PINCTRL_FUNC(TIMER4),
 737         ASPEED_PINCTRL_FUNC(TIMER5),
 738         ASPEED_PINCTRL_FUNC(TIMER6),
 739         ASPEED_PINCTRL_FUNC(TIMER7),
 740         ASPEED_PINCTRL_FUNC(TIMER8),
 741 };
 742
 743 static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
 744         .pins = aspeed_g5_pins,
 745         .npins = ARRAY_SIZE(aspeed_g5_pins),
 746         .groups = aspeed_g5_groups,
 747         .ngroups = ARRAY_SIZE(aspeed_g5_groups),
 748         .functions = aspeed_g5_functions,
 749         .nfunctions = ARRAY_SIZE(aspeed_g5_functions),
 750 };
 751
 752 static struct pinmux_ops aspeed_g5_pinmux_ops = {
 753         .get_functions_count = aspeed_pinmux_get_fn_count,
 754         .get_function_name = aspeed_pinmux_get_fn_name,
 755         .get_function_groups = aspeed_pinmux_get_fn_groups,
 756         .set_mux = aspeed_pinmux_set_mux,
 757         .gpio_request_enable = aspeed_gpio_request_enable,
 758         .strict = true,
 759 };
 760
 761 static struct pinctrl_ops aspeed_g5_pinctrl_ops = {
 762         .get_groups_count = aspeed_pinctrl_get_groups_count,
 763         .get_group_name = aspeed_pinctrl_get_group_name,
 764         .get_group_pins = aspeed_pinctrl_get_group_pins,
 765         .pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
 766         .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
 767         .dt_free_map = pinctrl_utils_free_map,
 768 };
 769
 770 static struct pinctrl_desc aspeed_g5_pinctrl_desc = {
 771         .name = "aspeed-g5-pinctrl",
 772         .pins = aspeed_g5_pins,
 773         .npins = ARRAY_SIZE(aspeed_g5_pins),
 774         .pctlops = &aspeed_g5_pinctrl_ops,
 775         .pmxops = &aspeed_g5_pinmux_ops,
 776 };
 777
 778 static int aspeed_g5_pinctrl_probe(struct platform_device *pdev)
 779 {
 780         int i;
 781
 782         for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++)
 783                 aspeed_g5_pins[i].number = i;
 784
 785         return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc,
 786                         &aspeed_g5_pinctrl_data);
 787 }
 788
 789 static const struct of_device_id aspeed_g5_pinctrl_of_match[] = {
 790         { .compatible = "aspeed,ast2500-pinctrl", },
 791         { .compatible = "aspeed,g5-pinctrl", },
 792         { },
 793 };
 794
 795 static struct platform_driver aspeed_g5_pinctrl_driver = {
 796         .probe = aspeed_g5_pinctrl_probe,
 797         .driver = {
 798                 .name = "aspeed-g5-pinctrl",
 799                 .of_match_table = aspeed_g5_pinctrl_of_match,
 800         },
 801 };
 802
 803 static int aspeed_g5_pinctrl_init(void)
 804 {
 805         return platform_driver_register(&aspeed_g5_pinctrl_driver);
 806 }
 807
 808 arch_initcall(aspeed_g5_pinctrl_init);