drivers/pinctrl/pinctrl-bcm281xx.c

   1 /*
   2  * Copyright (C) 2013 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation version 2.
   7  *
   8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9  * kind, whether express or implied; without even the implied warranty
  10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13 #include <linux/err.h>
  14 #include <linux/io.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pinctrl/pinctrl.h>
  19 #include <linux/pinctrl/pinmux.h>
  20 #include <linux/pinctrl/pinconf.h>
  21 #include <linux/pinctrl/pinconf-generic.h>
  22 #include <linux/regmap.h>
  23 #include <linux/slab.h>
  24 #include "core.h"
  25 #include "pinctrl-utils.h"
  26
  27 /* BCM281XX Pin Control Registers Definitions */
  28
  29 /* Function Select bits are the same for all pin control registers */
  30 #define BCM281XX_PIN_REG_F_SEL_MASK             0x0700
  31 #define BCM281XX_PIN_REG_F_SEL_SHIFT            8
  32
  33 /* Standard pin register */
  34 #define BCM281XX_STD_PIN_REG_DRV_STR_MASK       0x0007
  35 #define BCM281XX_STD_PIN_REG_DRV_STR_SHIFT      0
  36 #define BCM281XX_STD_PIN_REG_INPUT_DIS_MASK     0x0008
  37 #define BCM281XX_STD_PIN_REG_INPUT_DIS_SHIFT    3
  38 #define BCM281XX_STD_PIN_REG_SLEW_MASK          0x0010
  39 #define BCM281XX_STD_PIN_REG_SLEW_SHIFT         4
  40 #define BCM281XX_STD_PIN_REG_PULL_UP_MASK       0x0020
  41 #define BCM281XX_STD_PIN_REG_PULL_UP_SHIFT      5
  42 #define BCM281XX_STD_PIN_REG_PULL_DN_MASK       0x0040
  43 #define BCM281XX_STD_PIN_REG_PULL_DN_SHIFT      6
  44 #define BCM281XX_STD_PIN_REG_HYST_MASK          0x0080
  45 #define BCM281XX_STD_PIN_REG_HYST_SHIFT         7
  46
  47 /* I2C pin register */
  48 #define BCM281XX_I2C_PIN_REG_INPUT_DIS_MASK     0x0004
  49 #define BCM281XX_I2C_PIN_REG_INPUT_DIS_SHIFT    2
  50 #define BCM281XX_I2C_PIN_REG_SLEW_MASK          0x0008
  51 #define BCM281XX_I2C_PIN_REG_SLEW_SHIFT         3
  52 #define BCM281XX_I2C_PIN_REG_PULL_UP_STR_MASK   0x0070
  53 #define BCM281XX_I2C_PIN_REG_PULL_UP_STR_SHIFT  4
  54
  55 /* HDMI pin register */
  56 #define BCM281XX_HDMI_PIN_REG_INPUT_DIS_MASK    0x0008
  57 #define BCM281XX_HDMI_PIN_REG_INPUT_DIS_SHIFT   3
  58 #define BCM281XX_HDMI_PIN_REG_MODE_MASK         0x0010
  59 #define BCM281XX_HDMI_PIN_REG_MODE_SHIFT        4
  60
  61 /**
  62  * bcm281xx_pin_type - types of pin register
  63  */
  64 enum bcm281xx_pin_type {
  65         BCM281XX_PIN_TYPE_UNKNOWN = 0,
  66         BCM281XX_PIN_TYPE_STD,
  67         BCM281XX_PIN_TYPE_I2C,
  68         BCM281XX_PIN_TYPE_HDMI,
  69 };
  70
  71 static enum bcm281xx_pin_type std_pin = BCM281XX_PIN_TYPE_STD;
  72 static enum bcm281xx_pin_type i2c_pin = BCM281XX_PIN_TYPE_I2C;
  73 static enum bcm281xx_pin_type hdmi_pin = BCM281XX_PIN_TYPE_HDMI;
  74
  75 /**
  76  * bcm281xx_pin_function- define pin function
  77  */
  78 struct bcm281xx_pin_function {
  79         const char *name;
  80         const char * const *groups;
  81         const unsigned ngroups;
  82 };
  83
  84 /**
  85  * bcm281xx_pinctrl_data - Broadcom-specific pinctrl data
  86  * @reg_base - base of pinctrl registers
  87  */
  88 struct bcm281xx_pinctrl_data {
  89         void __iomem *reg_base;
  90
  91         /* List of all pins */
  92         const struct pinctrl_pin_desc *pins;
  93         const unsigned npins;
  94
  95         const struct bcm281xx_pin_function *functions;
  96         const unsigned nfunctions;
  97
  98         struct regmap *regmap;
  99 };
 100
 101 /*
 102  * Pin number definition.  The order here must be the same as defined in the
 103  * PADCTRLREG block in the RDB.
 104  */
 105 #define BCM281XX_PIN_ADCSYNC            0
 106 #define BCM281XX_PIN_BAT_RM             1
 107 #define BCM281XX_PIN_BSC1_SCL           2
 108 #define BCM281XX_PIN_BSC1_SDA           3
 109 #define BCM281XX_PIN_BSC2_SCL           4
 110 #define BCM281XX_PIN_BSC2_SDA           5
 111 #define BCM281XX_PIN_CLASSGPWR          6
 112 #define BCM281XX_PIN_CLK_CX8            7
 113 #define BCM281XX_PIN_CLKOUT_0           8
 114 #define BCM281XX_PIN_CLKOUT_1           9
 115 #define BCM281XX_PIN_CLKOUT_2           10
 116 #define BCM281XX_PIN_CLKOUT_3           11
 117 #define BCM281XX_PIN_CLKREQ_IN_0        12
 118 #define BCM281XX_PIN_CLKREQ_IN_1        13
 119 #define BCM281XX_PIN_CWS_SYS_REQ1       14
 120 #define BCM281XX_PIN_CWS_SYS_REQ2       15
 121 #define BCM281XX_PIN_CWS_SYS_REQ3       16
 122 #define BCM281XX_PIN_DIGMIC1_CLK        17
 123 #define BCM281XX_PIN_DIGMIC1_DQ         18
 124 #define BCM281XX_PIN_DIGMIC2_CLK        19
 125 #define BCM281XX_PIN_DIGMIC2_DQ         20
 126 #define BCM281XX_PIN_GPEN13             21
 127 #define BCM281XX_PIN_GPEN14             22
 128 #define BCM281XX_PIN_GPEN15             23
 129 #define BCM281XX_PIN_GPIO00             24
 130 #define BCM281XX_PIN_GPIO01             25
 131 #define BCM281XX_PIN_GPIO02             26
 132 #define BCM281XX_PIN_GPIO03             27
 133 #define BCM281XX_PIN_GPIO04             28
 134 #define BCM281XX_PIN_GPIO05             29
 135 #define BCM281XX_PIN_GPIO06             30
 136 #define BCM281XX_PIN_GPIO07             31
 137 #define BCM281XX_PIN_GPIO08             32
 138 #define BCM281XX_PIN_GPIO09             33
 139 #define BCM281XX_PIN_GPIO10             34
 140 #define BCM281XX_PIN_GPIO11             35
 141 #define BCM281XX_PIN_GPIO12             36
 142 #define BCM281XX_PIN_GPIO13             37
 143 #define BCM281XX_PIN_GPIO14             38
 144 #define BCM281XX_PIN_GPS_PABLANK        39
 145 #define BCM281XX_PIN_GPS_TMARK          40
 146 #define BCM281XX_PIN_HDMI_SCL           41
 147 #define BCM281XX_PIN_HDMI_SDA           42
 148 #define BCM281XX_PIN_IC_DM              43
 149 #define BCM281XX_PIN_IC_DP              44
 150 #define BCM281XX_PIN_KP_COL_IP_0        45
 151 #define BCM281XX_PIN_KP_COL_IP_1        46
 152 #define BCM281XX_PIN_KP_COL_IP_2        47
 153 #define BCM281XX_PIN_KP_COL_IP_3        48
 154 #define BCM281XX_PIN_KP_ROW_OP_0        49
 155 #define BCM281XX_PIN_KP_ROW_OP_1        50
 156 #define BCM281XX_PIN_KP_ROW_OP_2        51
 157 #define BCM281XX_PIN_KP_ROW_OP_3        52
 158 #define BCM281XX_PIN_LCD_B_0            53
 159 #define BCM281XX_PIN_LCD_B_1            54
 160 #define BCM281XX_PIN_LCD_B_2            55
 161 #define BCM281XX_PIN_LCD_B_3            56
 162 #define BCM281XX_PIN_LCD_B_4            57
 163 #define BCM281XX_PIN_LCD_B_5            58
 164 #define BCM281XX_PIN_LCD_B_6            59
 165 #define BCM281XX_PIN_LCD_B_7            60
 166 #define BCM281XX_PIN_LCD_G_0            61
 167 #define BCM281XX_PIN_LCD_G_1            62
 168 #define BCM281XX_PIN_LCD_G_2            63
 169 #define BCM281XX_PIN_LCD_G_3            64
 170 #define BCM281XX_PIN_LCD_G_4            65
 171 #define BCM281XX_PIN_LCD_G_5            66
 172 #define BCM281XX_PIN_LCD_G_6            67
 173 #define BCM281XX_PIN_LCD_G_7            68
 174 #define BCM281XX_PIN_LCD_HSYNC          69
 175 #define BCM281XX_PIN_LCD_OE             70
 176 #define BCM281XX_PIN_LCD_PCLK           71
 177 #define BCM281XX_PIN_LCD_R_0            72
 178 #define BCM281XX_PIN_LCD_R_1            73
 179 #define BCM281XX_PIN_LCD_R_2            74
 180 #define BCM281XX_PIN_LCD_R_3            75
 181 #define BCM281XX_PIN_LCD_R_4            76
 182 #define BCM281XX_PIN_LCD_R_5            77
 183 #define BCM281XX_PIN_LCD_R_6            78
 184 #define BCM281XX_PIN_LCD_R_7            79
 185 #define BCM281XX_PIN_LCD_VSYNC          80
 186 #define BCM281XX_PIN_MDMGPIO0           81
 187 #define BCM281XX_PIN_MDMGPIO1           82
 188 #define BCM281XX_PIN_MDMGPIO2           83
 189 #define BCM281XX_PIN_MDMGPIO3           84
 190 #define BCM281XX_PIN_MDMGPIO4           85
 191 #define BCM281XX_PIN_MDMGPIO5           86
 192 #define BCM281XX_PIN_MDMGPIO6           87
 193 #define BCM281XX_PIN_MDMGPIO7           88
 194 #define BCM281XX_PIN_MDMGPIO8           89
 195 #define BCM281XX_PIN_MPHI_DATA_0        90
 196 #define BCM281XX_PIN_MPHI_DATA_1        91
 197 #define BCM281XX_PIN_MPHI_DATA_2        92
 198 #define BCM281XX_PIN_MPHI_DATA_3        93
 199 #define BCM281XX_PIN_MPHI_DATA_4        94
 200 #define BCM281XX_PIN_MPHI_DATA_5        95
 201 #define BCM281XX_PIN_MPHI_DATA_6        96
 202 #define BCM281XX_PIN_MPHI_DATA_7        97
 203 #define BCM281XX_PIN_MPHI_DATA_8        98
 204 #define BCM281XX_PIN_MPHI_DATA_9        99
 205 #define BCM281XX_PIN_MPHI_DATA_10       100
 206 #define BCM281XX_PIN_MPHI_DATA_11       101
 207 #define BCM281XX_PIN_MPHI_DATA_12       102
 208 #define BCM281XX_PIN_MPHI_DATA_13       103
 209 #define BCM281XX_PIN_MPHI_DATA_14       104
 210 #define BCM281XX_PIN_MPHI_DATA_15       105
 211 #define BCM281XX_PIN_MPHI_HA0           106
 212 #define BCM281XX_PIN_MPHI_HAT0          107
 213 #define BCM281XX_PIN_MPHI_HAT1          108
 214 #define BCM281XX_PIN_MPHI_HCE0_N        109
 215 #define BCM281XX_PIN_MPHI_HCE1_N        110
 216 #define BCM281XX_PIN_MPHI_HRD_N         111
 217 #define BCM281XX_PIN_MPHI_HWR_N         112
 218 #define BCM281XX_PIN_MPHI_RUN0          113
 219 #define BCM281XX_PIN_MPHI_RUN1          114
 220 #define BCM281XX_PIN_MTX_SCAN_CLK       115
 221 #define BCM281XX_PIN_MTX_SCAN_DATA      116
 222 #define BCM281XX_PIN_NAND_AD_0          117
 223 #define BCM281XX_PIN_NAND_AD_1          118
 224 #define BCM281XX_PIN_NAND_AD_2          119
 225 #define BCM281XX_PIN_NAND_AD_3          120
 226 #define BCM281XX_PIN_NAND_AD_4          121
 227 #define BCM281XX_PIN_NAND_AD_5          122
 228 #define BCM281XX_PIN_NAND_AD_6          123
 229 #define BCM281XX_PIN_NAND_AD_7          124
 230 #define BCM281XX_PIN_NAND_ALE           125
 231 #define BCM281XX_PIN_NAND_CEN_0         126
 232 #define BCM281XX_PIN_NAND_CEN_1         127
 233 #define BCM281XX_PIN_NAND_CLE           128
 234 #define BCM281XX_PIN_NAND_OEN           129
 235 #define BCM281XX_PIN_NAND_RDY_0         130
 236 #define BCM281XX_PIN_NAND_RDY_1         131
 237 #define BCM281XX_PIN_NAND_WEN           132
 238 #define BCM281XX_PIN_NAND_WP            133
 239 #define BCM281XX_PIN_PC1                134
 240 #define BCM281XX_PIN_PC2                135
 241 #define BCM281XX_PIN_PMU_INT            136
 242 #define BCM281XX_PIN_PMU_SCL            137
 243 #define BCM281XX_PIN_PMU_SDA            138
 244 #define BCM281XX_PIN_RFST2G_MTSLOTEN3G  139
 245 #define BCM281XX_PIN_RGMII_0_RX_CTL     140
 246 #define BCM281XX_PIN_RGMII_0_RXC        141
 247 #define BCM281XX_PIN_RGMII_0_RXD_0      142
 248 #define BCM281XX_PIN_RGMII_0_RXD_1      143
 249 #define BCM281XX_PIN_RGMII_0_RXD_2      144
 250 #define BCM281XX_PIN_RGMII_0_RXD_3      145
 251 #define BCM281XX_PIN_RGMII_0_TX_CTL     146
 252 #define BCM281XX_PIN_RGMII_0_TXC        147
 253 #define BCM281XX_PIN_RGMII_0_TXD_0      148
 254 #define BCM281XX_PIN_RGMII_0_TXD_1      149
 255 #define BCM281XX_PIN_RGMII_0_TXD_2      150
 256 #define BCM281XX_PIN_RGMII_0_TXD_3      151
 257 #define BCM281XX_PIN_RGMII_1_RX_CTL     152
 258 #define BCM281XX_PIN_RGMII_1_RXC        153
 259 #define BCM281XX_PIN_RGMII_1_RXD_0      154
 260 #define BCM281XX_PIN_RGMII_1_RXD_1      155
 261 #define BCM281XX_PIN_RGMII_1_RXD_2      156
 262 #define BCM281XX_PIN_RGMII_1_RXD_3      157
 263 #define BCM281XX_PIN_RGMII_1_TX_CTL     158
 264 #define BCM281XX_PIN_RGMII_1_TXC        159
 265 #define BCM281XX_PIN_RGMII_1_TXD_0      160
 266 #define BCM281XX_PIN_RGMII_1_TXD_1      161
 267 #define BCM281XX_PIN_RGMII_1_TXD_2      162
 268 #define BCM281XX_PIN_RGMII_1_TXD_3      163
 269 #define BCM281XX_PIN_RGMII_GPIO_0       164
 270 #define BCM281XX_PIN_RGMII_GPIO_1       165
 271 #define BCM281XX_PIN_RGMII_GPIO_2       166
 272 #define BCM281XX_PIN_RGMII_GPIO_3       167
 273 #define BCM281XX_PIN_RTXDATA2G_TXDATA3G1        168
 274 #define BCM281XX_PIN_RTXEN2G_TXDATA3G2  169
 275 #define BCM281XX_PIN_RXDATA3G0          170
 276 #define BCM281XX_PIN_RXDATA3G1          171
 277 #define BCM281XX_PIN_RXDATA3G2          172
 278 #define BCM281XX_PIN_SDIO1_CLK          173
 279 #define BCM281XX_PIN_SDIO1_CMD          174
 280 #define BCM281XX_PIN_SDIO1_DATA_0       175
 281 #define BCM281XX_PIN_SDIO1_DATA_1       176
 282 #define BCM281XX_PIN_SDIO1_DATA_2       177
 283 #define BCM281XX_PIN_SDIO1_DATA_3       178
 284 #define BCM281XX_PIN_SDIO4_CLK          179
 285 #define BCM281XX_PIN_SDIO4_CMD          180
 286 #define BCM281XX_PIN_SDIO4_DATA_0       181
 287 #define BCM281XX_PIN_SDIO4_DATA_1       182
 288 #define BCM281XX_PIN_SDIO4_DATA_2       183
 289 #define BCM281XX_PIN_SDIO4_DATA_3       184
 290 #define BCM281XX_PIN_SIM_CLK            185
 291 #define BCM281XX_PIN_SIM_DATA           186
 292 #define BCM281XX_PIN_SIM_DET            187
 293 #define BCM281XX_PIN_SIM_RESETN         188
 294 #define BCM281XX_PIN_SIM2_CLK           189
 295 #define BCM281XX_PIN_SIM2_DATA          190
 296 #define BCM281XX_PIN_SIM2_DET           191
 297 #define BCM281XX_PIN_SIM2_RESETN        192
 298 #define BCM281XX_PIN_SRI_C              193
 299 #define BCM281XX_PIN_SRI_D              194
 300 #define BCM281XX_PIN_SRI_E              195
 301 #define BCM281XX_PIN_SSP_EXTCLK         196
 302 #define BCM281XX_PIN_SSP0_CLK           197
 303 #define BCM281XX_PIN_SSP0_FS            198
 304 #define BCM281XX_PIN_SSP0_RXD           199
 305 #define BCM281XX_PIN_SSP0_TXD           200
 306 #define BCM281XX_PIN_SSP2_CLK           201
 307 #define BCM281XX_PIN_SSP2_FS_0          202
 308 #define BCM281XX_PIN_SSP2_FS_1          203
 309 #define BCM281XX_PIN_SSP2_FS_2          204
 310 #define BCM281XX_PIN_SSP2_FS_3          205
 311 #define BCM281XX_PIN_SSP2_RXD_0         206
 312 #define BCM281XX_PIN_SSP2_RXD_1         207
 313 #define BCM281XX_PIN_SSP2_TXD_0         208
 314 #define BCM281XX_PIN_SSP2_TXD_1         209
 315 #define BCM281XX_PIN_SSP3_CLK           210
 316 #define BCM281XX_PIN_SSP3_FS            211
 317 #define BCM281XX_PIN_SSP3_RXD           212
 318 #define BCM281XX_PIN_SSP3_TXD           213
 319 #define BCM281XX_PIN_SSP4_CLK           214
 320 #define BCM281XX_PIN_SSP4_FS            215
 321 #define BCM281XX_PIN_SSP4_RXD           216
 322 #define BCM281XX_PIN_SSP4_TXD           217
 323 #define BCM281XX_PIN_SSP5_CLK           218
 324 #define BCM281XX_PIN_SSP5_FS            219
 325 #define BCM281XX_PIN_SSP5_RXD           220
 326 #define BCM281XX_PIN_SSP5_TXD           221
 327 #define BCM281XX_PIN_SSP6_CLK           222
 328 #define BCM281XX_PIN_SSP6_FS            223
 329 #define BCM281XX_PIN_SSP6_RXD           224
 330 #define BCM281XX_PIN_SSP6_TXD           225
 331 #define BCM281XX_PIN_STAT_1             226
 332 #define BCM281XX_PIN_STAT_2             227
 333 #define BCM281XX_PIN_SYSCLKEN           228
 334 #define BCM281XX_PIN_TRACECLK           229
 335 #define BCM281XX_PIN_TRACEDT00          230
 336 #define BCM281XX_PIN_TRACEDT01          231
 337 #define BCM281XX_PIN_TRACEDT02          232
 338 #define BCM281XX_PIN_TRACEDT03          233
 339 #define BCM281XX_PIN_TRACEDT04          234
 340 #define BCM281XX_PIN_TRACEDT05          235
 341 #define BCM281XX_PIN_TRACEDT06          236
 342 #define BCM281XX_PIN_TRACEDT07          237
 343 #define BCM281XX_PIN_TRACEDT08          238
 344 #define BCM281XX_PIN_TRACEDT09          239
 345 #define BCM281XX_PIN_TRACEDT10          240
 346 #define BCM281XX_PIN_TRACEDT11          241
 347 #define BCM281XX_PIN_TRACEDT12          242
 348 #define BCM281XX_PIN_TRACEDT13          243
 349 #define BCM281XX_PIN_TRACEDT14          244
 350 #define BCM281XX_PIN_TRACEDT15          245
 351 #define BCM281XX_PIN_TXDATA3G0          246
 352 #define BCM281XX_PIN_TXPWRIND           247
 353 #define BCM281XX_PIN_UARTB1_UCTS        248
 354 #define BCM281XX_PIN_UARTB1_URTS        249
 355 #define BCM281XX_PIN_UARTB1_URXD        250
 356 #define BCM281XX_PIN_UARTB1_UTXD        251
 357 #define BCM281XX_PIN_UARTB2_URXD        252
 358 #define BCM281XX_PIN_UARTB2_UTXD        253
 359 #define BCM281XX_PIN_UARTB3_UCTS        254
 360 #define BCM281XX_PIN_UARTB3_URTS        255
 361 #define BCM281XX_PIN_UARTB3_URXD        256
 362 #define BCM281XX_PIN_UARTB3_UTXD        257
 363 #define BCM281XX_PIN_UARTB4_UCTS        258
 364 #define BCM281XX_PIN_UARTB4_URTS        259
 365 #define BCM281XX_PIN_UARTB4_URXD        260
 366 #define BCM281XX_PIN_UARTB4_UTXD        261
 367 #define BCM281XX_PIN_VC_CAM1_SCL        262
 368 #define BCM281XX_PIN_VC_CAM1_SDA        263
 369 #define BCM281XX_PIN_VC_CAM2_SCL        264
 370 #define BCM281XX_PIN_VC_CAM2_SDA        265
 371 #define BCM281XX_PIN_VC_CAM3_SCL        266
 372 #define BCM281XX_PIN_VC_CAM3_SDA        267
 373
 374 #define BCM281XX_PIN_DESC(a, b, c) \
 375         { .number = a, .name = b, .drv_data = &c##_pin }
 376
 377 /*
 378  * Pin description definition.  The order here must be the same as defined in
 379  * the PADCTRLREG block in the RDB, since the pin number is used as an index
 380  * into this array.
 381  */
 382 static const struct pinctrl_pin_desc bcm281xx_pinctrl_pins[] = {
 383         BCM281XX_PIN_DESC(BCM281XX_PIN_ADCSYNC, "adcsync", std),
 384         BCM281XX_PIN_DESC(BCM281XX_PIN_BAT_RM, "bat_rm", std),
 385         BCM281XX_PIN_DESC(BCM281XX_PIN_BSC1_SCL, "bsc1_scl", i2c),
 386         BCM281XX_PIN_DESC(BCM281XX_PIN_BSC1_SDA, "bsc1_sda", i2c),
 387         BCM281XX_PIN_DESC(BCM281XX_PIN_BSC2_SCL, "bsc2_scl", i2c),
 388         BCM281XX_PIN_DESC(BCM281XX_PIN_BSC2_SDA, "bsc2_sda", i2c),
 389         BCM281XX_PIN_DESC(BCM281XX_PIN_CLASSGPWR, "classgpwr", std),
 390         BCM281XX_PIN_DESC(BCM281XX_PIN_CLK_CX8, "clk_cx8", std),
 391         BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_0, "clkout_0", std),
 392         BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_1, "clkout_1", std),
 393         BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_2, "clkout_2", std),
 394         BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_3, "clkout_3", std),
 395         BCM281XX_PIN_DESC(BCM281XX_PIN_CLKREQ_IN_0, "clkreq_in_0", std),
 396         BCM281XX_PIN_DESC(BCM281XX_PIN_CLKREQ_IN_1, "clkreq_in_1", std),
 397         BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ1, "cws_sys_req1", std),
 398         BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ2, "cws_sys_req2", std),
 399         BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ3, "cws_sys_req3", std),
 400         BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC1_CLK, "digmic1_clk", std),
 401         BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC1_DQ, "digmic1_dq", std),
 402         BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC2_CLK, "digmic2_clk", std),
 403         BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC2_DQ, "digmic2_dq", std),
 404         BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN13, "gpen13", std),
 405         BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN14, "gpen14", std),
 406         BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN15, "gpen15", std),
 407         BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO00, "gpio00", std),
 408         BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO01, "gpio01", std),
 409         BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO02, "gpio02", std),
 410         BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO03, "gpio03", std),
 411         BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO04, "gpio04", std),
 412         BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO05, "gpio05", std),
 413         BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO06, "gpio06", std),
 414         BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO07, "gpio07", std),
 415         BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO08, "gpio08", std),
 416         BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO09, "gpio09", std),
 417         BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO10, "gpio10", std),
 418         BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO11, "gpio11", std),
 419         BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO12, "gpio12", std),
 420         BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO13, "gpio13", std),
 421         BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO14, "gpio14", std),
 422         BCM281XX_PIN_DESC(BCM281XX_PIN_GPS_PABLANK, "gps_pablank", std),
 423         BCM281XX_PIN_DESC(BCM281XX_PIN_GPS_TMARK, "gps_tmark", std),
 424         BCM281XX_PIN_DESC(BCM281XX_PIN_HDMI_SCL, "hdmi_scl", hdmi),
 425         BCM281XX_PIN_DESC(BCM281XX_PIN_HDMI_SDA, "hdmi_sda", hdmi),
 426         BCM281XX_PIN_DESC(BCM281XX_PIN_IC_DM, "ic_dm", std),
 427         BCM281XX_PIN_DESC(BCM281XX_PIN_IC_DP, "ic_dp", std),
 428         BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_0, "kp_col_ip_0", std),
 429         BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_1, "kp_col_ip_1", std),
 430         BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_2, "kp_col_ip_2", std),
 431         BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_3, "kp_col_ip_3", std),
 432         BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_0, "kp_row_op_0", std),
 433         BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_1, "kp_row_op_1", std),
 434         BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_2, "kp_row_op_2", std),
 435         BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_3, "kp_row_op_3", std),
 436         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_0, "lcd_b_0", std),
 437         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_1, "lcd_b_1", std),
 438         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_2, "lcd_b_2", std),
 439         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_3, "lcd_b_3", std),
 440         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_4, "lcd_b_4", std),
 441         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_5, "lcd_b_5", std),
 442         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_6, "lcd_b_6", std),
 443         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_7, "lcd_b_7", std),
 444         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_0, "lcd_g_0", std),
 445         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_1, "lcd_g_1", std),
 446         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_2, "lcd_g_2", std),
 447         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_3, "lcd_g_3", std),
 448         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_4, "lcd_g_4", std),
 449         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_5, "lcd_g_5", std),
 450         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_6, "lcd_g_6", std),
 451         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_7, "lcd_g_7", std),
 452         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_HSYNC, "lcd_hsync", std),
 453         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_OE, "lcd_oe", std),
 454         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_PCLK, "lcd_pclk", std),
 455         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_0, "lcd_r_0", std),
 456         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_1, "lcd_r_1", std),
 457         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_2, "lcd_r_2", std),
 458         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_3, "lcd_r_3", std),
 459         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_4, "lcd_r_4", std),
 460         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_5, "lcd_r_5", std),
 461         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_6, "lcd_r_6", std),
 462         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_7, "lcd_r_7", std),
 463         BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_VSYNC, "lcd_vsync", std),
 464         BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO0, "mdmgpio0", std),
 465         BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO1, "mdmgpio1", std),
 466         BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO2, "mdmgpio2", std),
 467         BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO3, "mdmgpio3", std),
 468         BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO4, "mdmgpio4", std),
 469         BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO5, "mdmgpio5", std),
 470         BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO6, "mdmgpio6", std),
 471         BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO7, "mdmgpio7", std),
 472         BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO8, "mdmgpio8", std),
 473         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_0, "mphi_data_0", std),
 474         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_1, "mphi_data_1", std),
 475         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_2, "mphi_data_2", std),
 476         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_3, "mphi_data_3", std),
 477         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_4, "mphi_data_4", std),
 478         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_5, "mphi_data_5", std),
 479         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_6, "mphi_data_6", std),
 480         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_7, "mphi_data_7", std),
 481         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_8, "mphi_data_8", std),
 482         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_9, "mphi_data_9", std),
 483         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_10, "mphi_data_10", std),
 484         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_11, "mphi_data_11", std),
 485         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_12, "mphi_data_12", std),
 486         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_13, "mphi_data_13", std),
 487         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_14, "mphi_data_14", std),
 488         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_15, "mphi_data_15", std),
 489         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HA0, "mphi_ha0", std),
 490         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HAT0, "mphi_hat0", std),
 491         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HAT1, "mphi_hat1", std),
 492         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HCE0_N, "mphi_hce0_n", std),
 493         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HCE1_N, "mphi_hce1_n", std),
 494         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HRD_N, "mphi_hrd_n", std),
 495         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HWR_N, "mphi_hwr_n", std),
 496         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_RUN0, "mphi_run0", std),
 497         BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_RUN1, "mphi_run1", std),
 498         BCM281XX_PIN_DESC(BCM281XX_PIN_MTX_SCAN_CLK, "mtx_scan_clk", std),
 499         BCM281XX_PIN_DESC(BCM281XX_PIN_MTX_SCAN_DATA, "mtx_scan_data", std),
 500         BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_0, "nand_ad_0", std),
 501         BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_1, "nand_ad_1", std),
 502         BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_2, "nand_ad_2", std),
 503         BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_3, "nand_ad_3", std),
 504         BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_4, "nand_ad_4", std),
 505         BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_5, "nand_ad_5", std),
 506         BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_6, "nand_ad_6", std),
 507         BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_7, "nand_ad_7", std),
 508         BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_ALE, "nand_ale", std),
 509         BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CEN_0, "nand_cen_0", std),
 510         BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CEN_1, "nand_cen_1", std),
 511         BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CLE, "nand_cle", std),
 512         BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_OEN, "nand_oen", std),
 513         BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_RDY_0, "nand_rdy_0", std),
 514         BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_RDY_1, "nand_rdy_1", std),
 515         BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_WEN, "nand_wen", std),
 516         BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_WP, "nand_wp", std),
 517         BCM281XX_PIN_DESC(BCM281XX_PIN_PC1, "pc1", std),
 518         BCM281XX_PIN_DESC(BCM281XX_PIN_PC2, "pc2", std),
 519         BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_INT, "pmu_int", std),
 520         BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_SCL, "pmu_scl", i2c),
 521         BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_SDA, "pmu_sda", i2c),
 522         BCM281XX_PIN_DESC(BCM281XX_PIN_RFST2G_MTSLOTEN3G, "rfst2g_mtsloten3g",
 523                 std),
 524         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RX_CTL, "rgmii_0_rx_ctl", std),
 525         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXC, "rgmii_0_rxc", std),
 526         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_0, "rgmii_0_rxd_0", std),
 527         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_1, "rgmii_0_rxd_1", std),
 528         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_2, "rgmii_0_rxd_2", std),
 529         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_3, "rgmii_0_rxd_3", std),
 530         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TX_CTL, "rgmii_0_tx_ctl", std),
 531         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXC, "rgmii_0_txc", std),
 532         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_0, "rgmii_0_txd_0", std),
 533         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_1, "rgmii_0_txd_1", std),
 534         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_2, "rgmii_0_txd_2", std),
 535         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_3, "rgmii_0_txd_3", std),
 536         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RX_CTL, "rgmii_1_rx_ctl", std),
 537         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXC, "rgmii_1_rxc", std),
 538         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_0, "rgmii_1_rxd_0", std),
 539         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_1, "rgmii_1_rxd_1", std),
 540         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_2, "rgmii_1_rxd_2", std),
 541         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_3, "rgmii_1_rxd_3", std),
 542         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TX_CTL, "rgmii_1_tx_ctl", std),
 543         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXC, "rgmii_1_txc", std),
 544         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_0, "rgmii_1_txd_0", std),
 545         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_1, "rgmii_1_txd_1", std),
 546         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_2, "rgmii_1_txd_2", std),
 547         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_3, "rgmii_1_txd_3", std),
 548         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_0, "rgmii_gpio_0", std),
 549         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_1, "rgmii_gpio_1", std),
 550         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_2, "rgmii_gpio_2", std),
 551         BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_3, "rgmii_gpio_3", std),
 552         BCM281XX_PIN_DESC(BCM281XX_PIN_RTXDATA2G_TXDATA3G1,
 553                 "rtxdata2g_txdata3g1", std),
 554         BCM281XX_PIN_DESC(BCM281XX_PIN_RTXEN2G_TXDATA3G2, "rtxen2g_txdata3g2",
 555                 std),
 556         BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G0, "rxdata3g0", std),
 557         BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G1, "rxdata3g1", std),
 558         BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G2, "rxdata3g2", std),
 559         BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_CLK, "sdio1_clk", std),
 560         BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_CMD, "sdio1_cmd", std),
 561         BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_0, "sdio1_data_0", std),
 562         BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_1, "sdio1_data_1", std),
 563         BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_2, "sdio1_data_2", std),
 564         BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_3, "sdio1_data_3", std),
 565         BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_CLK, "sdio4_clk", std),
 566         BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_CMD, "sdio4_cmd", std),
 567         BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_0, "sdio4_data_0", std),
 568         BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_1, "sdio4_data_1", std),
 569         BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_2, "sdio4_data_2", std),
 570         BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_3, "sdio4_data_3", std),
 571         BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_CLK, "sim_clk", std),
 572         BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_DATA, "sim_data", std),
 573         BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_DET, "sim_det", std),
 574         BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_RESETN, "sim_resetn", std),
 575         BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_CLK, "sim2_clk", std),
 576         BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_DATA, "sim2_data", std),
 577         BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_DET, "sim2_det", std),
 578         BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_RESETN, "sim2_resetn", std),
 579         BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_C, "sri_c", std),
 580         BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_D, "sri_d", std),
 581         BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_E, "sri_e", std),
 582         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP_EXTCLK, "ssp_extclk", std),
 583         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_CLK, "ssp0_clk", std),
 584         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_FS, "ssp0_fs", std),
 585         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_RXD, "ssp0_rxd", std),
 586         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_TXD, "ssp0_txd", std),
 587         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_CLK, "ssp2_clk", std),
 588         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_0, "ssp2_fs_0", std),
 589         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_1, "ssp2_fs_1", std),
 590         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_2, "ssp2_fs_2", std),
 591         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_3, "ssp2_fs_3", std),
 592         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_RXD_0, "ssp2_rxd_0", std),
 593         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_RXD_1, "ssp2_rxd_1", std),
 594         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_TXD_0, "ssp2_txd_0", std),
 595         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_TXD_1, "ssp2_txd_1", std),
 596         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_CLK, "ssp3_clk", std),
 597         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_FS, "ssp3_fs", std),
 598         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_RXD, "ssp3_rxd", std),
 599         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_TXD, "ssp3_txd", std),
 600         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_CLK, "ssp4_clk", std),
 601         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_FS, "ssp4_fs", std),
 602         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_RXD, "ssp4_rxd", std),
 603         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_TXD, "ssp4_txd", std),
 604         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_CLK, "ssp5_clk", std),
 605         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_FS, "ssp5_fs", std),
 606         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_RXD, "ssp5_rxd", std),
 607         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_TXD, "ssp5_txd", std),
 608         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_CLK, "ssp6_clk", std),
 609         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_FS, "ssp6_fs", std),
 610         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_RXD, "ssp6_rxd", std),
 611         BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_TXD, "ssp6_txd", std),
 612         BCM281XX_PIN_DESC(BCM281XX_PIN_STAT_1, "stat_1", std),
 613         BCM281XX_PIN_DESC(BCM281XX_PIN_STAT_2, "stat_2", std),
 614         BCM281XX_PIN_DESC(BCM281XX_PIN_SYSCLKEN, "sysclken", std),
 615         BCM281XX_PIN_DESC(BCM281XX_PIN_TRACECLK, "traceclk", std),
 616         BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT00, "tracedt00", std),
 617         BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT01, "tracedt01", std),
 618         BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT02, "tracedt02", std),
 619         BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT03, "tracedt03", std),
 620         BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT04, "tracedt04", std),
 621         BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT05, "tracedt05", std),
 622         BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT06, "tracedt06", std),
 623         BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT07, "tracedt07", std),
 624         BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT08, "tracedt08", std),
 625         BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT09, "tracedt09", std),
 626         BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT10, "tracedt10", std),
 627         BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT11, "tracedt11", std),
 628         BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT12, "tracedt12", std),
 629         BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT13, "tracedt13", std),
 630         BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT14, "tracedt14", std),
 631         BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT15, "tracedt15", std),
 632         BCM281XX_PIN_DESC(BCM281XX_PIN_TXDATA3G0, "txdata3g0", std),
 633         BCM281XX_PIN_DESC(BCM281XX_PIN_TXPWRIND, "txpwrind", std),
 634         BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_UCTS, "uartb1_ucts", std),
 635         BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_URTS, "uartb1_urts", std),
 636         BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_URXD, "uartb1_urxd", std),
 637         BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_UTXD, "uartb1_utxd", std),
 638         BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB2_URXD, "uartb2_urxd", std),
 639         BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB2_UTXD, "uartb2_utxd", std),
 640         BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_UCTS, "uartb3_ucts", std),
 641         BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_URTS, "uartb3_urts", std),
 642         BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_URXD, "uartb3_urxd", std),
 643         BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_UTXD, "uartb3_utxd", std),
 644         BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_UCTS, "uartb4_ucts", std),
 645         BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_URTS, "uartb4_urts", std),
 646         BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_URXD, "uartb4_urxd", std),
 647         BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_UTXD, "uartb4_utxd", std),
 648         BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM1_SCL, "vc_cam1_scl", i2c),
 649         BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM1_SDA, "vc_cam1_sda", i2c),
 650         BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM2_SCL, "vc_cam2_scl", i2c),
 651         BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM2_SDA, "vc_cam2_sda", i2c),
 652         BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM3_SCL, "vc_cam3_scl", i2c),
 653         BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM3_SDA, "vc_cam3_sda", i2c),
 654 };
 655
 656 static const char * const bcm281xx_alt_groups[] = {
 657         "adcsync",
 658         "bat_rm",
 659         "bsc1_scl",
 660         "bsc1_sda",
 661         "bsc2_scl",
 662         "bsc2_sda",
 663         "classgpwr",
 664         "clk_cx8",
 665         "clkout_0",
 666         "clkout_1",
 667         "clkout_2",
 668         "clkout_3",
 669         "clkreq_in_0",
 670         "clkreq_in_1",
 671         "cws_sys_req1",
 672         "cws_sys_req2",
 673         "cws_sys_req3",
 674         "digmic1_clk",
 675         "digmic1_dq",
 676         "digmic2_clk",
 677         "digmic2_dq",
 678         "gpen13",
 679         "gpen14",
 680         "gpen15",
 681         "gpio00",
 682         "gpio01",
 683         "gpio02",
 684         "gpio03",
 685         "gpio04",
 686         "gpio05",
 687         "gpio06",
 688         "gpio07",
 689         "gpio08",
 690         "gpio09",
 691         "gpio10",
 692         "gpio11",
 693         "gpio12",
 694         "gpio13",
 695         "gpio14",
 696         "gps_pablank",
 697         "gps_tmark",
 698         "hdmi_scl",
 699         "hdmi_sda",
 700         "ic_dm",
 701         "ic_dp",
 702         "kp_col_ip_0",
 703         "kp_col_ip_1",
 704         "kp_col_ip_2",
 705         "kp_col_ip_3",
 706         "kp_row_op_0",
 707         "kp_row_op_1",
 708         "kp_row_op_2",
 709         "kp_row_op_3",
 710         "lcd_b_0",
 711         "lcd_b_1",
 712         "lcd_b_2",
 713         "lcd_b_3",
 714         "lcd_b_4",
 715         "lcd_b_5",
 716         "lcd_b_6",
 717         "lcd_b_7",
 718         "lcd_g_0",
 719         "lcd_g_1",
 720         "lcd_g_2",
 721         "lcd_g_3",
 722         "lcd_g_4",
 723         "lcd_g_5",
 724         "lcd_g_6",
 725         "lcd_g_7",
 726         "lcd_hsync",
 727         "lcd_oe",
 728         "lcd_pclk",
 729         "lcd_r_0",
 730         "lcd_r_1",
 731         "lcd_r_2",
 732         "lcd_r_3",
 733         "lcd_r_4",
 734         "lcd_r_5",
 735         "lcd_r_6",
 736         "lcd_r_7",
 737         "lcd_vsync",
 738         "mdmgpio0",
 739         "mdmgpio1",
 740         "mdmgpio2",
 741         "mdmgpio3",
 742         "mdmgpio4",
 743         "mdmgpio5",
 744         "mdmgpio6",
 745         "mdmgpio7",
 746         "mdmgpio8",
 747         "mphi_data_0",
 748         "mphi_data_1",
 749         "mphi_data_2",
 750         "mphi_data_3",
 751         "mphi_data_4",
 752         "mphi_data_5",
 753         "mphi_data_6",
 754         "mphi_data_7",
 755         "mphi_data_8",
 756         "mphi_data_9",
 757         "mphi_data_10",
 758         "mphi_data_11",
 759         "mphi_data_12",
 760         "mphi_data_13",
 761         "mphi_data_14",
 762         "mphi_data_15",
 763         "mphi_ha0",
 764         "mphi_hat0",
 765         "mphi_hat1",
 766         "mphi_hce0_n",
 767         "mphi_hce1_n",
 768         "mphi_hrd_n",
 769         "mphi_hwr_n",
 770         "mphi_run0",
 771         "mphi_run1",
 772         "mtx_scan_clk",
 773         "mtx_scan_data",
 774         "nand_ad_0",
 775         "nand_ad_1",
 776         "nand_ad_2",
 777         "nand_ad_3",
 778         "nand_ad_4",
 779         "nand_ad_5",
 780         "nand_ad_6",
 781         "nand_ad_7",
 782         "nand_ale",
 783         "nand_cen_0",
 784         "nand_cen_1",
 785         "nand_cle",
 786         "nand_oen",
 787         "nand_rdy_0",
 788         "nand_rdy_1",
 789         "nand_wen",
 790         "nand_wp",
 791         "pc1",
 792         "pc2",
 793         "pmu_int",
 794         "pmu_scl",
 795         "pmu_sda",
 796         "rfst2g_mtsloten3g",
 797         "rgmii_0_rx_ctl",
 798         "rgmii_0_rxc",
 799         "rgmii_0_rxd_0",
 800         "rgmii_0_rxd_1",
 801         "rgmii_0_rxd_2",
 802         "rgmii_0_rxd_3",
 803         "rgmii_0_tx_ctl",
 804         "rgmii_0_txc",
 805         "rgmii_0_txd_0",
 806         "rgmii_0_txd_1",
 807         "rgmii_0_txd_2",
 808         "rgmii_0_txd_3",
 809         "rgmii_1_rx_ctl",
 810         "rgmii_1_rxc",
 811         "rgmii_1_rxd_0",
 812         "rgmii_1_rxd_1",
 813         "rgmii_1_rxd_2",
 814         "rgmii_1_rxd_3",
 815         "rgmii_1_tx_ctl",
 816         "rgmii_1_txc",
 817         "rgmii_1_txd_0",
 818         "rgmii_1_txd_1",
 819         "rgmii_1_txd_2",
 820         "rgmii_1_txd_3",
 821         "rgmii_gpio_0",
 822         "rgmii_gpio_1",
 823         "rgmii_gpio_2",
 824         "rgmii_gpio_3",
 825         "rtxdata2g_txdata3g1",
 826         "rtxen2g_txdata3g2",
 827         "rxdata3g0",
 828         "rxdata3g1",
 829         "rxdata3g2",
 830         "sdio1_clk",
 831         "sdio1_cmd",
 832         "sdio1_data_0",
 833         "sdio1_data_1",
 834         "sdio1_data_2",
 835         "sdio1_data_3",
 836         "sdio4_clk",
 837         "sdio4_cmd",
 838         "sdio4_data_0",
 839         "sdio4_data_1",
 840         "sdio4_data_2",
 841         "sdio4_data_3",
 842         "sim_clk",
 843         "sim_data",
 844         "sim_det",
 845         "sim_resetn",
 846         "sim2_clk",
 847         "sim2_data",
 848         "sim2_det",
 849         "sim2_resetn",
 850         "sri_c",
 851         "sri_d",
 852         "sri_e",
 853         "ssp_extclk",
 854         "ssp0_clk",
 855         "ssp0_fs",
 856         "ssp0_rxd",
 857         "ssp0_txd",
 858         "ssp2_clk",
 859         "ssp2_fs_0",
 860         "ssp2_fs_1",
 861         "ssp2_fs_2",
 862         "ssp2_fs_3",
 863         "ssp2_rxd_0",
 864         "ssp2_rxd_1",
 865         "ssp2_txd_0",
 866         "ssp2_txd_1",
 867         "ssp3_clk",
 868         "ssp3_fs",
 869         "ssp3_rxd",
 870         "ssp3_txd",
 871         "ssp4_clk",
 872         "ssp4_fs",
 873         "ssp4_rxd",
 874         "ssp4_txd",
 875         "ssp5_clk",
 876         "ssp5_fs",
 877         "ssp5_rxd",
 878         "ssp5_txd",
 879         "ssp6_clk",
 880         "ssp6_fs",
 881         "ssp6_rxd",
 882         "ssp6_txd",
 883         "stat_1",
 884         "stat_2",
 885         "sysclken",
 886         "traceclk",
 887         "tracedt00",
 888         "tracedt01",
 889         "tracedt02",
 890         "tracedt03",
 891         "tracedt04",
 892         "tracedt05",
 893         "tracedt06",
 894         "tracedt07",
 895         "tracedt08",
 896         "tracedt09",
 897         "tracedt10",
 898         "tracedt11",
 899         "tracedt12",
 900         "tracedt13",
 901         "tracedt14",
 902         "tracedt15",
 903         "txdata3g0",
 904         "txpwrind",
 905         "uartb1_ucts",
 906         "uartb1_urts",
 907         "uartb1_urxd",
 908         "uartb1_utxd",
 909         "uartb2_urxd",
 910         "uartb2_utxd",
 911         "uartb3_ucts",
 912         "uartb3_urts",
 913         "uartb3_urxd",
 914         "uartb3_utxd",
 915         "uartb4_ucts",
 916         "uartb4_urts",
 917         "uartb4_urxd",
 918         "uartb4_utxd",
 919         "vc_cam1_scl",
 920         "vc_cam1_sda",
 921         "vc_cam2_scl",
 922         "vc_cam2_sda",
 923         "vc_cam3_scl",
 924         "vc_cam3_sda",
 925 };
 926
 927 /* Every pin can implement all ALT1-ALT4 functions */
 928 #define BCM281XX_PIN_FUNCTION(fcn_name)                 \
 929 {                                                       \
 930         .name = #fcn_name,                              \
 931         .groups = bcm281xx_alt_groups,                  \
 932         .ngroups = ARRAY_SIZE(bcm281xx_alt_groups),     \
 933 }
 934
 935 static const struct bcm281xx_pin_function bcm281xx_functions[] = {
 936         BCM281XX_PIN_FUNCTION(alt1),
 937         BCM281XX_PIN_FUNCTION(alt2),
 938         BCM281XX_PIN_FUNCTION(alt3),
 939         BCM281XX_PIN_FUNCTION(alt4),
 940 };
 941
 942 static struct bcm281xx_pinctrl_data bcm281xx_pinctrl = {
 943         .pins = bcm281xx_pinctrl_pins,
 944         .npins = ARRAY_SIZE(bcm281xx_pinctrl_pins),
 945         .functions = bcm281xx_functions,
 946         .nfunctions = ARRAY_SIZE(bcm281xx_functions),
 947 };
 948
 949 static inline enum bcm281xx_pin_type pin_type_get(struct pinctrl_dev *pctldev,
 950                                                   unsigned pin)
 951 {
 952         struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
 953
 954         if (pin >= pdata->npins)
 955                 return BCM281XX_PIN_TYPE_UNKNOWN;
 956
 957         return *(enum bcm281xx_pin_type *)(pdata->pins[pin].drv_data);
 958 }
 959
 960 #define BCM281XX_PIN_SHIFT(type, param) \
 961         (BCM281XX_ ## type ## _PIN_REG_ ## param ## _SHIFT)
 962
 963 #define BCM281XX_PIN_MASK(type, param) \
 964         (BCM281XX_ ## type ## _PIN_REG_ ## param ## _MASK)
 965
 966 /*
 967  * This helper function is used to build up the value and mask used to write to
 968  * a pin register, but does not actually write to the register.
 969  */
 970 static inline void bcm281xx_pin_update(u32 *reg_val, u32 *reg_mask,
 971                                        u32 param_val, u32 param_shift,
 972                                        u32 param_mask)
 973 {
 974         *reg_val &= ~param_mask;
 975         *reg_val |= (param_val << param_shift) & param_mask;
 976         *reg_mask |= param_mask;
 977 }
 978
 979 static struct regmap_config bcm281xx_pinctrl_regmap_config = {
 980         .reg_bits = 32,
 981         .reg_stride = 4,
 982         .val_bits = 32,
 983         .max_register = BCM281XX_PIN_VC_CAM3_SDA,
 984 };
 985
 986 static int bcm281xx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
 987 {
 988         struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
 989
 990         return pdata->npins;
 991 }
 992
 993 static const char *bcm281xx_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
 994                                                    unsigned group)
 995 {
 996         struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
 997
 998         return pdata->pins[group].name;
 999 }
1000
1001 static int bcm281xx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
1002                                            unsigned group,
1003                                            const unsigned **pins,
1004                                            unsigned *num_pins)
1005 {
1006         struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1007
1008         *pins = &pdata->pins[group].number;
1009         *num_pins = 1;
1010
1011         return 0;
1012 }
1013
1014 static void bcm281xx_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
1015                                           struct seq_file *s,
1016                                           unsigned offset)
1017 {
1018         seq_printf(s, " %s", dev_name(pctldev->dev));
1019 }
1020
1021 static struct pinctrl_ops bcm281xx_pinctrl_ops = {
1022         .get_groups_count = bcm281xx_pinctrl_get_groups_count,
1023         .get_group_name = bcm281xx_pinctrl_get_group_name,
1024         .get_group_pins = bcm281xx_pinctrl_get_group_pins,
1025         .pin_dbg_show = bcm281xx_pinctrl_pin_dbg_show,
1026         .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1027         .dt_free_map = pinctrl_utils_dt_free_map,
1028 };
1029
1030 static int bcm281xx_pinctrl_get_fcns_count(struct pinctrl_dev *pctldev)
1031 {
1032         struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1033
1034         return pdata->nfunctions;
1035 }
1036
1037 static const char *bcm281xx_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev,
1038                                                  unsigned function)
1039 {
1040         struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1041
1042         return pdata->functions[function].name;
1043 }
1044
1045 static int bcm281xx_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev,
1046                                            unsigned function,
1047                                            const char * const **groups,
1048                                            unsigned * const num_groups)
1049 {
1050         struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1051
1052         *groups = pdata->functions[function].groups;
1053         *num_groups = pdata->functions[function].ngroups;
1054
1055         return 0;
1056 }
1057
1058 static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev,
1059                                unsigned function,
1060                                unsigned group)
1061 {
1062         struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1063         const struct bcm281xx_pin_function *f = &pdata->functions[function];
1064         u32 offset = 4 * pdata->pins[group].number;
1065         int rc = 0;
1066
1067         dev_dbg(pctldev->dev,
1068                 "%s(): Enable function %s (%d) of pin %s (%d) @offset 0x%x.\n",
1069                 __func__, f->name, function, pdata->pins[group].name,
1070                 pdata->pins[group].number, offset);
1071
1072         rc = regmap_update_bits(pdata->regmap, offset,
1073                 BCM281XX_PIN_REG_F_SEL_MASK,
1074                 function << BCM281XX_PIN_REG_F_SEL_SHIFT);
1075         if (rc)
1076                 dev_err(pctldev->dev,
1077                         "Error updating register for pin %s (%d).\n",
1078                         pdata->pins[group].name, pdata->pins[group].number);
1079
1080         return rc;
1081 }
1082
1083 static struct pinmux_ops bcm281xx_pinctrl_pinmux_ops = {
1084         .get_functions_count = bcm281xx_pinctrl_get_fcns_count,
1085         .get_function_name = bcm281xx_pinctrl_get_fcn_name,
1086         .get_function_groups = bcm281xx_pinctrl_get_fcn_groups,
1087         .set_mux = bcm281xx_pinmux_set,
1088 };
1089
1090 static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev,
1091                                            unsigned pin,
1092                                            unsigned long *config)
1093 {
1094         return -ENOTSUPP;
1095 }
1096
1097
1098 /* Goes through the configs and update register val/mask */
1099 static int bcm281xx_std_pin_update(struct pinctrl_dev *pctldev,
1100                                    unsigned pin,
1101                                    unsigned long *configs,
1102                                    unsigned num_configs,
1103                                    u32 *val,
1104                                    u32 *mask)
1105 {
1106         struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1107         int i;
1108         enum pin_config_param param;
1109         u16 arg;
1110
1111         for (i = 0; i < num_configs; i++) {
1112                 param = pinconf_to_config_param(configs[i]);
1113                 arg = pinconf_to_config_argument(configs[i]);
1114
1115                 switch (param) {
1116                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1117                         arg = (arg >= 1 ? 1 : 0);
1118                         bcm281xx_pin_update(val, mask, arg,
1119                                 BCM281XX_PIN_SHIFT(STD, HYST),
1120                                 BCM281XX_PIN_MASK(STD, HYST));
1121                         break;
1122                 /*
1123                  * The pin bias can only be one of pull-up, pull-down, or
1124                  * disable.  The user does not need to specify a value for the
1125                  * property, and the default value from pinconf-generic is
1126                  * ignored.
1127                  */
1128                 case PIN_CONFIG_BIAS_DISABLE:
1129                         bcm281xx_pin_update(val, mask, 0,
1130                                 BCM281XX_PIN_SHIFT(STD, PULL_UP),
1131                                 BCM281XX_PIN_MASK(STD, PULL_UP));
1132                         bcm281xx_pin_update(val, mask, 0,
1133                                 BCM281XX_PIN_SHIFT(STD, PULL_DN),
1134                                 BCM281XX_PIN_MASK(STD, PULL_DN));
1135                         break;
1136
1137                 case PIN_CONFIG_BIAS_PULL_UP:
1138                         bcm281xx_pin_update(val, mask, 1,
1139                                 BCM281XX_PIN_SHIFT(STD, PULL_UP),
1140                                 BCM281XX_PIN_MASK(STD, PULL_UP));
1141                         bcm281xx_pin_update(val, mask, 0,
1142                                 BCM281XX_PIN_SHIFT(STD, PULL_DN),
1143                                 BCM281XX_PIN_MASK(STD, PULL_DN));
1144                         break;
1145
1146                 case PIN_CONFIG_BIAS_PULL_DOWN:
1147                         bcm281xx_pin_update(val, mask, 0,
1148                                 BCM281XX_PIN_SHIFT(STD, PULL_UP),
1149                                 BCM281XX_PIN_MASK(STD, PULL_UP));
1150                         bcm281xx_pin_update(val, mask, 1,
1151                                 BCM281XX_PIN_SHIFT(STD, PULL_DN),
1152                                 BCM281XX_PIN_MASK(STD, PULL_DN));
1153                         break;
1154
1155                 case PIN_CONFIG_SLEW_RATE:
1156                         arg = (arg >= 1 ? 1 : 0);
1157                         bcm281xx_pin_update(val, mask, arg,
1158                                 BCM281XX_PIN_SHIFT(STD, SLEW),
1159                                 BCM281XX_PIN_MASK(STD, SLEW));
1160                         break;
1161
1162                 case PIN_CONFIG_INPUT_ENABLE:
1163                         /* inversed since register is for input _disable_ */
1164                         arg = (arg >= 1 ? 0 : 1);
1165                         bcm281xx_pin_update(val, mask, arg,
1166                                 BCM281XX_PIN_SHIFT(STD, INPUT_DIS),
1167                                 BCM281XX_PIN_MASK(STD, INPUT_DIS));
1168                         break;
1169
1170                 case PIN_CONFIG_DRIVE_STRENGTH:
1171                         /* Valid range is 2-16 mA, even numbers only */
1172                         if ((arg < 2) || (arg > 16) || (arg % 2)) {
1173                                 dev_err(pctldev->dev,
1174                                         "Invalid Drive Strength value (%d) for "
1175                                         "pin %s (%d). Valid values are "
1176                                         "(2..16) mA, even numbers only.\n",
1177                                         arg, pdata->pins[pin].name, pin);
1178                                 return -EINVAL;
1179                         }
1180                         bcm281xx_pin_update(val, mask, (arg/2)-1,
1181                                 BCM281XX_PIN_SHIFT(STD, DRV_STR),
1182                                 BCM281XX_PIN_MASK(STD, DRV_STR));
1183                         break;
1184
1185                 default:
1186                         dev_err(pctldev->dev,
1187                                 "Unrecognized pin config %d for pin %s (%d).\n",
1188                                 param, pdata->pins[pin].name, pin);
1189                         return -EINVAL;
1190
1191                 } /* switch config */
1192         } /* for each config */
1193
1194         return 0;
1195 }
1196
1197 /*
1198  * The pull-up strength for an I2C pin is represented by bits 4-6 in the
1199  * register with the following mapping:
1200  *   0b000: No pull-up
1201  *   0b001: 1200 Ohm
1202  *   0b010: 1800 Ohm
1203  *   0b011: 720 Ohm
1204  *   0b100: 2700 Ohm
1205  *   0b101: 831 Ohm
1206  *   0b110: 1080 Ohm
1207  *   0b111: 568 Ohm
1208  * This array maps pull-up strength in Ohms to register values (1+index).
1209  */
1210 static const u16 bcm281xx_pullup_map[] = {
1211         1200, 1800, 720, 2700, 831, 1080, 568
1212 };
1213
1214 /* Goes through the configs and update register val/mask */
1215 static int bcm281xx_i2c_pin_update(struct pinctrl_dev *pctldev,
1216                                    unsigned pin,
1217                                    unsigned long *configs,
1218                                    unsigned num_configs,
1219                                    u32 *val,
1220                                    u32 *mask)
1221 {
1222         struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1223         int i, j;
1224         enum pin_config_param param;
1225         u16 arg;
1226
1227         for (i = 0; i < num_configs; i++) {
1228                 param = pinconf_to_config_param(configs[i]);
1229                 arg = pinconf_to_config_argument(configs[i]);
1230
1231                 switch (param) {
1232                 case PIN_CONFIG_BIAS_PULL_UP:
1233                         for (j = 0; j < ARRAY_SIZE(bcm281xx_pullup_map); j++)
1234                                 if (bcm281xx_pullup_map[j] == arg)
1235                                         break;
1236
1237                         if (j == ARRAY_SIZE(bcm281xx_pullup_map)) {
1238                                 dev_err(pctldev->dev,
1239                                         "Invalid pull-up value (%d) for pin %s "
1240                                         "(%d). Valid values are 568, 720, 831, "
1241                                         "1080, 1200, 1800, 2700 Ohms.\n",
1242                                         arg, pdata->pins[pin].name, pin);
1243                                 return -EINVAL;
1244                         }
1245
1246                         bcm281xx_pin_update(val, mask, j+1,
1247                                 BCM281XX_PIN_SHIFT(I2C, PULL_UP_STR),
1248                                 BCM281XX_PIN_MASK(I2C, PULL_UP_STR));
1249                         break;
1250
1251                 case PIN_CONFIG_BIAS_DISABLE:
1252                         bcm281xx_pin_update(val, mask, 0,
1253                                 BCM281XX_PIN_SHIFT(I2C, PULL_UP_STR),
1254                                 BCM281XX_PIN_MASK(I2C, PULL_UP_STR));
1255                         break;
1256
1257                 case PIN_CONFIG_SLEW_RATE:
1258                         arg = (arg >= 1 ? 1 : 0);
1259                         bcm281xx_pin_update(val, mask, arg,
1260                                 BCM281XX_PIN_SHIFT(I2C, SLEW),
1261                                 BCM281XX_PIN_MASK(I2C, SLEW));
1262                         break;
1263
1264                 case PIN_CONFIG_INPUT_ENABLE:
1265                         /* inversed since register is for input _disable_ */
1266                         arg = (arg >= 1 ? 0 : 1);
1267                         bcm281xx_pin_update(val, mask, arg,
1268                                 BCM281XX_PIN_SHIFT(I2C, INPUT_DIS),
1269                                 BCM281XX_PIN_MASK(I2C, INPUT_DIS));
1270                         break;
1271
1272                 default:
1273                         dev_err(pctldev->dev,
1274                                 "Unrecognized pin config %d for pin %s (%d).\n",
1275                                 param, pdata->pins[pin].name, pin);
1276                         return -EINVAL;
1277
1278                 } /* switch config */
1279         } /* for each config */
1280
1281         return 0;
1282 }
1283
1284 /* Goes through the configs and update register val/mask */
1285 static int bcm281xx_hdmi_pin_update(struct pinctrl_dev *pctldev,
1286                                     unsigned pin,
1287                                     unsigned long *configs,
1288                                     unsigned num_configs,
1289                                     u32 *val,
1290                                     u32 *mask)
1291 {
1292         struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1293         int i;
1294         enum pin_config_param param;
1295         u16 arg;
1296
1297         for (i = 0; i < num_configs; i++) {
1298                 param = pinconf_to_config_param(configs[i]);
1299                 arg = pinconf_to_config_argument(configs[i]);
1300
1301                 switch (param) {
1302                 case PIN_CONFIG_SLEW_RATE:
1303                         arg = (arg >= 1 ? 1 : 0);
1304                         bcm281xx_pin_update(val, mask, arg,
1305                                 BCM281XX_PIN_SHIFT(HDMI, MODE),
1306                                 BCM281XX_PIN_MASK(HDMI, MODE));
1307                         break;
1308
1309                 case PIN_CONFIG_INPUT_ENABLE:
1310                         /* inversed since register is for input _disable_ */
1311                         arg = (arg >= 1 ? 0 : 1);
1312                         bcm281xx_pin_update(val, mask, arg,
1313                                 BCM281XX_PIN_SHIFT(HDMI, INPUT_DIS),
1314                                 BCM281XX_PIN_MASK(HDMI, INPUT_DIS));
1315                         break;
1316
1317                 default:
1318                         dev_err(pctldev->dev,
1319                                 "Unrecognized pin config %d for pin %s (%d).\n",
1320                                 param, pdata->pins[pin].name, pin);
1321                         return -EINVAL;
1322
1323                 } /* switch config */
1324         } /* for each config */
1325
1326         return 0;
1327 }
1328
1329 static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev,
1330                                            unsigned pin,
1331                                            unsigned long *configs,
1332                                            unsigned num_configs)
1333 {
1334         struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1335         enum bcm281xx_pin_type pin_type;
1336         u32 offset = 4 * pin;
1337         u32 cfg_val, cfg_mask;
1338         int rc;
1339
1340         cfg_val = 0;
1341         cfg_mask = 0;
1342         pin_type = pin_type_get(pctldev, pin);
1343
1344         /* Different pins have different configuration options */
1345         switch (pin_type) {
1346         case BCM281XX_PIN_TYPE_STD:
1347                 rc = bcm281xx_std_pin_update(pctldev, pin, configs,
1348                         num_configs, &cfg_val, &cfg_mask);
1349                 break;
1350
1351         case BCM281XX_PIN_TYPE_I2C:
1352                 rc = bcm281xx_i2c_pin_update(pctldev, pin, configs,
1353                         num_configs, &cfg_val, &cfg_mask);
1354                 break;
1355
1356         case BCM281XX_PIN_TYPE_HDMI:
1357                 rc = bcm281xx_hdmi_pin_update(pctldev, pin, configs,
1358                         num_configs, &cfg_val, &cfg_mask);
1359                 break;
1360
1361         default:
1362                 dev_err(pctldev->dev, "Unknown pin type for pin %s (%d).\n",
1363                         pdata->pins[pin].name, pin);
1364                 return -EINVAL;
1365
1366         } /* switch pin type */
1367
1368         if (rc)
1369                 return rc;
1370
1371         dev_dbg(pctldev->dev,
1372                 "%s(): Set pin %s (%d) with config 0x%x, mask 0x%x\n",
1373                 __func__, pdata->pins[pin].name, pin, cfg_val, cfg_mask);
1374
1375         rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val);
1376         if (rc) {
1377                 dev_err(pctldev->dev,
1378                         "Error updating register for pin %s (%d).\n",
1379                         pdata->pins[pin].name, pin);
1380                 return rc;
1381         }
1382
1383         return 0;
1384 }
1385
1386 static struct pinconf_ops bcm281xx_pinctrl_pinconf_ops = {
1387         .pin_config_get = bcm281xx_pinctrl_pin_config_get,
1388         .pin_config_set = bcm281xx_pinctrl_pin_config_set,
1389 };
1390
1391 static struct pinctrl_desc bcm281xx_pinctrl_desc = {
1392         /* name, pins, npins members initialized in probe function */
1393         .pctlops = &bcm281xx_pinctrl_ops,
1394         .pmxops = &bcm281xx_pinctrl_pinmux_ops,
1395         .confops = &bcm281xx_pinctrl_pinconf_ops,
1396         .owner = THIS_MODULE,
1397 };
1398
1399 static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev)
1400 {
1401         struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl;
1402         struct resource *res;
1403         struct pinctrl_dev *pctl;
1404
1405         /* So far We can assume there is only 1 bank of registers */
1406         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1407         pdata->reg_base = devm_ioremap_resource(&pdev->dev, res);
1408         if (IS_ERR(pdata->reg_base)) {
1409                 dev_err(&pdev->dev, "Failed to ioremap MEM resource\n");
1410                 return -ENODEV;
1411         }
1412
1413         /* Initialize the dynamic part of pinctrl_desc */
1414         pdata->regmap = devm_regmap_init_mmio(&pdev->dev, pdata->reg_base,
1415                 &bcm281xx_pinctrl_regmap_config);
1416         if (IS_ERR(pdata->regmap)) {
1417                 dev_err(&pdev->dev, "Regmap MMIO init failed.\n");
1418                 return -ENODEV;
1419         }
1420
1421         bcm281xx_pinctrl_desc.name = dev_name(&pdev->dev);
1422         bcm281xx_pinctrl_desc.pins = bcm281xx_pinctrl.pins;
1423         bcm281xx_pinctrl_desc.npins = bcm281xx_pinctrl.npins;
1424
1425         pctl = pinctrl_register(&bcm281xx_pinctrl_desc,
1426                                 &pdev->dev,
1427                                 pdata);
1428         if (!pctl) {
1429                 dev_err(&pdev->dev, "Failed to register pinctrl\n");
1430                 return -ENODEV;
1431         }
1432
1433         platform_set_drvdata(pdev, pdata);
1434
1435         return 0;
1436 }
1437
1438 static struct of_device_id bcm281xx_pinctrl_of_match[] = {
1439         { .compatible = "brcm,bcm11351-pinctrl", },
1440         { },
1441 };
1442
1443 static struct platform_driver bcm281xx_pinctrl_driver = {
1444         .driver = {
1445                 .name = "bcm281xx-pinctrl",
1446                 .of_match_table = bcm281xx_pinctrl_of_match,
1447         },
1448 };
1449
1450 module_platform_driver_probe(bcm281xx_pinctrl_driver, bcm281xx_pinctrl_probe);
1451
1452 MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>");
1453 MODULE_AUTHOR("Sherman Yin <syin@broadcom.com>");
1454 MODULE_DESCRIPTION("Broadcom BCM281xx pinctrl driver");
1455 MODULE_LICENSE("GPL v2");