drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/pinctrl/machine.h>
  34 #include <linux/pinctrl/pinconf.h>
  35 #include <linux/pinctrl/pinctrl.h>
  36 #include <linux/pinctrl/pinmux.h>
  37 #include <linux/pinctrl/pinconf-generic.h>
  38 #include <linux/irqchip/chained_irq.h>
  39 #include <linux/clk.h>
  40 #include <linux/regmap.h>
  41 #include <linux/mfd/syscon.h>
  42 #include <dt-bindings/pinctrl/rockchip.h>
  43
  44 #include "core.h"
  45 #include "pinconf.h"
  46
  47 /* GPIO control registers */
  48 #define GPIO_SWPORT_DR          0x00
  49 #define GPIO_SWPORT_DDR         0x04
  50 #define GPIO_INTEN              0x30
  51 #define GPIO_INTMASK            0x34
  52 #define GPIO_INTTYPE_LEVEL      0x38
  53 #define GPIO_INT_POLARITY       0x3c
  54 #define GPIO_INT_STATUS         0x40
  55 #define GPIO_INT_RAWSTATUS      0x44
  56 #define GPIO_DEBOUNCE           0x48
  57 #define GPIO_PORTS_EOI          0x4c
  58 #define GPIO_EXT_PORT           0x50
  59 #define GPIO_LS_SYNC            0x60
  60
  61 enum rockchip_pinctrl_type {
  62         RK2928,
  63         RK3066B,
  64         RK3188,
  65         RK3288,
  66 };
  67
  68 /**
  69  * Encode variants of iomux registers into a type variable
  70  */
  71 #define IOMUX_GPIO_ONLY         BIT(0)
  72 #define IOMUX_WIDTH_4BIT        BIT(1)
  73 #define IOMUX_SOURCE_PMU        BIT(2)
  74 #define IOMUX_UNROUTED          BIT(3)
  75
  76 /**
  77  * @type: iomux variant using IOMUX_* constants
  78  * @offset: if initialized to -1 it will be autocalculated, by specifying
  79  *          an initial offset value the relevant source offset can be reset
  80  *          to a new value for autocalculating the following iomux registers.
  81  */
  82 struct rockchip_iomux {
  83         int                             type;
  84         int                             offset;
  85 };
  86
  87 /**
  88  * @reg_base: register base of the gpio bank
  89  * @reg_pull: optional separate register for additional pull settings
  90  * @clk: clock of the gpio bank
  91  * @irq: interrupt of the gpio bank
  92  * @pin_base: first pin number
  93  * @nr_pins: number of pins in this bank
  94  * @name: name of the bank
  95  * @bank_num: number of the bank, to account for holes
  96  * @iomux: array describing the 4 iomux sources of the bank
  97  * @valid: are all necessary informations present
  98  * @of_node: dt node of this bank
  99  * @drvdata: common pinctrl basedata
 100  * @domain: irqdomain of the gpio bank
 101  * @gpio_chip: gpiolib chip
 102  * @grange: gpio range
 103  * @slock: spinlock for the gpio bank
 104  */
 105 struct rockchip_pin_bank {
 106         void __iomem                    *reg_base;
 107         struct regmap                   *regmap_pull;
 108         struct clk                      *clk;
 109         int                             irq;
 110         u32                             pin_base;
 111         u8                              nr_pins;
 112         char                            *name;
 113         u8                              bank_num;
 114         struct rockchip_iomux           iomux[4];
 115         bool                            valid;
 116         struct device_node              *of_node;
 117         struct rockchip_pinctrl         *drvdata;
 118         struct irq_domain               *domain;
 119         struct gpio_chip                gpio_chip;
 120         struct pinctrl_gpio_range       grange;
 121         spinlock_t                      slock;
 122         u32                             toggle_edge_mode;
 123 };
 124
 125 #define PIN_BANK(id, pins, label)                       \
 126         {                                               \
 127                 .bank_num       = id,                   \
 128                 .nr_pins        = pins,                 \
 129                 .name           = label,                \
 130                 .iomux          = {                     \
 131                         { .offset = -1 },               \
 132                         { .offset = -1 },               \
 133                         { .offset = -1 },               \
 134                         { .offset = -1 },               \
 135                 },                                      \
 136         }
 137
 138 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
 139         {                                                               \
 140                 .bank_num       = id,                                   \
 141                 .nr_pins        = pins,                                 \
 142                 .name           = label,                                \
 143                 .iomux          = {                                     \
 144                         { .type = iom0, .offset = -1 },                 \
 145                         { .type = iom1, .offset = -1 },                 \
 146                         { .type = iom2, .offset = -1 },                 \
 147                         { .type = iom3, .offset = -1 },                 \
 148                 },                                                      \
 149         }
 150
 151 /**
 152  */
 153 struct rockchip_pin_ctrl {
 154         struct rockchip_pin_bank        *pin_banks;
 155         u32                             nr_banks;
 156         u32                             nr_pins;
 157         char                            *label;
 158         enum rockchip_pinctrl_type      type;
 159         int                             grf_mux_offset;
 160         int                             pmu_mux_offset;
 161         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
 162                                     int pin_num, struct regmap **regmap,
 163                                     int *reg, u8 *bit);
 164 };
 165
 166 struct rockchip_pin_config {
 167         unsigned int            func;
 168         unsigned long           *configs;
 169         unsigned int            nconfigs;
 170 };
 171
 172 /**
 173  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 174  * @name: name of the pin group, used to lookup the group.
 175  * @pins: the pins included in this group.
 176  * @npins: number of pins included in this group.
 177  * @func: the mux function number to be programmed when selected.
 178  * @configs: the config values to be set for each pin
 179  * @nconfigs: number of configs for each pin
 180  */
 181 struct rockchip_pin_group {
 182         const char                      *name;
 183         unsigned int                    npins;
 184         unsigned int                    *pins;
 185         struct rockchip_pin_config      *data;
 186 };
 187
 188 /**
 189  * struct rockchip_pmx_func: represent a pin function.
 190  * @name: name of the pin function, used to lookup the function.
 191  * @groups: one or more names of pin groups that provide this function.
 192  * @num_groups: number of groups included in @groups.
 193  */
 194 struct rockchip_pmx_func {
 195         const char              *name;
 196         const char              **groups;
 197         u8                      ngroups;
 198 };
 199
 200 struct rockchip_pinctrl {
 201         struct regmap                   *regmap_base;
 202         int                             reg_size;
 203         struct regmap                   *regmap_pull;
 204         struct regmap                   *regmap_pmu;
 205         struct device                   *dev;
 206         struct rockchip_pin_ctrl        *ctrl;
 207         struct pinctrl_desc             pctl;
 208         struct pinctrl_dev              *pctl_dev;
 209         struct rockchip_pin_group       *groups;
 210         unsigned int                    ngroups;
 211         struct rockchip_pmx_func        *functions;
 212         unsigned int                    nfunctions;
 213 };
 214
 215 static struct regmap_config rockchip_regmap_config = {
 216         .reg_bits = 32,
 217         .val_bits = 32,
 218         .reg_stride = 4,
 219 };
 220
 221 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 222 {
 223         return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 224 }
 225
 226 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 227                                         const struct rockchip_pinctrl *info,
 228                                         const char *name)
 229 {
 230         int i;
 231
 232         for (i = 0; i < info->ngroups; i++) {
 233                 if (!strcmp(info->groups[i].name, name))
 234                         return &info->groups[i];
 235         }
 236
 237         return NULL;
 238 }
 239
 240 /*
 241  * given a pin number that is local to a pin controller, find out the pin bank
 242  * and the register base of the pin bank.
 243  */
 244 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 245                                                                 unsigned pin)
 246 {
 247         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 248
 249         while (pin >= (b->pin_base + b->nr_pins))
 250                 b++;
 251
 252         return b;
 253 }
 254
 255 static struct rockchip_pin_bank *bank_num_to_bank(
 256                                         struct rockchip_pinctrl *info,
 257                                         unsigned num)
 258 {
 259         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 260         int i;
 261
 262         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 263                 if (b->bank_num == num)
 264                         return b;
 265         }
 266
 267         return ERR_PTR(-EINVAL);
 268 }
 269
 270 /*
 271  * Pinctrl_ops handling
 272  */
 273
 274 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 275 {
 276         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 277
 278         return info->ngroups;
 279 }
 280
 281 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 282                                                         unsigned selector)
 283 {
 284         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 285
 286         return info->groups[selector].name;
 287 }
 288
 289 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 290                                       unsigned selector, const unsigned **pins,
 291                                       unsigned *npins)
 292 {
 293         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 294
 295         if (selector >= info->ngroups)
 296                 return -EINVAL;
 297
 298         *pins = info->groups[selector].pins;
 299         *npins = info->groups[selector].npins;
 300
 301         return 0;
 302 }
 303
 304 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 305                                  struct device_node *np,
 306                                  struct pinctrl_map **map, unsigned *num_maps)
 307 {
 308         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 309         const struct rockchip_pin_group *grp;
 310         struct pinctrl_map *new_map;
 311         struct device_node *parent;
 312         int map_num = 1;
 313         int i;
 314
 315         /*
 316          * first find the group of this node and check if we need to create
 317          * config maps for pins
 318          */
 319         grp = pinctrl_name_to_group(info, np->name);
 320         if (!grp) {
 321                 dev_err(info->dev, "unable to find group for node %s\n",
 322                         np->name);
 323                 return -EINVAL;
 324         }
 325
 326         map_num += grp->npins;
 327         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 328                                                                 GFP_KERNEL);
 329         if (!new_map)
 330                 return -ENOMEM;
 331
 332         *map = new_map;
 333         *num_maps = map_num;
 334
 335         /* create mux map */
 336         parent = of_get_parent(np);
 337         if (!parent) {
 338                 devm_kfree(pctldev->dev, new_map);
 339                 return -EINVAL;
 340         }
 341         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 342         new_map[0].data.mux.function = parent->name;
 343         new_map[0].data.mux.group = np->name;
 344         of_node_put(parent);
 345
 346         /* create config map */
 347         new_map++;
 348         for (i = 0; i < grp->npins; i++) {
 349                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 350                 new_map[i].data.configs.group_or_pin =
 351                                 pin_get_name(pctldev, grp->pins[i]);
 352                 new_map[i].data.configs.configs = grp->data[i].configs;
 353                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 354         }
 355
 356         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 357                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 358
 359         return 0;
 360 }
 361
 362 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 363                                     struct pinctrl_map *map, unsigned num_maps)
 364 {
 365 }
 366
 367 static const struct pinctrl_ops rockchip_pctrl_ops = {
 368         .get_groups_count       = rockchip_get_groups_count,
 369         .get_group_name         = rockchip_get_group_name,
 370         .get_group_pins         = rockchip_get_group_pins,
 371         .dt_node_to_map         = rockchip_dt_node_to_map,
 372         .dt_free_map            = rockchip_dt_free_map,
 373 };
 374
 375 /*
 376  * Hardware access
 377  */
 378
 379 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
 380 {
 381         struct rockchip_pinctrl *info = bank->drvdata;
 382         int iomux_num = (pin / 8);
 383         struct regmap *regmap;
 384         unsigned int val;
 385         int reg, ret, mask;
 386         u8 bit;
 387
 388         if (iomux_num > 3)
 389                 return -EINVAL;
 390
 391         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 392                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 393                 return -EINVAL;
 394         }
 395
 396         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 397                 return RK_FUNC_GPIO;
 398
 399         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 400                                 ? info->regmap_pmu : info->regmap_base;
 401
 402         /* get basic quadrupel of mux registers and the correct reg inside */
 403         mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
 404         reg = bank->iomux[iomux_num].offset;
 405         if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
 406                 if ((pin % 8) >= 4)
 407                         reg += 0x4;
 408                 bit = (pin % 4) * 4;
 409         } else {
 410                 bit = (pin % 8) * 2;
 411         }
 412
 413         ret = regmap_read(regmap, reg, &val);
 414         if (ret)
 415                 return ret;
 416
 417         return ((val >> bit) & mask);
 418 }
 419
 420 /*
 421  * Set a new mux function for a pin.
 422  *
 423  * The register is divided into the upper and lower 16 bit. When changing
 424  * a value, the previous register value is not read and changed. Instead
 425  * it seems the changed bits are marked in the upper 16 bit, while the
 426  * changed value gets set in the same offset in the lower 16 bit.
 427  * All pin settings seem to be 2 bit wide in both the upper and lower
 428  * parts.
 429  * @bank: pin bank to change
 430  * @pin: pin to change
 431  * @mux: new mux function to set
 432  */
 433 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 434 {
 435         struct rockchip_pinctrl *info = bank->drvdata;
 436         int iomux_num = (pin / 8);
 437         struct regmap *regmap;
 438         int reg, ret, mask;
 439         unsigned long flags;
 440         u8 bit;
 441         u32 data, rmask;
 442
 443         if (iomux_num > 3)
 444                 return -EINVAL;
 445
 446         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 447                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 448                 return -EINVAL;
 449         }
 450
 451         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
 452                 if (mux != RK_FUNC_GPIO) {
 453                         dev_err(info->dev,
 454                                 "pin %d only supports a gpio mux\n", pin);
 455                         return -ENOTSUPP;
 456                 } else {
 457                         return 0;
 458                 }
 459         }
 460
 461         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 462                                                 bank->bank_num, pin, mux);
 463
 464         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 465                                 ? info->regmap_pmu : info->regmap_base;
 466
 467         /* get basic quadrupel of mux registers and the correct reg inside */
 468         mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
 469         reg = bank->iomux[iomux_num].offset;
 470         if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
 471                 if ((pin % 8) >= 4)
 472                         reg += 0x4;
 473                 bit = (pin % 4) * 4;
 474         } else {
 475                 bit = (pin % 8) * 2;
 476         }
 477
 478         spin_lock_irqsave(&bank->slock, flags);
 479
 480         data = (mask << (bit + 16));
 481         rmask = data | (data >> 16);
 482         data |= (mux & mask) << bit;
 483         ret = regmap_update_bits(regmap, reg, rmask, data);
 484
 485         spin_unlock_irqrestore(&bank->slock, flags);
 486
 487         return ret;
 488 }
 489
 490 #define RK2928_PULL_OFFSET              0x118
 491 #define RK2928_PULL_PINS_PER_REG        16
 492 #define RK2928_PULL_BANK_STRIDE         8
 493
 494 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 495                                     int pin_num, struct regmap **regmap,
 496                                     int *reg, u8 *bit)
 497 {
 498         struct rockchip_pinctrl *info = bank->drvdata;
 499
 500         *regmap = info->regmap_base;
 501         *reg = RK2928_PULL_OFFSET;
 502         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
 503         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
 504
 505         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
 506 };
 507
 508 #define RK3188_PULL_OFFSET              0x164
 509 #define RK3188_PULL_BITS_PER_PIN        2
 510 #define RK3188_PULL_PINS_PER_REG        8
 511 #define RK3188_PULL_BANK_STRIDE         16
 512 #define RK3188_PULL_PMU_OFFSET          0x64
 513
 514 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 515                                     int pin_num, struct regmap **regmap,
 516                                     int *reg, u8 *bit)
 517 {
 518         struct rockchip_pinctrl *info = bank->drvdata;
 519
 520         /* The first 12 pins of the first bank are located elsewhere */
 521         if (bank->bank_num == 0 && pin_num < 12) {
 522                 *regmap = info->regmap_pmu ? info->regmap_pmu
 523                                            : bank->regmap_pull;
 524                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
 525                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 526                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 527                 *bit *= RK3188_PULL_BITS_PER_PIN;
 528         } else {
 529                 *regmap = info->regmap_pull ? info->regmap_pull
 530                                             : info->regmap_base;
 531                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
 532
 533                 /* correct the offset, as it is the 2nd pull register */
 534                 *reg -= 4;
 535                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 536                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 537
 538                 /*
 539                  * The bits in these registers have an inverse ordering
 540                  * with the lowest pin being in bits 15:14 and the highest
 541                  * pin in bits 1:0
 542                  */
 543                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
 544                 *bit *= RK3188_PULL_BITS_PER_PIN;
 545         }
 546 }
 547
 548 #define RK3288_PULL_OFFSET              0x140
 549 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 550                                     int pin_num, struct regmap **regmap,
 551                                     int *reg, u8 *bit)
 552 {
 553         struct rockchip_pinctrl *info = bank->drvdata;
 554
 555         /* The first 24 pins of the first bank are located in PMU */
 556         if (bank->bank_num == 0) {
 557                 *regmap = info->regmap_pmu;
 558                 *reg = RK3188_PULL_PMU_OFFSET;
 559
 560                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 561                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 562                 *bit *= RK3188_PULL_BITS_PER_PIN;
 563         } else {
 564                 *regmap = info->regmap_base;
 565                 *reg = RK3288_PULL_OFFSET;
 566
 567                 /* correct the offset, as we're starting with the 2nd bank */
 568                 *reg -= 0x10;
 569                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 570                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 571
 572                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 573                 *bit *= RK3188_PULL_BITS_PER_PIN;
 574         }
 575 }
 576
 577 #define RK3288_DRV_PMU_OFFSET           0x70
 578 #define RK3288_DRV_GRF_OFFSET           0x1c0
 579 #define RK3288_DRV_BITS_PER_PIN         2
 580 #define RK3288_DRV_PINS_PER_REG         8
 581 #define RK3288_DRV_BANK_STRIDE          16
 582 static int rk3288_drv_list[] = { 2, 4, 8, 12 };
 583
 584 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 585                                     int pin_num, struct regmap **regmap,
 586                                     int *reg, u8 *bit)
 587 {
 588         struct rockchip_pinctrl *info = bank->drvdata;
 589
 590         /* The first 24 pins of the first bank are located in PMU */
 591         if (bank->bank_num == 0) {
 592                 *regmap = info->regmap_pmu;
 593                 *reg = RK3288_DRV_PMU_OFFSET;
 594
 595                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 596                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
 597                 *bit *= RK3288_DRV_BITS_PER_PIN;
 598         } else {
 599                 *regmap = info->regmap_base;
 600                 *reg = RK3288_DRV_GRF_OFFSET;
 601
 602                 /* correct the offset, as we're starting with the 2nd bank */
 603                 *reg -= 0x10;
 604                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
 605                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 606
 607                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
 608                 *bit *= RK3288_DRV_BITS_PER_PIN;
 609         }
 610 }
 611
 612 static int rk3288_get_drive(struct rockchip_pin_bank *bank, int pin_num)
 613 {
 614         struct regmap *regmap;
 615         int reg, ret;
 616         u32 data;
 617         u8 bit;
 618
 619         rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
 620
 621         ret = regmap_read(regmap, reg, &data);
 622         if (ret)
 623                 return ret;
 624
 625         data >>= bit;
 626         data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1;
 627
 628         return rk3288_drv_list[data];
 629 }
 630
 631 static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num,
 632                             int strength)
 633 {
 634         struct rockchip_pinctrl *info = bank->drvdata;
 635         struct regmap *regmap;
 636         unsigned long flags;
 637         int reg, ret, i;
 638         u32 data, rmask;
 639         u8 bit;
 640
 641         rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
 642
 643         ret = -EINVAL;
 644         for (i = 0; i < ARRAY_SIZE(rk3288_drv_list); i++) {
 645                 if (rk3288_drv_list[i] == strength) {
 646                         ret = i;
 647                         break;
 648                 }
 649         }
 650
 651         if (ret < 0) {
 652                 dev_err(info->dev, "unsupported driver strength %d\n",
 653                         strength);
 654                 return ret;
 655         }
 656
 657         spin_lock_irqsave(&bank->slock, flags);
 658
 659         /* enable the write to the equivalent lower bits */
 660         data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16);
 661         rmask = data | (data >> 16);
 662         data |= (ret << bit);
 663
 664         ret = regmap_update_bits(regmap, reg, rmask, data);
 665         spin_unlock_irqrestore(&bank->slock, flags);
 666
 667         return ret;
 668 }
 669
 670 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 671 {
 672         struct rockchip_pinctrl *info = bank->drvdata;
 673         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 674         struct regmap *regmap;
 675         int reg, ret;
 676         u8 bit;
 677         u32 data;
 678
 679         /* rk3066b does support any pulls */
 680         if (ctrl->type == RK3066B)
 681                 return PIN_CONFIG_BIAS_DISABLE;
 682
 683         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 684
 685         ret = regmap_read(regmap, reg, &data);
 686         if (ret)
 687                 return ret;
 688
 689         switch (ctrl->type) {
 690         case RK2928:
 691                 return !(data & BIT(bit))
 692                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
 693                                 : PIN_CONFIG_BIAS_DISABLE;
 694         case RK3188:
 695         case RK3288:
 696                 data >>= bit;
 697                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
 698
 699                 switch (data) {
 700                 case 0:
 701                         return PIN_CONFIG_BIAS_DISABLE;
 702                 case 1:
 703                         return PIN_CONFIG_BIAS_PULL_UP;
 704                 case 2:
 705                         return PIN_CONFIG_BIAS_PULL_DOWN;
 706                 case 3:
 707                         return PIN_CONFIG_BIAS_BUS_HOLD;
 708                 }
 709
 710                 dev_err(info->dev, "unknown pull setting\n");
 711                 return -EIO;
 712         default:
 713                 dev_err(info->dev, "unsupported pinctrl type\n");
 714                 return -EINVAL;
 715         };
 716 }
 717
 718 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 719                                         int pin_num, int pull)
 720 {
 721         struct rockchip_pinctrl *info = bank->drvdata;
 722         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 723         struct regmap *regmap;
 724         int reg, ret;
 725         unsigned long flags;
 726         u8 bit;
 727         u32 data, rmask;
 728
 729         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
 730                  bank->bank_num, pin_num, pull);
 731
 732         /* rk3066b does support any pulls */
 733         if (ctrl->type == RK3066B)
 734                 return pull ? -EINVAL : 0;
 735
 736         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 737
 738         switch (ctrl->type) {
 739         case RK2928:
 740                 spin_lock_irqsave(&bank->slock, flags);
 741
 742                 data = BIT(bit + 16);
 743                 if (pull == PIN_CONFIG_BIAS_DISABLE)
 744                         data |= BIT(bit);
 745                 ret = regmap_write(regmap, reg, data);
 746
 747                 spin_unlock_irqrestore(&bank->slock, flags);
 748                 break;
 749         case RK3188:
 750         case RK3288:
 751                 spin_lock_irqsave(&bank->slock, flags);
 752
 753                 /* enable the write to the equivalent lower bits */
 754                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
 755                 rmask = data | (data >> 16);
 756
 757                 switch (pull) {
 758                 case PIN_CONFIG_BIAS_DISABLE:
 759                         break;
 760                 case PIN_CONFIG_BIAS_PULL_UP:
 761                         data |= (1 << bit);
 762                         break;
 763                 case PIN_CONFIG_BIAS_PULL_DOWN:
 764                         data |= (2 << bit);
 765                         break;
 766                 case PIN_CONFIG_BIAS_BUS_HOLD:
 767                         data |= (3 << bit);
 768                         break;
 769                 default:
 770                         spin_unlock_irqrestore(&bank->slock, flags);
 771                         dev_err(info->dev, "unsupported pull setting %d\n",
 772                                 pull);
 773                         return -EINVAL;
 774                 }
 775
 776                 ret = regmap_update_bits(regmap, reg, rmask, data);
 777
 778                 spin_unlock_irqrestore(&bank->slock, flags);
 779                 break;
 780         default:
 781                 dev_err(info->dev, "unsupported pinctrl type\n");
 782                 return -EINVAL;
 783         }
 784
 785         return ret;
 786 }
 787
 788 /*
 789  * Pinmux_ops handling
 790  */
 791
 792 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 793 {
 794         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 795
 796         return info->nfunctions;
 797 }
 798
 799 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
 800                                           unsigned selector)
 801 {
 802         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 803
 804         return info->functions[selector].name;
 805 }
 806
 807 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
 808                                 unsigned selector, const char * const **groups,
 809                                 unsigned * const num_groups)
 810 {
 811         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 812
 813         *groups = info->functions[selector].groups;
 814         *num_groups = info->functions[selector].ngroups;
 815
 816         return 0;
 817 }
 818
 819 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 820                             unsigned group)
 821 {
 822         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 823         const unsigned int *pins = info->groups[group].pins;
 824         const struct rockchip_pin_config *data = info->groups[group].data;
 825         struct rockchip_pin_bank *bank;
 826         int cnt, ret = 0;
 827
 828         dev_dbg(info->dev, "enable function %s group %s\n",
 829                 info->functions[selector].name, info->groups[group].name);
 830
 831         /*
 832          * for each pin in the pin group selected, program the correspoding pin
 833          * pin function number in the config register.
 834          */
 835         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 836                 bank = pin_to_bank(info, pins[cnt]);
 837                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
 838                                        data[cnt].func);
 839                 if (ret)
 840                         break;
 841         }
 842
 843         if (ret) {
 844                 /* revert the already done pin settings */
 845                 for (cnt--; cnt >= 0; cnt--)
 846                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 847
 848                 return ret;
 849         }
 850
 851         return 0;
 852 }
 853
 854 /*
 855  * The calls to gpio_direction_output() and gpio_direction_input()
 856  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
 857  * function called from the gpiolib interface).
 858  */
 859 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
 860                                             int pin, bool input)
 861 {
 862         struct rockchip_pin_bank *bank;
 863         int ret;
 864         unsigned long flags;
 865         u32 data;
 866
 867         bank = gc_to_pin_bank(chip);
 868
 869         ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
 870         if (ret < 0)
 871                 return ret;
 872
 873         spin_lock_irqsave(&bank->slock, flags);
 874
 875         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
 876         /* set bit to 1 for output, 0 for input */
 877         if (!input)
 878                 data |= BIT(pin);
 879         else
 880                 data &= ~BIT(pin);
 881         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
 882
 883         spin_unlock_irqrestore(&bank->slock, flags);
 884
 885         return 0;
 886 }
 887
 888 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 889                                               struct pinctrl_gpio_range *range,
 890                                               unsigned offset, bool input)
 891 {
 892         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 893         struct gpio_chip *chip;
 894         int pin;
 895
 896         chip = range->gc;
 897         pin = offset - chip->base;
 898         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
 899                  offset, range->name, pin, input ? "input" : "output");
 900
 901         return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
 902                                                 input);
 903 }
 904
 905 static const struct pinmux_ops rockchip_pmx_ops = {
 906         .get_functions_count    = rockchip_pmx_get_funcs_count,
 907         .get_function_name      = rockchip_pmx_get_func_name,
 908         .get_function_groups    = rockchip_pmx_get_groups,
 909         .set_mux                = rockchip_pmx_set,
 910         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
 911 };
 912
 913 /*
 914  * Pinconf_ops handling
 915  */
 916
 917 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 918                                         enum pin_config_param pull)
 919 {
 920         switch (ctrl->type) {
 921         case RK2928:
 922                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
 923                                         pull == PIN_CONFIG_BIAS_DISABLE);
 924         case RK3066B:
 925                 return pull ? false : true;
 926         case RK3188:
 927         case RK3288:
 928                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
 929         }
 930
 931         return false;
 932 }
 933
 934 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
 935 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
 936
 937 /* set the pin config settings for a specified pin */
 938 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 939                                 unsigned long *configs, unsigned num_configs)
 940 {
 941         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 942         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 943         enum pin_config_param param;
 944         u16 arg;
 945         int i;
 946         int rc;
 947
 948         for (i = 0; i < num_configs; i++) {
 949                 param = pinconf_to_config_param(configs[i]);
 950                 arg = pinconf_to_config_argument(configs[i]);
 951
 952                 switch (param) {
 953                 case PIN_CONFIG_BIAS_DISABLE:
 954                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
 955                                 param);
 956                         if (rc)
 957                                 return rc;
 958                         break;
 959                 case PIN_CONFIG_BIAS_PULL_UP:
 960                 case PIN_CONFIG_BIAS_PULL_DOWN:
 961                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 962                 case PIN_CONFIG_BIAS_BUS_HOLD:
 963                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 964                                 return -ENOTSUPP;
 965
 966                         if (!arg)
 967                                 return -EINVAL;
 968
 969                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
 970                                 param);
 971                         if (rc)
 972                                 return rc;
 973                         break;
 974                 case PIN_CONFIG_OUTPUT:
 975                         rockchip_gpio_set(&bank->gpio_chip,
 976                                           pin - bank->pin_base, arg);
 977                         rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
 978                                           pin - bank->pin_base, false);
 979                         if (rc)
 980                                 return rc;
 981                         break;
 982                 case PIN_CONFIG_DRIVE_STRENGTH:
 983                         /* rk3288 is the first with per-pin drive-strength */
 984                         if (info->ctrl->type != RK3288)
 985                                 return -ENOTSUPP;
 986
 987                         rc = rk3288_set_drive(bank, pin - bank->pin_base, arg);
 988                         if (rc < 0)
 989                                 return rc;
 990                         break;
 991                 default:
 992                         return -ENOTSUPP;
 993                         break;
 994                 }
 995         } /* for each config */
 996
 997         return 0;
 998 }
 999
1000 /* get the pin config settings for a specified pin */
1001 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1002                                                         unsigned long *config)
1003 {
1004         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1005         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1006         enum pin_config_param param = pinconf_to_config_param(*config);
1007         u16 arg;
1008         int rc;
1009
1010         switch (param) {
1011         case PIN_CONFIG_BIAS_DISABLE:
1012                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1013                         return -EINVAL;
1014
1015                 arg = 0;
1016                 break;
1017         case PIN_CONFIG_BIAS_PULL_UP:
1018         case PIN_CONFIG_BIAS_PULL_DOWN:
1019         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1020         case PIN_CONFIG_BIAS_BUS_HOLD:
1021                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1022                         return -ENOTSUPP;
1023
1024                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1025                         return -EINVAL;
1026
1027                 arg = 1;
1028                 break;
1029         case PIN_CONFIG_OUTPUT:
1030                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1031                 if (rc != RK_FUNC_GPIO)
1032                         return -EINVAL;
1033
1034                 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1035                 if (rc < 0)
1036                         return rc;
1037
1038                 arg = rc ? 1 : 0;
1039                 break;
1040         case PIN_CONFIG_DRIVE_STRENGTH:
1041                 /* rk3288 is the first with per-pin drive-strength */
1042                 if (info->ctrl->type != RK3288)
1043                         return -ENOTSUPP;
1044
1045                 rc = rk3288_get_drive(bank, pin - bank->pin_base);
1046                 if (rc < 0)
1047                         return rc;
1048
1049                 arg = rc;
1050                 break;
1051         default:
1052                 return -ENOTSUPP;
1053                 break;
1054         }
1055
1056         *config = pinconf_to_config_packed(param, arg);
1057
1058         return 0;
1059 }
1060
1061 static const struct pinconf_ops rockchip_pinconf_ops = {
1062         .pin_config_get                 = rockchip_pinconf_get,
1063         .pin_config_set                 = rockchip_pinconf_set,
1064         .is_generic                     = true,
1065 };
1066
1067 static const struct of_device_id rockchip_bank_match[] = {
1068         { .compatible = "rockchip,gpio-bank" },
1069         { .compatible = "rockchip,rk3188-gpio-bank0" },
1070         {},
1071 };
1072
1073 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1074                                                 struct device_node *np)
1075 {
1076         struct device_node *child;
1077
1078         for_each_child_of_node(np, child) {
1079                 if (of_match_node(rockchip_bank_match, child))
1080                         continue;
1081
1082                 info->nfunctions++;
1083                 info->ngroups += of_get_child_count(child);
1084         }
1085 }
1086
1087 static int rockchip_pinctrl_parse_groups(struct device_node *np,
1088                                               struct rockchip_pin_group *grp,
1089                                               struct rockchip_pinctrl *info,
1090                                               u32 index)
1091 {
1092         struct rockchip_pin_bank *bank;
1093         int size;
1094         const __be32 *list;
1095         int num;
1096         int i, j;
1097         int ret;
1098
1099         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1100
1101         /* Initialise group */
1102         grp->name = np->name;
1103
1104         /*
1105          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1106          * do sanity check and calculate pins number
1107          */
1108         list = of_get_property(np, "rockchip,pins", &size);
1109         /* we do not check return since it's safe node passed down */
1110         size /= sizeof(*list);
1111         if (!size || size % 4) {
1112                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1113                 return -EINVAL;
1114         }
1115
1116         grp->npins = size / 4;
1117
1118         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1119                                                 GFP_KERNEL);
1120         grp->data = devm_kzalloc(info->dev, grp->npins *
1121                                           sizeof(struct rockchip_pin_config),
1122                                         GFP_KERNEL);
1123         if (!grp->pins || !grp->data)
1124                 return -ENOMEM;
1125
1126         for (i = 0, j = 0; i < size; i += 4, j++) {
1127                 const __be32 *phandle;
1128                 struct device_node *np_config;
1129
1130                 num = be32_to_cpu(*list++);
1131                 bank = bank_num_to_bank(info, num);
1132                 if (IS_ERR(bank))
1133                         return PTR_ERR(bank);
1134
1135                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1136                 grp->data[j].func = be32_to_cpu(*list++);
1137
1138                 phandle = list++;
1139                 if (!phandle)
1140                         return -EINVAL;
1141
1142                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
1143                 ret = pinconf_generic_parse_dt_config(np_config,
1144                                 &grp->data[j].configs, &grp->data[j].nconfigs);
1145                 if (ret)
1146                         return ret;
1147         }
1148
1149         return 0;
1150 }
1151
1152 static int rockchip_pinctrl_parse_functions(struct device_node *np,
1153                                                 struct rockchip_pinctrl *info,
1154                                                 u32 index)
1155 {
1156         struct device_node *child;
1157         struct rockchip_pmx_func *func;
1158         struct rockchip_pin_group *grp;
1159         int ret;
1160         static u32 grp_index;
1161         u32 i = 0;
1162
1163         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1164
1165         func = &info->functions[index];
1166
1167         /* Initialise function */
1168         func->name = np->name;
1169         func->ngroups = of_get_child_count(np);
1170         if (func->ngroups <= 0)
1171                 return 0;
1172
1173         func->groups = devm_kzalloc(info->dev,
1174                         func->ngroups * sizeof(char *), GFP_KERNEL);
1175         if (!func->groups)
1176                 return -ENOMEM;
1177
1178         for_each_child_of_node(np, child) {
1179                 func->groups[i] = child->name;
1180                 grp = &info->groups[grp_index++];
1181                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
1182                 if (ret)
1183                         return ret;
1184         }
1185
1186         return 0;
1187 }
1188
1189 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1190                                               struct rockchip_pinctrl *info)
1191 {
1192         struct device *dev = &pdev->dev;
1193         struct device_node *np = dev->of_node;
1194         struct device_node *child;
1195         int ret;
1196         int i;
1197
1198         rockchip_pinctrl_child_count(info, np);
1199
1200         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1201         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1202
1203         info->functions = devm_kzalloc(dev, info->nfunctions *
1204                                               sizeof(struct rockchip_pmx_func),
1205                                               GFP_KERNEL);
1206         if (!info->functions) {
1207                 dev_err(dev, "failed to allocate memory for function list\n");
1208                 return -EINVAL;
1209         }
1210
1211         info->groups = devm_kzalloc(dev, info->ngroups *
1212                                             sizeof(struct rockchip_pin_group),
1213                                             GFP_KERNEL);
1214         if (!info->groups) {
1215                 dev_err(dev, "failed allocate memory for ping group list\n");
1216                 return -EINVAL;
1217         }
1218
1219         i = 0;
1220
1221         for_each_child_of_node(np, child) {
1222                 if (of_match_node(rockchip_bank_match, child))
1223                         continue;
1224
1225                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1226                 if (ret) {
1227                         dev_err(&pdev->dev, "failed to parse function\n");
1228                         return ret;
1229                 }
1230         }
1231
1232         return 0;
1233 }
1234
1235 static int rockchip_pinctrl_register(struct platform_device *pdev,
1236                                         struct rockchip_pinctrl *info)
1237 {
1238         struct pinctrl_desc *ctrldesc = &info->pctl;
1239         struct pinctrl_pin_desc *pindesc, *pdesc;
1240         struct rockchip_pin_bank *pin_bank;
1241         int pin, bank, ret;
1242         int k;
1243
1244         ctrldesc->name = "rockchip-pinctrl";
1245         ctrldesc->owner = THIS_MODULE;
1246         ctrldesc->pctlops = &rockchip_pctrl_ops;
1247         ctrldesc->pmxops = &rockchip_pmx_ops;
1248         ctrldesc->confops = &rockchip_pinconf_ops;
1249
1250         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1251                         info->ctrl->nr_pins, GFP_KERNEL);
1252         if (!pindesc) {
1253                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1254                 return -ENOMEM;
1255         }
1256         ctrldesc->pins = pindesc;
1257         ctrldesc->npins = info->ctrl->nr_pins;
1258
1259         pdesc = pindesc;
1260         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1261                 pin_bank = &info->ctrl->pin_banks[bank];
1262                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1263                         pdesc->number = k;
1264                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1265                                                 pin_bank->name, pin);
1266                         pdesc++;
1267                 }
1268         }
1269
1270         ret = rockchip_pinctrl_parse_dt(pdev, info);
1271         if (ret)
1272                 return ret;
1273
1274         info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
1275         if (!info->pctl_dev) {
1276                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1277                 return -EINVAL;
1278         }
1279
1280         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1281                 pin_bank = &info->ctrl->pin_banks[bank];
1282                 pin_bank->grange.name = pin_bank->name;
1283                 pin_bank->grange.id = bank;
1284                 pin_bank->grange.pin_base = pin_bank->pin_base;
1285                 pin_bank->grange.base = pin_bank->gpio_chip.base;
1286                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1287                 pin_bank->grange.gc = &pin_bank->gpio_chip;
1288                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1289         }
1290
1291         return 0;
1292 }
1293
1294 /*
1295  * GPIO handling
1296  */
1297
1298 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
1299 {
1300         return pinctrl_request_gpio(chip->base + offset);
1301 }
1302
1303 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
1304 {
1305         pinctrl_free_gpio(chip->base + offset);
1306 }
1307
1308 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1309 {
1310         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1311         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1312         unsigned long flags;
1313         u32 data;
1314
1315         spin_lock_irqsave(&bank->slock, flags);
1316
1317         data = readl(reg);
1318         data &= ~BIT(offset);
1319         if (value)
1320                 data |= BIT(offset);
1321         writel(data, reg);
1322
1323         spin_unlock_irqrestore(&bank->slock, flags);
1324 }
1325
1326 /*
1327  * Returns the level of the pin for input direction and setting of the DR
1328  * register for output gpios.
1329  */
1330 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1331 {
1332         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1333         u32 data;
1334
1335         data = readl(bank->reg_base + GPIO_EXT_PORT);
1336         data >>= offset;
1337         data &= 1;
1338         return data;
1339 }
1340
1341 /*
1342  * gpiolib gpio_direction_input callback function. The setting of the pin
1343  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1344  * interface.
1345  */
1346 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1347 {
1348         return pinctrl_gpio_direction_input(gc->base + offset);
1349 }
1350
1351 /*
1352  * gpiolib gpio_direction_output callback function. The setting of the pin
1353  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1354  * interface.
1355  */
1356 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1357                                           unsigned offset, int value)
1358 {
1359         rockchip_gpio_set(gc, offset, value);
1360         return pinctrl_gpio_direction_output(gc->base + offset);
1361 }
1362
1363 /*
1364  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1365  * and a virtual IRQ, if not already present.
1366  */
1367 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1368 {
1369         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1370         unsigned int virq;
1371
1372         if (!bank->domain)
1373                 return -ENXIO;
1374
1375         virq = irq_create_mapping(bank->domain, offset);
1376
1377         return (virq) ? : -ENXIO;
1378 }
1379
1380 static const struct gpio_chip rockchip_gpiolib_chip = {
1381         .request = rockchip_gpio_request,
1382         .free = rockchip_gpio_free,
1383         .set = rockchip_gpio_set,
1384         .get = rockchip_gpio_get,
1385         .direction_input = rockchip_gpio_direction_input,
1386         .direction_output = rockchip_gpio_direction_output,
1387         .to_irq = rockchip_gpio_to_irq,
1388         .owner = THIS_MODULE,
1389 };
1390
1391 /*
1392  * Interrupt handling
1393  */
1394
1395 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1396 {
1397         struct irq_chip *chip = irq_get_chip(irq);
1398         struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
1399         u32 polarity = 0, data = 0;
1400         u32 pend;
1401         bool edge_changed = false;
1402         unsigned long flags;
1403
1404         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1405
1406         chained_irq_enter(chip, desc);
1407
1408         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1409
1410         if (bank->toggle_edge_mode) {
1411                 polarity = readl_relaxed(bank->reg_base +
1412                                          GPIO_INT_POLARITY);
1413                 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1414         }
1415
1416         while (pend) {
1417                 unsigned int virq;
1418
1419                 irq = __ffs(pend);
1420                 pend &= ~BIT(irq);
1421                 virq = irq_linear_revmap(bank->domain, irq);
1422
1423                 if (!virq) {
1424                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1425                         continue;
1426                 }
1427
1428                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1429
1430                 /*
1431                  * Triggering IRQ on both rising and falling edge
1432                  * needs manual intervention.
1433                  */
1434                 if (bank->toggle_edge_mode & BIT(irq)) {
1435                         if (data & BIT(irq))
1436                                 polarity &= ~BIT(irq);
1437                         else
1438                                 polarity |= BIT(irq);
1439
1440                         edge_changed = true;
1441                 }
1442
1443                 generic_handle_irq(virq);
1444         }
1445
1446         if (bank->toggle_edge_mode && edge_changed) {
1447                 /* Interrupt params should only be set with ints disabled */
1448                 spin_lock_irqsave(&bank->slock, flags);
1449
1450                 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
1451                 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
1452                 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
1453                 writel(data, bank->reg_base + GPIO_INTEN);
1454
1455                 spin_unlock_irqrestore(&bank->slock, flags);
1456         }
1457
1458         chained_irq_exit(chip, desc);
1459 }
1460
1461 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1462 {
1463         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1464         struct rockchip_pin_bank *bank = gc->private;
1465         u32 mask = BIT(d->hwirq);
1466         u32 polarity;
1467         u32 level;
1468         u32 data;
1469         unsigned long flags;
1470         int ret;
1471
1472         /* make sure the pin is configured as gpio input */
1473         ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1474         if (ret < 0)
1475                 return ret;
1476
1477         spin_lock_irqsave(&bank->slock, flags);
1478
1479         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1480         data &= ~mask;
1481         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1482
1483         spin_unlock_irqrestore(&bank->slock, flags);
1484
1485         if (type & IRQ_TYPE_EDGE_BOTH)
1486                 __irq_set_handler_locked(d->irq, handle_edge_irq);
1487         else
1488                 __irq_set_handler_locked(d->irq, handle_level_irq);
1489
1490         spin_lock_irqsave(&bank->slock, flags);
1491         irq_gc_lock(gc);
1492
1493         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1494         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1495
1496         switch (type) {
1497         case IRQ_TYPE_EDGE_BOTH:
1498                 bank->toggle_edge_mode |= mask;
1499                 level |= mask;
1500
1501                 /*
1502                  * Determine gpio state. If 1 next interrupt should be falling
1503                  * otherwise rising.
1504                  */
1505                 data = readl(bank->reg_base + GPIO_EXT_PORT);
1506                 if (data & mask)
1507                         polarity &= ~mask;
1508                 else
1509                         polarity |= mask;
1510                 break;
1511         case IRQ_TYPE_EDGE_RISING:
1512                 bank->toggle_edge_mode &= ~mask;
1513                 level |= mask;
1514                 polarity |= mask;
1515                 break;
1516         case IRQ_TYPE_EDGE_FALLING:
1517                 bank->toggle_edge_mode &= ~mask;
1518                 level |= mask;
1519                 polarity &= ~mask;
1520                 break;
1521         case IRQ_TYPE_LEVEL_HIGH:
1522                 bank->toggle_edge_mode &= ~mask;
1523                 level &= ~mask;
1524                 polarity |= mask;
1525                 break;
1526         case IRQ_TYPE_LEVEL_LOW:
1527                 bank->toggle_edge_mode &= ~mask;
1528                 level &= ~mask;
1529                 polarity &= ~mask;
1530                 break;
1531         default:
1532                 irq_gc_unlock(gc);
1533                 spin_unlock_irqrestore(&bank->slock, flags);
1534                 return -EINVAL;
1535         }
1536
1537         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1538         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1539
1540         irq_gc_unlock(gc);
1541         spin_unlock_irqrestore(&bank->slock, flags);
1542
1543         return 0;
1544 }
1545
1546 static int rockchip_interrupts_register(struct platform_device *pdev,
1547                                                 struct rockchip_pinctrl *info)
1548 {
1549         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1550         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1551         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1552         struct irq_chip_generic *gc;
1553         int ret;
1554         int i;
1555
1556         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1557                 if (!bank->valid) {
1558                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1559                                  bank->name);
1560                         continue;
1561                 }
1562
1563                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1564                                                 &irq_generic_chip_ops, NULL);
1565                 if (!bank->domain) {
1566                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1567                                  bank->name);
1568                         continue;
1569                 }
1570
1571                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1572                                          "rockchip_gpio_irq", handle_level_irq,
1573                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
1574                 if (ret) {
1575                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1576                                 bank->name);
1577                         irq_domain_remove(bank->domain);
1578                         continue;
1579                 }
1580
1581                 gc = irq_get_domain_generic_chip(bank->domain, 0);
1582                 gc->reg_base = bank->reg_base;
1583                 gc->private = bank;
1584                 gc->chip_types[0].regs.mask = GPIO_INTEN;
1585                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1586                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1587                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1588                 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1589                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1590                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1591                 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
1592
1593                 irq_set_handler_data(bank->irq, bank);
1594                 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1595         }
1596
1597         return 0;
1598 }
1599
1600 static int rockchip_gpiolib_register(struct platform_device *pdev,
1601                                                 struct rockchip_pinctrl *info)
1602 {
1603         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1604         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1605         struct gpio_chip *gc;
1606         int ret;
1607         int i;
1608
1609         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1610                 if (!bank->valid) {
1611                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1612                                  bank->name);
1613                         continue;
1614                 }
1615
1616                 bank->gpio_chip = rockchip_gpiolib_chip;
1617
1618                 gc = &bank->gpio_chip;
1619                 gc->base = bank->pin_base;
1620                 gc->ngpio = bank->nr_pins;
1621                 gc->dev = &pdev->dev;
1622                 gc->of_node = bank->of_node;
1623                 gc->label = bank->name;
1624
1625                 ret = gpiochip_add(gc);
1626                 if (ret) {
1627                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1628                                                         gc->label, ret);
1629                         goto fail;
1630                 }
1631         }
1632
1633         rockchip_interrupts_register(pdev, info);
1634
1635         return 0;
1636
1637 fail:
1638         for (--i, --bank; i >= 0; --i, --bank) {
1639                 if (!bank->valid)
1640                         continue;
1641                 gpiochip_remove(&bank->gpio_chip);
1642         }
1643         return ret;
1644 }
1645
1646 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1647                                                 struct rockchip_pinctrl *info)
1648 {
1649         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1650         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1651         int i;
1652
1653         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1654                 if (!bank->valid)
1655                         continue;
1656                 gpiochip_remove(&bank->gpio_chip);
1657         }
1658
1659         return 0;
1660 }
1661
1662 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1663                                   struct rockchip_pinctrl *info)
1664 {
1665         struct resource res;
1666         void __iomem *base;
1667
1668         if (of_address_to_resource(bank->of_node, 0, &res)) {
1669                 dev_err(info->dev, "cannot find IO resource for bank\n");
1670                 return -ENOENT;
1671         }
1672
1673         bank->reg_base = devm_ioremap_resource(info->dev, &res);
1674         if (IS_ERR(bank->reg_base))
1675                 return PTR_ERR(bank->reg_base);
1676
1677         /*
1678          * special case, where parts of the pull setting-registers are
1679          * part of the PMU register space
1680          */
1681         if (of_device_is_compatible(bank->of_node,
1682                                     "rockchip,rk3188-gpio-bank0")) {
1683                 struct device_node *node;
1684
1685                 node = of_parse_phandle(bank->of_node->parent,
1686                                         "rockchip,pmu", 0);
1687                 if (!node) {
1688                         if (of_address_to_resource(bank->of_node, 1, &res)) {
1689                                 dev_err(info->dev, "cannot find IO resource for bank\n");
1690                                 return -ENOENT;
1691                         }
1692
1693                         base = devm_ioremap_resource(info->dev, &res);
1694                         if (IS_ERR(base))
1695                                 return PTR_ERR(base);
1696                         rockchip_regmap_config.max_register =
1697                                                     resource_size(&res) - 4;
1698                         rockchip_regmap_config.name =
1699                                             "rockchip,rk3188-gpio-bank0-pull";
1700                         bank->regmap_pull = devm_regmap_init_mmio(info->dev,
1701                                                     base,
1702                                                     &rockchip_regmap_config);
1703                 }
1704         }
1705
1706         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1707
1708         bank->clk = of_clk_get(bank->of_node, 0);
1709         if (IS_ERR(bank->clk))
1710                 return PTR_ERR(bank->clk);
1711
1712         return clk_prepare_enable(bank->clk);
1713 }
1714
1715 static const struct of_device_id rockchip_pinctrl_dt_match[];
1716
1717 /* retrieve the soc specific data */
1718 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1719                                                 struct rockchip_pinctrl *d,
1720                                                 struct platform_device *pdev)
1721 {
1722         const struct of_device_id *match;
1723         struct device_node *node = pdev->dev.of_node;
1724         struct device_node *np;
1725         struct rockchip_pin_ctrl *ctrl;
1726         struct rockchip_pin_bank *bank;
1727         int grf_offs, pmu_offs, i, j;
1728
1729         match = of_match_node(rockchip_pinctrl_dt_match, node);
1730         ctrl = (struct rockchip_pin_ctrl *)match->data;
1731
1732         for_each_child_of_node(node, np) {
1733                 if (!of_find_property(np, "gpio-controller", NULL))
1734                         continue;
1735
1736                 bank = ctrl->pin_banks;
1737                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1738                         if (!strcmp(bank->name, np->name)) {
1739                                 bank->of_node = np;
1740
1741                                 if (!rockchip_get_bank_data(bank, d))
1742                                         bank->valid = true;
1743
1744                                 break;
1745                         }
1746                 }
1747         }
1748
1749         grf_offs = ctrl->grf_mux_offset;
1750         pmu_offs = ctrl->pmu_mux_offset;
1751         bank = ctrl->pin_banks;
1752         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1753                 int bank_pins = 0;
1754
1755                 spin_lock_init(&bank->slock);
1756                 bank->drvdata = d;
1757                 bank->pin_base = ctrl->nr_pins;
1758                 ctrl->nr_pins += bank->nr_pins;
1759
1760                 /* calculate iomux offsets */
1761                 for (j = 0; j < 4; j++) {
1762                         struct rockchip_iomux *iom = &bank->iomux[j];
1763                         int inc;
1764
1765                         if (bank_pins >= bank->nr_pins)
1766                                 break;
1767
1768                         /* preset offset value, set new start value */
1769                         if (iom->offset >= 0) {
1770                                 if (iom->type & IOMUX_SOURCE_PMU)
1771                                         pmu_offs = iom->offset;
1772                                 else
1773                                         grf_offs = iom->offset;
1774                         } else { /* set current offset */
1775                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
1776                                                         pmu_offs : grf_offs;
1777                         }
1778
1779                         dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n",
1780                                  i, j, iom->offset);
1781
1782                         /*
1783                          * Increase offset according to iomux width.
1784                          * 4bit iomux'es are spread over two registers.
1785                          */
1786                         inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
1787                         if (iom->type & IOMUX_SOURCE_PMU)
1788                                 pmu_offs += inc;
1789                         else
1790                                 grf_offs += inc;
1791
1792                         bank_pins += 8;
1793                 }
1794         }
1795
1796         return ctrl;
1797 }
1798
1799 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1800 {
1801         struct rockchip_pinctrl *info;
1802         struct device *dev = &pdev->dev;
1803         struct rockchip_pin_ctrl *ctrl;
1804         struct device_node *np = pdev->dev.of_node, *node;
1805         struct resource *res;
1806         void __iomem *base;
1807         int ret;
1808
1809         if (!dev->of_node) {
1810                 dev_err(dev, "device tree node not found\n");
1811                 return -ENODEV;
1812         }
1813
1814         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1815         if (!info)
1816                 return -ENOMEM;
1817
1818         info->dev = dev;
1819
1820         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1821         if (!ctrl) {
1822                 dev_err(dev, "driver data not available\n");
1823                 return -EINVAL;
1824         }
1825         info->ctrl = ctrl;
1826
1827         node = of_parse_phandle(np, "rockchip,grf", 0);
1828         if (node) {
1829                 info->regmap_base = syscon_node_to_regmap(node);
1830                 if (IS_ERR(info->regmap_base))
1831                         return PTR_ERR(info->regmap_base);
1832         } else {
1833                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1834                 base = devm_ioremap_resource(&pdev->dev, res);
1835                 if (IS_ERR(base))
1836                         return PTR_ERR(base);
1837
1838                 rockchip_regmap_config.max_register = resource_size(res) - 4;
1839                 rockchip_regmap_config.name = "rockchip,pinctrl";
1840                 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
1841                                                     &rockchip_regmap_config);
1842
1843                 /* to check for the old dt-bindings */
1844                 info->reg_size = resource_size(res);
1845
1846                 /* Honor the old binding, with pull registers as 2nd resource */
1847                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
1848                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1849                         base = devm_ioremap_resource(&pdev->dev, res);
1850                         if (IS_ERR(base))
1851                                 return PTR_ERR(base);
1852
1853                         rockchip_regmap_config.max_register =
1854                                                         resource_size(res) - 4;
1855                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
1856                         info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
1857                                                     base,
1858                                                     &rockchip_regmap_config);
1859                 }
1860         }
1861
1862         /* try to find the optional reference to the pmu syscon */
1863         node = of_parse_phandle(np, "rockchip,pmu", 0);
1864         if (node) {
1865                 info->regmap_pmu = syscon_node_to_regmap(node);
1866                 if (IS_ERR(info->regmap_pmu))
1867                         return PTR_ERR(info->regmap_pmu);
1868         }
1869
1870         ret = rockchip_gpiolib_register(pdev, info);
1871         if (ret)
1872                 return ret;
1873
1874         ret = rockchip_pinctrl_register(pdev, info);
1875         if (ret) {
1876                 rockchip_gpiolib_unregister(pdev, info);
1877                 return ret;
1878         }
1879
1880         platform_set_drvdata(pdev, info);
1881
1882         return 0;
1883 }
1884
1885 static struct rockchip_pin_bank rk2928_pin_banks[] = {
1886         PIN_BANK(0, 32, "gpio0"),
1887         PIN_BANK(1, 32, "gpio1"),
1888         PIN_BANK(2, 32, "gpio2"),
1889         PIN_BANK(3, 32, "gpio3"),
1890 };
1891
1892 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1893                 .pin_banks              = rk2928_pin_banks,
1894                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
1895                 .label                  = "RK2928-GPIO",
1896                 .type                   = RK2928,
1897                 .grf_mux_offset         = 0xa8,
1898                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
1899 };
1900
1901 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1902         PIN_BANK(0, 32, "gpio0"),
1903         PIN_BANK(1, 32, "gpio1"),
1904         PIN_BANK(2, 32, "gpio2"),
1905         PIN_BANK(3, 32, "gpio3"),
1906         PIN_BANK(4, 32, "gpio4"),
1907         PIN_BANK(6, 16, "gpio6"),
1908 };
1909
1910 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1911                 .pin_banks              = rk3066a_pin_banks,
1912                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
1913                 .label                  = "RK3066a-GPIO",
1914                 .type                   = RK2928,
1915                 .grf_mux_offset         = 0xa8,
1916                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
1917 };
1918
1919 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1920         PIN_BANK(0, 32, "gpio0"),
1921         PIN_BANK(1, 32, "gpio1"),
1922         PIN_BANK(2, 32, "gpio2"),
1923         PIN_BANK(3, 32, "gpio3"),
1924 };
1925
1926 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1927                 .pin_banks      = rk3066b_pin_banks,
1928                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
1929                 .label          = "RK3066b-GPIO",
1930                 .type           = RK3066B,
1931                 .grf_mux_offset = 0x60,
1932 };
1933
1934 static struct rockchip_pin_bank rk3188_pin_banks[] = {
1935         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
1936         PIN_BANK(1, 32, "gpio1"),
1937         PIN_BANK(2, 32, "gpio2"),
1938         PIN_BANK(3, 32, "gpio3"),
1939 };
1940
1941 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1942                 .pin_banks              = rk3188_pin_banks,
1943                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
1944                 .label                  = "RK3188-GPIO",
1945                 .type                   = RK3188,
1946                 .grf_mux_offset         = 0x60,
1947                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
1948 };
1949
1950 static struct rockchip_pin_bank rk3288_pin_banks[] = {
1951         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
1952                                              IOMUX_SOURCE_PMU,
1953                                              IOMUX_SOURCE_PMU,
1954                                              IOMUX_UNROUTED
1955                             ),
1956         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
1957                                              IOMUX_UNROUTED,
1958                                              IOMUX_UNROUTED,
1959                                              0
1960                             ),
1961         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
1962         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
1963         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
1964                                              IOMUX_WIDTH_4BIT,
1965                                              0,
1966                                              0
1967                             ),
1968         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
1969                                              0,
1970                                              0,
1971                                              IOMUX_UNROUTED
1972                             ),
1973         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
1974         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
1975                                              0,
1976                                              IOMUX_WIDTH_4BIT,
1977                                              IOMUX_UNROUTED
1978                             ),
1979         PIN_BANK(8, 16, "gpio8"),
1980 };
1981
1982 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
1983                 .pin_banks              = rk3288_pin_banks,
1984                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
1985                 .label                  = "RK3288-GPIO",
1986                 .type                   = RK3288,
1987                 .grf_mux_offset         = 0x0,
1988                 .pmu_mux_offset         = 0x84,
1989                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
1990 };
1991
1992 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1993         { .compatible = "rockchip,rk2928-pinctrl",
1994                 .data = (void *)&rk2928_pin_ctrl },
1995         { .compatible = "rockchip,rk3066a-pinctrl",
1996                 .data = (void *)&rk3066a_pin_ctrl },
1997         { .compatible = "rockchip,rk3066b-pinctrl",
1998                 .data = (void *)&rk3066b_pin_ctrl },
1999         { .compatible = "rockchip,rk3188-pinctrl",
2000                 .data = (void *)&rk3188_pin_ctrl },
2001         { .compatible = "rockchip,rk3288-pinctrl",
2002                 .data = (void *)&rk3288_pin_ctrl },
2003         {},
2004 };
2005 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
2006
2007 static struct platform_driver rockchip_pinctrl_driver = {
2008         .probe          = rockchip_pinctrl_probe,
2009         .driver = {
2010                 .name   = "rockchip-pinctrl",
2011                 .owner  = THIS_MODULE,
2012                 .of_match_table = rockchip_pinctrl_dt_match,
2013         },
2014 };
2015
2016 static int __init rockchip_pinctrl_drv_register(void)
2017 {
2018         return platform_driver_register(&rockchip_pinctrl_driver);
2019 }
2020 postcore_initcall(rockchip_pinctrl_drv_register);
2021
2022 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
2023 MODULE_DESCRIPTION("Rockchip pinctrl driver");
2024 MODULE_LICENSE("GPL v2");