drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/pinctrl/machine.h>
  34 #include <linux/pinctrl/pinconf.h>
  35 #include <linux/pinctrl/pinctrl.h>
  36 #include <linux/pinctrl/pinmux.h>
  37 #include <linux/pinctrl/pinconf-generic.h>
  38 #include <linux/irqchip/chained_irq.h>
  39 #include <linux/clk.h>
  40 #include <linux/regmap.h>
  41 #include <linux/mfd/syscon.h>
  42 #include <dt-bindings/pinctrl/rockchip.h>
  43
  44 #include "core.h"
  45 #include "pinconf.h"
  46
  47 /* GPIO control registers */
  48 #define GPIO_SWPORT_DR          0x00
  49 #define GPIO_SWPORT_DDR         0x04
  50 #define GPIO_INTEN              0x30
  51 #define GPIO_INTMASK            0x34
  52 #define GPIO_INTTYPE_LEVEL      0x38
  53 #define GPIO_INT_POLARITY       0x3c
  54 #define GPIO_INT_STATUS         0x40
  55 #define GPIO_INT_RAWSTATUS      0x44
  56 #define GPIO_DEBOUNCE           0x48
  57 #define GPIO_PORTS_EOI          0x4c
  58 #define GPIO_EXT_PORT           0x50
  59 #define GPIO_LS_SYNC            0x60
  60
  61 enum rockchip_pinctrl_type {
  62         RK2928,
  63         RK3066B,
  64         RK3188,
  65         RK3288,
  66 };
  67
  68 /**
  69  * Encode variants of iomux registers into a type variable
  70  */
  71 #define IOMUX_GPIO_ONLY         BIT(0)
  72 #define IOMUX_WIDTH_4BIT        BIT(1)
  73 #define IOMUX_SOURCE_PMU        BIT(2)
  74 #define IOMUX_UNROUTED          BIT(3)
  75
  76 /**
  77  * @type: iomux variant using IOMUX_* constants
  78  * @offset: if initialized to -1 it will be autocalculated, by specifying
  79  *          an initial offset value the relevant source offset can be reset
  80  *          to a new value for autocalculating the following iomux registers.
  81  */
  82 struct rockchip_iomux {
  83         int                             type;
  84         int                             offset;
  85 };
  86
  87 /**
  88  * @reg_base: register base of the gpio bank
  89  * @reg_pull: optional separate register for additional pull settings
  90  * @clk: clock of the gpio bank
  91  * @irq: interrupt of the gpio bank
  92  * @pin_base: first pin number
  93  * @nr_pins: number of pins in this bank
  94  * @name: name of the bank
  95  * @bank_num: number of the bank, to account for holes
  96  * @iomux: array describing the 4 iomux sources of the bank
  97  * @valid: are all necessary informations present
  98  * @of_node: dt node of this bank
  99  * @drvdata: common pinctrl basedata
 100  * @domain: irqdomain of the gpio bank
 101  * @gpio_chip: gpiolib chip
 102  * @grange: gpio range
 103  * @slock: spinlock for the gpio bank
 104  */
 105 struct rockchip_pin_bank {
 106         void __iomem                    *reg_base;
 107         struct regmap                   *regmap_pull;
 108         struct clk                      *clk;
 109         int                             irq;
 110         u32                             pin_base;
 111         u8                              nr_pins;
 112         char                            *name;
 113         u8                              bank_num;
 114         struct rockchip_iomux           iomux[4];
 115         bool                            valid;
 116         struct device_node              *of_node;
 117         struct rockchip_pinctrl         *drvdata;
 118         struct irq_domain               *domain;
 119         struct gpio_chip                gpio_chip;
 120         struct pinctrl_gpio_range       grange;
 121         spinlock_t                      slock;
 122         u32                             toggle_edge_mode;
 123 };
 124
 125 #define PIN_BANK(id, pins, label)                       \
 126         {                                               \
 127                 .bank_num       = id,                   \
 128                 .nr_pins        = pins,                 \
 129                 .name           = label,                \
 130                 .iomux          = {                     \
 131                         { .offset = -1 },               \
 132                         { .offset = -1 },               \
 133                         { .offset = -1 },               \
 134                         { .offset = -1 },               \
 135                 },                                      \
 136         }
 137
 138 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
 139         {                                                               \
 140                 .bank_num       = id,                                   \
 141                 .nr_pins        = pins,                                 \
 142                 .name           = label,                                \
 143                 .iomux          = {                                     \
 144                         { .type = iom0, .offset = -1 },                 \
 145                         { .type = iom1, .offset = -1 },                 \
 146                         { .type = iom2, .offset = -1 },                 \
 147                         { .type = iom3, .offset = -1 },                 \
 148                 },                                                      \
 149         }
 150
 151 /**
 152  */
 153 struct rockchip_pin_ctrl {
 154         struct rockchip_pin_bank        *pin_banks;
 155         u32                             nr_banks;
 156         u32                             nr_pins;
 157         char                            *label;
 158         enum rockchip_pinctrl_type      type;
 159         int                             grf_mux_offset;
 160         int                             pmu_mux_offset;
 161         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
 162                                     int pin_num, struct regmap **regmap,
 163                                     int *reg, u8 *bit);
 164 };
 165
 166 struct rockchip_pin_config {
 167         unsigned int            func;
 168         unsigned long           *configs;
 169         unsigned int            nconfigs;
 170 };
 171
 172 /**
 173  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 174  * @name: name of the pin group, used to lookup the group.
 175  * @pins: the pins included in this group.
 176  * @npins: number of pins included in this group.
 177  * @func: the mux function number to be programmed when selected.
 178  * @configs: the config values to be set for each pin
 179  * @nconfigs: number of configs for each pin
 180  */
 181 struct rockchip_pin_group {
 182         const char                      *name;
 183         unsigned int                    npins;
 184         unsigned int                    *pins;
 185         struct rockchip_pin_config      *data;
 186 };
 187
 188 /**
 189  * struct rockchip_pmx_func: represent a pin function.
 190  * @name: name of the pin function, used to lookup the function.
 191  * @groups: one or more names of pin groups that provide this function.
 192  * @num_groups: number of groups included in @groups.
 193  */
 194 struct rockchip_pmx_func {
 195         const char              *name;
 196         const char              **groups;
 197         u8                      ngroups;
 198 };
 199
 200 struct rockchip_pinctrl {
 201         struct regmap                   *regmap_base;
 202         int                             reg_size;
 203         struct regmap                   *regmap_pull;
 204         struct regmap                   *regmap_pmu;
 205         struct device                   *dev;
 206         struct rockchip_pin_ctrl        *ctrl;
 207         struct pinctrl_desc             pctl;
 208         struct pinctrl_dev              *pctl_dev;
 209         struct rockchip_pin_group       *groups;
 210         unsigned int                    ngroups;
 211         struct rockchip_pmx_func        *functions;
 212         unsigned int                    nfunctions;
 213 };
 214
 215 static struct regmap_config rockchip_regmap_config = {
 216         .reg_bits = 32,
 217         .val_bits = 32,
 218         .reg_stride = 4,
 219 };
 220
 221 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 222 {
 223         return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 224 }
 225
 226 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 227                                         const struct rockchip_pinctrl *info,
 228                                         const char *name)
 229 {
 230         int i;
 231
 232         for (i = 0; i < info->ngroups; i++) {
 233                 if (!strcmp(info->groups[i].name, name))
 234                         return &info->groups[i];
 235         }
 236
 237         return NULL;
 238 }
 239
 240 /*
 241  * given a pin number that is local to a pin controller, find out the pin bank
 242  * and the register base of the pin bank.
 243  */
 244 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 245                                                                 unsigned pin)
 246 {
 247         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 248
 249         while (pin >= (b->pin_base + b->nr_pins))
 250                 b++;
 251
 252         return b;
 253 }
 254
 255 static struct rockchip_pin_bank *bank_num_to_bank(
 256                                         struct rockchip_pinctrl *info,
 257                                         unsigned num)
 258 {
 259         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 260         int i;
 261
 262         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 263                 if (b->bank_num == num)
 264                         return b;
 265         }
 266
 267         return ERR_PTR(-EINVAL);
 268 }
 269
 270 /*
 271  * Pinctrl_ops handling
 272  */
 273
 274 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 275 {
 276         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 277
 278         return info->ngroups;
 279 }
 280
 281 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 282                                                         unsigned selector)
 283 {
 284         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 285
 286         return info->groups[selector].name;
 287 }
 288
 289 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 290                                       unsigned selector, const unsigned **pins,
 291                                       unsigned *npins)
 292 {
 293         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 294
 295         if (selector >= info->ngroups)
 296                 return -EINVAL;
 297
 298         *pins = info->groups[selector].pins;
 299         *npins = info->groups[selector].npins;
 300
 301         return 0;
 302 }
 303
 304 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 305                                  struct device_node *np,
 306                                  struct pinctrl_map **map, unsigned *num_maps)
 307 {
 308         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 309         const struct rockchip_pin_group *grp;
 310         struct pinctrl_map *new_map;
 311         struct device_node *parent;
 312         int map_num = 1;
 313         int i;
 314
 315         /*
 316          * first find the group of this node and check if we need to create
 317          * config maps for pins
 318          */
 319         grp = pinctrl_name_to_group(info, np->name);
 320         if (!grp) {
 321                 dev_err(info->dev, "unable to find group for node %s\n",
 322                         np->name);
 323                 return -EINVAL;
 324         }
 325
 326         map_num += grp->npins;
 327         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 328                                                                 GFP_KERNEL);
 329         if (!new_map)
 330                 return -ENOMEM;
 331
 332         *map = new_map;
 333         *num_maps = map_num;
 334
 335         /* create mux map */
 336         parent = of_get_parent(np);
 337         if (!parent) {
 338                 devm_kfree(pctldev->dev, new_map);
 339                 return -EINVAL;
 340         }
 341         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 342         new_map[0].data.mux.function = parent->name;
 343         new_map[0].data.mux.group = np->name;
 344         of_node_put(parent);
 345
 346         /* create config map */
 347         new_map++;
 348         for (i = 0; i < grp->npins; i++) {
 349                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 350                 new_map[i].data.configs.group_or_pin =
 351                                 pin_get_name(pctldev, grp->pins[i]);
 352                 new_map[i].data.configs.configs = grp->data[i].configs;
 353                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 354         }
 355
 356         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 357                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 358
 359         return 0;
 360 }
 361
 362 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 363                                     struct pinctrl_map *map, unsigned num_maps)
 364 {
 365 }
 366
 367 static const struct pinctrl_ops rockchip_pctrl_ops = {
 368         .get_groups_count       = rockchip_get_groups_count,
 369         .get_group_name         = rockchip_get_group_name,
 370         .get_group_pins         = rockchip_get_group_pins,
 371         .dt_node_to_map         = rockchip_dt_node_to_map,
 372         .dt_free_map            = rockchip_dt_free_map,
 373 };
 374
 375 /*
 376  * Hardware access
 377  */
 378
 379 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
 380 {
 381         struct rockchip_pinctrl *info = bank->drvdata;
 382         int iomux_num = (pin / 8);
 383         struct regmap *regmap;
 384         unsigned int val;
 385         int reg, ret, mask;
 386         u8 bit;
 387
 388         if (iomux_num > 3)
 389                 return -EINVAL;
 390
 391         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 392                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 393                 return -EINVAL;
 394         }
 395
 396         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 397                 return RK_FUNC_GPIO;
 398
 399         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 400                                 ? info->regmap_pmu : info->regmap_base;
 401
 402         /* get basic quadrupel of mux registers and the correct reg inside */
 403         mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
 404         reg = bank->iomux[iomux_num].offset;
 405         if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
 406                 if ((pin % 8) >= 4)
 407                         reg += 0x4;
 408                 bit = (pin % 4) * 4;
 409         } else {
 410                 bit = (pin % 8) * 2;
 411         }
 412
 413         ret = regmap_read(regmap, reg, &val);
 414         if (ret)
 415                 return ret;
 416
 417         return ((val >> bit) & mask);
 418 }
 419
 420 /*
 421  * Set a new mux function for a pin.
 422  *
 423  * The register is divided into the upper and lower 16 bit. When changing
 424  * a value, the previous register value is not read and changed. Instead
 425  * it seems the changed bits are marked in the upper 16 bit, while the
 426  * changed value gets set in the same offset in the lower 16 bit.
 427  * All pin settings seem to be 2 bit wide in both the upper and lower
 428  * parts.
 429  * @bank: pin bank to change
 430  * @pin: pin to change
 431  * @mux: new mux function to set
 432  */
 433 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 434 {
 435         struct rockchip_pinctrl *info = bank->drvdata;
 436         int iomux_num = (pin / 8);
 437         struct regmap *regmap;
 438         int reg, ret, mask;
 439         unsigned long flags;
 440         u8 bit;
 441         u32 data, rmask;
 442
 443         if (iomux_num > 3)
 444                 return -EINVAL;
 445
 446         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 447                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 448                 return -EINVAL;
 449         }
 450
 451         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
 452                 if (mux != RK_FUNC_GPIO) {
 453                         dev_err(info->dev,
 454                                 "pin %d only supports a gpio mux\n", pin);
 455                         return -ENOTSUPP;
 456                 } else {
 457                         return 0;
 458                 }
 459         }
 460
 461         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 462                                                 bank->bank_num, pin, mux);
 463
 464         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 465                                 ? info->regmap_pmu : info->regmap_base;
 466
 467         /* get basic quadrupel of mux registers and the correct reg inside */
 468         mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
 469         reg = bank->iomux[iomux_num].offset;
 470         if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
 471                 if ((pin % 8) >= 4)
 472                         reg += 0x4;
 473                 bit = (pin % 4) * 4;
 474         } else {
 475                 bit = (pin % 8) * 2;
 476         }
 477
 478         spin_lock_irqsave(&bank->slock, flags);
 479
 480         data = (mask << (bit + 16));
 481         rmask = data | (data >> 16);
 482         data |= (mux & mask) << bit;
 483         ret = regmap_update_bits(regmap, reg, rmask, data);
 484
 485         spin_unlock_irqrestore(&bank->slock, flags);
 486
 487         return ret;
 488 }
 489
 490 #define RK2928_PULL_OFFSET              0x118
 491 #define RK2928_PULL_PINS_PER_REG        16
 492 #define RK2928_PULL_BANK_STRIDE         8
 493
 494 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 495                                     int pin_num, struct regmap **regmap,
 496                                     int *reg, u8 *bit)
 497 {
 498         struct rockchip_pinctrl *info = bank->drvdata;
 499
 500         *regmap = info->regmap_base;
 501         *reg = RK2928_PULL_OFFSET;
 502         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
 503         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
 504
 505         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
 506 };
 507
 508 #define RK3188_PULL_OFFSET              0x164
 509 #define RK3188_PULL_BITS_PER_PIN        2
 510 #define RK3188_PULL_PINS_PER_REG        8
 511 #define RK3188_PULL_BANK_STRIDE         16
 512 #define RK3188_PULL_PMU_OFFSET          0x64
 513
 514 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 515                                     int pin_num, struct regmap **regmap,
 516                                     int *reg, u8 *bit)
 517 {
 518         struct rockchip_pinctrl *info = bank->drvdata;
 519
 520         /* The first 12 pins of the first bank are located elsewhere */
 521         if (bank->bank_num == 0 && pin_num < 12) {
 522                 *regmap = info->regmap_pmu ? info->regmap_pmu
 523                                            : bank->regmap_pull;
 524                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
 525                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 526                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 527                 *bit *= RK3188_PULL_BITS_PER_PIN;
 528         } else {
 529                 *regmap = info->regmap_pull ? info->regmap_pull
 530                                             : info->regmap_base;
 531                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
 532
 533                 /* correct the offset, as it is the 2nd pull register */
 534                 *reg -= 4;
 535                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 536                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 537
 538                 /*
 539                  * The bits in these registers have an inverse ordering
 540                  * with the lowest pin being in bits 15:14 and the highest
 541                  * pin in bits 1:0
 542                  */
 543                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
 544                 *bit *= RK3188_PULL_BITS_PER_PIN;
 545         }
 546 }
 547
 548 #define RK3288_PULL_OFFSET              0x140
 549 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 550                                     int pin_num, struct regmap **regmap,
 551                                     int *reg, u8 *bit)
 552 {
 553         struct rockchip_pinctrl *info = bank->drvdata;
 554
 555         /* The first 24 pins of the first bank are located in PMU */
 556         if (bank->bank_num == 0) {
 557                 *regmap = info->regmap_pmu;
 558                 *reg = RK3188_PULL_PMU_OFFSET;
 559
 560                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 561                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 562                 *bit *= RK3188_PULL_BITS_PER_PIN;
 563         } else {
 564                 *regmap = info->regmap_base;
 565                 *reg = RK3288_PULL_OFFSET;
 566
 567                 /* correct the offset, as we're starting with the 2nd bank */
 568                 *reg -= 0x10;
 569                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 570                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 571
 572                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 573                 *bit *= RK3188_PULL_BITS_PER_PIN;
 574         }
 575 }
 576
 577 #define RK3288_DRV_PMU_OFFSET           0x70
 578 #define RK3288_DRV_GRF_OFFSET           0x1c0
 579 #define RK3288_DRV_BITS_PER_PIN         2
 580 #define RK3288_DRV_PINS_PER_REG         8
 581 #define RK3288_DRV_BANK_STRIDE          16
 582 static int rk3288_drv_list[] = { 2, 4, 8, 12 };
 583
 584 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 585                                     int pin_num, struct regmap **regmap,
 586                                     int *reg, u8 *bit)
 587 {
 588         struct rockchip_pinctrl *info = bank->drvdata;
 589
 590         /* The first 24 pins of the first bank are located in PMU */
 591         if (bank->bank_num == 0) {
 592                 *regmap = info->regmap_pmu;
 593                 *reg = RK3288_DRV_PMU_OFFSET;
 594
 595                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 596                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
 597                 *bit *= RK3288_DRV_BITS_PER_PIN;
 598         } else {
 599                 *regmap = info->regmap_base;
 600                 *reg = RK3288_DRV_GRF_OFFSET;
 601
 602                 /* correct the offset, as we're starting with the 2nd bank */
 603                 *reg -= 0x10;
 604                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
 605                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 606
 607                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
 608                 *bit *= RK3288_DRV_BITS_PER_PIN;
 609         }
 610 }
 611
 612 static int rk3288_get_drive(struct rockchip_pin_bank *bank, int pin_num)
 613 {
 614         struct regmap *regmap;
 615         int reg, ret;
 616         u32 data;
 617         u8 bit;
 618
 619         rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
 620
 621         ret = regmap_read(regmap, reg, &data);
 622         if (ret)
 623                 return ret;
 624
 625         data >>= bit;
 626         data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1;
 627
 628         return rk3288_drv_list[data];
 629 }
 630
 631 static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num,
 632                             int strength)
 633 {
 634         struct rockchip_pinctrl *info = bank->drvdata;
 635         struct regmap *regmap;
 636         unsigned long flags;
 637         int reg, ret, i;
 638         u32 data, rmask;
 639         u8 bit;
 640
 641         rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
 642
 643         ret = -EINVAL;
 644         for (i = 0; i < ARRAY_SIZE(rk3288_drv_list); i++) {
 645                 if (rk3288_drv_list[i] == strength) {
 646                         ret = i;
 647                         break;
 648                 }
 649         }
 650
 651         if (ret < 0) {
 652                 dev_err(info->dev, "unsupported driver strength %d\n",
 653                         strength);
 654                 return ret;
 655         }
 656
 657         spin_lock_irqsave(&bank->slock, flags);
 658
 659         /* enable the write to the equivalent lower bits */
 660         data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16);
 661         rmask = data | (data >> 16);
 662         data |= (ret << bit);
 663
 664         ret = regmap_update_bits(regmap, reg, rmask, data);
 665         spin_unlock_irqrestore(&bank->slock, flags);
 666
 667         return ret;
 668 }
 669
 670 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 671 {
 672         struct rockchip_pinctrl *info = bank->drvdata;
 673         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 674         struct regmap *regmap;
 675         int reg, ret;
 676         u8 bit;
 677         u32 data;
 678
 679         /* rk3066b does support any pulls */
 680         if (ctrl->type == RK3066B)
 681                 return PIN_CONFIG_BIAS_DISABLE;
 682
 683         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 684
 685         ret = regmap_read(regmap, reg, &data);
 686         if (ret)
 687                 return ret;
 688
 689         switch (ctrl->type) {
 690         case RK2928:
 691                 return !(data & BIT(bit))
 692                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
 693                                 : PIN_CONFIG_BIAS_DISABLE;
 694         case RK3188:
 695         case RK3288:
 696                 data >>= bit;
 697                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
 698
 699                 switch (data) {
 700                 case 0:
 701                         return PIN_CONFIG_BIAS_DISABLE;
 702                 case 1:
 703                         return PIN_CONFIG_BIAS_PULL_UP;
 704                 case 2:
 705                         return PIN_CONFIG_BIAS_PULL_DOWN;
 706                 case 3:
 707                         return PIN_CONFIG_BIAS_BUS_HOLD;
 708                 }
 709
 710                 dev_err(info->dev, "unknown pull setting\n");
 711                 return -EIO;
 712         default:
 713                 dev_err(info->dev, "unsupported pinctrl type\n");
 714                 return -EINVAL;
 715         };
 716 }
 717
 718 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 719                                         int pin_num, int pull)
 720 {
 721         struct rockchip_pinctrl *info = bank->drvdata;
 722         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 723         struct regmap *regmap;
 724         int reg, ret;
 725         unsigned long flags;
 726         u8 bit;
 727         u32 data, rmask;
 728
 729         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
 730                  bank->bank_num, pin_num, pull);
 731
 732         /* rk3066b does support any pulls */
 733         if (ctrl->type == RK3066B)
 734                 return pull ? -EINVAL : 0;
 735
 736         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 737
 738         switch (ctrl->type) {
 739         case RK2928:
 740                 spin_lock_irqsave(&bank->slock, flags);
 741
 742                 data = BIT(bit + 16);
 743                 if (pull == PIN_CONFIG_BIAS_DISABLE)
 744                         data |= BIT(bit);
 745                 ret = regmap_write(regmap, reg, data);
 746
 747                 spin_unlock_irqrestore(&bank->slock, flags);
 748                 break;
 749         case RK3188:
 750         case RK3288:
 751                 spin_lock_irqsave(&bank->slock, flags);
 752
 753                 /* enable the write to the equivalent lower bits */
 754                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
 755                 rmask = data | (data >> 16);
 756
 757                 switch (pull) {
 758                 case PIN_CONFIG_BIAS_DISABLE:
 759                         break;
 760                 case PIN_CONFIG_BIAS_PULL_UP:
 761                         data |= (1 << bit);
 762                         break;
 763                 case PIN_CONFIG_BIAS_PULL_DOWN:
 764                         data |= (2 << bit);
 765                         break;
 766                 case PIN_CONFIG_BIAS_BUS_HOLD:
 767                         data |= (3 << bit);
 768                         break;
 769                 default:
 770                         spin_unlock_irqrestore(&bank->slock, flags);
 771                         dev_err(info->dev, "unsupported pull setting %d\n",
 772                                 pull);
 773                         return -EINVAL;
 774                 }
 775
 776                 ret = regmap_update_bits(regmap, reg, rmask, data);
 777
 778                 spin_unlock_irqrestore(&bank->slock, flags);
 779                 break;
 780         default:
 781                 dev_err(info->dev, "unsupported pinctrl type\n");
 782                 return -EINVAL;
 783         }
 784
 785         return ret;
 786 }
 787
 788 /*
 789  * Pinmux_ops handling
 790  */
 791
 792 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 793 {
 794         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 795
 796         return info->nfunctions;
 797 }
 798
 799 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
 800                                           unsigned selector)
 801 {
 802         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 803
 804         return info->functions[selector].name;
 805 }
 806
 807 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
 808                                 unsigned selector, const char * const **groups,
 809                                 unsigned * const num_groups)
 810 {
 811         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 812
 813         *groups = info->functions[selector].groups;
 814         *num_groups = info->functions[selector].ngroups;
 815
 816         return 0;
 817 }
 818
 819 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 820                             unsigned group)
 821 {
 822         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 823         const unsigned int *pins = info->groups[group].pins;
 824         const struct rockchip_pin_config *data = info->groups[group].data;
 825         struct rockchip_pin_bank *bank;
 826         int cnt, ret = 0;
 827
 828         dev_dbg(info->dev, "enable function %s group %s\n",
 829                 info->functions[selector].name, info->groups[group].name);
 830
 831         /*
 832          * for each pin in the pin group selected, program the correspoding pin
 833          * pin function number in the config register.
 834          */
 835         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 836                 bank = pin_to_bank(info, pins[cnt]);
 837                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
 838                                        data[cnt].func);
 839                 if (ret)
 840                         break;
 841         }
 842
 843         if (ret) {
 844                 /* revert the already done pin settings */
 845                 for (cnt--; cnt >= 0; cnt--)
 846                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 847
 848                 return ret;
 849         }
 850
 851         return 0;
 852 }
 853
 854 /*
 855  * The calls to gpio_direction_output() and gpio_direction_input()
 856  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
 857  * function called from the gpiolib interface).
 858  */
 859 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
 860                                             int pin, bool input)
 861 {
 862         struct rockchip_pin_bank *bank;
 863         int ret;
 864         u32 data;
 865
 866         bank = gc_to_pin_bank(chip);
 867
 868         ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
 869         if (ret < 0)
 870                 return ret;
 871
 872         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
 873         /* set bit to 1 for output, 0 for input */
 874         if (!input)
 875                 data |= BIT(pin);
 876         else
 877                 data &= ~BIT(pin);
 878         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
 879
 880         return 0;
 881 }
 882
 883 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 884                                               struct pinctrl_gpio_range *range,
 885                                               unsigned offset, bool input)
 886 {
 887         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 888         struct gpio_chip *chip;
 889         int pin;
 890
 891         chip = range->gc;
 892         pin = offset - chip->base;
 893         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
 894                  offset, range->name, pin, input ? "input" : "output");
 895
 896         return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
 897                                                 input);
 898 }
 899
 900 static const struct pinmux_ops rockchip_pmx_ops = {
 901         .get_functions_count    = rockchip_pmx_get_funcs_count,
 902         .get_function_name      = rockchip_pmx_get_func_name,
 903         .get_function_groups    = rockchip_pmx_get_groups,
 904         .set_mux                = rockchip_pmx_set,
 905         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
 906 };
 907
 908 /*
 909  * Pinconf_ops handling
 910  */
 911
 912 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 913                                         enum pin_config_param pull)
 914 {
 915         switch (ctrl->type) {
 916         case RK2928:
 917                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
 918                                         pull == PIN_CONFIG_BIAS_DISABLE);
 919         case RK3066B:
 920                 return pull ? false : true;
 921         case RK3188:
 922         case RK3288:
 923                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
 924         }
 925
 926         return false;
 927 }
 928
 929 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
 930 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
 931
 932 /* set the pin config settings for a specified pin */
 933 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 934                                 unsigned long *configs, unsigned num_configs)
 935 {
 936         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 937         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 938         enum pin_config_param param;
 939         u16 arg;
 940         int i;
 941         int rc;
 942
 943         for (i = 0; i < num_configs; i++) {
 944                 param = pinconf_to_config_param(configs[i]);
 945                 arg = pinconf_to_config_argument(configs[i]);
 946
 947                 switch (param) {
 948                 case PIN_CONFIG_BIAS_DISABLE:
 949                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
 950                                 param);
 951                         if (rc)
 952                                 return rc;
 953                         break;
 954                 case PIN_CONFIG_BIAS_PULL_UP:
 955                 case PIN_CONFIG_BIAS_PULL_DOWN:
 956                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 957                 case PIN_CONFIG_BIAS_BUS_HOLD:
 958                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 959                                 return -ENOTSUPP;
 960
 961                         if (!arg)
 962                                 return -EINVAL;
 963
 964                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
 965                                 param);
 966                         if (rc)
 967                                 return rc;
 968                         break;
 969                 case PIN_CONFIG_OUTPUT:
 970                         rockchip_gpio_set(&bank->gpio_chip,
 971                                           pin - bank->pin_base, arg);
 972                         rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
 973                                           pin - bank->pin_base, false);
 974                         if (rc)
 975                                 return rc;
 976                         break;
 977                 case PIN_CONFIG_DRIVE_STRENGTH:
 978                         /* rk3288 is the first with per-pin drive-strength */
 979                         if (info->ctrl->type != RK3288)
 980                                 return -ENOTSUPP;
 981
 982                         rc = rk3288_set_drive(bank, pin - bank->pin_base, arg);
 983                         if (rc < 0)
 984                                 return rc;
 985                         break;
 986                 default:
 987                         return -ENOTSUPP;
 988                         break;
 989                 }
 990         } /* for each config */
 991
 992         return 0;
 993 }
 994
 995 /* get the pin config settings for a specified pin */
 996 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
 997                                                         unsigned long *config)
 998 {
 999         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1000         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1001         enum pin_config_param param = pinconf_to_config_param(*config);
1002         u16 arg;
1003         int rc;
1004
1005         switch (param) {
1006         case PIN_CONFIG_BIAS_DISABLE:
1007                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1008                         return -EINVAL;
1009
1010                 arg = 0;
1011                 break;
1012         case PIN_CONFIG_BIAS_PULL_UP:
1013         case PIN_CONFIG_BIAS_PULL_DOWN:
1014         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1015         case PIN_CONFIG_BIAS_BUS_HOLD:
1016                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1017                         return -ENOTSUPP;
1018
1019                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1020                         return -EINVAL;
1021
1022                 arg = 1;
1023                 break;
1024         case PIN_CONFIG_OUTPUT:
1025                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1026                 if (rc != RK_FUNC_GPIO)
1027                         return -EINVAL;
1028
1029                 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1030                 if (rc < 0)
1031                         return rc;
1032
1033                 arg = rc ? 1 : 0;
1034                 break;
1035         case PIN_CONFIG_DRIVE_STRENGTH:
1036                 /* rk3288 is the first with per-pin drive-strength */
1037                 if (info->ctrl->type != RK3288)
1038                         return -ENOTSUPP;
1039
1040                 rc = rk3288_get_drive(bank, pin - bank->pin_base);
1041                 if (rc < 0)
1042                         return rc;
1043
1044                 arg = rc;
1045                 break;
1046         default:
1047                 return -ENOTSUPP;
1048                 break;
1049         }
1050
1051         *config = pinconf_to_config_packed(param, arg);
1052
1053         return 0;
1054 }
1055
1056 static const struct pinconf_ops rockchip_pinconf_ops = {
1057         .pin_config_get                 = rockchip_pinconf_get,
1058         .pin_config_set                 = rockchip_pinconf_set,
1059         .is_generic                     = true,
1060 };
1061
1062 static const struct of_device_id rockchip_bank_match[] = {
1063         { .compatible = "rockchip,gpio-bank" },
1064         { .compatible = "rockchip,rk3188-gpio-bank0" },
1065         {},
1066 };
1067
1068 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1069                                                 struct device_node *np)
1070 {
1071         struct device_node *child;
1072
1073         for_each_child_of_node(np, child) {
1074                 if (of_match_node(rockchip_bank_match, child))
1075                         continue;
1076
1077                 info->nfunctions++;
1078                 info->ngroups += of_get_child_count(child);
1079         }
1080 }
1081
1082 static int rockchip_pinctrl_parse_groups(struct device_node *np,
1083                                               struct rockchip_pin_group *grp,
1084                                               struct rockchip_pinctrl *info,
1085                                               u32 index)
1086 {
1087         struct rockchip_pin_bank *bank;
1088         int size;
1089         const __be32 *list;
1090         int num;
1091         int i, j;
1092         int ret;
1093
1094         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1095
1096         /* Initialise group */
1097         grp->name = np->name;
1098
1099         /*
1100          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1101          * do sanity check and calculate pins number
1102          */
1103         list = of_get_property(np, "rockchip,pins", &size);
1104         /* we do not check return since it's safe node passed down */
1105         size /= sizeof(*list);
1106         if (!size || size % 4) {
1107                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1108                 return -EINVAL;
1109         }
1110
1111         grp->npins = size / 4;
1112
1113         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1114                                                 GFP_KERNEL);
1115         grp->data = devm_kzalloc(info->dev, grp->npins *
1116                                           sizeof(struct rockchip_pin_config),
1117                                         GFP_KERNEL);
1118         if (!grp->pins || !grp->data)
1119                 return -ENOMEM;
1120
1121         for (i = 0, j = 0; i < size; i += 4, j++) {
1122                 const __be32 *phandle;
1123                 struct device_node *np_config;
1124
1125                 num = be32_to_cpu(*list++);
1126                 bank = bank_num_to_bank(info, num);
1127                 if (IS_ERR(bank))
1128                         return PTR_ERR(bank);
1129
1130                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1131                 grp->data[j].func = be32_to_cpu(*list++);
1132
1133                 phandle = list++;
1134                 if (!phandle)
1135                         return -EINVAL;
1136
1137                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
1138                 ret = pinconf_generic_parse_dt_config(np_config,
1139                                 &grp->data[j].configs, &grp->data[j].nconfigs);
1140                 if (ret)
1141                         return ret;
1142         }
1143
1144         return 0;
1145 }
1146
1147 static int rockchip_pinctrl_parse_functions(struct device_node *np,
1148                                                 struct rockchip_pinctrl *info,
1149                                                 u32 index)
1150 {
1151         struct device_node *child;
1152         struct rockchip_pmx_func *func;
1153         struct rockchip_pin_group *grp;
1154         int ret;
1155         static u32 grp_index;
1156         u32 i = 0;
1157
1158         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1159
1160         func = &info->functions[index];
1161
1162         /* Initialise function */
1163         func->name = np->name;
1164         func->ngroups = of_get_child_count(np);
1165         if (func->ngroups <= 0)
1166                 return 0;
1167
1168         func->groups = devm_kzalloc(info->dev,
1169                         func->ngroups * sizeof(char *), GFP_KERNEL);
1170         if (!func->groups)
1171                 return -ENOMEM;
1172
1173         for_each_child_of_node(np, child) {
1174                 func->groups[i] = child->name;
1175                 grp = &info->groups[grp_index++];
1176                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
1177                 if (ret)
1178                         return ret;
1179         }
1180
1181         return 0;
1182 }
1183
1184 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1185                                               struct rockchip_pinctrl *info)
1186 {
1187         struct device *dev = &pdev->dev;
1188         struct device_node *np = dev->of_node;
1189         struct device_node *child;
1190         int ret;
1191         int i;
1192
1193         rockchip_pinctrl_child_count(info, np);
1194
1195         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1196         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1197
1198         info->functions = devm_kzalloc(dev, info->nfunctions *
1199                                               sizeof(struct rockchip_pmx_func),
1200                                               GFP_KERNEL);
1201         if (!info->functions) {
1202                 dev_err(dev, "failed to allocate memory for function list\n");
1203                 return -EINVAL;
1204         }
1205
1206         info->groups = devm_kzalloc(dev, info->ngroups *
1207                                             sizeof(struct rockchip_pin_group),
1208                                             GFP_KERNEL);
1209         if (!info->groups) {
1210                 dev_err(dev, "failed allocate memory for ping group list\n");
1211                 return -EINVAL;
1212         }
1213
1214         i = 0;
1215
1216         for_each_child_of_node(np, child) {
1217                 if (of_match_node(rockchip_bank_match, child))
1218                         continue;
1219
1220                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1221                 if (ret) {
1222                         dev_err(&pdev->dev, "failed to parse function\n");
1223                         return ret;
1224                 }
1225         }
1226
1227         return 0;
1228 }
1229
1230 static int rockchip_pinctrl_register(struct platform_device *pdev,
1231                                         struct rockchip_pinctrl *info)
1232 {
1233         struct pinctrl_desc *ctrldesc = &info->pctl;
1234         struct pinctrl_pin_desc *pindesc, *pdesc;
1235         struct rockchip_pin_bank *pin_bank;
1236         int pin, bank, ret;
1237         int k;
1238
1239         ctrldesc->name = "rockchip-pinctrl";
1240         ctrldesc->owner = THIS_MODULE;
1241         ctrldesc->pctlops = &rockchip_pctrl_ops;
1242         ctrldesc->pmxops = &rockchip_pmx_ops;
1243         ctrldesc->confops = &rockchip_pinconf_ops;
1244
1245         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1246                         info->ctrl->nr_pins, GFP_KERNEL);
1247         if (!pindesc) {
1248                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1249                 return -ENOMEM;
1250         }
1251         ctrldesc->pins = pindesc;
1252         ctrldesc->npins = info->ctrl->nr_pins;
1253
1254         pdesc = pindesc;
1255         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1256                 pin_bank = &info->ctrl->pin_banks[bank];
1257                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1258                         pdesc->number = k;
1259                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1260                                                 pin_bank->name, pin);
1261                         pdesc++;
1262                 }
1263         }
1264
1265         ret = rockchip_pinctrl_parse_dt(pdev, info);
1266         if (ret)
1267                 return ret;
1268
1269         info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
1270         if (!info->pctl_dev) {
1271                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1272                 return -EINVAL;
1273         }
1274
1275         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1276                 pin_bank = &info->ctrl->pin_banks[bank];
1277                 pin_bank->grange.name = pin_bank->name;
1278                 pin_bank->grange.id = bank;
1279                 pin_bank->grange.pin_base = pin_bank->pin_base;
1280                 pin_bank->grange.base = pin_bank->gpio_chip.base;
1281                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1282                 pin_bank->grange.gc = &pin_bank->gpio_chip;
1283                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1284         }
1285
1286         return 0;
1287 }
1288
1289 /*
1290  * GPIO handling
1291  */
1292
1293 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
1294 {
1295         return pinctrl_request_gpio(chip->base + offset);
1296 }
1297
1298 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
1299 {
1300         pinctrl_free_gpio(chip->base + offset);
1301 }
1302
1303 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1304 {
1305         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1306         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1307         unsigned long flags;
1308         u32 data;
1309
1310         spin_lock_irqsave(&bank->slock, flags);
1311
1312         data = readl(reg);
1313         data &= ~BIT(offset);
1314         if (value)
1315                 data |= BIT(offset);
1316         writel(data, reg);
1317
1318         spin_unlock_irqrestore(&bank->slock, flags);
1319 }
1320
1321 /*
1322  * Returns the level of the pin for input direction and setting of the DR
1323  * register for output gpios.
1324  */
1325 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1326 {
1327         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1328         u32 data;
1329
1330         data = readl(bank->reg_base + GPIO_EXT_PORT);
1331         data >>= offset;
1332         data &= 1;
1333         return data;
1334 }
1335
1336 /*
1337  * gpiolib gpio_direction_input callback function. The setting of the pin
1338  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1339  * interface.
1340  */
1341 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1342 {
1343         return pinctrl_gpio_direction_input(gc->base + offset);
1344 }
1345
1346 /*
1347  * gpiolib gpio_direction_output callback function. The setting of the pin
1348  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1349  * interface.
1350  */
1351 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1352                                           unsigned offset, int value)
1353 {
1354         rockchip_gpio_set(gc, offset, value);
1355         return pinctrl_gpio_direction_output(gc->base + offset);
1356 }
1357
1358 /*
1359  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1360  * and a virtual IRQ, if not already present.
1361  */
1362 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1363 {
1364         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1365         unsigned int virq;
1366
1367         if (!bank->domain)
1368                 return -ENXIO;
1369
1370         virq = irq_create_mapping(bank->domain, offset);
1371
1372         return (virq) ? : -ENXIO;
1373 }
1374
1375 static const struct gpio_chip rockchip_gpiolib_chip = {
1376         .request = rockchip_gpio_request,
1377         .free = rockchip_gpio_free,
1378         .set = rockchip_gpio_set,
1379         .get = rockchip_gpio_get,
1380         .direction_input = rockchip_gpio_direction_input,
1381         .direction_output = rockchip_gpio_direction_output,
1382         .to_irq = rockchip_gpio_to_irq,
1383         .owner = THIS_MODULE,
1384 };
1385
1386 /*
1387  * Interrupt handling
1388  */
1389
1390 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1391 {
1392         struct irq_chip *chip = irq_get_chip(irq);
1393         struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
1394         u32 polarity = 0, data = 0;
1395         u32 pend;
1396         bool edge_changed = false;
1397
1398         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1399
1400         chained_irq_enter(chip, desc);
1401
1402         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1403
1404         if (bank->toggle_edge_mode) {
1405                 polarity = readl_relaxed(bank->reg_base +
1406                                          GPIO_INT_POLARITY);
1407                 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1408         }
1409
1410         while (pend) {
1411                 unsigned int virq;
1412
1413                 irq = __ffs(pend);
1414                 pend &= ~BIT(irq);
1415                 virq = irq_linear_revmap(bank->domain, irq);
1416
1417                 if (!virq) {
1418                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1419                         continue;
1420                 }
1421
1422                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1423
1424                 /*
1425                  * Triggering IRQ on both rising and falling edge
1426                  * needs manual intervention.
1427                  */
1428                 if (bank->toggle_edge_mode & BIT(irq)) {
1429                         if (data & BIT(irq))
1430                                 polarity &= ~BIT(irq);
1431                         else
1432                                 polarity |= BIT(irq);
1433
1434                         edge_changed = true;
1435                 }
1436
1437                 generic_handle_irq(virq);
1438         }
1439
1440         if (bank->toggle_edge_mode && edge_changed) {
1441                 /* Interrupt params should only be set with ints disabled */
1442                 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
1443                 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
1444                 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
1445                 writel(data, bank->reg_base + GPIO_INTEN);
1446         }
1447
1448         chained_irq_exit(chip, desc);
1449 }
1450
1451 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1452 {
1453         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1454         struct rockchip_pin_bank *bank = gc->private;
1455         u32 mask = BIT(d->hwirq);
1456         u32 polarity;
1457         u32 level;
1458         u32 data;
1459         int ret;
1460
1461         /* make sure the pin is configured as gpio input */
1462         ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1463         if (ret < 0)
1464                 return ret;
1465
1466         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1467         data &= ~mask;
1468         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1469
1470         if (type & IRQ_TYPE_EDGE_BOTH)
1471                 __irq_set_handler_locked(d->irq, handle_edge_irq);
1472         else
1473                 __irq_set_handler_locked(d->irq, handle_level_irq);
1474
1475         irq_gc_lock(gc);
1476
1477         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1478         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1479
1480         switch (type) {
1481         case IRQ_TYPE_EDGE_BOTH:
1482                 bank->toggle_edge_mode |= mask;
1483                 level |= mask;
1484
1485                 /*
1486                  * Determine gpio state. If 1 next interrupt should be falling
1487                  * otherwise rising.
1488                  */
1489                 data = readl(bank->reg_base + GPIO_EXT_PORT);
1490                 if (data & mask)
1491                         polarity &= ~mask;
1492                 else
1493                         polarity |= mask;
1494                 break;
1495         case IRQ_TYPE_EDGE_RISING:
1496                 bank->toggle_edge_mode &= ~mask;
1497                 level |= mask;
1498                 polarity |= mask;
1499                 break;
1500         case IRQ_TYPE_EDGE_FALLING:
1501                 bank->toggle_edge_mode &= ~mask;
1502                 level |= mask;
1503                 polarity &= ~mask;
1504                 break;
1505         case IRQ_TYPE_LEVEL_HIGH:
1506                 bank->toggle_edge_mode &= ~mask;
1507                 level &= ~mask;
1508                 polarity |= mask;
1509                 break;
1510         case IRQ_TYPE_LEVEL_LOW:
1511                 bank->toggle_edge_mode &= ~mask;
1512                 level &= ~mask;
1513                 polarity &= ~mask;
1514                 break;
1515         default:
1516                 irq_gc_unlock(gc);
1517                 return -EINVAL;
1518         }
1519
1520         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1521         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1522
1523         irq_gc_unlock(gc);
1524
1525         return 0;
1526 }
1527
1528 static int rockchip_interrupts_register(struct platform_device *pdev,
1529                                                 struct rockchip_pinctrl *info)
1530 {
1531         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1532         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1533         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1534         struct irq_chip_generic *gc;
1535         int ret;
1536         int i;
1537
1538         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1539                 if (!bank->valid) {
1540                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1541                                  bank->name);
1542                         continue;
1543                 }
1544
1545                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1546                                                 &irq_generic_chip_ops, NULL);
1547                 if (!bank->domain) {
1548                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1549                                  bank->name);
1550                         continue;
1551                 }
1552
1553                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1554                                          "rockchip_gpio_irq", handle_level_irq,
1555                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
1556                 if (ret) {
1557                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1558                                 bank->name);
1559                         irq_domain_remove(bank->domain);
1560                         continue;
1561                 }
1562
1563                 gc = irq_get_domain_generic_chip(bank->domain, 0);
1564                 gc->reg_base = bank->reg_base;
1565                 gc->private = bank;
1566                 gc->chip_types[0].regs.mask = GPIO_INTEN;
1567                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1568                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1569                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1570                 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1571                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1572                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1573                 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
1574
1575                 irq_set_handler_data(bank->irq, bank);
1576                 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1577         }
1578
1579         return 0;
1580 }
1581
1582 static int rockchip_gpiolib_register(struct platform_device *pdev,
1583                                                 struct rockchip_pinctrl *info)
1584 {
1585         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1586         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1587         struct gpio_chip *gc;
1588         int ret;
1589         int i;
1590
1591         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1592                 if (!bank->valid) {
1593                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1594                                  bank->name);
1595                         continue;
1596                 }
1597
1598                 bank->gpio_chip = rockchip_gpiolib_chip;
1599
1600                 gc = &bank->gpio_chip;
1601                 gc->base = bank->pin_base;
1602                 gc->ngpio = bank->nr_pins;
1603                 gc->dev = &pdev->dev;
1604                 gc->of_node = bank->of_node;
1605                 gc->label = bank->name;
1606
1607                 ret = gpiochip_add(gc);
1608                 if (ret) {
1609                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1610                                                         gc->label, ret);
1611                         goto fail;
1612                 }
1613         }
1614
1615         rockchip_interrupts_register(pdev, info);
1616
1617         return 0;
1618
1619 fail:
1620         for (--i, --bank; i >= 0; --i, --bank) {
1621                 if (!bank->valid)
1622                         continue;
1623                 gpiochip_remove(&bank->gpio_chip);
1624         }
1625         return ret;
1626 }
1627
1628 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1629                                                 struct rockchip_pinctrl *info)
1630 {
1631         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1632         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1633         int i;
1634
1635         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1636                 if (!bank->valid)
1637                         continue;
1638                 gpiochip_remove(&bank->gpio_chip);
1639         }
1640
1641         return 0;
1642 }
1643
1644 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1645                                   struct rockchip_pinctrl *info)
1646 {
1647         struct resource res;
1648         void __iomem *base;
1649
1650         if (of_address_to_resource(bank->of_node, 0, &res)) {
1651                 dev_err(info->dev, "cannot find IO resource for bank\n");
1652                 return -ENOENT;
1653         }
1654
1655         bank->reg_base = devm_ioremap_resource(info->dev, &res);
1656         if (IS_ERR(bank->reg_base))
1657                 return PTR_ERR(bank->reg_base);
1658
1659         /*
1660          * special case, where parts of the pull setting-registers are
1661          * part of the PMU register space
1662          */
1663         if (of_device_is_compatible(bank->of_node,
1664                                     "rockchip,rk3188-gpio-bank0")) {
1665                 struct device_node *node;
1666
1667                 node = of_parse_phandle(bank->of_node->parent,
1668                                         "rockchip,pmu", 0);
1669                 if (!node) {
1670                         if (of_address_to_resource(bank->of_node, 1, &res)) {
1671                                 dev_err(info->dev, "cannot find IO resource for bank\n");
1672                                 return -ENOENT;
1673                         }
1674
1675                         base = devm_ioremap_resource(info->dev, &res);
1676                         if (IS_ERR(base))
1677                                 return PTR_ERR(base);
1678                         rockchip_regmap_config.max_register =
1679                                                     resource_size(&res) - 4;
1680                         rockchip_regmap_config.name =
1681                                             "rockchip,rk3188-gpio-bank0-pull";
1682                         bank->regmap_pull = devm_regmap_init_mmio(info->dev,
1683                                                     base,
1684                                                     &rockchip_regmap_config);
1685                 }
1686         }
1687
1688         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1689
1690         bank->clk = of_clk_get(bank->of_node, 0);
1691         if (IS_ERR(bank->clk))
1692                 return PTR_ERR(bank->clk);
1693
1694         return clk_prepare_enable(bank->clk);
1695 }
1696
1697 static const struct of_device_id rockchip_pinctrl_dt_match[];
1698
1699 /* retrieve the soc specific data */
1700 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1701                                                 struct rockchip_pinctrl *d,
1702                                                 struct platform_device *pdev)
1703 {
1704         const struct of_device_id *match;
1705         struct device_node *node = pdev->dev.of_node;
1706         struct device_node *np;
1707         struct rockchip_pin_ctrl *ctrl;
1708         struct rockchip_pin_bank *bank;
1709         int grf_offs, pmu_offs, i, j;
1710
1711         match = of_match_node(rockchip_pinctrl_dt_match, node);
1712         ctrl = (struct rockchip_pin_ctrl *)match->data;
1713
1714         for_each_child_of_node(node, np) {
1715                 if (!of_find_property(np, "gpio-controller", NULL))
1716                         continue;
1717
1718                 bank = ctrl->pin_banks;
1719                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1720                         if (!strcmp(bank->name, np->name)) {
1721                                 bank->of_node = np;
1722
1723                                 if (!rockchip_get_bank_data(bank, d))
1724                                         bank->valid = true;
1725
1726                                 break;
1727                         }
1728                 }
1729         }
1730
1731         grf_offs = ctrl->grf_mux_offset;
1732         pmu_offs = ctrl->pmu_mux_offset;
1733         bank = ctrl->pin_banks;
1734         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1735                 int bank_pins = 0;
1736
1737                 spin_lock_init(&bank->slock);
1738                 bank->drvdata = d;
1739                 bank->pin_base = ctrl->nr_pins;
1740                 ctrl->nr_pins += bank->nr_pins;
1741
1742                 /* calculate iomux offsets */
1743                 for (j = 0; j < 4; j++) {
1744                         struct rockchip_iomux *iom = &bank->iomux[j];
1745                         int inc;
1746
1747                         if (bank_pins >= bank->nr_pins)
1748                                 break;
1749
1750                         /* preset offset value, set new start value */
1751                         if (iom->offset >= 0) {
1752                                 if (iom->type & IOMUX_SOURCE_PMU)
1753                                         pmu_offs = iom->offset;
1754                                 else
1755                                         grf_offs = iom->offset;
1756                         } else { /* set current offset */
1757                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
1758                                                         pmu_offs : grf_offs;
1759                         }
1760
1761                         dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n",
1762                                  i, j, iom->offset);
1763
1764                         /*
1765                          * Increase offset according to iomux width.
1766                          * 4bit iomux'es are spread over two registers.
1767                          */
1768                         inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
1769                         if (iom->type & IOMUX_SOURCE_PMU)
1770                                 pmu_offs += inc;
1771                         else
1772                                 grf_offs += inc;
1773
1774                         bank_pins += 8;
1775                 }
1776         }
1777
1778         return ctrl;
1779 }
1780
1781 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1782 {
1783         struct rockchip_pinctrl *info;
1784         struct device *dev = &pdev->dev;
1785         struct rockchip_pin_ctrl *ctrl;
1786         struct device_node *np = pdev->dev.of_node, *node;
1787         struct resource *res;
1788         void __iomem *base;
1789         int ret;
1790
1791         if (!dev->of_node) {
1792                 dev_err(dev, "device tree node not found\n");
1793                 return -ENODEV;
1794         }
1795
1796         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1797         if (!info)
1798                 return -ENOMEM;
1799
1800         info->dev = dev;
1801
1802         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1803         if (!ctrl) {
1804                 dev_err(dev, "driver data not available\n");
1805                 return -EINVAL;
1806         }
1807         info->ctrl = ctrl;
1808
1809         node = of_parse_phandle(np, "rockchip,grf", 0);
1810         if (node) {
1811                 info->regmap_base = syscon_node_to_regmap(node);
1812                 if (IS_ERR(info->regmap_base))
1813                         return PTR_ERR(info->regmap_base);
1814         } else {
1815                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1816                 base = devm_ioremap_resource(&pdev->dev, res);
1817                 if (IS_ERR(base))
1818                         return PTR_ERR(base);
1819
1820                 rockchip_regmap_config.max_register = resource_size(res) - 4;
1821                 rockchip_regmap_config.name = "rockchip,pinctrl";
1822                 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
1823                                                     &rockchip_regmap_config);
1824
1825                 /* to check for the old dt-bindings */
1826                 info->reg_size = resource_size(res);
1827
1828                 /* Honor the old binding, with pull registers as 2nd resource */
1829                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
1830                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1831                         base = devm_ioremap_resource(&pdev->dev, res);
1832                         if (IS_ERR(base))
1833                                 return PTR_ERR(base);
1834
1835                         rockchip_regmap_config.max_register =
1836                                                         resource_size(res) - 4;
1837                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
1838                         info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
1839                                                     base,
1840                                                     &rockchip_regmap_config);
1841                 }
1842         }
1843
1844         /* try to find the optional reference to the pmu syscon */
1845         node = of_parse_phandle(np, "rockchip,pmu", 0);
1846         if (node) {
1847                 info->regmap_pmu = syscon_node_to_regmap(node);
1848                 if (IS_ERR(info->regmap_pmu))
1849                         return PTR_ERR(info->regmap_pmu);
1850         }
1851
1852         ret = rockchip_gpiolib_register(pdev, info);
1853         if (ret)
1854                 return ret;
1855
1856         ret = rockchip_pinctrl_register(pdev, info);
1857         if (ret) {
1858                 rockchip_gpiolib_unregister(pdev, info);
1859                 return ret;
1860         }
1861
1862         platform_set_drvdata(pdev, info);
1863
1864         return 0;
1865 }
1866
1867 static struct rockchip_pin_bank rk2928_pin_banks[] = {
1868         PIN_BANK(0, 32, "gpio0"),
1869         PIN_BANK(1, 32, "gpio1"),
1870         PIN_BANK(2, 32, "gpio2"),
1871         PIN_BANK(3, 32, "gpio3"),
1872 };
1873
1874 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1875                 .pin_banks              = rk2928_pin_banks,
1876                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
1877                 .label                  = "RK2928-GPIO",
1878                 .type                   = RK2928,
1879                 .grf_mux_offset         = 0xa8,
1880                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
1881 };
1882
1883 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1884         PIN_BANK(0, 32, "gpio0"),
1885         PIN_BANK(1, 32, "gpio1"),
1886         PIN_BANK(2, 32, "gpio2"),
1887         PIN_BANK(3, 32, "gpio3"),
1888         PIN_BANK(4, 32, "gpio4"),
1889         PIN_BANK(6, 16, "gpio6"),
1890 };
1891
1892 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1893                 .pin_banks              = rk3066a_pin_banks,
1894                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
1895                 .label                  = "RK3066a-GPIO",
1896                 .type                   = RK2928,
1897                 .grf_mux_offset         = 0xa8,
1898                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
1899 };
1900
1901 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1902         PIN_BANK(0, 32, "gpio0"),
1903         PIN_BANK(1, 32, "gpio1"),
1904         PIN_BANK(2, 32, "gpio2"),
1905         PIN_BANK(3, 32, "gpio3"),
1906 };
1907
1908 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1909                 .pin_banks      = rk3066b_pin_banks,
1910                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
1911                 .label          = "RK3066b-GPIO",
1912                 .type           = RK3066B,
1913                 .grf_mux_offset = 0x60,
1914 };
1915
1916 static struct rockchip_pin_bank rk3188_pin_banks[] = {
1917         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
1918         PIN_BANK(1, 32, "gpio1"),
1919         PIN_BANK(2, 32, "gpio2"),
1920         PIN_BANK(3, 32, "gpio3"),
1921 };
1922
1923 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1924                 .pin_banks              = rk3188_pin_banks,
1925                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
1926                 .label                  = "RK3188-GPIO",
1927                 .type                   = RK3188,
1928                 .grf_mux_offset         = 0x60,
1929                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
1930 };
1931
1932 static struct rockchip_pin_bank rk3288_pin_banks[] = {
1933         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
1934                                              IOMUX_SOURCE_PMU,
1935                                              IOMUX_SOURCE_PMU,
1936                                              IOMUX_UNROUTED
1937                             ),
1938         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
1939                                              IOMUX_UNROUTED,
1940                                              IOMUX_UNROUTED,
1941                                              0
1942                             ),
1943         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
1944         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
1945         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
1946                                              IOMUX_WIDTH_4BIT,
1947                                              0,
1948                                              0
1949                             ),
1950         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
1951                                              0,
1952                                              0,
1953                                              IOMUX_UNROUTED
1954                             ),
1955         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
1956         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
1957                                              0,
1958                                              IOMUX_WIDTH_4BIT,
1959                                              IOMUX_UNROUTED
1960                             ),
1961         PIN_BANK(8, 16, "gpio8"),
1962 };
1963
1964 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
1965                 .pin_banks              = rk3288_pin_banks,
1966                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
1967                 .label                  = "RK3288-GPIO",
1968                 .type                   = RK3288,
1969                 .grf_mux_offset         = 0x0,
1970                 .pmu_mux_offset         = 0x84,
1971                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
1972 };
1973
1974 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1975         { .compatible = "rockchip,rk2928-pinctrl",
1976                 .data = (void *)&rk2928_pin_ctrl },
1977         { .compatible = "rockchip,rk3066a-pinctrl",
1978                 .data = (void *)&rk3066a_pin_ctrl },
1979         { .compatible = "rockchip,rk3066b-pinctrl",
1980                 .data = (void *)&rk3066b_pin_ctrl },
1981         { .compatible = "rockchip,rk3188-pinctrl",
1982                 .data = (void *)&rk3188_pin_ctrl },
1983         { .compatible = "rockchip,rk3288-pinctrl",
1984                 .data = (void *)&rk3288_pin_ctrl },
1985         {},
1986 };
1987 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1988
1989 static struct platform_driver rockchip_pinctrl_driver = {
1990         .probe          = rockchip_pinctrl_probe,
1991         .driver = {
1992                 .name   = "rockchip-pinctrl",
1993                 .owner  = THIS_MODULE,
1994                 .of_match_table = rockchip_pinctrl_dt_match,
1995         },
1996 };
1997
1998 static int __init rockchip_pinctrl_drv_register(void)
1999 {
2000         return platform_driver_register(&rockchip_pinctrl_driver);
2001 }
2002 postcore_initcall(rockchip_pinctrl_drv_register);
2003
2004 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
2005 MODULE_DESCRIPTION("Rockchip pinctrl driver");
2006 MODULE_LICENSE("GPL v2");