drivers/scsi/mvsas/mv_init.c

   1 /*
   2  * Marvell 88SE64xx/88SE94xx pci init
   3  *
   4  * Copyright 2007 Red Hat, Inc.
   5  * Copyright 2008 Marvell. <kewei@marvell.com>
   6  * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
   7  *
   8  * This file is licensed under GPLv2.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; version 2 of the
  13  * License.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  23  * USA
  24 */
  25
  26
  27 #include "mv_sas.h"
  28
  29 int interrupt_coalescing = 0x80;
  30
  31 static struct scsi_transport_template *mvs_stt;
  32 static const struct mvs_chip_info mvs_chips[] = {
  33         [chip_6320] =   { 1, 2, 0x400, 17, 16, 6,  9, &mvs_64xx_dispatch, },
  34         [chip_6440] =   { 1, 4, 0x400, 17, 16, 6,  9, &mvs_64xx_dispatch, },
  35         [chip_6485] =   { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, },
  36         [chip_9180] =   { 2, 4, 0x800, 17, 64, 8,  9, &mvs_94xx_dispatch, },
  37         [chip_9480] =   { 2, 4, 0x800, 17, 64, 8,  9, &mvs_94xx_dispatch, },
  38         [chip_9445] =   { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
  39         [chip_9485] =   { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
  40         [chip_1300] =   { 1, 4, 0x400, 17, 16, 6,  9, &mvs_64xx_dispatch, },
  41         [chip_1320] =   { 2, 4, 0x800, 17, 64, 8,  9, &mvs_94xx_dispatch, },
  42 };
  43
  44 struct device_attribute *mvst_host_attrs[];
  45
  46 #define SOC_SAS_NUM 2
  47
  48 static struct scsi_host_template mvs_sht = {
  49         .module                 = THIS_MODULE,
  50         .name                   = DRV_NAME,
  51         .queuecommand           = sas_queuecommand,
  52         .target_alloc           = sas_target_alloc,
  53         .slave_configure        = sas_slave_configure,
  54         .scan_finished          = mvs_scan_finished,
  55         .scan_start             = mvs_scan_start,
  56         .change_queue_depth     = sas_change_queue_depth,
  57         .bios_param             = sas_bios_param,
  58         .can_queue              = 1,
  59         .this_id                = -1,
  60         .sg_tablesize           = SG_ALL,
  61         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
  62         .use_clustering         = ENABLE_CLUSTERING,
  63         .eh_device_reset_handler = sas_eh_device_reset_handler,
  64         .eh_bus_reset_handler   = sas_eh_bus_reset_handler,
  65         .target_destroy         = sas_target_destroy,
  66         .ioctl                  = sas_ioctl,
  67         .shost_attrs            = mvst_host_attrs,
  68         .use_blk_tags           = 1,
  69         .track_queue_depth      = 1,
  70 };
  71
  72 static struct sas_domain_function_template mvs_transport_ops = {
  73         .lldd_dev_found         = mvs_dev_found,
  74         .lldd_dev_gone          = mvs_dev_gone,
  75         .lldd_execute_task      = mvs_queue_command,
  76         .lldd_control_phy       = mvs_phy_control,
  77
  78         .lldd_abort_task        = mvs_abort_task,
  79         .lldd_abort_task_set    = mvs_abort_task_set,
  80         .lldd_clear_aca         = mvs_clear_aca,
  81         .lldd_clear_task_set    = mvs_clear_task_set,
  82         .lldd_I_T_nexus_reset   = mvs_I_T_nexus_reset,
  83         .lldd_lu_reset          = mvs_lu_reset,
  84         .lldd_query_task        = mvs_query_task,
  85         .lldd_port_formed       = mvs_port_formed,
  86         .lldd_port_deformed     = mvs_port_deformed,
  87
  88 };
  89
  90 static void mvs_phy_init(struct mvs_info *mvi, int phy_id)
  91 {
  92         struct mvs_phy *phy = &mvi->phy[phy_id];
  93         struct asd_sas_phy *sas_phy = &phy->sas_phy;
  94
  95         phy->mvi = mvi;
  96         phy->port = NULL;
  97         init_timer(&phy->timer);
  98         sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;
  99         sas_phy->class = SAS;
 100         sas_phy->iproto = SAS_PROTOCOL_ALL;
 101         sas_phy->tproto = 0;
 102         sas_phy->type = PHY_TYPE_PHYSICAL;
 103         sas_phy->role = PHY_ROLE_INITIATOR;
 104         sas_phy->oob_mode = OOB_NOT_CONNECTED;
 105         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
 106
 107         sas_phy->id = phy_id;
 108         sas_phy->sas_addr = &mvi->sas_addr[0];
 109         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
 110         sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata;
 111         sas_phy->lldd_phy = phy;
 112 }
 113
 114 static void mvs_free(struct mvs_info *mvi)
 115 {
 116         struct mvs_wq *mwq;
 117         int slot_nr;
 118
 119         if (!mvi)
 120                 return;
 121
 122         if (mvi->flags & MVF_FLAG_SOC)
 123                 slot_nr = MVS_SOC_SLOTS;
 124         else
 125                 slot_nr = MVS_CHIP_SLOT_SZ;
 126
 127         if (mvi->dma_pool)
 128                 pci_pool_destroy(mvi->dma_pool);
 129
 130         if (mvi->tx)
 131                 dma_free_coherent(mvi->dev,
 132                                   sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
 133                                   mvi->tx, mvi->tx_dma);
 134         if (mvi->rx_fis)
 135                 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ,
 136                                   mvi->rx_fis, mvi->rx_fis_dma);
 137         if (mvi->rx)
 138                 dma_free_coherent(mvi->dev,
 139                                   sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
 140                                   mvi->rx, mvi->rx_dma);
 141         if (mvi->slot)
 142                 dma_free_coherent(mvi->dev,
 143                                   sizeof(*mvi->slot) * slot_nr,
 144                                   mvi->slot, mvi->slot_dma);
 145
 146         if (mvi->bulk_buffer)
 147                 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
 148                                   mvi->bulk_buffer, mvi->bulk_buffer_dma);
 149         if (mvi->bulk_buffer1)
 150                 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
 151                                   mvi->bulk_buffer1, mvi->bulk_buffer_dma1);
 152
 153         MVS_CHIP_DISP->chip_iounmap(mvi);
 154         if (mvi->shost)
 155                 scsi_host_put(mvi->shost);
 156         list_for_each_entry(mwq, &mvi->wq_list, entry)
 157                 cancel_delayed_work(&mwq->work_q);
 158         kfree(mvi->tags);
 159         kfree(mvi);
 160 }
 161
 162 #ifdef CONFIG_SCSI_MVSAS_TASKLET
 163 static void mvs_tasklet(unsigned long opaque)
 164 {
 165         u32 stat;
 166         u16 core_nr, i = 0;
 167
 168         struct mvs_info *mvi;
 169         struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque;
 170
 171         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 172         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
 173
 174         if (unlikely(!mvi))
 175                 BUG_ON(1);
 176
 177         stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq);
 178         if (!stat)
 179                 goto out;
 180
 181         for (i = 0; i < core_nr; i++) {
 182                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
 183                 MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat);
 184         }
 185 out:
 186         MVS_CHIP_DISP->interrupt_enable(mvi);
 187
 188 }
 189 #endif
 190
 191 static irqreturn_t mvs_interrupt(int irq, void *opaque)
 192 {
 193         u32 core_nr;
 194         u32 stat;
 195         struct mvs_info *mvi;
 196         struct sas_ha_struct *sha = opaque;
 197 #ifndef CONFIG_SCSI_MVSAS_TASKLET
 198         u32 i;
 199 #endif
 200
 201         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 202         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
 203
 204         if (unlikely(!mvi))
 205                 return IRQ_NONE;
 206 #ifdef CONFIG_SCSI_MVSAS_TASKLET
 207         MVS_CHIP_DISP->interrupt_disable(mvi);
 208 #endif
 209
 210         stat = MVS_CHIP_DISP->isr_status(mvi, irq);
 211         if (!stat) {
 212         #ifdef CONFIG_SCSI_MVSAS_TASKLET
 213                 MVS_CHIP_DISP->interrupt_enable(mvi);
 214         #endif
 215                 return IRQ_NONE;
 216         }
 217
 218 #ifdef CONFIG_SCSI_MVSAS_TASKLET
 219         tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
 220 #else
 221         for (i = 0; i < core_nr; i++) {
 222                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
 223                 MVS_CHIP_DISP->isr(mvi, irq, stat);
 224         }
 225 #endif
 226         return IRQ_HANDLED;
 227 }
 228
 229 static int mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost)
 230 {
 231         int i = 0, slot_nr;
 232         char pool_name[32];
 233
 234         if (mvi->flags & MVF_FLAG_SOC)
 235                 slot_nr = MVS_SOC_SLOTS;
 236         else
 237                 slot_nr = MVS_CHIP_SLOT_SZ;
 238
 239         spin_lock_init(&mvi->lock);
 240         for (i = 0; i < mvi->chip->n_phy; i++) {
 241                 mvs_phy_init(mvi, i);
 242                 mvi->port[i].wide_port_phymap = 0;
 243                 mvi->port[i].port_attached = 0;
 244                 INIT_LIST_HEAD(&mvi->port[i].list);
 245         }
 246         for (i = 0; i < MVS_MAX_DEVICES; i++) {
 247                 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED;
 248                 mvi->devices[i].dev_type = SAS_PHY_UNUSED;
 249                 mvi->devices[i].device_id = i;
 250                 mvi->devices[i].dev_status = MVS_DEV_NORMAL;
 251                 init_timer(&mvi->devices[i].timer);
 252         }
 253
 254         /*
 255          * alloc and init our DMA areas
 256          */
 257         mvi->tx = dma_alloc_coherent(mvi->dev,
 258                                      sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
 259                                      &mvi->tx_dma, GFP_KERNEL);
 260         if (!mvi->tx)
 261                 goto err_out;
 262         memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ);
 263         mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ,
 264                                          &mvi->rx_fis_dma, GFP_KERNEL);
 265         if (!mvi->rx_fis)
 266                 goto err_out;
 267         memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ);
 268
 269         mvi->rx = dma_alloc_coherent(mvi->dev,
 270                                      sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
 271                                      &mvi->rx_dma, GFP_KERNEL);
 272         if (!mvi->rx)
 273                 goto err_out;
 274         memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1));
 275         mvi->rx[0] = cpu_to_le32(0xfff);
 276         mvi->rx_cons = 0xfff;
 277
 278         mvi->slot = dma_alloc_coherent(mvi->dev,
 279                                        sizeof(*mvi->slot) * slot_nr,
 280                                        &mvi->slot_dma, GFP_KERNEL);
 281         if (!mvi->slot)
 282                 goto err_out;
 283         memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr);
 284
 285         mvi->bulk_buffer = dma_alloc_coherent(mvi->dev,
 286                                        TRASH_BUCKET_SIZE,
 287                                        &mvi->bulk_buffer_dma, GFP_KERNEL);
 288         if (!mvi->bulk_buffer)
 289                 goto err_out;
 290
 291         mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev,
 292                                        TRASH_BUCKET_SIZE,
 293                                        &mvi->bulk_buffer_dma1, GFP_KERNEL);
 294         if (!mvi->bulk_buffer1)
 295                 goto err_out;
 296
 297         sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id);
 298         mvi->dma_pool = pci_pool_create(pool_name, mvi->pdev, MVS_SLOT_BUF_SZ, 16, 0);
 299         if (!mvi->dma_pool) {
 300                         printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name);
 301                         goto err_out;
 302         }
 303         mvi->tags_num = slot_nr;
 304
 305         /* Initialize tags */
 306         mvs_tag_init(mvi);
 307         return 0;
 308 err_out:
 309         return 1;
 310 }
 311
 312
 313 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex)
 314 {
 315         unsigned long res_start, res_len, res_flag, res_flag_ex = 0;
 316         struct pci_dev *pdev = mvi->pdev;
 317         if (bar_ex != -1) {
 318                 /*
 319                  * ioremap main and peripheral registers
 320                  */
 321                 res_start = pci_resource_start(pdev, bar_ex);
 322                 res_len = pci_resource_len(pdev, bar_ex);
 323                 if (!res_start || !res_len)
 324                         goto err_out;
 325
 326                 res_flag_ex = pci_resource_flags(pdev, bar_ex);
 327                 if (res_flag_ex & IORESOURCE_MEM) {
 328                         if (res_flag_ex & IORESOURCE_CACHEABLE)
 329                                 mvi->regs_ex = ioremap(res_start, res_len);
 330                         else
 331                                 mvi->regs_ex = ioremap_nocache(res_start,
 332                                                 res_len);
 333                 } else
 334                         mvi->regs_ex = (void *)res_start;
 335                 if (!mvi->regs_ex)
 336                         goto err_out;
 337         }
 338
 339         res_start = pci_resource_start(pdev, bar);
 340         res_len = pci_resource_len(pdev, bar);
 341         if (!res_start || !res_len) {
 342                 iounmap(mvi->regs_ex);
 343                 mvi->regs_ex = NULL;
 344                 goto err_out;
 345         }
 346
 347         res_flag = pci_resource_flags(pdev, bar);
 348         if (res_flag & IORESOURCE_CACHEABLE)
 349                 mvi->regs = ioremap(res_start, res_len);
 350         else
 351                 mvi->regs = ioremap_nocache(res_start, res_len);
 352
 353         if (!mvi->regs) {
 354                 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM))
 355                         iounmap(mvi->regs_ex);
 356                 mvi->regs_ex = NULL;
 357                 goto err_out;
 358         }
 359
 360         return 0;
 361 err_out:
 362         return -1;
 363 }
 364
 365 void mvs_iounmap(void __iomem *regs)
 366 {
 367         iounmap(regs);
 368 }
 369
 370 static struct mvs_info *mvs_pci_alloc(struct pci_dev *pdev,
 371                                 const struct pci_device_id *ent,
 372                                 struct Scsi_Host *shost, unsigned int id)
 373 {
 374         struct mvs_info *mvi = NULL;
 375         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 376
 377         mvi = kzalloc(sizeof(*mvi) +
 378                 (1L << mvs_chips[ent->driver_data].slot_width) *
 379                 sizeof(struct mvs_slot_info), GFP_KERNEL);
 380         if (!mvi)
 381                 return NULL;
 382
 383         mvi->pdev = pdev;
 384         mvi->dev = &pdev->dev;
 385         mvi->chip_id = ent->driver_data;
 386         mvi->chip = &mvs_chips[mvi->chip_id];
 387         INIT_LIST_HEAD(&mvi->wq_list);
 388
 389         ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi;
 390         ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy;
 391
 392         mvi->id = id;
 393         mvi->sas = sha;
 394         mvi->shost = shost;
 395
 396         mvi->tags = kzalloc(MVS_CHIP_SLOT_SZ>>3, GFP_KERNEL);
 397         if (!mvi->tags)
 398                 goto err_out;
 399
 400         if (MVS_CHIP_DISP->chip_ioremap(mvi))
 401                 goto err_out;
 402         if (!mvs_alloc(mvi, shost))
 403                 return mvi;
 404 err_out:
 405         mvs_free(mvi);
 406         return NULL;
 407 }
 408
 409 static int pci_go_64(struct pci_dev *pdev)
 410 {
 411         int rc;
 412
 413         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
 414                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
 415                 if (rc) {
 416                         rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 417                         if (rc) {
 418                                 dev_printk(KERN_ERR, &pdev->dev,
 419                                            "64-bit DMA enable failed\n");
 420                                 return rc;
 421                         }
 422                 }
 423         } else {
 424                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 425                 if (rc) {
 426                         dev_printk(KERN_ERR, &pdev->dev,
 427                                    "32-bit DMA enable failed\n");
 428                         return rc;
 429                 }
 430                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 431                 if (rc) {
 432                         dev_printk(KERN_ERR, &pdev->dev,
 433                                    "32-bit consistent DMA enable failed\n");
 434                         return rc;
 435                 }
 436         }
 437
 438         return rc;
 439 }
 440
 441 static int mvs_prep_sas_ha_init(struct Scsi_Host *shost,
 442                                 const struct mvs_chip_info *chip_info)
 443 {
 444         int phy_nr, port_nr; unsigned short core_nr;
 445         struct asd_sas_phy **arr_phy;
 446         struct asd_sas_port **arr_port;
 447         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 448
 449         core_nr = chip_info->n_host;
 450         phy_nr  = core_nr * chip_info->n_phy;
 451         port_nr = phy_nr;
 452
 453         memset(sha, 0x00, sizeof(struct sas_ha_struct));
 454         arr_phy  = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
 455         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
 456         if (!arr_phy || !arr_port)
 457                 goto exit_free;
 458
 459         sha->sas_phy = arr_phy;
 460         sha->sas_port = arr_port;
 461         sha->core.shost = shost;
 462
 463         sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL);
 464         if (!sha->lldd_ha)
 465                 goto exit_free;
 466
 467         ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr;
 468
 469         shost->transportt = mvs_stt;
 470         shost->max_id = MVS_MAX_DEVICES;
 471         shost->max_lun = ~0;
 472         shost->max_channel = 1;
 473         shost->max_cmd_len = 16;
 474
 475         return 0;
 476 exit_free:
 477         kfree(arr_phy);
 478         kfree(arr_port);
 479         return -1;
 480
 481 }
 482
 483 static void  mvs_post_sas_ha_init(struct Scsi_Host *shost,
 484                         const struct mvs_chip_info *chip_info)
 485 {
 486         int can_queue, i = 0, j = 0;
 487         struct mvs_info *mvi = NULL;
 488         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 489         unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 490
 491         for (j = 0; j < nr_core; j++) {
 492                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
 493                 for (i = 0; i < chip_info->n_phy; i++) {
 494                         sha->sas_phy[j * chip_info->n_phy  + i] =
 495                                 &mvi->phy[i].sas_phy;
 496                         sha->sas_port[j * chip_info->n_phy + i] =
 497                                 &mvi->port[i].sas_port;
 498                 }
 499         }
 500
 501         sha->sas_ha_name = DRV_NAME;
 502         sha->dev = mvi->dev;
 503         sha->lldd_module = THIS_MODULE;
 504         sha->sas_addr = &mvi->sas_addr[0];
 505
 506         sha->num_phys = nr_core * chip_info->n_phy;
 507
 508         if (mvi->flags & MVF_FLAG_SOC)
 509                 can_queue = MVS_SOC_CAN_QUEUE;
 510         else
 511                 can_queue = MVS_CHIP_SLOT_SZ;
 512
 513         shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG);
 514         shost->can_queue = can_queue;
 515         mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE;
 516         sha->core.shost = mvi->shost;
 517 }
 518
 519 static void mvs_init_sas_add(struct mvs_info *mvi)
 520 {
 521         u8 i;
 522         for (i = 0; i < mvi->chip->n_phy; i++) {
 523                 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL;
 524                 mvi->phy[i].dev_sas_addr =
 525                         cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr));
 526         }
 527
 528         memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE);
 529 }
 530
 531 static int mvs_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent)
 532 {
 533         unsigned int rc, nhost = 0;
 534         struct mvs_info *mvi;
 535         struct mvs_prv_info *mpi;
 536         irq_handler_t irq_handler = mvs_interrupt;
 537         struct Scsi_Host *shost = NULL;
 538         const struct mvs_chip_info *chip;
 539
 540         dev_printk(KERN_INFO, &pdev->dev,
 541                 "mvsas: driver version %s\n", DRV_VERSION);
 542         rc = pci_enable_device(pdev);
 543         if (rc)
 544                 goto err_out_enable;
 545
 546         pci_set_master(pdev);
 547
 548         rc = pci_request_regions(pdev, DRV_NAME);
 549         if (rc)
 550                 goto err_out_disable;
 551
 552         rc = pci_go_64(pdev);
 553         if (rc)
 554                 goto err_out_regions;
 555
 556         shost = scsi_host_alloc(&mvs_sht, sizeof(void *));
 557         if (!shost) {
 558                 rc = -ENOMEM;
 559                 goto err_out_regions;
 560         }
 561
 562         chip = &mvs_chips[ent->driver_data];
 563         SHOST_TO_SAS_HA(shost) =
 564                 kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL);
 565         if (!SHOST_TO_SAS_HA(shost)) {
 566                 kfree(shost);
 567                 rc = -ENOMEM;
 568                 goto err_out_regions;
 569         }
 570
 571         rc = mvs_prep_sas_ha_init(shost, chip);
 572         if (rc) {
 573                 kfree(shost);
 574                 rc = -ENOMEM;
 575                 goto err_out_regions;
 576         }
 577
 578         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
 579
 580         do {
 581                 mvi = mvs_pci_alloc(pdev, ent, shost, nhost);
 582                 if (!mvi) {
 583                         rc = -ENOMEM;
 584                         goto err_out_regions;
 585                 }
 586
 587                 memset(&mvi->hba_info_param, 0xFF,
 588                         sizeof(struct hba_info_page));
 589
 590                 mvs_init_sas_add(mvi);
 591
 592                 mvi->instance = nhost;
 593                 rc = MVS_CHIP_DISP->chip_init(mvi);
 594                 if (rc) {
 595                         mvs_free(mvi);
 596                         goto err_out_regions;
 597                 }
 598                 nhost++;
 599         } while (nhost < chip->n_host);
 600         mpi = (struct mvs_prv_info *)(SHOST_TO_SAS_HA(shost)->lldd_ha);
 601 #ifdef CONFIG_SCSI_MVSAS_TASKLET
 602         tasklet_init(&(mpi->mv_tasklet), mvs_tasklet,
 603                      (unsigned long)SHOST_TO_SAS_HA(shost));
 604 #endif
 605
 606         mvs_post_sas_ha_init(shost, chip);
 607
 608         rc = scsi_add_host(shost, &pdev->dev);
 609         if (rc)
 610                 goto err_out_shost;
 611
 612         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
 613         if (rc)
 614                 goto err_out_shost;
 615         rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED,
 616                 DRV_NAME, SHOST_TO_SAS_HA(shost));
 617         if (rc)
 618                 goto err_not_sas;
 619
 620         MVS_CHIP_DISP->interrupt_enable(mvi);
 621
 622         scsi_scan_host(mvi->shost);
 623
 624         return 0;
 625
 626 err_not_sas:
 627         sas_unregister_ha(SHOST_TO_SAS_HA(shost));
 628 err_out_shost:
 629         scsi_remove_host(mvi->shost);
 630 err_out_regions:
 631         pci_release_regions(pdev);
 632 err_out_disable:
 633         pci_disable_device(pdev);
 634 err_out_enable:
 635         return rc;
 636 }
 637
 638 static void mvs_pci_remove(struct pci_dev *pdev)
 639 {
 640         unsigned short core_nr, i = 0;
 641         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
 642         struct mvs_info *mvi = NULL;
 643
 644         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 645         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
 646
 647 #ifdef CONFIG_SCSI_MVSAS_TASKLET
 648         tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
 649 #endif
 650
 651         sas_unregister_ha(sha);
 652         sas_remove_host(mvi->shost);
 653         scsi_remove_host(mvi->shost);
 654
 655         MVS_CHIP_DISP->interrupt_disable(mvi);
 656         free_irq(mvi->pdev->irq, sha);
 657         for (i = 0; i < core_nr; i++) {
 658                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
 659                 mvs_free(mvi);
 660         }
 661         kfree(sha->sas_phy);
 662         kfree(sha->sas_port);
 663         kfree(sha);
 664         pci_release_regions(pdev);
 665         pci_disable_device(pdev);
 666         return;
 667 }
 668
 669 static struct pci_device_id mvs_pci_table[] = {
 670         { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 },
 671         { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 },
 672         {
 673                 .vendor         = PCI_VENDOR_ID_MARVELL,
 674                 .device         = 0x6440,
 675                 .subvendor      = PCI_ANY_ID,
 676                 .subdevice      = 0x6480,
 677                 .class          = 0,
 678                 .class_mask     = 0,
 679                 .driver_data    = chip_6485,
 680         },
 681         { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 },
 682         { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 },
 683         { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 },
 684         { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 },
 685         { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 },
 686         { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 },
 687         { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 },
 688         { PCI_VDEVICE(TTI, 0x2710), chip_9480 },
 689         { PCI_VDEVICE(TTI, 0x2720), chip_9480 },
 690         { PCI_VDEVICE(TTI, 0x2721), chip_9480 },
 691         { PCI_VDEVICE(TTI, 0x2722), chip_9480 },
 692         { PCI_VDEVICE(TTI, 0x2740), chip_9480 },
 693         { PCI_VDEVICE(TTI, 0x2744), chip_9480 },
 694         { PCI_VDEVICE(TTI, 0x2760), chip_9480 },
 695         {
 696                 .vendor         = PCI_VENDOR_ID_MARVELL_EXT,
 697                 .device         = 0x9480,
 698                 .subvendor      = PCI_ANY_ID,
 699                 .subdevice      = 0x9480,
 700                 .class          = 0,
 701                 .class_mask     = 0,
 702                 .driver_data    = chip_9480,
 703         },
 704         {
 705                 .vendor         = PCI_VENDOR_ID_MARVELL_EXT,
 706                 .device         = 0x9445,
 707                 .subvendor      = PCI_ANY_ID,
 708                 .subdevice      = 0x9480,
 709                 .class          = 0,
 710                 .class_mask     = 0,
 711                 .driver_data    = chip_9445,
 712         },
 713         {
 714                 .vendor         = PCI_VENDOR_ID_MARVELL_EXT,
 715                 .device         = 0x9485,
 716                 .subvendor      = PCI_ANY_ID,
 717                 .subdevice      = 0x9480,
 718                 .class          = 0,
 719                 .class_mask     = 0,
 720                 .driver_data    = chip_9485,
 721         },
 722         {
 723                 .vendor         = PCI_VENDOR_ID_MARVELL_EXT,
 724                 .device         = 0x9485,
 725                 .subvendor      = PCI_ANY_ID,
 726                 .subdevice      = 0x9485,
 727                 .class          = 0,
 728                 .class_mask     = 0,
 729                 .driver_data    = chip_9485,
 730         },
 731         { PCI_VDEVICE(OCZ, 0x1021), chip_9485}, /* OCZ RevoDrive3 */
 732         { PCI_VDEVICE(OCZ, 0x1022), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 733         { PCI_VDEVICE(OCZ, 0x1040), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 734         { PCI_VDEVICE(OCZ, 0x1041), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 735         { PCI_VDEVICE(OCZ, 0x1042), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 736         { PCI_VDEVICE(OCZ, 0x1043), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 737         { PCI_VDEVICE(OCZ, 0x1044), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 738         { PCI_VDEVICE(OCZ, 0x1080), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 739         { PCI_VDEVICE(OCZ, 0x1083), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 740         { PCI_VDEVICE(OCZ, 0x1084), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 741
 742         { }     /* terminate list */
 743 };
 744
 745 static struct pci_driver mvs_pci_driver = {
 746         .name           = DRV_NAME,
 747         .id_table       = mvs_pci_table,
 748         .probe          = mvs_pci_init,
 749         .remove         = mvs_pci_remove,
 750 };
 751
 752 static ssize_t
 753 mvs_show_driver_version(struct device *cdev,
 754                 struct device_attribute *attr,  char *buffer)
 755 {
 756         return snprintf(buffer, PAGE_SIZE, "%s\n", DRV_VERSION);
 757 }
 758
 759 static DEVICE_ATTR(driver_version,
 760                          S_IRUGO,
 761                          mvs_show_driver_version,
 762                          NULL);
 763
 764 static ssize_t
 765 mvs_store_interrupt_coalescing(struct device *cdev,
 766                         struct device_attribute *attr,
 767                         const char *buffer, size_t size)
 768 {
 769         int val = 0;
 770         struct mvs_info *mvi = NULL;
 771         struct Scsi_Host *shost = class_to_shost(cdev);
 772         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 773         u8 i, core_nr;
 774         if (buffer == NULL)
 775                 return size;
 776
 777         if (sscanf(buffer, "%d", &val) != 1)
 778                 return -EINVAL;
 779
 780         if (val >= 0x10000) {
 781                 mv_dprintk("interrupt coalescing timer %d us is"
 782                         "too long\n", val);
 783                 return strlen(buffer);
 784         }
 785
 786         interrupt_coalescing = val;
 787
 788         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 789         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
 790
 791         if (unlikely(!mvi))
 792                 return -EINVAL;
 793
 794         for (i = 0; i < core_nr; i++) {
 795                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
 796                 if (MVS_CHIP_DISP->tune_interrupt)
 797                         MVS_CHIP_DISP->tune_interrupt(mvi,
 798                                 interrupt_coalescing);
 799         }
 800         mv_dprintk("set interrupt coalescing time to %d us\n",
 801                 interrupt_coalescing);
 802         return strlen(buffer);
 803 }
 804
 805 static ssize_t mvs_show_interrupt_coalescing(struct device *cdev,
 806                         struct device_attribute *attr, char *buffer)
 807 {
 808         return snprintf(buffer, PAGE_SIZE, "%d\n", interrupt_coalescing);
 809 }
 810
 811 static DEVICE_ATTR(interrupt_coalescing,
 812                          S_IRUGO|S_IWUSR,
 813                          mvs_show_interrupt_coalescing,
 814                          mvs_store_interrupt_coalescing);
 815
 816 /* task handler */
 817 struct task_struct *mvs_th;
 818 static int __init mvs_init(void)
 819 {
 820         int rc;
 821         mvs_stt = sas_domain_attach_transport(&mvs_transport_ops);
 822         if (!mvs_stt)
 823                 return -ENOMEM;
 824
 825         rc = pci_register_driver(&mvs_pci_driver);
 826         if (rc)
 827                 goto err_out;
 828
 829         return 0;
 830
 831 err_out:
 832         sas_release_transport(mvs_stt);
 833         return rc;
 834 }
 835
 836 static void __exit mvs_exit(void)
 837 {
 838         pci_unregister_driver(&mvs_pci_driver);
 839         sas_release_transport(mvs_stt);
 840 }
 841
 842 struct device_attribute *mvst_host_attrs[] = {
 843         &dev_attr_driver_version,
 844         &dev_attr_interrupt_coalescing,
 845         NULL,
 846 };
 847
 848 module_init(mvs_init);
 849 module_exit(mvs_exit);
 850
 851 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
 852 MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver");
 853 MODULE_VERSION(DRV_VERSION);
 854 MODULE_LICENSE("GPL");
 855 #ifdef CONFIG_PCI
 856 MODULE_DEVICE_TABLE(pci, mvs_pci_table);
 857 #endif