drivers/scsi/pm8001/pm80xx_hwi.c

   1 /*
   2  * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  * notice, this list of conditions, and the following disclaimer,
  12  * without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  * substantially similar to the "NO WARRANTY" disclaimer below
  15  * ("Disclaimer") and any redistribution must be conditioned upon
  16  * including a substantially similar Disclaimer requirement for further
  17  * binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  * of any contributors may be used to endorse or promote products derived
  20  * from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include <linux/slab.h>
  41  #include "pm8001_sas.h"
  42  #include "pm80xx_hwi.h"
  43  #include "pm8001_chips.h"
  44  #include "pm8001_ctl.h"
  45
  46 #define SMP_DIRECT 1
  47 #define SMP_INDIRECT 2
  48
  49
  50 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
  51 {
  52         u32 reg_val;
  53         unsigned long start;
  54         pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
  55         /* confirm the setting is written */
  56         start = jiffies + HZ; /* 1 sec */
  57         do {
  58                 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
  59         } while ((reg_val != shift_value) && time_before(jiffies, start));
  60         if (reg_val != shift_value) {
  61                 PM8001_FAIL_DBG(pm8001_ha,
  62                         pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
  63                         " = 0x%x\n", reg_val));
  64                 return -1;
  65         }
  66         return 0;
  67 }
  68
  69 void pm80xx_pci_mem_copy(struct pm8001_hba_info  *pm8001_ha, u32 soffset,
  70                                 const void *destination,
  71                                 u32 dw_count, u32 bus_base_number)
  72 {
  73         u32 index, value, offset;
  74         u32 *destination1;
  75         destination1 = (u32 *)destination;
  76
  77         for (index = 0; index < dw_count; index += 4, destination1++) {
  78                 offset = (soffset + index / 4);
  79                 if (offset < (64 * 1024)) {
  80                         value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
  81                         *destination1 =  cpu_to_le32(value);
  82                 }
  83         }
  84         return;
  85 }
  86
  87 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
  88         struct device_attribute *attr, char *buf)
  89 {
  90         struct Scsi_Host *shost = class_to_shost(cdev);
  91         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  92         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
  93         void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
  94         u32 accum_len , reg_val, index, *temp;
  95         unsigned long start;
  96         u8 *direct_data;
  97         char *fatal_error_data = buf;
  98
  99         pm8001_ha->forensic_info.data_buf.direct_data = buf;
 100         if (pm8001_ha->chip_id == chip_8001) {
 101                 pm8001_ha->forensic_info.data_buf.direct_data +=
 102                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 103                         "Not supported for SPC controller");
 104                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 105                         (char *)buf;
 106         }
 107         if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
 108                 PM8001_IO_DBG(pm8001_ha,
 109                 pm8001_printk("forensic_info TYPE_NON_FATAL..............\n"));
 110                 direct_data = (u8 *)fatal_error_data;
 111                 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
 112                 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
 113                 pm8001_ha->forensic_info.data_buf.read_len = 0;
 114
 115                 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
 116
 117                 /* start to get data */
 118                 /* Program the MEMBASE II Shifting Register with 0x00.*/
 119                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 120                                 pm8001_ha->fatal_forensic_shift_offset);
 121                 pm8001_ha->forensic_last_offset = 0;
 122                 pm8001_ha->forensic_fatal_step = 0;
 123                 pm8001_ha->fatal_bar_loc = 0;
 124         }
 125
 126         /* Read until accum_len is retrived */
 127         accum_len = pm8001_mr32(fatal_table_address,
 128                                 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
 129         PM8001_IO_DBG(pm8001_ha, pm8001_printk("accum_len 0x%x\n",
 130                                                 accum_len));
 131         if (accum_len == 0xFFFFFFFF) {
 132                 PM8001_IO_DBG(pm8001_ha,
 133                         pm8001_printk("Possible PCI issue 0x%x not expected\n",
 134                                 accum_len));
 135                 return -EIO;
 136         }
 137         if (accum_len == 0 || accum_len >= 0x100000) {
 138                 pm8001_ha->forensic_info.data_buf.direct_data +=
 139                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 140                                 "%08x ", 0xFFFFFFFF);
 141                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 142                         (char *)buf;
 143         }
 144         temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
 145         if (pm8001_ha->forensic_fatal_step == 0) {
 146 moreData:
 147                 if (pm8001_ha->forensic_info.data_buf.direct_data) {
 148                         /* Data is in bar, copy to host memory */
 149                         pm80xx_pci_mem_copy(pm8001_ha, pm8001_ha->fatal_bar_loc,
 150                          pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
 151                                 pm8001_ha->forensic_info.data_buf.direct_len ,
 152                                         1);
 153                 }
 154                 pm8001_ha->fatal_bar_loc +=
 155                         pm8001_ha->forensic_info.data_buf.direct_len;
 156                 pm8001_ha->forensic_info.data_buf.direct_offset +=
 157                         pm8001_ha->forensic_info.data_buf.direct_len;
 158                 pm8001_ha->forensic_last_offset +=
 159                         pm8001_ha->forensic_info.data_buf.direct_len;
 160                 pm8001_ha->forensic_info.data_buf.read_len =
 161                         pm8001_ha->forensic_info.data_buf.direct_len;
 162
 163                 if (pm8001_ha->forensic_last_offset  >= accum_len) {
 164                         pm8001_ha->forensic_info.data_buf.direct_data +=
 165                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 166                                 "%08x ", 3);
 167                         for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
 168                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 169                                         sprintf(pm8001_ha->
 170                                          forensic_info.data_buf.direct_data,
 171                                                 "%08x ", *(temp + index));
 172                         }
 173
 174                         pm8001_ha->fatal_bar_loc = 0;
 175                         pm8001_ha->forensic_fatal_step = 1;
 176                         pm8001_ha->fatal_forensic_shift_offset = 0;
 177                         pm8001_ha->forensic_last_offset = 0;
 178                         return (char *)pm8001_ha->
 179                                 forensic_info.data_buf.direct_data -
 180                                 (char *)buf;
 181                 }
 182                 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
 183                         pm8001_ha->forensic_info.data_buf.direct_data +=
 184                                 sprintf(pm8001_ha->
 185                                         forensic_info.data_buf.direct_data,
 186                                         "%08x ", 2);
 187                         for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
 188                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 189                                         sprintf(pm8001_ha->
 190                                         forensic_info.data_buf.direct_data,
 191                                         "%08x ", *(temp + index));
 192                         }
 193                         return (char *)pm8001_ha->
 194                                 forensic_info.data_buf.direct_data -
 195                                 (char *)buf;
 196                 }
 197
 198                 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
 199                 pm8001_ha->forensic_info.data_buf.direct_data +=
 200                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 201                                 "%08x ", 2);
 202                 for (index = 0; index < 256; index++) {
 203                         pm8001_ha->forensic_info.data_buf.direct_data +=
 204                                 sprintf(pm8001_ha->
 205                                         forensic_info.data_buf.direct_data,
 206                                                 "%08x ", *(temp + index));
 207                 }
 208                 pm8001_ha->fatal_forensic_shift_offset += 0x100;
 209                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 210                         pm8001_ha->fatal_forensic_shift_offset);
 211                 pm8001_ha->fatal_bar_loc = 0;
 212                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 213                         (char *)buf;
 214         }
 215         if (pm8001_ha->forensic_fatal_step == 1) {
 216                 pm8001_ha->fatal_forensic_shift_offset = 0;
 217                 /* Read 64K of the debug data. */
 218                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 219                         pm8001_ha->fatal_forensic_shift_offset);
 220                 pm8001_mw32(fatal_table_address,
 221                         MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
 222                                 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
 223
 224                 /* Poll FDDHSHK  until clear  */
 225                 start = jiffies + (2 * HZ); /* 2 sec */
 226
 227                 do {
 228                         reg_val = pm8001_mr32(fatal_table_address,
 229                                         MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
 230                 } while ((reg_val) && time_before(jiffies, start));
 231
 232                 if (reg_val != 0) {
 233                         PM8001_FAIL_DBG(pm8001_ha,
 234                         pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
 235                         " = 0x%x\n", reg_val));
 236                         return -EIO;
 237                 }
 238
 239                 /* Read the next 64K of the debug data. */
 240                 pm8001_ha->forensic_fatal_step = 0;
 241                 if (pm8001_mr32(fatal_table_address,
 242                         MPI_FATAL_EDUMP_TABLE_STATUS) !=
 243                                 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
 244                         pm8001_mw32(fatal_table_address,
 245                                 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 0);
 246                         goto moreData;
 247                 } else {
 248                         pm8001_ha->forensic_info.data_buf.direct_data +=
 249                                 sprintf(pm8001_ha->
 250                                         forensic_info.data_buf.direct_data,
 251                                                 "%08x ", 4);
 252                         pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF;
 253                         pm8001_ha->forensic_info.data_buf.direct_len =  0;
 254                         pm8001_ha->forensic_info.data_buf.direct_offset = 0;
 255                         pm8001_ha->forensic_info.data_buf.read_len = 0;
 256                 }
 257         }
 258
 259         return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 260                 (char *)buf;
 261 }
 262
 263 /**
 264  * read_main_config_table - read the configure table and save it.
 265  * @pm8001_ha: our hba card information
 266  */
 267 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
 268 {
 269         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 270
 271         pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature    =
 272                 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
 273         pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
 274                 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
 275         pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
 276                 pm8001_mr32(address, MAIN_FW_REVISION);
 277         pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io   =
 278                 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
 279         pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl      =
 280                 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
 281         pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
 282                 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
 283         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset   =
 284                 pm8001_mr32(address, MAIN_GST_OFFSET);
 285         pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
 286                 pm8001_mr32(address, MAIN_IBQ_OFFSET);
 287         pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
 288                 pm8001_mr32(address, MAIN_OBQ_OFFSET);
 289
 290         /* read Error Dump Offset and Length */
 291         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
 292                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
 293         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
 294                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
 295         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
 296                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
 297         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
 298                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
 299
 300         /* read GPIO LED settings from the configuration table */
 301         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
 302                 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
 303
 304         /* read analog Setting offset from the configuration table */
 305         pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
 306                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
 307
 308         pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
 309                 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
 310         pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
 311                 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
 312 }
 313
 314 /**
 315  * read_general_status_table - read the general status table and save it.
 316  * @pm8001_ha: our hba card information
 317  */
 318 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
 319 {
 320         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
 321         pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate   =
 322                         pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
 323         pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0   =
 324                         pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
 325         pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1   =
 326                         pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
 327         pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt          =
 328                         pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
 329         pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt           =
 330                         pm8001_mr32(address, GST_IOPTCNT_OFFSET);
 331         pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val     =
 332                         pm8001_mr32(address, GST_GPIO_INPUT_VAL);
 333         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
 334                         pm8001_mr32(address, GST_RERRINFO_OFFSET0);
 335         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
 336                         pm8001_mr32(address, GST_RERRINFO_OFFSET1);
 337         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
 338                         pm8001_mr32(address, GST_RERRINFO_OFFSET2);
 339         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
 340                         pm8001_mr32(address, GST_RERRINFO_OFFSET3);
 341         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
 342                         pm8001_mr32(address, GST_RERRINFO_OFFSET4);
 343         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
 344                         pm8001_mr32(address, GST_RERRINFO_OFFSET5);
 345         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
 346                         pm8001_mr32(address, GST_RERRINFO_OFFSET6);
 347         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
 348                          pm8001_mr32(address, GST_RERRINFO_OFFSET7);
 349 }
 350 /**
 351  * read_phy_attr_table - read the phy attribute table and save it.
 352  * @pm8001_ha: our hba card information
 353  */
 354 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
 355 {
 356         void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
 357         pm8001_ha->phy_attr_table.phystart1_16[0] =
 358                         pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
 359         pm8001_ha->phy_attr_table.phystart1_16[1] =
 360                         pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
 361         pm8001_ha->phy_attr_table.phystart1_16[2] =
 362                         pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
 363         pm8001_ha->phy_attr_table.phystart1_16[3] =
 364                         pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
 365         pm8001_ha->phy_attr_table.phystart1_16[4] =
 366                         pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
 367         pm8001_ha->phy_attr_table.phystart1_16[5] =
 368                         pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
 369         pm8001_ha->phy_attr_table.phystart1_16[6] =
 370                         pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
 371         pm8001_ha->phy_attr_table.phystart1_16[7] =
 372                         pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
 373         pm8001_ha->phy_attr_table.phystart1_16[8] =
 374                         pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
 375         pm8001_ha->phy_attr_table.phystart1_16[9] =
 376                         pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
 377         pm8001_ha->phy_attr_table.phystart1_16[10] =
 378                         pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
 379         pm8001_ha->phy_attr_table.phystart1_16[11] =
 380                         pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
 381         pm8001_ha->phy_attr_table.phystart1_16[12] =
 382                         pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
 383         pm8001_ha->phy_attr_table.phystart1_16[13] =
 384                         pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
 385         pm8001_ha->phy_attr_table.phystart1_16[14] =
 386                         pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
 387         pm8001_ha->phy_attr_table.phystart1_16[15] =
 388                         pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
 389
 390         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
 391                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
 392         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
 393                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
 394         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
 395                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
 396         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
 397                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
 398         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
 399                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
 400         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
 401                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
 402         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
 403                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
 404         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
 405                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
 406         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
 407                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
 408         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
 409                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
 410         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
 411                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
 412         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
 413                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
 414         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
 415                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
 416         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
 417                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
 418         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
 419                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
 420         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
 421                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
 422
 423 }
 424
 425 /**
 426  * read_inbnd_queue_table - read the inbound queue table and save it.
 427  * @pm8001_ha: our hba card information
 428  */
 429 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 430 {
 431         int i;
 432         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 433         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
 434                 u32 offset = i * 0x20;
 435                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 436                         get_pci_bar_index(pm8001_mr32(address,
 437                                 (offset + IB_PIPCI_BAR)));
 438                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 439                         pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
 440         }
 441 }
 442
 443 /**
 444  * read_outbnd_queue_table - read the outbound queue table and save it.
 445  * @pm8001_ha: our hba card information
 446  */
 447 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 448 {
 449         int i;
 450         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 451         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
 452                 u32 offset = i * 0x24;
 453                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 454                         get_pci_bar_index(pm8001_mr32(address,
 455                                 (offset + OB_CIPCI_BAR)));
 456                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 457                         pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
 458         }
 459 }
 460
 461 /**
 462  * init_default_table_values - init the default table.
 463  * @pm8001_ha: our hba card information
 464  */
 465 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 466 {
 467         int i;
 468         u32 offsetib, offsetob;
 469         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 470         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 471
 472         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr         =
 473                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 474         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr         =
 475                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 476         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size               =
 477                                                         PM8001_EVENT_LOG_SIZE;
 478         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity           = 0x01;
 479         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr     =
 480                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 481         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr     =
 482                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 483         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size           =
 484                                                         PM8001_EVENT_LOG_SIZE;
 485         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity       = 0x01;
 486         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt          = 0x01;
 487
 488         /* Disable end to end CRC checking */
 489         pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
 490
 491         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
 492                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 493                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
 494                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 495                         pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
 496                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 497                 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
 498                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 499                         (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
 500                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 501                         pm8001_ha->memoryMap.region[IB + i].total_len;
 502                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 503                         pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
 504                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 505                         pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
 506                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 507                         pm8001_ha->memoryMap.region[CI + i].virt_ptr;
 508                 offsetib = i * 0x20;
 509                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 510                         get_pci_bar_index(pm8001_mr32(addressib,
 511                                 (offsetib + 0x14)));
 512                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 513                         pm8001_mr32(addressib, (offsetib + 0x18));
 514                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 515                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 516         }
 517         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
 518                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 519                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
 520                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 521                         pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
 522                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 523                         pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
 524                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 525                         (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
 526                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 527                         pm8001_ha->memoryMap.region[OB + i].total_len;
 528                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 529                         pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
 530                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 531                         pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
 532                 /* interrupt vector based on oq */
 533                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
 534                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 535                         pm8001_ha->memoryMap.region[PI + i].virt_ptr;
 536                 offsetob = i * 0x24;
 537                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 538                         get_pci_bar_index(pm8001_mr32(addressob,
 539                         offsetob + 0x14));
 540                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 541                         pm8001_mr32(addressob, (offsetob + 0x18));
 542                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 543                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 544         }
 545 }
 546
 547 /**
 548  * update_main_config_table - update the main default table to the HBA.
 549  * @pm8001_ha: our hba card information
 550  */
 551 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 552 {
 553         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 554         pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
 555                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
 556         pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
 557                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
 558         pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
 559                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
 560         pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
 561                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
 562         pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
 563                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
 564         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
 565                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
 566         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
 567                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
 568         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
 569                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
 570         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
 571                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
 572         pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
 573                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
 574         pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
 575                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
 576
 577         /* SPCv specific */
 578         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
 579         /* Set GPIOLED to 0x2 for LED indicator */
 580         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
 581         pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
 582                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
 583
 584         pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
 585                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
 586         pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
 587                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
 588 }
 589
 590 /**
 591  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 592  * @pm8001_ha: our hba card information
 593  */
 594 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 595                                          int number)
 596 {
 597         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 598         u16 offset = number * 0x20;
 599         pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
 600                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 601         pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
 602                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 603         pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
 604                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 605         pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
 606                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 607         pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
 608                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 609 }
 610
 611 /**
 612  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 613  * @pm8001_ha: our hba card information
 614  */
 615 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 616                                                  int number)
 617 {
 618         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 619         u16 offset = number * 0x24;
 620         pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
 621                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 622         pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
 623                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 624         pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
 625                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 626         pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
 627                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 628         pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
 629                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 630         pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
 631                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 632 }
 633
 634 /**
 635  * mpi_init_check - check firmware initialization status.
 636  * @pm8001_ha: our hba card information
 637  */
 638 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 639 {
 640         u32 max_wait_count;
 641         u32 value;
 642         u32 gst_len_mpistate;
 643
 644         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 645         table is updated */
 646         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
 647         /* wait until Inbound DoorBell Clear Register toggled */
 648         if (IS_SPCV_12G(pm8001_ha->pdev)) {
 649                 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
 650         } else {
 651                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
 652         }
 653         do {
 654                 udelay(1);
 655                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 656                 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
 657         } while ((value != 0) && (--max_wait_count));
 658
 659         if (!max_wait_count)
 660                 return -1;
 661         /* check the MPI-State for initialization upto 100ms*/
 662         max_wait_count = 100 * 1000;/* 100 msec */
 663         do {
 664                 udelay(1);
 665                 gst_len_mpistate =
 666                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 667                                         GST_GSTLEN_MPIS_OFFSET);
 668         } while ((GST_MPI_STATE_INIT !=
 669                 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
 670         if (!max_wait_count)
 671                 return -1;
 672
 673         /* check MPI Initialization error */
 674         gst_len_mpistate = gst_len_mpistate >> 16;
 675         if (0x0000 != gst_len_mpistate)
 676                 return -1;
 677
 678         return 0;
 679 }
 680
 681 /**
 682  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
 683  * @pm8001_ha: our hba card information
 684  */
 685 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
 686 {
 687         u32 value;
 688         u32 max_wait_count;
 689         u32 max_wait_time;
 690         int ret = 0;
 691
 692         /* reset / PCIe ready */
 693         max_wait_time = max_wait_count = 100 * 1000;    /* 100 milli sec */
 694         do {
 695                 udelay(1);
 696                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 697         } while ((value == 0xFFFFFFFF) && (--max_wait_count));
 698
 699         /* check ila status */
 700         max_wait_time = max_wait_count = 1000 * 1000;   /* 1000 milli sec */
 701         do {
 702                 udelay(1);
 703                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 704         } while (((value & SCRATCH_PAD_ILA_READY) !=
 705                         SCRATCH_PAD_ILA_READY) && (--max_wait_count));
 706         if (!max_wait_count)
 707                 ret = -1;
 708         else {
 709                 PM8001_MSG_DBG(pm8001_ha,
 710                         pm8001_printk(" ila ready status in %d millisec\n",
 711                                 (max_wait_time - max_wait_count)));
 712         }
 713
 714         /* check RAAE status */
 715         max_wait_time = max_wait_count = 1800 * 1000;   /* 1800 milli sec */
 716         do {
 717                 udelay(1);
 718                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 719         } while (((value & SCRATCH_PAD_RAAE_READY) !=
 720                                 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
 721         if (!max_wait_count)
 722                 ret = -1;
 723         else {
 724                 PM8001_MSG_DBG(pm8001_ha,
 725                         pm8001_printk(" raae ready status in %d millisec\n",
 726                                         (max_wait_time - max_wait_count)));
 727         }
 728
 729         /* check iop0 status */
 730         max_wait_time = max_wait_count = 600 * 1000;    /* 600 milli sec */
 731         do {
 732                 udelay(1);
 733                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 734         } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
 735                         (--max_wait_count));
 736         if (!max_wait_count)
 737                 ret = -1;
 738         else {
 739                 PM8001_MSG_DBG(pm8001_ha,
 740                         pm8001_printk(" iop0 ready status in %d millisec\n",
 741                                 (max_wait_time - max_wait_count)));
 742         }
 743
 744         /* check iop1 status only for 16 port controllers */
 745         if ((pm8001_ha->chip_id != chip_8008) &&
 746                         (pm8001_ha->chip_id != chip_8009)) {
 747                 /* 200 milli sec */
 748                 max_wait_time = max_wait_count = 200 * 1000;
 749                 do {
 750                         udelay(1);
 751                         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 752                 } while (((value & SCRATCH_PAD_IOP1_READY) !=
 753                                 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
 754                 if (!max_wait_count)
 755                         ret = -1;
 756                 else {
 757                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
 758                                 "iop1 ready status in %d millisec\n",
 759                                 (max_wait_time - max_wait_count)));
 760                 }
 761         }
 762
 763         return ret;
 764 }
 765
 766 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
 767 {
 768         void __iomem *base_addr;
 769         u32     value;
 770         u32     offset;
 771         u32     pcibar;
 772         u32     pcilogic;
 773
 774         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 775         offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
 776
 777         PM8001_INIT_DBG(pm8001_ha,
 778                 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
 779                                 offset, value));
 780         pcilogic = (value & 0xFC000000) >> 26;
 781         pcibar = get_pci_bar_index(pcilogic);
 782         PM8001_INIT_DBG(pm8001_ha,
 783                 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
 784         pm8001_ha->main_cfg_tbl_addr = base_addr =
 785                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
 786         pm8001_ha->general_stat_tbl_addr =
 787                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
 788                                         0xFFFFFF);
 789         pm8001_ha->inbnd_q_tbl_addr =
 790                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
 791                                         0xFFFFFF);
 792         pm8001_ha->outbnd_q_tbl_addr =
 793                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
 794                                         0xFFFFFF);
 795         pm8001_ha->ivt_tbl_addr =
 796                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
 797                                         0xFFFFFF);
 798         pm8001_ha->pspa_q_tbl_addr =
 799                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
 800                                         0xFFFFFF);
 801         pm8001_ha->fatal_tbl_addr =
 802                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
 803                                         0xFFFFFF);
 804
 805         PM8001_INIT_DBG(pm8001_ha,
 806                         pm8001_printk("GST OFFSET 0x%x\n",
 807                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
 808         PM8001_INIT_DBG(pm8001_ha,
 809                         pm8001_printk("INBND OFFSET 0x%x\n",
 810                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
 811         PM8001_INIT_DBG(pm8001_ha,
 812                         pm8001_printk("OBND OFFSET 0x%x\n",
 813                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
 814         PM8001_INIT_DBG(pm8001_ha,
 815                         pm8001_printk("IVT OFFSET 0x%x\n",
 816                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
 817         PM8001_INIT_DBG(pm8001_ha,
 818                         pm8001_printk("PSPA OFFSET 0x%x\n",
 819                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
 820         PM8001_INIT_DBG(pm8001_ha,
 821                         pm8001_printk("addr - main cfg %p general status %p\n",
 822                         pm8001_ha->main_cfg_tbl_addr,
 823                         pm8001_ha->general_stat_tbl_addr));
 824         PM8001_INIT_DBG(pm8001_ha,
 825                         pm8001_printk("addr - inbnd %p obnd %p\n",
 826                         pm8001_ha->inbnd_q_tbl_addr,
 827                         pm8001_ha->outbnd_q_tbl_addr));
 828         PM8001_INIT_DBG(pm8001_ha,
 829                         pm8001_printk("addr - pspa %p ivt %p\n",
 830                         pm8001_ha->pspa_q_tbl_addr,
 831                         pm8001_ha->ivt_tbl_addr));
 832 }
 833
 834 /**
 835  * pm80xx_set_thermal_config - support the thermal configuration
 836  * @pm8001_ha: our hba card information.
 837  */
 838 int
 839 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
 840 {
 841         struct set_ctrl_cfg_req payload;
 842         struct inbound_queue_table *circularQ;
 843         int rc;
 844         u32 tag;
 845         u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
 846
 847         memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
 848         rc = pm8001_tag_alloc(pm8001_ha, &tag);
 849         if (rc)
 850                 return -1;
 851
 852         circularQ = &pm8001_ha->inbnd_q_tbl[0];
 853         payload.tag = cpu_to_le32(tag);
 854         payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
 855                         (THERMAL_ENABLE << 8) | THERMAL_OP_CODE;
 856         payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);
 857
 858         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
 859         if (rc)
 860                 pm8001_tag_free(pm8001_ha, tag);
 861         return rc;
 862
 863 }
 864
 865 /**
 866 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
 867 * Timer configuration page
 868 * @pm8001_ha: our hba card information.
 869 */
 870 static int
 871 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
 872 {
 873         struct set_ctrl_cfg_req payload;
 874         struct inbound_queue_table *circularQ;
 875         SASProtocolTimerConfig_t SASConfigPage;
 876         int rc;
 877         u32 tag;
 878         u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
 879
 880         memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
 881         memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
 882
 883         rc = pm8001_tag_alloc(pm8001_ha, &tag);
 884
 885         if (rc)
 886                 return -1;
 887
 888         circularQ = &pm8001_ha->inbnd_q_tbl[0];
 889         payload.tag = cpu_to_le32(tag);
 890
 891         SASConfigPage.pageCode        =  SAS_PROTOCOL_TIMER_CONFIG_PAGE;
 892         SASConfigPage.MST_MSI         =  3 << 15;
 893         SASConfigPage.STP_SSP_MCT_TMO =  (STP_MCT_TMO << 16) | SSP_MCT_TMO;
 894         SASConfigPage.STP_FRM_TMO     = (SAS_MAX_OPEN_TIME << 24) |
 895                                 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
 896         SASConfigPage.STP_IDLE_TMO    =  STP_IDLE_TIME;
 897
 898         if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
 899                 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;
 900
 901
 902         SASConfigPage.OPNRJT_RTRY_INTVL =         (SAS_MFD << 16) |
 903                                                 SAS_OPNRJT_RTRY_INTVL;
 904         SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO =  (SAS_DOPNRJT_RTRY_TMO << 16)
 905                                                 | SAS_COPNRJT_RTRY_TMO;
 906         SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR =  (SAS_DOPNRJT_RTRY_THR << 16)
 907                                                 | SAS_COPNRJT_RTRY_THR;
 908         SASConfigPage.MAX_AIP =  SAS_MAX_AIP;
 909
 910         PM8001_INIT_DBG(pm8001_ha,
 911                         pm8001_printk("SASConfigPage.pageCode "
 912                         "0x%08x\n", SASConfigPage.pageCode));
 913         PM8001_INIT_DBG(pm8001_ha,
 914                         pm8001_printk("SASConfigPage.MST_MSI "
 915                         " 0x%08x\n", SASConfigPage.MST_MSI));
 916         PM8001_INIT_DBG(pm8001_ha,
 917                         pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO "
 918                         " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO));
 919         PM8001_INIT_DBG(pm8001_ha,
 920                         pm8001_printk("SASConfigPage.STP_FRM_TMO "
 921                         " 0x%08x\n", SASConfigPage.STP_FRM_TMO));
 922         PM8001_INIT_DBG(pm8001_ha,
 923                         pm8001_printk("SASConfigPage.STP_IDLE_TMO "
 924                         " 0x%08x\n", SASConfigPage.STP_IDLE_TMO));
 925         PM8001_INIT_DBG(pm8001_ha,
 926                         pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL "
 927                         " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL));
 928         PM8001_INIT_DBG(pm8001_ha,
 929                         pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO "
 930                         " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
 931         PM8001_INIT_DBG(pm8001_ha,
 932                         pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR "
 933                         " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
 934         PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP "
 935                         " 0x%08x\n", SASConfigPage.MAX_AIP));
 936
 937         memcpy(&payload.cfg_pg, &SASConfigPage,
 938                          sizeof(SASProtocolTimerConfig_t));
 939
 940         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
 941         if (rc)
 942                 pm8001_tag_free(pm8001_ha, tag);
 943
 944         return rc;
 945 }
 946
 947 /**
 948  * pm80xx_get_encrypt_info - Check for encryption
 949  * @pm8001_ha: our hba card information.
 950  */
 951 static int
 952 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
 953 {
 954         u32 scratch3_value;
 955         int ret;
 956
 957         /* Read encryption status from SCRATCH PAD 3 */
 958         scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
 959
 960         if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
 961                                         SCRATCH_PAD3_ENC_READY) {
 962                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
 963                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
 964                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 965                                                 SCRATCH_PAD3_SMF_ENABLED)
 966                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
 967                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 968                                                 SCRATCH_PAD3_SMA_ENABLED)
 969                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
 970                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 971                                                 SCRATCH_PAD3_SMB_ENABLED)
 972                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
 973                 pm8001_ha->encrypt_info.status = 0;
 974                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 975                         "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
 976                         "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
 977                         scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
 978                         pm8001_ha->encrypt_info.sec_mode,
 979                         pm8001_ha->encrypt_info.status));
 980                 ret = 0;
 981         } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
 982                                         SCRATCH_PAD3_ENC_DISABLED) {
 983                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 984                         "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
 985                         scratch3_value));
 986                 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
 987                 pm8001_ha->encrypt_info.cipher_mode = 0;
 988                 pm8001_ha->encrypt_info.sec_mode = 0;
 989                 return 0;
 990         } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
 991                                 SCRATCH_PAD3_ENC_DIS_ERR) {
 992                 pm8001_ha->encrypt_info.status =
 993                         (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
 994                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
 995                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
 996                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 997                                         SCRATCH_PAD3_SMF_ENABLED)
 998                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
 999                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1000                                         SCRATCH_PAD3_SMA_ENABLED)
1001                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1002                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1003                                         SCRATCH_PAD3_SMB_ENABLED)
1004                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1005                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1006                         "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
1007                         "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1008                         scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1009                         pm8001_ha->encrypt_info.sec_mode,
1010                         pm8001_ha->encrypt_info.status));
1011                 ret = -1;
1012         } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1013                                  SCRATCH_PAD3_ENC_ENA_ERR) {
1014
1015                 pm8001_ha->encrypt_info.status =
1016                         (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1017                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1018                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1019                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1020                                         SCRATCH_PAD3_SMF_ENABLED)
1021                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1022                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1023                                         SCRATCH_PAD3_SMA_ENABLED)
1024                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1025                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1026                                         SCRATCH_PAD3_SMB_ENABLED)
1027                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1028
1029                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1030                         "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
1031                         "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1032                         scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1033                         pm8001_ha->encrypt_info.sec_mode,
1034                         pm8001_ha->encrypt_info.status));
1035                 ret = -1;
1036         }
1037         return ret;
1038 }
1039
1040 /**
1041  * pm80xx_encrypt_update - update flash with encryption informtion
1042  * @pm8001_ha: our hba card information.
1043  */
1044 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1045 {
1046         struct kek_mgmt_req payload;
1047         struct inbound_queue_table *circularQ;
1048         int rc;
1049         u32 tag;
1050         u32 opc = OPC_INB_KEK_MANAGEMENT;
1051
1052         memset(&payload, 0, sizeof(struct kek_mgmt_req));
1053         rc = pm8001_tag_alloc(pm8001_ha, &tag);
1054         if (rc)
1055                 return -1;
1056
1057         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1058         payload.tag = cpu_to_le32(tag);
1059         /* Currently only one key is used. New KEK index is 1.
1060          * Current KEK index is 1. Store KEK to NVRAM is 1.
1061          */
1062         payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
1063                                         KEK_MGMT_SUBOP_KEYCARDUPDATE);
1064
1065         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
1066         if (rc)
1067                 pm8001_tag_free(pm8001_ha, tag);
1068
1069         return rc;
1070 }
1071
1072 /**
1073  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
1074  * @pm8001_ha: our hba card information
1075  */
1076 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1077 {
1078         int ret;
1079         u8 i = 0;
1080
1081         /* check the firmware status */
1082         if (-1 == check_fw_ready(pm8001_ha)) {
1083                 PM8001_FAIL_DBG(pm8001_ha,
1084                         pm8001_printk("Firmware is not ready!\n"));
1085                 return -EBUSY;
1086         }
1087
1088         /* Initialize pci space address eg: mpi offset */
1089         init_pci_device_addresses(pm8001_ha);
1090         init_default_table_values(pm8001_ha);
1091         read_main_config_table(pm8001_ha);
1092         read_general_status_table(pm8001_ha);
1093         read_inbnd_queue_table(pm8001_ha);
1094         read_outbnd_queue_table(pm8001_ha);
1095         read_phy_attr_table(pm8001_ha);
1096
1097         /* update main config table ,inbound table and outbound table */
1098         update_main_config_table(pm8001_ha);
1099         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++)
1100                 update_inbnd_queue_table(pm8001_ha, i);
1101         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++)
1102                 update_outbnd_queue_table(pm8001_ha, i);
1103
1104         /* notify firmware update finished and check initialization status */
1105         if (0 == mpi_init_check(pm8001_ha)) {
1106                 PM8001_INIT_DBG(pm8001_ha,
1107                         pm8001_printk("MPI initialize successful!\n"));
1108         } else
1109                 return -EBUSY;
1110
1111         /* send SAS protocol timer configuration page to FW */
1112         ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1113
1114         /* Check for encryption */
1115         if (pm8001_ha->chip->encrypt) {
1116                 PM8001_INIT_DBG(pm8001_ha,
1117                         pm8001_printk("Checking for encryption\n"));
1118                 ret = pm80xx_get_encrypt_info(pm8001_ha);
1119                 if (ret == -1) {
1120                         PM8001_INIT_DBG(pm8001_ha,
1121                                 pm8001_printk("Encryption error !!\n"));
1122                         if (pm8001_ha->encrypt_info.status == 0x81) {
1123                                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1124                                         "Encryption enabled with error."
1125                                         "Saving encryption key to flash\n"));
1126                                 pm80xx_encrypt_update(pm8001_ha);
1127                         }
1128                 }
1129         }
1130         return 0;
1131 }
1132
1133 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1134 {
1135         u32 max_wait_count;
1136         u32 value;
1137         u32 gst_len_mpistate;
1138         init_pci_device_addresses(pm8001_ha);
1139         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1140         table is stop */
1141         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1142
1143         /* wait until Inbound DoorBell Clear Register toggled */
1144         if (IS_SPCV_12G(pm8001_ha->pdev)) {
1145                 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
1146         } else {
1147                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1148         }
1149         do {
1150                 udelay(1);
1151                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1152                 value &= SPCv_MSGU_CFG_TABLE_RESET;
1153         } while ((value != 0) && (--max_wait_count));
1154
1155         if (!max_wait_count) {
1156                 PM8001_FAIL_DBG(pm8001_ha,
1157                         pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
1158                 return -1;
1159         }
1160
1161         /* check the MPI-State for termination in progress */
1162         /* wait until Inbound DoorBell Clear Register toggled */
1163         max_wait_count = 2 * 1000 * 1000;       /* 2 sec for spcv/ve */
1164         do {
1165                 udelay(1);
1166                 gst_len_mpistate =
1167                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1168                         GST_GSTLEN_MPIS_OFFSET);
1169                 if (GST_MPI_STATE_UNINIT ==
1170                         (gst_len_mpistate & GST_MPI_STATE_MASK))
1171                         break;
1172         } while (--max_wait_count);
1173         if (!max_wait_count) {
1174                 PM8001_FAIL_DBG(pm8001_ha,
1175                         pm8001_printk(" TIME OUT MPI State = 0x%x\n",
1176                                 gst_len_mpistate & GST_MPI_STATE_MASK));
1177                 return -1;
1178         }
1179
1180         return 0;
1181 }
1182
1183 /**
1184  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
1185  * the FW register status to the originated status.
1186  * @pm8001_ha: our hba card information
1187  */
1188
1189 static int
1190 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1191 {
1192         u32 regval;
1193         u32 bootloader_state;
1194         u32 ibutton0, ibutton1;
1195
1196         /* Check if MPI is in ready state to reset */
1197         if (mpi_uninit_check(pm8001_ha) != 0) {
1198                 PM8001_FAIL_DBG(pm8001_ha,
1199                         pm8001_printk("MPI state is not ready\n"));
1200                 return -1;
1201         }
1202
1203         /* checked for reset register normal state; 0x0 */
1204         regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1205         PM8001_INIT_DBG(pm8001_ha,
1206                 pm8001_printk("reset register before write : 0x%x\n", regval));
1207
1208         pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1209         mdelay(500);
1210
1211         regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1212         PM8001_INIT_DBG(pm8001_ha,
1213         pm8001_printk("reset register after write 0x%x\n", regval));
1214
1215         if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1216                         SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1217                 PM8001_MSG_DBG(pm8001_ha,
1218                         pm8001_printk(" soft reset successful [regval: 0x%x]\n",
1219                                         regval));
1220         } else {
1221                 PM8001_MSG_DBG(pm8001_ha,
1222                         pm8001_printk(" soft reset failed [regval: 0x%x]\n",
1223                                         regval));
1224
1225                 /* check bootloader is successfully executed or in HDA mode */
1226                 bootloader_state =
1227                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1228                         SCRATCH_PAD1_BOOTSTATE_MASK;
1229
1230                 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1231                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1232                                 "Bootloader state - HDA mode SEEPROM\n"));
1233                 } else if (bootloader_state ==
1234                                 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1235                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1236                                 "Bootloader state - HDA mode Bootstrap Pin\n"));
1237                 } else if (bootloader_state ==
1238                                 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1239                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1240                                 "Bootloader state - HDA mode soft reset\n"));
1241                 } else if (bootloader_state ==
1242                                         SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1243                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1244                                 "Bootloader state-HDA mode critical error\n"));
1245                 }
1246                 return -EBUSY;
1247         }
1248
1249         /* check the firmware status after reset */
1250         if (-1 == check_fw_ready(pm8001_ha)) {
1251                 PM8001_FAIL_DBG(pm8001_ha,
1252                         pm8001_printk("Firmware is not ready!\n"));
1253                 /* check iButton feature support for motherboard controller */
1254                 if (pm8001_ha->pdev->subsystem_vendor !=
1255                         PCI_VENDOR_ID_ADAPTEC2 &&
1256                         pm8001_ha->pdev->subsystem_vendor != 0) {
1257                         ibutton0 = pm8001_cr32(pm8001_ha, 0,
1258                                         MSGU_HOST_SCRATCH_PAD_6);
1259                         ibutton1 = pm8001_cr32(pm8001_ha, 0,
1260                                         MSGU_HOST_SCRATCH_PAD_7);
1261                         if (!ibutton0 && !ibutton1) {
1262                                 PM8001_FAIL_DBG(pm8001_ha,
1263                                         pm8001_printk("iButton Feature is"
1264                                         " not Available!!!\n"));
1265                                 return -EBUSY;
1266                         }
1267                         if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1268                                 PM8001_FAIL_DBG(pm8001_ha,
1269                                         pm8001_printk("CRC Check for iButton"
1270                                         " Feature Failed!!!\n"));
1271                                 return -EBUSY;
1272                         }
1273                 }
1274         }
1275         PM8001_INIT_DBG(pm8001_ha,
1276                 pm8001_printk("SPCv soft reset Complete\n"));
1277         return 0;
1278 }
1279
1280 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1281 {
1282          u32 i;
1283
1284         PM8001_INIT_DBG(pm8001_ha,
1285                 pm8001_printk("chip reset start\n"));
1286
1287         /* do SPCv chip reset. */
1288         pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1289         PM8001_INIT_DBG(pm8001_ha,
1290                 pm8001_printk("SPC soft reset Complete\n"));
1291
1292         /* Check this ..whether delay is required or no */
1293         /* delay 10 usec */
1294         udelay(10);
1295
1296         /* wait for 20 msec until the firmware gets reloaded */
1297         i = 20;
1298         do {
1299                 mdelay(1);
1300         } while ((--i) != 0);
1301
1302         PM8001_INIT_DBG(pm8001_ha,
1303                 pm8001_printk("chip reset finished\n"));
1304 }
1305
1306 /**
1307  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1308  * @pm8001_ha: our hba card information
1309  */
1310 static void
1311 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1312 {
1313         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1314         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1315 }
1316
1317 /**
1318  * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1319  * @pm8001_ha: our hba card information
1320  */
1321 static void
1322 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1323 {
1324         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1325 }
1326
1327 /**
1328  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1329  * @pm8001_ha: our hba card information
1330  */
1331 static void
1332 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1333 {
1334 #ifdef PM8001_USE_MSIX
1335         u32 mask;
1336         mask = (u32)(1 << vec);
1337
1338         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1339         return;
1340 #endif
1341         pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1342
1343 }
1344
1345 /**
1346  * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1347  * @pm8001_ha: our hba card information
1348  */
1349 static void
1350 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1351 {
1352 #ifdef PM8001_USE_MSIX
1353         u32 mask;
1354         if (vec == 0xFF)
1355                 mask = 0xFFFFFFFF;
1356         else
1357                 mask = (u32)(1 << vec);
1358         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1359         return;
1360 #endif
1361         pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1362 }
1363
1364 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1365                 struct pm8001_device *pm8001_ha_dev)
1366 {
1367         int res;
1368         u32 ccb_tag;
1369         struct pm8001_ccb_info *ccb;
1370         struct sas_task *task = NULL;
1371         struct task_abort_req task_abort;
1372         struct inbound_queue_table *circularQ;
1373         u32 opc = OPC_INB_SATA_ABORT;
1374         int ret;
1375
1376         if (!pm8001_ha_dev) {
1377                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1378                 return;
1379         }
1380
1381         task = sas_alloc_slow_task(GFP_ATOMIC);
1382
1383         if (!task) {
1384                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1385                                                 "allocate task\n"));
1386                 return;
1387         }
1388
1389         task->task_done = pm8001_task_done;
1390
1391         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1392         if (res) {
1393                 sas_free_task(task);
1394                 return;
1395         }
1396
1397         ccb = &pm8001_ha->ccb_info[ccb_tag];
1398         ccb->device = pm8001_ha_dev;
1399         ccb->ccb_tag = ccb_tag;
1400         ccb->task = task;
1401
1402         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1403
1404         memset(&task_abort, 0, sizeof(task_abort));
1405         task_abort.abort_all = cpu_to_le32(1);
1406         task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1407         task_abort.tag = cpu_to_le32(ccb_tag);
1408
1409         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
1410         if (ret) {
1411                 sas_free_task(task);
1412                 pm8001_tag_free(pm8001_ha, ccb_tag);
1413         }
1414 }
1415
1416 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1417                 struct pm8001_device *pm8001_ha_dev)
1418 {
1419         struct sata_start_req sata_cmd;
1420         int res;
1421         u32 ccb_tag;
1422         struct pm8001_ccb_info *ccb;
1423         struct sas_task *task = NULL;
1424         struct host_to_dev_fis fis;
1425         struct domain_device *dev;
1426         struct inbound_queue_table *circularQ;
1427         u32 opc = OPC_INB_SATA_HOST_OPSTART;
1428
1429         task = sas_alloc_slow_task(GFP_ATOMIC);
1430
1431         if (!task) {
1432                 PM8001_FAIL_DBG(pm8001_ha,
1433                         pm8001_printk("cannot allocate task !!!\n"));
1434                 return;
1435         }
1436         task->task_done = pm8001_task_done;
1437
1438         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1439         if (res) {
1440                 sas_free_task(task);
1441                 PM8001_FAIL_DBG(pm8001_ha,
1442                         pm8001_printk("cannot allocate tag !!!\n"));
1443                 return;
1444         }
1445
1446         /* allocate domain device by ourselves as libsas
1447          * is not going to provide any
1448         */
1449         dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1450         if (!dev) {
1451                 sas_free_task(task);
1452                 pm8001_tag_free(pm8001_ha, ccb_tag);
1453                 PM8001_FAIL_DBG(pm8001_ha,
1454                         pm8001_printk("Domain device cannot be allocated\n"));
1455                 return;
1456         }
1457
1458         task->dev = dev;
1459         task->dev->lldd_dev = pm8001_ha_dev;
1460
1461         ccb = &pm8001_ha->ccb_info[ccb_tag];
1462         ccb->device = pm8001_ha_dev;
1463         ccb->ccb_tag = ccb_tag;
1464         ccb->task = task;
1465         pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1466         pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1467
1468         memset(&sata_cmd, 0, sizeof(sata_cmd));
1469         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1470
1471         /* construct read log FIS */
1472         memset(&fis, 0, sizeof(struct host_to_dev_fis));
1473         fis.fis_type = 0x27;
1474         fis.flags = 0x80;
1475         fis.command = ATA_CMD_READ_LOG_EXT;
1476         fis.lbal = 0x10;
1477         fis.sector_count = 0x1;
1478
1479         sata_cmd.tag = cpu_to_le32(ccb_tag);
1480         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1481         sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9));
1482         memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1483
1484         res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
1485         if (res) {
1486                 sas_free_task(task);
1487                 pm8001_tag_free(pm8001_ha, ccb_tag);
1488                 kfree(dev);
1489         }
1490 }
1491
1492 /**
1493  * mpi_ssp_completion- process the event that FW response to the SSP request.
1494  * @pm8001_ha: our hba card information
1495  * @piomb: the message contents of this outbound message.
1496  *
1497  * When FW has completed a ssp request for example a IO request, after it has
1498  * filled the SG data with the data, it will trigger this event represent
1499  * that he has finished the job,please check the coresponding buffer.
1500  * So we will tell the caller who maybe waiting the result to tell upper layer
1501  * that the task has been finished.
1502  */
1503 static void
1504 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1505 {
1506         struct sas_task *t;
1507         struct pm8001_ccb_info *ccb;
1508         unsigned long flags;
1509         u32 status;
1510         u32 param;
1511         u32 tag;
1512         struct ssp_completion_resp *psspPayload;
1513         struct task_status_struct *ts;
1514         struct ssp_response_iu *iu;
1515         struct pm8001_device *pm8001_dev;
1516         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1517         status = le32_to_cpu(psspPayload->status);
1518         tag = le32_to_cpu(psspPayload->tag);
1519         ccb = &pm8001_ha->ccb_info[tag];
1520         if ((status == IO_ABORTED) && ccb->open_retry) {
1521                 /* Being completed by another */
1522                 ccb->open_retry = 0;
1523                 return;
1524         }
1525         pm8001_dev = ccb->device;
1526         param = le32_to_cpu(psspPayload->param);
1527         t = ccb->task;
1528
1529         if (status && status != IO_UNDERFLOW)
1530                 PM8001_FAIL_DBG(pm8001_ha,
1531                         pm8001_printk("sas IO status 0x%x\n", status));
1532         if (unlikely(!t || !t->lldd_task || !t->dev))
1533                 return;
1534         ts = &t->task_status;
1535         /* Print sas address of IO failed device */
1536         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1537                 (status != IO_UNDERFLOW))
1538                 PM8001_FAIL_DBG(pm8001_ha,
1539                         pm8001_printk("SAS Address of IO Failure Drive"
1540                         ":%016llx", SAS_ADDR(t->dev->sas_addr)));
1541
1542         switch (status) {
1543         case IO_SUCCESS:
1544                 PM8001_IO_DBG(pm8001_ha,
1545                         pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
1546                                 param));
1547                 if (param == 0) {
1548                         ts->resp = SAS_TASK_COMPLETE;
1549                         ts->stat = SAM_STAT_GOOD;
1550                 } else {
1551                         ts->resp = SAS_TASK_COMPLETE;
1552                         ts->stat = SAS_PROTO_RESPONSE;
1553                         ts->residual = param;
1554                         iu = &psspPayload->ssp_resp_iu;
1555                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1556                 }
1557                 if (pm8001_dev)
1558                         pm8001_dev->running_req--;
1559                 break;
1560         case IO_ABORTED:
1561                 PM8001_IO_DBG(pm8001_ha,
1562                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
1563                 ts->resp = SAS_TASK_COMPLETE;
1564                 ts->stat = SAS_ABORTED_TASK;
1565                 break;
1566         case IO_UNDERFLOW:
1567                 /* SSP Completion with error */
1568                 PM8001_IO_DBG(pm8001_ha,
1569                         pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
1570                                 param));
1571                 ts->resp = SAS_TASK_COMPLETE;
1572                 ts->stat = SAS_DATA_UNDERRUN;
1573                 ts->residual = param;
1574                 if (pm8001_dev)
1575                         pm8001_dev->running_req--;
1576                 break;
1577         case IO_NO_DEVICE:
1578                 PM8001_IO_DBG(pm8001_ha,
1579                         pm8001_printk("IO_NO_DEVICE\n"));
1580                 ts->resp = SAS_TASK_UNDELIVERED;
1581                 ts->stat = SAS_PHY_DOWN;
1582                 break;
1583         case IO_XFER_ERROR_BREAK:
1584                 PM8001_IO_DBG(pm8001_ha,
1585                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1586                 ts->resp = SAS_TASK_COMPLETE;
1587                 ts->stat = SAS_OPEN_REJECT;
1588                 /* Force the midlayer to retry */
1589                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1590                 break;
1591         case IO_XFER_ERROR_PHY_NOT_READY:
1592                 PM8001_IO_DBG(pm8001_ha,
1593                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1594                 ts->resp = SAS_TASK_COMPLETE;
1595                 ts->stat = SAS_OPEN_REJECT;
1596                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1597                 break;
1598         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1599                 PM8001_IO_DBG(pm8001_ha,
1600                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1601                 ts->resp = SAS_TASK_COMPLETE;
1602                 ts->stat = SAS_OPEN_REJECT;
1603                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1604                 break;
1605         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1606                 PM8001_IO_DBG(pm8001_ha,
1607                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1608                 ts->resp = SAS_TASK_COMPLETE;
1609                 ts->stat = SAS_OPEN_REJECT;
1610                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1611                 break;
1612         case IO_OPEN_CNX_ERROR_BREAK:
1613                 PM8001_IO_DBG(pm8001_ha,
1614                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1615                 ts->resp = SAS_TASK_COMPLETE;
1616                 ts->stat = SAS_OPEN_REJECT;
1617                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1618                 break;
1619         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1620         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1621         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1622         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1623         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1624         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1625                 PM8001_IO_DBG(pm8001_ha,
1626                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1627                 ts->resp = SAS_TASK_COMPLETE;
1628                 ts->stat = SAS_OPEN_REJECT;
1629                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1630                 if (!t->uldd_task)
1631                         pm8001_handle_event(pm8001_ha,
1632                                 pm8001_dev,
1633                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1634                 break;
1635         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1636                 PM8001_IO_DBG(pm8001_ha,
1637                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1638                 ts->resp = SAS_TASK_COMPLETE;
1639                 ts->stat = SAS_OPEN_REJECT;
1640                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1641                 break;
1642         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1643                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1644                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1645                 ts->resp = SAS_TASK_COMPLETE;
1646                 ts->stat = SAS_OPEN_REJECT;
1647                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1648                 break;
1649         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1650                 PM8001_IO_DBG(pm8001_ha,
1651                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1652                 ts->resp = SAS_TASK_UNDELIVERED;
1653                 ts->stat = SAS_OPEN_REJECT;
1654                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1655                 break;
1656         case IO_XFER_ERROR_NAK_RECEIVED:
1657                 PM8001_IO_DBG(pm8001_ha,
1658                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1659                 ts->resp = SAS_TASK_COMPLETE;
1660                 ts->stat = SAS_OPEN_REJECT;
1661                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1662                 break;
1663         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1664                 PM8001_IO_DBG(pm8001_ha,
1665                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1666                 ts->resp = SAS_TASK_COMPLETE;
1667                 ts->stat = SAS_NAK_R_ERR;
1668                 break;
1669         case IO_XFER_ERROR_DMA:
1670                 PM8001_IO_DBG(pm8001_ha,
1671                 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1672                 ts->resp = SAS_TASK_COMPLETE;
1673                 ts->stat = SAS_OPEN_REJECT;
1674                 break;
1675         case IO_XFER_OPEN_RETRY_TIMEOUT:
1676                 PM8001_IO_DBG(pm8001_ha,
1677                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1678                 ts->resp = SAS_TASK_COMPLETE;
1679                 ts->stat = SAS_OPEN_REJECT;
1680                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1681                 break;
1682         case IO_XFER_ERROR_OFFSET_MISMATCH:
1683                 PM8001_IO_DBG(pm8001_ha,
1684                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1685                 ts->resp = SAS_TASK_COMPLETE;
1686                 ts->stat = SAS_OPEN_REJECT;
1687                 break;
1688         case IO_PORT_IN_RESET:
1689                 PM8001_IO_DBG(pm8001_ha,
1690                         pm8001_printk("IO_PORT_IN_RESET\n"));
1691                 ts->resp = SAS_TASK_COMPLETE;
1692                 ts->stat = SAS_OPEN_REJECT;
1693                 break;
1694         case IO_DS_NON_OPERATIONAL:
1695                 PM8001_IO_DBG(pm8001_ha,
1696                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1697                 ts->resp = SAS_TASK_COMPLETE;
1698                 ts->stat = SAS_OPEN_REJECT;
1699                 if (!t->uldd_task)
1700                         pm8001_handle_event(pm8001_ha,
1701                                 pm8001_dev,
1702                                 IO_DS_NON_OPERATIONAL);
1703                 break;
1704         case IO_DS_IN_RECOVERY:
1705                 PM8001_IO_DBG(pm8001_ha,
1706                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
1707                 ts->resp = SAS_TASK_COMPLETE;
1708                 ts->stat = SAS_OPEN_REJECT;
1709                 break;
1710         case IO_TM_TAG_NOT_FOUND:
1711                 PM8001_IO_DBG(pm8001_ha,
1712                         pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1713                 ts->resp = SAS_TASK_COMPLETE;
1714                 ts->stat = SAS_OPEN_REJECT;
1715                 break;
1716         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1717                 PM8001_IO_DBG(pm8001_ha,
1718                         pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1719                 ts->resp = SAS_TASK_COMPLETE;
1720                 ts->stat = SAS_OPEN_REJECT;
1721                 break;
1722         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1723                 PM8001_IO_DBG(pm8001_ha,
1724                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1725                 ts->resp = SAS_TASK_COMPLETE;
1726                 ts->stat = SAS_OPEN_REJECT;
1727                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1728                 break;
1729         default:
1730                 PM8001_IO_DBG(pm8001_ha,
1731                         pm8001_printk("Unknown status 0x%x\n", status));
1732                 /* not allowed case. Therefore, return failed status */
1733                 ts->resp = SAS_TASK_COMPLETE;
1734                 ts->stat = SAS_OPEN_REJECT;
1735                 break;
1736         }
1737         PM8001_IO_DBG(pm8001_ha,
1738                 pm8001_printk("scsi_status = 0x%x\n ",
1739                 psspPayload->ssp_resp_iu.status));
1740         spin_lock_irqsave(&t->task_state_lock, flags);
1741         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1742         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1743         t->task_state_flags |= SAS_TASK_STATE_DONE;
1744         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1745                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1746                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1747                         "task 0x%p done with io_status 0x%x resp 0x%x "
1748                         "stat 0x%x but aborted by upper layer!\n",
1749                         t, status, ts->resp, ts->stat));
1750                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1751         } else {
1752                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1753                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1754                 mb();/* in order to force CPU ordering */
1755                 t->task_done(t);
1756         }
1757 }
1758
1759 /*See the comments for mpi_ssp_completion */
1760 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1761 {
1762         struct sas_task *t;
1763         unsigned long flags;
1764         struct task_status_struct *ts;
1765         struct pm8001_ccb_info *ccb;
1766         struct pm8001_device *pm8001_dev;
1767         struct ssp_event_resp *psspPayload =
1768                 (struct ssp_event_resp *)(piomb + 4);
1769         u32 event = le32_to_cpu(psspPayload->event);
1770         u32 tag = le32_to_cpu(psspPayload->tag);
1771         u32 port_id = le32_to_cpu(psspPayload->port_id);
1772
1773         ccb = &pm8001_ha->ccb_info[tag];
1774         t = ccb->task;
1775         pm8001_dev = ccb->device;
1776         if (event)
1777                 PM8001_FAIL_DBG(pm8001_ha,
1778                         pm8001_printk("sas IO status 0x%x\n", event));
1779         if (unlikely(!t || !t->lldd_task || !t->dev))
1780                 return;
1781         ts = &t->task_status;
1782         PM8001_IO_DBG(pm8001_ha,
1783                 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
1784                                 port_id, tag, event));
1785         switch (event) {
1786         case IO_OVERFLOW:
1787                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1788                 ts->resp = SAS_TASK_COMPLETE;
1789                 ts->stat = SAS_DATA_OVERRUN;
1790                 ts->residual = 0;
1791                 if (pm8001_dev)
1792                         pm8001_dev->running_req--;
1793                 break;
1794         case IO_XFER_ERROR_BREAK:
1795                 PM8001_IO_DBG(pm8001_ha,
1796                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1797                 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1798                 return;
1799         case IO_XFER_ERROR_PHY_NOT_READY:
1800                 PM8001_IO_DBG(pm8001_ha,
1801                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1802                 ts->resp = SAS_TASK_COMPLETE;
1803                 ts->stat = SAS_OPEN_REJECT;
1804                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1805                 break;
1806         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1807                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1808                         "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1809                 ts->resp = SAS_TASK_COMPLETE;
1810                 ts->stat = SAS_OPEN_REJECT;
1811                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1812                 break;
1813         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1814                 PM8001_IO_DBG(pm8001_ha,
1815                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1816                 ts->resp = SAS_TASK_COMPLETE;
1817                 ts->stat = SAS_OPEN_REJECT;
1818                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1819                 break;
1820         case IO_OPEN_CNX_ERROR_BREAK:
1821                 PM8001_IO_DBG(pm8001_ha,
1822                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1823                 ts->resp = SAS_TASK_COMPLETE;
1824                 ts->stat = SAS_OPEN_REJECT;
1825                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1826                 break;
1827         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1828         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1829         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1830         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1831         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1832         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1833                 PM8001_IO_DBG(pm8001_ha,
1834                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1835                 ts->resp = SAS_TASK_COMPLETE;
1836                 ts->stat = SAS_OPEN_REJECT;
1837                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1838                 if (!t->uldd_task)
1839                         pm8001_handle_event(pm8001_ha,
1840                                 pm8001_dev,
1841                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1842                 break;
1843         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1844                 PM8001_IO_DBG(pm8001_ha,
1845                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1846                 ts->resp = SAS_TASK_COMPLETE;
1847                 ts->stat = SAS_OPEN_REJECT;
1848                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1849                 break;
1850         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1851                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1852                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1853                 ts->resp = SAS_TASK_COMPLETE;
1854                 ts->stat = SAS_OPEN_REJECT;
1855                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1856                 break;
1857         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1858                 PM8001_IO_DBG(pm8001_ha,
1859                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1860                 ts->resp = SAS_TASK_COMPLETE;
1861                 ts->stat = SAS_OPEN_REJECT;
1862                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1863                 break;
1864         case IO_XFER_ERROR_NAK_RECEIVED:
1865                 PM8001_IO_DBG(pm8001_ha,
1866                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1867                 ts->resp = SAS_TASK_COMPLETE;
1868                 ts->stat = SAS_OPEN_REJECT;
1869                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1870                 break;
1871         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1872                 PM8001_IO_DBG(pm8001_ha,
1873                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1874                 ts->resp = SAS_TASK_COMPLETE;
1875                 ts->stat = SAS_NAK_R_ERR;
1876                 break;
1877         case IO_XFER_OPEN_RETRY_TIMEOUT:
1878                 PM8001_IO_DBG(pm8001_ha,
1879                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1880                 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
1881                 return;
1882         case IO_XFER_ERROR_UNEXPECTED_PHASE:
1883                 PM8001_IO_DBG(pm8001_ha,
1884                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1885                 ts->resp = SAS_TASK_COMPLETE;
1886                 ts->stat = SAS_DATA_OVERRUN;
1887                 break;
1888         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1889                 PM8001_IO_DBG(pm8001_ha,
1890                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1891                 ts->resp = SAS_TASK_COMPLETE;
1892                 ts->stat = SAS_DATA_OVERRUN;
1893                 break;
1894         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1895                 PM8001_IO_DBG(pm8001_ha,
1896                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1897                 ts->resp = SAS_TASK_COMPLETE;
1898                 ts->stat = SAS_DATA_OVERRUN;
1899                 break;
1900         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
1901                 PM8001_IO_DBG(pm8001_ha,
1902                 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
1903                 ts->resp = SAS_TASK_COMPLETE;
1904                 ts->stat = SAS_DATA_OVERRUN;
1905                 break;
1906         case IO_XFER_ERROR_OFFSET_MISMATCH:
1907                 PM8001_IO_DBG(pm8001_ha,
1908                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1909                 ts->resp = SAS_TASK_COMPLETE;
1910                 ts->stat = SAS_DATA_OVERRUN;
1911                 break;
1912         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1913                 PM8001_IO_DBG(pm8001_ha,
1914                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1915                 ts->resp = SAS_TASK_COMPLETE;
1916                 ts->stat = SAS_DATA_OVERRUN;
1917                 break;
1918         case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
1919                 PM8001_IO_DBG(pm8001_ha,
1920                         pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
1921                 /* TBC: used default set values */
1922                 ts->resp = SAS_TASK_COMPLETE;
1923                 ts->stat = SAS_DATA_OVERRUN;
1924                 break;
1925         case IO_XFER_CMD_FRAME_ISSUED:
1926                 PM8001_IO_DBG(pm8001_ha,
1927                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
1928                 return;
1929         default:
1930                 PM8001_IO_DBG(pm8001_ha,
1931                         pm8001_printk("Unknown status 0x%x\n", event));
1932                 /* not allowed case. Therefore, return failed status */
1933                 ts->resp = SAS_TASK_COMPLETE;
1934                 ts->stat = SAS_DATA_OVERRUN;
1935                 break;
1936         }
1937         spin_lock_irqsave(&t->task_state_lock, flags);
1938         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1939         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1940         t->task_state_flags |= SAS_TASK_STATE_DONE;
1941         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1942                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1943                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1944                         "task 0x%p done with event 0x%x resp 0x%x "
1945                         "stat 0x%x but aborted by upper layer!\n",
1946                         t, event, ts->resp, ts->stat));
1947                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1948         } else {
1949                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1950                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1951                 mb();/* in order to force CPU ordering */
1952                 t->task_done(t);
1953         }
1954 }
1955
1956 /*See the comments for mpi_ssp_completion */
1957 static void
1958 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1959 {
1960         struct sas_task *t;
1961         struct pm8001_ccb_info *ccb;
1962         u32 param;
1963         u32 status;
1964         u32 tag;
1965         int i, j;
1966         u8 sata_addr_low[4];
1967         u32 temp_sata_addr_low, temp_sata_addr_hi;
1968         u8 sata_addr_hi[4];
1969         struct sata_completion_resp *psataPayload;
1970         struct task_status_struct *ts;
1971         struct ata_task_resp *resp ;
1972         u32 *sata_resp;
1973         struct pm8001_device *pm8001_dev;
1974         unsigned long flags;
1975
1976         psataPayload = (struct sata_completion_resp *)(piomb + 4);
1977         status = le32_to_cpu(psataPayload->status);
1978         tag = le32_to_cpu(psataPayload->tag);
1979
1980         if (!tag) {
1981                 PM8001_FAIL_DBG(pm8001_ha,
1982                         pm8001_printk("tag null\n"));
1983                 return;
1984         }
1985         ccb = &pm8001_ha->ccb_info[tag];
1986         param = le32_to_cpu(psataPayload->param);
1987         if (ccb) {
1988                 t = ccb->task;
1989                 pm8001_dev = ccb->device;
1990         } else {
1991                 PM8001_FAIL_DBG(pm8001_ha,
1992                         pm8001_printk("ccb null\n"));
1993                 return;
1994         }
1995
1996         if (t) {
1997                 if (t->dev && (t->dev->lldd_dev))
1998                         pm8001_dev = t->dev->lldd_dev;
1999         } else {
2000                 PM8001_FAIL_DBG(pm8001_ha,
2001                         pm8001_printk("task null\n"));
2002                 return;
2003         }
2004
2005         if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2006                 && unlikely(!t || !t->lldd_task || !t->dev)) {
2007                 PM8001_FAIL_DBG(pm8001_ha,
2008                         pm8001_printk("task or dev null\n"));
2009                 return;
2010         }
2011
2012         ts = &t->task_status;
2013         if (!ts) {
2014                 PM8001_FAIL_DBG(pm8001_ha,
2015                         pm8001_printk("ts null\n"));
2016                 return;
2017         }
2018         /* Print sas address of IO failed device */
2019         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2020                 (status != IO_UNDERFLOW)) {
2021                 if (!((t->dev->parent) &&
2022                         (DEV_IS_EXPANDER(t->dev->parent->dev_type)))) {
2023                         for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++)
2024                                 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2025                         for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++)
2026                                 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2027                         memcpy(&temp_sata_addr_low, sata_addr_low,
2028                                 sizeof(sata_addr_low));
2029                         memcpy(&temp_sata_addr_hi, sata_addr_hi,
2030                                 sizeof(sata_addr_hi));
2031                         temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2032                                                 |((temp_sata_addr_hi << 8) &
2033                                                 0xff0000) |
2034                                                 ((temp_sata_addr_hi >> 8)
2035                                                 & 0xff00) |
2036                                                 ((temp_sata_addr_hi << 24) &
2037                                                 0xff000000));
2038                         temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2039                                                 & 0xff) |
2040                                                 ((temp_sata_addr_low << 8)
2041                                                 & 0xff0000) |
2042                                                 ((temp_sata_addr_low >> 8)
2043                                                 & 0xff00) |
2044                                                 ((temp_sata_addr_low << 24)
2045                                                 & 0xff000000)) +
2046                                                 pm8001_dev->attached_phy +
2047                                                 0x10);
2048                         PM8001_FAIL_DBG(pm8001_ha,
2049                                 pm8001_printk("SAS Address of IO Failure Drive:"
2050                                 "%08x%08x", temp_sata_addr_hi,
2051                                         temp_sata_addr_low));
2052
2053                 } else {
2054                         PM8001_FAIL_DBG(pm8001_ha,
2055                                 pm8001_printk("SAS Address of IO Failure Drive:"
2056                                 "%016llx", SAS_ADDR(t->dev->sas_addr)));
2057                 }
2058         }
2059         switch (status) {
2060         case IO_SUCCESS:
2061                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2062                 if (param == 0) {
2063                         ts->resp = SAS_TASK_COMPLETE;
2064                         ts->stat = SAM_STAT_GOOD;
2065                         /* check if response is for SEND READ LOG */
2066                         if (pm8001_dev &&
2067                                 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2068                                 /* set new bit for abort_all */
2069                                 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2070                                 /* clear bit for read log */
2071                                 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2072                                 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2073                                 /* Free the tag */
2074                                 pm8001_tag_free(pm8001_ha, tag);
2075                                 sas_free_task(t);
2076                                 return;
2077                         }
2078                 } else {
2079                         u8 len;
2080                         ts->resp = SAS_TASK_COMPLETE;
2081                         ts->stat = SAS_PROTO_RESPONSE;
2082                         ts->residual = param;
2083                         PM8001_IO_DBG(pm8001_ha,
2084                                 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2085                                 param));
2086                         sata_resp = &psataPayload->sata_resp[0];
2087                         resp = (struct ata_task_resp *)ts->buf;
2088                         if (t->ata_task.dma_xfer == 0 &&
2089                         t->data_dir == PCI_DMA_FROMDEVICE) {
2090                                 len = sizeof(struct pio_setup_fis);
2091                                 PM8001_IO_DBG(pm8001_ha,
2092                                 pm8001_printk("PIO read len = %d\n", len));
2093                         } else if (t->ata_task.use_ncq) {
2094                                 len = sizeof(struct set_dev_bits_fis);
2095                                 PM8001_IO_DBG(pm8001_ha,
2096                                         pm8001_printk("FPDMA len = %d\n", len));
2097                         } else {
2098                                 len = sizeof(struct dev_to_host_fis);
2099                                 PM8001_IO_DBG(pm8001_ha,
2100                                 pm8001_printk("other len = %d\n", len));
2101                         }
2102                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2103                                 resp->frame_len = len;
2104                                 memcpy(&resp->ending_fis[0], sata_resp, len);
2105                                 ts->buf_valid_size = sizeof(*resp);
2106                         } else
2107                                 PM8001_IO_DBG(pm8001_ha,
2108                                         pm8001_printk("response to large\n"));
2109                 }
2110                 if (pm8001_dev)
2111                         pm8001_dev->running_req--;
2112                 break;
2113         case IO_ABORTED:
2114                 PM8001_IO_DBG(pm8001_ha,
2115                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
2116                 ts->resp = SAS_TASK_COMPLETE;
2117                 ts->stat = SAS_ABORTED_TASK;
2118                 if (pm8001_dev)
2119                         pm8001_dev->running_req--;
2120                 break;
2121                 /* following cases are to do cases */
2122         case IO_UNDERFLOW:
2123                 /* SATA Completion with error */
2124                 PM8001_IO_DBG(pm8001_ha,
2125                         pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2126                 ts->resp = SAS_TASK_COMPLETE;
2127                 ts->stat = SAS_DATA_UNDERRUN;
2128                 ts->residual = param;
2129                 if (pm8001_dev)
2130                         pm8001_dev->running_req--;
2131                 break;
2132         case IO_NO_DEVICE:
2133                 PM8001_IO_DBG(pm8001_ha,
2134                         pm8001_printk("IO_NO_DEVICE\n"));
2135                 ts->resp = SAS_TASK_UNDELIVERED;
2136                 ts->stat = SAS_PHY_DOWN;
2137                 break;
2138         case IO_XFER_ERROR_BREAK:
2139                 PM8001_IO_DBG(pm8001_ha,
2140                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2141                 ts->resp = SAS_TASK_COMPLETE;
2142                 ts->stat = SAS_INTERRUPTED;
2143                 break;
2144         case IO_XFER_ERROR_PHY_NOT_READY:
2145                 PM8001_IO_DBG(pm8001_ha,
2146                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2147                 ts->resp = SAS_TASK_COMPLETE;
2148                 ts->stat = SAS_OPEN_REJECT;
2149                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2150                 break;
2151         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2152                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2153                         "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2154                 ts->resp = SAS_TASK_COMPLETE;
2155                 ts->stat = SAS_OPEN_REJECT;
2156                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2157                 break;
2158         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2159                 PM8001_IO_DBG(pm8001_ha,
2160                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2161                 ts->resp = SAS_TASK_COMPLETE;
2162                 ts->stat = SAS_OPEN_REJECT;
2163                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2164                 break;
2165         case IO_OPEN_CNX_ERROR_BREAK:
2166                 PM8001_IO_DBG(pm8001_ha,
2167                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2168                 ts->resp = SAS_TASK_COMPLETE;
2169                 ts->stat = SAS_OPEN_REJECT;
2170                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2171                 break;
2172         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2173         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2174         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2175         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2176         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2177         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2178                 PM8001_IO_DBG(pm8001_ha,
2179                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2180                 ts->resp = SAS_TASK_COMPLETE;
2181                 ts->stat = SAS_DEV_NO_RESPONSE;
2182                 if (!t->uldd_task) {
2183                         pm8001_handle_event(pm8001_ha,
2184                                 pm8001_dev,
2185                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2186                         ts->resp = SAS_TASK_UNDELIVERED;
2187                         ts->stat = SAS_QUEUE_FULL;
2188                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2189                         return;
2190                 }
2191                 break;
2192         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2193                 PM8001_IO_DBG(pm8001_ha,
2194                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2195                 ts->resp = SAS_TASK_UNDELIVERED;
2196                 ts->stat = SAS_OPEN_REJECT;
2197                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2198                 if (!t->uldd_task) {
2199                         pm8001_handle_event(pm8001_ha,
2200                                 pm8001_dev,
2201                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2202                         ts->resp = SAS_TASK_UNDELIVERED;
2203                         ts->stat = SAS_QUEUE_FULL;
2204                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2205                         return;
2206                 }
2207                 break;
2208         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2209                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2210                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2211                 ts->resp = SAS_TASK_COMPLETE;
2212                 ts->stat = SAS_OPEN_REJECT;
2213                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2214                 break;
2215         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2216                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2217                         "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
2218                 ts->resp = SAS_TASK_COMPLETE;
2219                 ts->stat = SAS_DEV_NO_RESPONSE;
2220                 if (!t->uldd_task) {
2221                         pm8001_handle_event(pm8001_ha,
2222                                 pm8001_dev,
2223                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2224                         ts->resp = SAS_TASK_UNDELIVERED;
2225                         ts->stat = SAS_QUEUE_FULL;
2226                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2227                         return;
2228                 }
2229                 break;
2230         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2231                 PM8001_IO_DBG(pm8001_ha,
2232                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2233                 ts->resp = SAS_TASK_COMPLETE;
2234                 ts->stat = SAS_OPEN_REJECT;
2235                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2236                 break;
2237         case IO_XFER_ERROR_NAK_RECEIVED:
2238                 PM8001_IO_DBG(pm8001_ha,
2239                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2240                 ts->resp = SAS_TASK_COMPLETE;
2241                 ts->stat = SAS_NAK_R_ERR;
2242                 break;
2243         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2244                 PM8001_IO_DBG(pm8001_ha,
2245                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2246                 ts->resp = SAS_TASK_COMPLETE;
2247                 ts->stat = SAS_NAK_R_ERR;
2248                 break;
2249         case IO_XFER_ERROR_DMA:
2250                 PM8001_IO_DBG(pm8001_ha,
2251                         pm8001_printk("IO_XFER_ERROR_DMA\n"));
2252                 ts->resp = SAS_TASK_COMPLETE;
2253                 ts->stat = SAS_ABORTED_TASK;
2254                 break;
2255         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2256                 PM8001_IO_DBG(pm8001_ha,
2257                         pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2258                 ts->resp = SAS_TASK_UNDELIVERED;
2259                 ts->stat = SAS_DEV_NO_RESPONSE;
2260                 break;
2261         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2262                 PM8001_IO_DBG(pm8001_ha,
2263                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2264                 ts->resp = SAS_TASK_COMPLETE;
2265                 ts->stat = SAS_DATA_UNDERRUN;
2266                 break;
2267         case IO_XFER_OPEN_RETRY_TIMEOUT:
2268                 PM8001_IO_DBG(pm8001_ha,
2269                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2270                 ts->resp = SAS_TASK_COMPLETE;
2271                 ts->stat = SAS_OPEN_TO;
2272                 break;
2273         case IO_PORT_IN_RESET:
2274                 PM8001_IO_DBG(pm8001_ha,
2275                         pm8001_printk("IO_PORT_IN_RESET\n"));
2276                 ts->resp = SAS_TASK_COMPLETE;
2277                 ts->stat = SAS_DEV_NO_RESPONSE;
2278                 break;
2279         case IO_DS_NON_OPERATIONAL:
2280                 PM8001_IO_DBG(pm8001_ha,
2281                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2282                 ts->resp = SAS_TASK_COMPLETE;
2283                 ts->stat = SAS_DEV_NO_RESPONSE;
2284                 if (!t->uldd_task) {
2285                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2286                                         IO_DS_NON_OPERATIONAL);
2287                         ts->resp = SAS_TASK_UNDELIVERED;
2288                         ts->stat = SAS_QUEUE_FULL;
2289                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2290                         return;
2291                 }
2292                 break;
2293         case IO_DS_IN_RECOVERY:
2294                 PM8001_IO_DBG(pm8001_ha,
2295                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2296                 ts->resp = SAS_TASK_COMPLETE;
2297                 ts->stat = SAS_DEV_NO_RESPONSE;
2298                 break;
2299         case IO_DS_IN_ERROR:
2300                 PM8001_IO_DBG(pm8001_ha,
2301                         pm8001_printk("IO_DS_IN_ERROR\n"));
2302                 ts->resp = SAS_TASK_COMPLETE;
2303                 ts->stat = SAS_DEV_NO_RESPONSE;
2304                 if (!t->uldd_task) {
2305                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2306                                         IO_DS_IN_ERROR);
2307                         ts->resp = SAS_TASK_UNDELIVERED;
2308                         ts->stat = SAS_QUEUE_FULL;
2309                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2310                         return;
2311                 }
2312                 break;
2313         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2314                 PM8001_IO_DBG(pm8001_ha,
2315                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2316                 ts->resp = SAS_TASK_COMPLETE;
2317                 ts->stat = SAS_OPEN_REJECT;
2318                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2319         default:
2320                 PM8001_IO_DBG(pm8001_ha,
2321                         pm8001_printk("Unknown status 0x%x\n", status));
2322                 /* not allowed case. Therefore, return failed status */
2323                 ts->resp = SAS_TASK_COMPLETE;
2324                 ts->stat = SAS_DEV_NO_RESPONSE;
2325                 break;
2326         }
2327         spin_lock_irqsave(&t->task_state_lock, flags);
2328         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2329         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2330         t->task_state_flags |= SAS_TASK_STATE_DONE;
2331         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2332                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2333                 PM8001_FAIL_DBG(pm8001_ha,
2334                         pm8001_printk("task 0x%p done with io_status 0x%x"
2335                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2336                         t, status, ts->resp, ts->stat));
2337                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2338         } else {
2339                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2340                 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2341         }
2342 }
2343
2344 /*See the comments for mpi_ssp_completion */
2345 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2346 {
2347         struct sas_task *t;
2348         struct task_status_struct *ts;
2349         struct pm8001_ccb_info *ccb;
2350         struct pm8001_device *pm8001_dev;
2351         struct sata_event_resp *psataPayload =
2352                 (struct sata_event_resp *)(piomb + 4);
2353         u32 event = le32_to_cpu(psataPayload->event);
2354         u32 tag = le32_to_cpu(psataPayload->tag);
2355         u32 port_id = le32_to_cpu(psataPayload->port_id);
2356         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2357         unsigned long flags;
2358
2359         ccb = &pm8001_ha->ccb_info[tag];
2360
2361         if (ccb) {
2362                 t = ccb->task;
2363                 pm8001_dev = ccb->device;
2364         } else {
2365                 PM8001_FAIL_DBG(pm8001_ha,
2366                         pm8001_printk("No CCB !!!. returning\n"));
2367                 return;
2368         }
2369         if (event)
2370                 PM8001_FAIL_DBG(pm8001_ha,
2371                         pm8001_printk("SATA EVENT 0x%x\n", event));
2372
2373         /* Check if this is NCQ error */
2374         if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2375                 /* find device using device id */
2376                 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2377                 /* send read log extension */
2378                 if (pm8001_dev)
2379                         pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2380                 return;
2381         }
2382
2383         if (unlikely(!t || !t->lldd_task || !t->dev)) {
2384                 PM8001_FAIL_DBG(pm8001_ha,
2385                         pm8001_printk("task or dev null\n"));
2386                 return;
2387         }
2388
2389         ts = &t->task_status;
2390         PM8001_IO_DBG(pm8001_ha,
2391                 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2392                                 port_id, tag, event));
2393         switch (event) {
2394         case IO_OVERFLOW:
2395                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2396                 ts->resp = SAS_TASK_COMPLETE;
2397                 ts->stat = SAS_DATA_OVERRUN;
2398                 ts->residual = 0;
2399                 if (pm8001_dev)
2400                         pm8001_dev->running_req--;
2401                 break;
2402         case IO_XFER_ERROR_BREAK:
2403                 PM8001_IO_DBG(pm8001_ha,
2404                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2405                 ts->resp = SAS_TASK_COMPLETE;
2406                 ts->stat = SAS_INTERRUPTED;
2407                 break;
2408         case IO_XFER_ERROR_PHY_NOT_READY:
2409                 PM8001_IO_DBG(pm8001_ha,
2410                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2411                 ts->resp = SAS_TASK_COMPLETE;
2412                 ts->stat = SAS_OPEN_REJECT;
2413                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2414                 break;
2415         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2416                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2417                         "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2418                 ts->resp = SAS_TASK_COMPLETE;
2419                 ts->stat = SAS_OPEN_REJECT;
2420                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2421                 break;
2422         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2423                 PM8001_IO_DBG(pm8001_ha,
2424                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2425                 ts->resp = SAS_TASK_COMPLETE;
2426                 ts->stat = SAS_OPEN_REJECT;
2427                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2428                 break;
2429         case IO_OPEN_CNX_ERROR_BREAK:
2430                 PM8001_IO_DBG(pm8001_ha,
2431                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2432                 ts->resp = SAS_TASK_COMPLETE;
2433                 ts->stat = SAS_OPEN_REJECT;
2434                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2435                 break;
2436         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2437         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2438         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2439         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2440         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2441         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2442                 PM8001_FAIL_DBG(pm8001_ha,
2443                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2444                 ts->resp = SAS_TASK_UNDELIVERED;
2445                 ts->stat = SAS_DEV_NO_RESPONSE;
2446                 if (!t->uldd_task) {
2447                         pm8001_handle_event(pm8001_ha,
2448                                 pm8001_dev,
2449                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2450                         ts->resp = SAS_TASK_COMPLETE;
2451                         ts->stat = SAS_QUEUE_FULL;
2452                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2453                         return;
2454                 }
2455                 break;
2456         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2457                 PM8001_IO_DBG(pm8001_ha,
2458                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2459                 ts->resp = SAS_TASK_UNDELIVERED;
2460                 ts->stat = SAS_OPEN_REJECT;
2461                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2462                 break;
2463         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2464                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2465                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2466                 ts->resp = SAS_TASK_COMPLETE;
2467                 ts->stat = SAS_OPEN_REJECT;
2468                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2469                 break;
2470         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2471                 PM8001_IO_DBG(pm8001_ha,
2472                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2473                 ts->resp = SAS_TASK_COMPLETE;
2474                 ts->stat = SAS_OPEN_REJECT;
2475                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2476                 break;
2477         case IO_XFER_ERROR_NAK_RECEIVED:
2478                 PM8001_IO_DBG(pm8001_ha,
2479                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2480                 ts->resp = SAS_TASK_COMPLETE;
2481                 ts->stat = SAS_NAK_R_ERR;
2482                 break;
2483         case IO_XFER_ERROR_PEER_ABORTED:
2484                 PM8001_IO_DBG(pm8001_ha,
2485                         pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2486                 ts->resp = SAS_TASK_COMPLETE;
2487                 ts->stat = SAS_NAK_R_ERR;
2488                 break;
2489         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2490                 PM8001_IO_DBG(pm8001_ha,
2491                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2492                 ts->resp = SAS_TASK_COMPLETE;
2493                 ts->stat = SAS_DATA_UNDERRUN;
2494                 break;
2495         case IO_XFER_OPEN_RETRY_TIMEOUT:
2496                 PM8001_IO_DBG(pm8001_ha,
2497                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2498                 ts->resp = SAS_TASK_COMPLETE;
2499                 ts->stat = SAS_OPEN_TO;
2500                 break;
2501         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2502                 PM8001_IO_DBG(pm8001_ha,
2503                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2504                 ts->resp = SAS_TASK_COMPLETE;
2505                 ts->stat = SAS_OPEN_TO;
2506                 break;
2507         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2508                 PM8001_IO_DBG(pm8001_ha,
2509                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2510                 ts->resp = SAS_TASK_COMPLETE;
2511                 ts->stat = SAS_OPEN_TO;
2512                 break;
2513         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2514                 PM8001_IO_DBG(pm8001_ha,
2515                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2516                 ts->resp = SAS_TASK_COMPLETE;
2517                 ts->stat = SAS_OPEN_TO;
2518                 break;
2519         case IO_XFER_ERROR_OFFSET_MISMATCH:
2520                 PM8001_IO_DBG(pm8001_ha,
2521                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2522                 ts->resp = SAS_TASK_COMPLETE;
2523                 ts->stat = SAS_OPEN_TO;
2524                 break;
2525         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2526                 PM8001_IO_DBG(pm8001_ha,
2527                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2528                 ts->resp = SAS_TASK_COMPLETE;
2529                 ts->stat = SAS_OPEN_TO;
2530                 break;
2531         case IO_XFER_CMD_FRAME_ISSUED:
2532                 PM8001_IO_DBG(pm8001_ha,
2533                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2534                 break;
2535         case IO_XFER_PIO_SETUP_ERROR:
2536                 PM8001_IO_DBG(pm8001_ha,
2537                         pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2538                 ts->resp = SAS_TASK_COMPLETE;
2539                 ts->stat = SAS_OPEN_TO;
2540                 break;
2541         case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2542                 PM8001_FAIL_DBG(pm8001_ha,
2543                         pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2544                 /* TBC: used default set values */
2545                 ts->resp = SAS_TASK_COMPLETE;
2546                 ts->stat = SAS_OPEN_TO;
2547                 break;
2548         case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2549                 PM8001_FAIL_DBG(pm8001_ha,
2550                         pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n"));
2551                 /* TBC: used default set values */
2552                 ts->resp = SAS_TASK_COMPLETE;
2553                 ts->stat = SAS_OPEN_TO;
2554                 break;
2555         default:
2556                 PM8001_IO_DBG(pm8001_ha,
2557                         pm8001_printk("Unknown status 0x%x\n", event));
2558                 /* not allowed case. Therefore, return failed status */
2559                 ts->resp = SAS_TASK_COMPLETE;
2560                 ts->stat = SAS_OPEN_TO;
2561                 break;
2562         }
2563         spin_lock_irqsave(&t->task_state_lock, flags);
2564         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2565         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2566         t->task_state_flags |= SAS_TASK_STATE_DONE;
2567         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2568                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2569                 PM8001_FAIL_DBG(pm8001_ha,
2570                         pm8001_printk("task 0x%p done with io_status 0x%x"
2571                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2572                         t, event, ts->resp, ts->stat));
2573                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2574         } else {
2575                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2576                 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2577         }
2578 }
2579
2580 /*See the comments for mpi_ssp_completion */
2581 static void
2582 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2583 {
2584         u32 param, i;
2585         struct sas_task *t;
2586         struct pm8001_ccb_info *ccb;
2587         unsigned long flags;
2588         u32 status;
2589         u32 tag;
2590         struct smp_completion_resp *psmpPayload;
2591         struct task_status_struct *ts;
2592         struct pm8001_device *pm8001_dev;
2593         char *pdma_respaddr = NULL;
2594
2595         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2596         status = le32_to_cpu(psmpPayload->status);
2597         tag = le32_to_cpu(psmpPayload->tag);
2598
2599         ccb = &pm8001_ha->ccb_info[tag];
2600         param = le32_to_cpu(psmpPayload->param);
2601         t = ccb->task;
2602         ts = &t->task_status;
2603         pm8001_dev = ccb->device;
2604         if (status)
2605                 PM8001_FAIL_DBG(pm8001_ha,
2606                         pm8001_printk("smp IO status 0x%x\n", status));
2607         if (unlikely(!t || !t->lldd_task || !t->dev))
2608                 return;
2609
2610         switch (status) {
2611
2612         case IO_SUCCESS:
2613                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2614                 ts->resp = SAS_TASK_COMPLETE;
2615                 ts->stat = SAM_STAT_GOOD;
2616                 if (pm8001_dev)
2617                         pm8001_dev->running_req--;
2618                 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2619                         PM8001_IO_DBG(pm8001_ha,
2620                                 pm8001_printk("DIRECT RESPONSE Length:%d\n",
2621                                                 param));
2622                         pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
2623                                                 ((u64)sg_dma_address
2624                                                 (&t->smp_task.smp_resp))));
2625                         for (i = 0; i < param; i++) {
2626                                 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
2627                                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2628                                         "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
2629                                         i, *(pdma_respaddr+i),
2630                                         psmpPayload->_r_a[i]));
2631                         }
2632                 }
2633                 break;
2634         case IO_ABORTED:
2635                 PM8001_IO_DBG(pm8001_ha,
2636                         pm8001_printk("IO_ABORTED IOMB\n"));
2637                 ts->resp = SAS_TASK_COMPLETE;
2638                 ts->stat = SAS_ABORTED_TASK;
2639                 if (pm8001_dev)
2640                         pm8001_dev->running_req--;
2641                 break;
2642         case IO_OVERFLOW:
2643                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2644                 ts->resp = SAS_TASK_COMPLETE;
2645                 ts->stat = SAS_DATA_OVERRUN;
2646                 ts->residual = 0;
2647                 if (pm8001_dev)
2648                         pm8001_dev->running_req--;
2649                 break;
2650         case IO_NO_DEVICE:
2651                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2652                 ts->resp = SAS_TASK_COMPLETE;
2653                 ts->stat = SAS_PHY_DOWN;
2654                 break;
2655         case IO_ERROR_HW_TIMEOUT:
2656                 PM8001_IO_DBG(pm8001_ha,
2657                         pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2658                 ts->resp = SAS_TASK_COMPLETE;
2659                 ts->stat = SAM_STAT_BUSY;
2660                 break;
2661         case IO_XFER_ERROR_BREAK:
2662                 PM8001_IO_DBG(pm8001_ha,
2663                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2664                 ts->resp = SAS_TASK_COMPLETE;
2665                 ts->stat = SAM_STAT_BUSY;
2666                 break;
2667         case IO_XFER_ERROR_PHY_NOT_READY:
2668                 PM8001_IO_DBG(pm8001_ha,
2669                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2670                 ts->resp = SAS_TASK_COMPLETE;
2671                 ts->stat = SAM_STAT_BUSY;
2672                 break;
2673         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2674                 PM8001_IO_DBG(pm8001_ha,
2675                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2676                 ts->resp = SAS_TASK_COMPLETE;
2677                 ts->stat = SAS_OPEN_REJECT;
2678                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2679                 break;
2680         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2681                 PM8001_IO_DBG(pm8001_ha,
2682                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2683                 ts->resp = SAS_TASK_COMPLETE;
2684                 ts->stat = SAS_OPEN_REJECT;
2685                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2686                 break;
2687         case IO_OPEN_CNX_ERROR_BREAK:
2688                 PM8001_IO_DBG(pm8001_ha,
2689                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2690                 ts->resp = SAS_TASK_COMPLETE;
2691                 ts->stat = SAS_OPEN_REJECT;
2692                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2693                 break;
2694         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2695         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2696         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2697         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2698         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2699         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2700                 PM8001_IO_DBG(pm8001_ha,
2701                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2702                 ts->resp = SAS_TASK_COMPLETE;
2703                 ts->stat = SAS_OPEN_REJECT;
2704                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2705                 pm8001_handle_event(pm8001_ha,
2706                                 pm8001_dev,
2707                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2708                 break;
2709         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2710                 PM8001_IO_DBG(pm8001_ha,
2711                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2712                 ts->resp = SAS_TASK_COMPLETE;
2713                 ts->stat = SAS_OPEN_REJECT;
2714                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2715                 break;
2716         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2717                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
2718                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2719                 ts->resp = SAS_TASK_COMPLETE;
2720                 ts->stat = SAS_OPEN_REJECT;
2721                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2722                 break;
2723         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2724                 PM8001_IO_DBG(pm8001_ha,
2725                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2726                 ts->resp = SAS_TASK_COMPLETE;
2727                 ts->stat = SAS_OPEN_REJECT;
2728                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2729                 break;
2730         case IO_XFER_ERROR_RX_FRAME:
2731                 PM8001_IO_DBG(pm8001_ha,
2732                         pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2733                 ts->resp = SAS_TASK_COMPLETE;
2734                 ts->stat = SAS_DEV_NO_RESPONSE;
2735                 break;
2736         case IO_XFER_OPEN_RETRY_TIMEOUT:
2737                 PM8001_IO_DBG(pm8001_ha,
2738                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2739                 ts->resp = SAS_TASK_COMPLETE;
2740                 ts->stat = SAS_OPEN_REJECT;
2741                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2742                 break;
2743         case IO_ERROR_INTERNAL_SMP_RESOURCE:
2744                 PM8001_IO_DBG(pm8001_ha,
2745                         pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2746                 ts->resp = SAS_TASK_COMPLETE;
2747                 ts->stat = SAS_QUEUE_FULL;
2748                 break;
2749         case IO_PORT_IN_RESET:
2750                 PM8001_IO_DBG(pm8001_ha,
2751                         pm8001_printk("IO_PORT_IN_RESET\n"));
2752                 ts->resp = SAS_TASK_COMPLETE;
2753                 ts->stat = SAS_OPEN_REJECT;
2754                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2755                 break;
2756         case IO_DS_NON_OPERATIONAL:
2757                 PM8001_IO_DBG(pm8001_ha,
2758                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2759                 ts->resp = SAS_TASK_COMPLETE;
2760                 ts->stat = SAS_DEV_NO_RESPONSE;
2761                 break;
2762         case IO_DS_IN_RECOVERY:
2763                 PM8001_IO_DBG(pm8001_ha,
2764                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2765                 ts->resp = SAS_TASK_COMPLETE;
2766                 ts->stat = SAS_OPEN_REJECT;
2767                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2768                 break;
2769         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2770                 PM8001_IO_DBG(pm8001_ha,
2771                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2772                 ts->resp = SAS_TASK_COMPLETE;
2773                 ts->stat = SAS_OPEN_REJECT;
2774                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2775                 break;
2776         default:
2777                 PM8001_IO_DBG(pm8001_ha,
2778                         pm8001_printk("Unknown status 0x%x\n", status));
2779                 ts->resp = SAS_TASK_COMPLETE;
2780                 ts->stat = SAS_DEV_NO_RESPONSE;
2781                 /* not allowed case. Therefore, return failed status */
2782                 break;
2783         }
2784         spin_lock_irqsave(&t->task_state_lock, flags);
2785         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2786         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2787         t->task_state_flags |= SAS_TASK_STATE_DONE;
2788         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2789                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2790                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2791                         "task 0x%p done with io_status 0x%x resp 0x%x"
2792                         "stat 0x%x but aborted by upper layer!\n",
2793                         t, status, ts->resp, ts->stat));
2794                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2795         } else {
2796                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2797                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2798                 mb();/* in order to force CPU ordering */
2799                 t->task_done(t);
2800         }
2801 }
2802
2803 /**
2804  * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2805  * @pm8001_ha: our hba card information
2806  * @Qnum: the outbound queue message number.
2807  * @SEA: source of event to ack
2808  * @port_id: port id.
2809  * @phyId: phy id.
2810  * @param0: parameter 0.
2811  * @param1: parameter 1.
2812  */
2813 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2814         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2815 {
2816         struct hw_event_ack_req  payload;
2817         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2818
2819         struct inbound_queue_table *circularQ;
2820
2821         memset((u8 *)&payload, 0, sizeof(payload));
2822         circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2823         payload.tag = cpu_to_le32(1);
2824         payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2825                 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
2826         payload.param0 = cpu_to_le32(param0);
2827         payload.param1 = cpu_to_le32(param1);
2828         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
2829 }
2830
2831 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2832         u32 phyId, u32 phy_op);
2833
2834 /**
2835  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2836  * @pm8001_ha: our hba card information
2837  * @piomb: IO message buffer
2838  */
2839 static void
2840 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2841 {
2842         struct hw_event_resp *pPayload =
2843                 (struct hw_event_resp *)(piomb + 4);
2844         u32 lr_status_evt_portid =
2845                 le32_to_cpu(pPayload->lr_status_evt_portid);
2846         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2847
2848         u8 link_rate =
2849                 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2850         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2851         u8 phy_id =
2852                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2853         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2854
2855         struct pm8001_port *port = &pm8001_ha->port[port_id];
2856         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2857         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2858         unsigned long flags;
2859         u8 deviceType = pPayload->sas_identify.dev_type;
2860         port->port_state = portstate;
2861         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2862         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2863                 "portid:%d; phyid:%d; linkrate:%d; "
2864                 "portstate:%x; devicetype:%x\n",
2865                 port_id, phy_id, link_rate, portstate, deviceType));
2866
2867         switch (deviceType) {
2868         case SAS_PHY_UNUSED:
2869                 PM8001_MSG_DBG(pm8001_ha,
2870                         pm8001_printk("device type no device.\n"));
2871                 break;
2872         case SAS_END_DEVICE:
2873                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
2874                 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2875                         PHY_NOTIFY_ENABLE_SPINUP);
2876                 port->port_attached = 1;
2877                 pm8001_get_lrate_mode(phy, link_rate);
2878                 break;
2879         case SAS_EDGE_EXPANDER_DEVICE:
2880                 PM8001_MSG_DBG(pm8001_ha,
2881                         pm8001_printk("expander device.\n"));
2882                 port->port_attached = 1;
2883                 pm8001_get_lrate_mode(phy, link_rate);
2884                 break;
2885         case SAS_FANOUT_EXPANDER_DEVICE:
2886                 PM8001_MSG_DBG(pm8001_ha,
2887                         pm8001_printk("fanout expander device.\n"));
2888                 port->port_attached = 1;
2889                 pm8001_get_lrate_mode(phy, link_rate);
2890                 break;
2891         default:
2892                 PM8001_MSG_DBG(pm8001_ha,
2893                         pm8001_printk("unknown device type(%x)\n", deviceType));
2894                 break;
2895         }
2896         phy->phy_type |= PORT_TYPE_SAS;
2897         phy->identify.device_type = deviceType;
2898         phy->phy_attached = 1;
2899         if (phy->identify.device_type == SAS_END_DEVICE)
2900                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
2901         else if (phy->identify.device_type != SAS_PHY_UNUSED)
2902                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
2903         phy->sas_phy.oob_mode = SAS_OOB_MODE;
2904         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2905         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2906         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
2907                 sizeof(struct sas_identify_frame)-4);
2908         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
2909         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2910         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2911         if (pm8001_ha->flags == PM8001F_RUN_TIME)
2912                 mdelay(200);/*delay a moment to wait disk to spinup*/
2913         pm8001_bytes_dmaed(pm8001_ha, phy_id);
2914 }
2915
2916 /**
2917  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
2918  * @pm8001_ha: our hba card information
2919  * @piomb: IO message buffer
2920  */
2921 static void
2922 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2923 {
2924         struct hw_event_resp *pPayload =
2925                 (struct hw_event_resp *)(piomb + 4);
2926         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2927         u32 lr_status_evt_portid =
2928                 le32_to_cpu(pPayload->lr_status_evt_portid);
2929         u8 link_rate =
2930                 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2931         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2932         u8 phy_id =
2933                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2934
2935         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2936
2937         struct pm8001_port *port = &pm8001_ha->port[port_id];
2938         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2939         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2940         unsigned long flags;
2941         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2942                 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
2943                                 port_id, phy_id, link_rate, portstate));
2944
2945         port->port_state = portstate;
2946         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2947         port->port_attached = 1;
2948         pm8001_get_lrate_mode(phy, link_rate);
2949         phy->phy_type |= PORT_TYPE_SATA;
2950         phy->phy_attached = 1;
2951         phy->sas_phy.oob_mode = SATA_OOB_MODE;
2952         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2953         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2954         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
2955                 sizeof(struct dev_to_host_fis));
2956         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2957         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
2958         phy->identify.device_type = SAS_SATA_DEV;
2959         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2960         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2961         pm8001_bytes_dmaed(pm8001_ha, phy_id);
2962 }
2963
2964 /**
2965  * hw_event_phy_down -we should notify the libsas the phy is down.
2966  * @pm8001_ha: our hba card information
2967  * @piomb: IO message buffer
2968  */
2969 static void
2970 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
2971 {
2972         struct hw_event_resp *pPayload =
2973                 (struct hw_event_resp *)(piomb + 4);
2974
2975         u32 lr_status_evt_portid =
2976                 le32_to_cpu(pPayload->lr_status_evt_portid);
2977         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2978         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2979         u8 phy_id =
2980                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2981         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2982
2983         struct pm8001_port *port = &pm8001_ha->port[port_id];
2984         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2985         port->port_state = portstate;
2986         phy->phy_type = 0;
2987         phy->identify.device_type = 0;
2988         phy->phy_attached = 0;
2989         memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
2990         switch (portstate) {
2991         case PORT_VALID:
2992                 break;
2993         case PORT_INVALID:
2994                 PM8001_MSG_DBG(pm8001_ha,
2995                         pm8001_printk(" PortInvalid portID %d\n", port_id));
2996                 PM8001_MSG_DBG(pm8001_ha,
2997                         pm8001_printk(" Last phy Down and port invalid\n"));
2998                 port->port_attached = 0;
2999                 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3000                         port_id, phy_id, 0, 0);
3001                 break;
3002         case PORT_IN_RESET:
3003                 PM8001_MSG_DBG(pm8001_ha,
3004                         pm8001_printk(" Port In Reset portID %d\n", port_id));
3005                 break;
3006         case PORT_NOT_ESTABLISHED:
3007                 PM8001_MSG_DBG(pm8001_ha,
3008                         pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
3009                 port->port_attached = 0;
3010                 break;
3011         case PORT_LOSTCOMM:
3012                 PM8001_MSG_DBG(pm8001_ha,
3013                         pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
3014                 PM8001_MSG_DBG(pm8001_ha,
3015                         pm8001_printk(" Last phy Down and port invalid\n"));
3016                 port->port_attached = 0;
3017                 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3018                         port_id, phy_id, 0, 0);
3019                 break;
3020         default:
3021                 port->port_attached = 0;
3022                 PM8001_MSG_DBG(pm8001_ha,
3023                         pm8001_printk(" phy Down and(default) = 0x%x\n",
3024                         portstate));
3025                 break;
3026
3027         }
3028 }
3029
3030 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3031 {
3032         struct phy_start_resp *pPayload =
3033                 (struct phy_start_resp *)(piomb + 4);
3034         u32 status =
3035                 le32_to_cpu(pPayload->status);
3036         u32 phy_id =
3037                 le32_to_cpu(pPayload->phyid);
3038         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3039
3040         PM8001_INIT_DBG(pm8001_ha,
3041                 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
3042                                 status, phy_id));
3043         if (status == 0) {
3044                 phy->phy_state = 1;
3045                 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3046                         complete(phy->enable_completion);
3047         }
3048         return 0;
3049
3050 }
3051
3052 /**
3053  * mpi_thermal_hw_event -The hw event has come.
3054  * @pm8001_ha: our hba card information
3055  * @piomb: IO message buffer
3056  */
3057 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3058 {
3059         struct thermal_hw_event *pPayload =
3060                 (struct thermal_hw_event *)(piomb + 4);
3061
3062         u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3063         u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3064
3065         if (thermal_event & 0x40) {
3066                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3067                         "Thermal Event: Local high temperature violated!\n"));
3068                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3069                         "Thermal Event: Measured local high temperature %d\n",
3070                                 ((rht_lht & 0xFF00) >> 8)));
3071         }
3072         if (thermal_event & 0x10) {
3073                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3074                         "Thermal Event: Remote high temperature violated!\n"));
3075                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3076                         "Thermal Event: Measured remote high temperature %d\n",
3077                                 ((rht_lht & 0xFF000000) >> 24)));
3078         }
3079         return 0;
3080 }
3081
3082 /**
3083  * mpi_hw_event -The hw event has come.
3084  * @pm8001_ha: our hba card information
3085  * @piomb: IO message buffer
3086  */
3087 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3088 {
3089         unsigned long flags;
3090         struct hw_event_resp *pPayload =
3091                 (struct hw_event_resp *)(piomb + 4);
3092         u32 lr_status_evt_portid =
3093                 le32_to_cpu(pPayload->lr_status_evt_portid);
3094         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3095         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3096         u8 phy_id =
3097                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3098         u16 eventType =
3099                 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3100         u8 status =
3101                 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3102
3103         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3104         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3105         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3106         PM8001_MSG_DBG(pm8001_ha,
3107                 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
3108                                 port_id, phy_id, eventType, status));
3109
3110         switch (eventType) {
3111
3112         case HW_EVENT_SAS_PHY_UP:
3113                 PM8001_MSG_DBG(pm8001_ha,
3114                         pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3115                 hw_event_sas_phy_up(pm8001_ha, piomb);
3116                 break;
3117         case HW_EVENT_SATA_PHY_UP:
3118                 PM8001_MSG_DBG(pm8001_ha,
3119                         pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3120                 hw_event_sata_phy_up(pm8001_ha, piomb);
3121                 break;
3122         case HW_EVENT_SATA_SPINUP_HOLD:
3123                 PM8001_MSG_DBG(pm8001_ha,
3124                         pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3125                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3126                 break;
3127         case HW_EVENT_PHY_DOWN:
3128                 PM8001_MSG_DBG(pm8001_ha,
3129                         pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3130                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3131                 phy->phy_attached = 0;
3132                 phy->phy_state = 0;
3133                 hw_event_phy_down(pm8001_ha, piomb);
3134                 break;
3135         case HW_EVENT_PORT_INVALID:
3136                 PM8001_MSG_DBG(pm8001_ha,
3137                         pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3138                 sas_phy_disconnected(sas_phy);
3139                 phy->phy_attached = 0;
3140                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3141                 break;
3142         /* the broadcast change primitive received, tell the LIBSAS this event
3143         to revalidate the sas domain*/
3144         case HW_EVENT_BROADCAST_CHANGE:
3145                 PM8001_MSG_DBG(pm8001_ha,
3146                         pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3147                 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3148                         port_id, phy_id, 1, 0);
3149                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3150                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3151                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3152                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3153                 break;
3154         case HW_EVENT_PHY_ERROR:
3155                 PM8001_MSG_DBG(pm8001_ha,
3156                         pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3157                 sas_phy_disconnected(&phy->sas_phy);
3158                 phy->phy_attached = 0;
3159                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3160                 break;
3161         case HW_EVENT_BROADCAST_EXP:
3162                 PM8001_MSG_DBG(pm8001_ha,
3163                         pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3164                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3165                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3166                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3167                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3168                 break;
3169         case HW_EVENT_LINK_ERR_INVALID_DWORD:
3170                 PM8001_MSG_DBG(pm8001_ha,
3171                         pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3172                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3173                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3174                 sas_phy_disconnected(sas_phy);
3175                 phy->phy_attached = 0;
3176                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3177                 break;
3178         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3179                 PM8001_MSG_DBG(pm8001_ha,
3180                         pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3181                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3182                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3183                         port_id, phy_id, 0, 0);
3184                 sas_phy_disconnected(sas_phy);
3185                 phy->phy_attached = 0;
3186                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3187                 break;
3188         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3189                 PM8001_MSG_DBG(pm8001_ha,
3190                         pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3191                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3192                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3193                         port_id, phy_id, 0, 0);
3194                 sas_phy_disconnected(sas_phy);
3195                 phy->phy_attached = 0;
3196                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3197                 break;
3198         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3199                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3200                                 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3201                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3202                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3203                         port_id, phy_id, 0, 0);
3204                 sas_phy_disconnected(sas_phy);
3205                 phy->phy_attached = 0;
3206                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3207                 break;
3208         case HW_EVENT_MALFUNCTION:
3209                 PM8001_MSG_DBG(pm8001_ha,
3210                         pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3211                 break;
3212         case HW_EVENT_BROADCAST_SES:
3213                 PM8001_MSG_DBG(pm8001_ha,
3214                         pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3215                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3216                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3217                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3218                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3219                 break;
3220         case HW_EVENT_INBOUND_CRC_ERROR:
3221                 PM8001_MSG_DBG(pm8001_ha,
3222                         pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3223                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3224                         HW_EVENT_INBOUND_CRC_ERROR,
3225                         port_id, phy_id, 0, 0);
3226                 break;
3227         case HW_EVENT_HARD_RESET_RECEIVED:
3228                 PM8001_MSG_DBG(pm8001_ha,
3229                         pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3230                 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3231                 break;
3232         case HW_EVENT_ID_FRAME_TIMEOUT:
3233                 PM8001_MSG_DBG(pm8001_ha,
3234                         pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3235                 sas_phy_disconnected(sas_phy);
3236                 phy->phy_attached = 0;
3237                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3238                 break;
3239         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3240                 PM8001_MSG_DBG(pm8001_ha,
3241                         pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3242                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3243                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3244                         port_id, phy_id, 0, 0);
3245                 sas_phy_disconnected(sas_phy);
3246                 phy->phy_attached = 0;
3247                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3248                 break;
3249         case HW_EVENT_PORT_RESET_TIMER_TMO:
3250                 PM8001_MSG_DBG(pm8001_ha,
3251                         pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3252                 sas_phy_disconnected(sas_phy);
3253                 phy->phy_attached = 0;
3254                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3255                 break;
3256         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3257                 PM8001_MSG_DBG(pm8001_ha,
3258                         pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3259                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3260                         HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3261                         port_id, phy_id, 0, 0);
3262                 sas_phy_disconnected(sas_phy);
3263                 phy->phy_attached = 0;
3264                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3265                 break;
3266         case HW_EVENT_PORT_RECOVER:
3267                 PM8001_MSG_DBG(pm8001_ha,
3268                         pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3269                 break;
3270         case HW_EVENT_PORT_RESET_COMPLETE:
3271                 PM8001_MSG_DBG(pm8001_ha,
3272                         pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3273                 break;
3274         case EVENT_BROADCAST_ASYNCH_EVENT:
3275                 PM8001_MSG_DBG(pm8001_ha,
3276                         pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3277                 break;
3278         default:
3279                 PM8001_MSG_DBG(pm8001_ha,
3280                         pm8001_printk("Unknown event type 0x%x\n", eventType));
3281                 break;
3282         }
3283         return 0;
3284 }
3285
3286 /**
3287  * mpi_phy_stop_resp - SPCv specific
3288  * @pm8001_ha: our hba card information
3289  * @piomb: IO message buffer
3290  */
3291 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3292 {
3293         struct phy_stop_resp *pPayload =
3294                 (struct phy_stop_resp *)(piomb + 4);
3295         u32 status =
3296                 le32_to_cpu(pPayload->status);
3297         u32 phyid =
3298                 le32_to_cpu(pPayload->phyid);
3299         struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3300         PM8001_MSG_DBG(pm8001_ha,
3301                         pm8001_printk("phy:0x%x status:0x%x\n",
3302                                         phyid, status));
3303         if (status == 0)
3304                 phy->phy_state = 0;
3305         return 0;
3306 }
3307
3308 /**
3309  * mpi_set_controller_config_resp - SPCv specific
3310  * @pm8001_ha: our hba card information
3311  * @piomb: IO message buffer
3312  */
3313 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3314                         void *piomb)
3315 {
3316         struct set_ctrl_cfg_resp *pPayload =
3317                         (struct set_ctrl_cfg_resp *)(piomb + 4);
3318         u32 status = le32_to_cpu(pPayload->status);
3319         u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3320
3321         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3322                         "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3323                         status, err_qlfr_pgcd));
3324
3325         return 0;
3326 }
3327
3328 /**
3329  * mpi_get_controller_config_resp - SPCv specific
3330  * @pm8001_ha: our hba card information
3331  * @piomb: IO message buffer
3332  */
3333 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3334                         void *piomb)
3335 {
3336         PM8001_MSG_DBG(pm8001_ha,
3337                         pm8001_printk(" pm80xx_addition_functionality\n"));
3338
3339         return 0;
3340 }
3341
3342 /**
3343  * mpi_get_phy_profile_resp - SPCv specific
3344  * @pm8001_ha: our hba card information
3345  * @piomb: IO message buffer
3346  */
3347 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3348                         void *piomb)
3349 {
3350         PM8001_MSG_DBG(pm8001_ha,
3351                         pm8001_printk(" pm80xx_addition_functionality\n"));
3352
3353         return 0;
3354 }
3355
3356 /**
3357  * mpi_flash_op_ext_resp - SPCv specific
3358  * @pm8001_ha: our hba card information
3359  * @piomb: IO message buffer
3360  */
3361 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3362 {
3363         PM8001_MSG_DBG(pm8001_ha,
3364                         pm8001_printk(" pm80xx_addition_functionality\n"));
3365
3366         return 0;
3367 }
3368
3369 /**
3370  * mpi_set_phy_profile_resp - SPCv specific
3371  * @pm8001_ha: our hba card information
3372  * @piomb: IO message buffer
3373  */
3374 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3375                         void *piomb)
3376 {
3377         u8 page_code;
3378         struct set_phy_profile_resp *pPayload =
3379                 (struct set_phy_profile_resp *)(piomb + 4);
3380         u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3381         u32 status = le32_to_cpu(pPayload->status);
3382
3383         page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3384         if (status) {
3385                 /* status is FAILED */
3386                 PM8001_FAIL_DBG(pm8001_ha,
3387                         pm8001_printk("PhyProfile command failed  with status "
3388                         "0x%08X \n", status));
3389                 return -1;
3390         } else {
3391                 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3392                         PM8001_FAIL_DBG(pm8001_ha,
3393                                 pm8001_printk("Invalid page code 0x%X\n",
3394                                         page_code));
3395                         return -1;
3396                 }
3397         }
3398         return 0;
3399 }
3400
3401 /**
3402  * mpi_kek_management_resp - SPCv specific
3403  * @pm8001_ha: our hba card information
3404  * @piomb: IO message buffer
3405  */
3406 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3407                         void *piomb)
3408 {
3409         struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3410
3411         u32 status = le32_to_cpu(pPayload->status);
3412         u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3413         u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3414
3415         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3416                 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3417                 status, kidx_new_curr_ksop, err_qlfr));
3418
3419         return 0;
3420 }
3421
3422 /**
3423  * mpi_dek_management_resp - SPCv specific
3424  * @pm8001_ha: our hba card information
3425  * @piomb: IO message buffer
3426  */
3427 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3428                         void *piomb)
3429 {
3430         PM8001_MSG_DBG(pm8001_ha,
3431                         pm8001_printk(" pm80xx_addition_functionality\n"));
3432
3433         return 0;
3434 }
3435
3436 /**
3437  * ssp_coalesced_comp_resp - SPCv specific
3438  * @pm8001_ha: our hba card information
3439  * @piomb: IO message buffer
3440  */
3441 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3442                         void *piomb)
3443 {
3444         PM8001_MSG_DBG(pm8001_ha,
3445                         pm8001_printk(" pm80xx_addition_functionality\n"));
3446
3447         return 0;
3448 }
3449
3450 /**
3451  * process_one_iomb - process one outbound Queue memory block
3452  * @pm8001_ha: our hba card information
3453  * @piomb: IO message buffer
3454  */
3455 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3456 {
3457         __le32 pHeader = *(__le32 *)piomb;
3458         u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3459
3460         switch (opc) {
3461         case OPC_OUB_ECHO:
3462                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3463                 break;
3464         case OPC_OUB_HW_EVENT:
3465                 PM8001_MSG_DBG(pm8001_ha,
3466                         pm8001_printk("OPC_OUB_HW_EVENT\n"));
3467                 mpi_hw_event(pm8001_ha, piomb);
3468                 break;
3469         case OPC_OUB_THERM_HW_EVENT:
3470                 PM8001_MSG_DBG(pm8001_ha,
3471                         pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
3472                 mpi_thermal_hw_event(pm8001_ha, piomb);
3473                 break;
3474         case OPC_OUB_SSP_COMP:
3475                 PM8001_MSG_DBG(pm8001_ha,
3476                         pm8001_printk("OPC_OUB_SSP_COMP\n"));
3477                 mpi_ssp_completion(pm8001_ha, piomb);
3478                 break;
3479         case OPC_OUB_SMP_COMP:
3480                 PM8001_MSG_DBG(pm8001_ha,
3481                         pm8001_printk("OPC_OUB_SMP_COMP\n"));
3482                 mpi_smp_completion(pm8001_ha, piomb);
3483                 break;
3484         case OPC_OUB_LOCAL_PHY_CNTRL:
3485                 PM8001_MSG_DBG(pm8001_ha,
3486                         pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3487                 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3488                 break;
3489         case OPC_OUB_DEV_REGIST:
3490                 PM8001_MSG_DBG(pm8001_ha,
3491                 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3492                 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3493                 break;
3494         case OPC_OUB_DEREG_DEV:
3495                 PM8001_MSG_DBG(pm8001_ha,
3496                         pm8001_printk("unregister the device\n"));
3497                 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3498                 break;
3499         case OPC_OUB_GET_DEV_HANDLE:
3500                 PM8001_MSG_DBG(pm8001_ha,
3501                         pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3502                 break;
3503         case OPC_OUB_SATA_COMP:
3504                 PM8001_MSG_DBG(pm8001_ha,
3505                         pm8001_printk("OPC_OUB_SATA_COMP\n"));
3506                 mpi_sata_completion(pm8001_ha, piomb);
3507                 break;
3508         case OPC_OUB_SATA_EVENT:
3509                 PM8001_MSG_DBG(pm8001_ha,
3510                         pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3511                 mpi_sata_event(pm8001_ha, piomb);
3512                 break;
3513         case OPC_OUB_SSP_EVENT:
3514                 PM8001_MSG_DBG(pm8001_ha,
3515                         pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3516                 mpi_ssp_event(pm8001_ha, piomb);
3517                 break;
3518         case OPC_OUB_DEV_HANDLE_ARRIV:
3519                 PM8001_MSG_DBG(pm8001_ha,
3520                         pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3521                 /*This is for target*/
3522                 break;
3523         case OPC_OUB_SSP_RECV_EVENT:
3524                 PM8001_MSG_DBG(pm8001_ha,
3525                         pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3526                 /*This is for target*/
3527                 break;
3528         case OPC_OUB_FW_FLASH_UPDATE:
3529                 PM8001_MSG_DBG(pm8001_ha,
3530                         pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3531                 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3532                 break;
3533         case OPC_OUB_GPIO_RESPONSE:
3534                 PM8001_MSG_DBG(pm8001_ha,
3535                         pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3536                 break;
3537         case OPC_OUB_GPIO_EVENT:
3538                 PM8001_MSG_DBG(pm8001_ha,
3539                         pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3540                 break;
3541         case OPC_OUB_GENERAL_EVENT:
3542                 PM8001_MSG_DBG(pm8001_ha,
3543                         pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3544                 pm8001_mpi_general_event(pm8001_ha, piomb);
3545                 break;
3546         case OPC_OUB_SSP_ABORT_RSP:
3547                 PM8001_MSG_DBG(pm8001_ha,
3548                         pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3549                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3550                 break;
3551         case OPC_OUB_SATA_ABORT_RSP:
3552                 PM8001_MSG_DBG(pm8001_ha,
3553                         pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3554                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3555                 break;
3556         case OPC_OUB_SAS_DIAG_MODE_START_END:
3557                 PM8001_MSG_DBG(pm8001_ha,
3558                         pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3559                 break;
3560         case OPC_OUB_SAS_DIAG_EXECUTE:
3561                 PM8001_MSG_DBG(pm8001_ha,
3562                         pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3563                 break;
3564         case OPC_OUB_GET_TIME_STAMP:
3565                 PM8001_MSG_DBG(pm8001_ha,
3566                         pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3567                 break;
3568         case OPC_OUB_SAS_HW_EVENT_ACK:
3569                 PM8001_MSG_DBG(pm8001_ha,
3570                         pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3571                 break;
3572         case OPC_OUB_PORT_CONTROL:
3573                 PM8001_MSG_DBG(pm8001_ha,
3574                         pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3575                 break;
3576         case OPC_OUB_SMP_ABORT_RSP:
3577                 PM8001_MSG_DBG(pm8001_ha,
3578                         pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3579                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3580                 break;
3581         case OPC_OUB_GET_NVMD_DATA:
3582                 PM8001_MSG_DBG(pm8001_ha,
3583                         pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3584                 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3585                 break;
3586         case OPC_OUB_SET_NVMD_DATA:
3587                 PM8001_MSG_DBG(pm8001_ha,
3588                         pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3589                 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3590                 break;
3591         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3592                 PM8001_MSG_DBG(pm8001_ha,
3593                         pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3594                 break;
3595         case OPC_OUB_SET_DEVICE_STATE:
3596                 PM8001_MSG_DBG(pm8001_ha,
3597                         pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3598                 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3599                 break;
3600         case OPC_OUB_GET_DEVICE_STATE:
3601                 PM8001_MSG_DBG(pm8001_ha,
3602                         pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3603                 break;
3604         case OPC_OUB_SET_DEV_INFO:
3605                 PM8001_MSG_DBG(pm8001_ha,
3606                         pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3607                 break;
3608         /* spcv specifc commands */
3609         case OPC_OUB_PHY_START_RESP:
3610                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3611                         "OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
3612                 mpi_phy_start_resp(pm8001_ha, piomb);
3613                 break;
3614         case OPC_OUB_PHY_STOP_RESP:
3615                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3616                         "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
3617                 mpi_phy_stop_resp(pm8001_ha, piomb);
3618                 break;
3619         case OPC_OUB_SET_CONTROLLER_CONFIG:
3620                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3621                         "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
3622                 mpi_set_controller_config_resp(pm8001_ha, piomb);
3623                 break;
3624         case OPC_OUB_GET_CONTROLLER_CONFIG:
3625                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3626                         "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
3627                 mpi_get_controller_config_resp(pm8001_ha, piomb);
3628                 break;
3629         case OPC_OUB_GET_PHY_PROFILE:
3630                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3631                         "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
3632                 mpi_get_phy_profile_resp(pm8001_ha, piomb);
3633                 break;
3634         case OPC_OUB_FLASH_OP_EXT:
3635                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3636                         "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
3637                 mpi_flash_op_ext_resp(pm8001_ha, piomb);
3638                 break;
3639         case OPC_OUB_SET_PHY_PROFILE:
3640                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3641                         "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
3642                 mpi_set_phy_profile_resp(pm8001_ha, piomb);
3643                 break;
3644         case OPC_OUB_KEK_MANAGEMENT_RESP:
3645                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3646                         "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
3647                 mpi_kek_management_resp(pm8001_ha, piomb);
3648                 break;
3649         case OPC_OUB_DEK_MANAGEMENT_RESP:
3650                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3651                         "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
3652                 mpi_dek_management_resp(pm8001_ha, piomb);
3653                 break;
3654         case OPC_OUB_SSP_COALESCED_COMP_RESP:
3655                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3656                         "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
3657                 ssp_coalesced_comp_resp(pm8001_ha, piomb);
3658                 break;
3659         default:
3660                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3661                         "Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
3662                 break;
3663         }
3664 }
3665
3666 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
3667 {
3668         struct outbound_queue_table *circularQ;
3669         void *pMsg1 = NULL;
3670         u8 uninitialized_var(bc);
3671         u32 ret = MPI_IO_STATUS_FAIL;
3672         unsigned long flags;
3673
3674         spin_lock_irqsave(&pm8001_ha->lock, flags);
3675         circularQ = &pm8001_ha->outbnd_q_tbl[vec];
3676         do {
3677                 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3678                 if (MPI_IO_STATUS_SUCCESS == ret) {
3679                         /* process the outbound message */
3680                         process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3681                         /* free the message from the outbound circular buffer */
3682                         pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
3683                                                         circularQ, bc);
3684                 }
3685                 if (MPI_IO_STATUS_BUSY == ret) {
3686                         /* Update the producer index from SPC */
3687                         circularQ->producer_index =
3688                                 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3689                         if (le32_to_cpu(circularQ->producer_index) ==
3690                                 circularQ->consumer_idx)
3691                                 /* OQ is empty */
3692                                 break;
3693                 }
3694         } while (1);
3695         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3696         return ret;
3697 }
3698
3699 /* PCI_DMA_... to our direction translation. */
3700 static const u8 data_dir_flags[] = {
3701         [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3702         [PCI_DMA_TODEVICE]      = DATA_DIR_OUT,/* OUTBOUND */
3703         [PCI_DMA_FROMDEVICE]    = DATA_DIR_IN,/* INBOUND */
3704         [PCI_DMA_NONE]          = DATA_DIR_NONE,/* NO TRANSFER */
3705 };
3706
3707 static void build_smp_cmd(u32 deviceID, __le32 hTag,
3708                         struct smp_req *psmp_cmd, int mode, int length)
3709 {
3710         psmp_cmd->tag = hTag;
3711         psmp_cmd->device_id = cpu_to_le32(deviceID);
3712         if (mode == SMP_DIRECT) {
3713                 length = length - 4; /* subtract crc */
3714                 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
3715         } else {
3716                 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3717         }
3718 }
3719
3720 /**
3721  * pm8001_chip_smp_req - send a SMP task to FW
3722  * @pm8001_ha: our hba card information.
3723  * @ccb: the ccb information this request used.
3724  */
3725 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3726         struct pm8001_ccb_info *ccb)
3727 {
3728         int elem, rc;
3729         struct sas_task *task = ccb->task;
3730         struct domain_device *dev = task->dev;
3731         struct pm8001_device *pm8001_dev = dev->lldd_dev;
3732         struct scatterlist *sg_req, *sg_resp;
3733         u32 req_len, resp_len;
3734         struct smp_req smp_cmd;
3735         u32 opc;
3736         struct inbound_queue_table *circularQ;
3737         char *preq_dma_addr = NULL;
3738         __le64 tmp_addr;
3739         u32 i, length;
3740
3741         memset(&smp_cmd, 0, sizeof(smp_cmd));
3742         /*
3743          * DMA-map SMP request, response buffers
3744          */
3745         sg_req = &task->smp_task.smp_req;
3746         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3747         if (!elem)
3748                 return -ENOMEM;
3749         req_len = sg_dma_len(sg_req);
3750
3751         sg_resp = &task->smp_task.smp_resp;
3752         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3753         if (!elem) {
3754                 rc = -ENOMEM;
3755                 goto err_out;
3756         }
3757         resp_len = sg_dma_len(sg_resp);
3758         /* must be in dwords */
3759         if ((req_len & 0x3) || (resp_len & 0x3)) {
3760                 rc = -EINVAL;
3761                 goto err_out_2;
3762         }
3763
3764         opc = OPC_INB_SMP_REQUEST;
3765         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3766         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3767
3768         length = sg_req->length;
3769         PM8001_IO_DBG(pm8001_ha,
3770                 pm8001_printk("SMP Frame Length %d\n", sg_req->length));
3771         if (!(length - 8))
3772                 pm8001_ha->smp_exp_mode = SMP_DIRECT;
3773         else
3774                 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
3775
3776
3777         tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3778         preq_dma_addr = (char *)phys_to_virt(tmp_addr);
3779
3780         /* INDIRECT MODE command settings. Use DMA */
3781         if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
3782                 PM8001_IO_DBG(pm8001_ha,
3783                         pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
3784                 /* for SPCv indirect mode. Place the top 4 bytes of
3785                  * SMP Request header here. */
3786                 for (i = 0; i < 4; i++)
3787                         smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
3788                 /* exclude top 4 bytes for SMP req header */
3789                 smp_cmd.long_smp_req.long_req_addr =
3790                         cpu_to_le64((u64)sg_dma_address
3791                                 (&task->smp_task.smp_req) + 4);
3792                 /* exclude 4 bytes for SMP req header and CRC */
3793                 smp_cmd.long_smp_req.long_req_size =
3794                         cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
3795                 smp_cmd.long_smp_req.long_resp_addr =
3796                                 cpu_to_le64((u64)sg_dma_address
3797                                         (&task->smp_task.smp_resp));
3798                 smp_cmd.long_smp_req.long_resp_size =
3799                                 cpu_to_le32((u32)sg_dma_len
3800                                         (&task->smp_task.smp_resp)-4);
3801         } else { /* DIRECT MODE */
3802                 smp_cmd.long_smp_req.long_req_addr =
3803                         cpu_to_le64((u64)sg_dma_address
3804                                         (&task->smp_task.smp_req));
3805                 smp_cmd.long_smp_req.long_req_size =
3806                         cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3807                 smp_cmd.long_smp_req.long_resp_addr =
3808                         cpu_to_le64((u64)sg_dma_address
3809                                 (&task->smp_task.smp_resp));
3810                 smp_cmd.long_smp_req.long_resp_size =
3811                         cpu_to_le32
3812                         ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3813         }
3814         if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3815                 PM8001_IO_DBG(pm8001_ha,
3816                         pm8001_printk("SMP REQUEST DIRECT MODE\n"));
3817                 for (i = 0; i < length; i++)
3818                         if (i < 16) {
3819                                 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
3820                                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3821                                         "Byte[%d]:%x (DMA data:%x)\n",
3822                                         i, smp_cmd.smp_req16[i],
3823                                         *(preq_dma_addr)));
3824                         } else {
3825                                 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
3826                                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3827                                         "Byte[%d]:%x (DMA data:%x)\n",
3828                                         i, smp_cmd.smp_req[i],
3829                                         *(preq_dma_addr)));
3830                         }
3831         }
3832
3833         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
3834                                 &smp_cmd, pm8001_ha->smp_exp_mode, length);
3835         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
3836                                         (u32 *)&smp_cmd, 0);
3837         if (rc)
3838                 goto err_out_2;
3839         return 0;
3840
3841 err_out_2:
3842         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3843                         PCI_DMA_FROMDEVICE);
3844 err_out:
3845         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3846                         PCI_DMA_TODEVICE);
3847         return rc;
3848 }
3849
3850 static int check_enc_sas_cmd(struct sas_task *task)
3851 {
3852         u8 cmd = task->ssp_task.cmd->cmnd[0];
3853
3854         if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
3855                 return 1;
3856         else
3857                 return 0;
3858 }
3859
3860 static int check_enc_sat_cmd(struct sas_task *task)
3861 {
3862         int ret = 0;
3863         switch (task->ata_task.fis.command) {
3864         case ATA_CMD_FPDMA_READ:
3865         case ATA_CMD_READ_EXT:
3866         case ATA_CMD_READ:
3867         case ATA_CMD_FPDMA_WRITE:
3868         case ATA_CMD_WRITE_EXT:
3869         case ATA_CMD_WRITE:
3870         case ATA_CMD_PIO_READ:
3871         case ATA_CMD_PIO_READ_EXT:
3872         case ATA_CMD_PIO_WRITE:
3873         case ATA_CMD_PIO_WRITE_EXT:
3874                 ret = 1;
3875                 break;
3876         default:
3877                 ret = 0;
3878                 break;
3879         }
3880         return ret;
3881 }
3882
3883 /**
3884  * pm80xx_chip_ssp_io_req - send a SSP task to FW
3885  * @pm8001_ha: our hba card information.
3886  * @ccb: the ccb information this request used.
3887  */
3888 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
3889         struct pm8001_ccb_info *ccb)
3890 {
3891         struct sas_task *task = ccb->task;
3892         struct domain_device *dev = task->dev;
3893         struct pm8001_device *pm8001_dev = dev->lldd_dev;
3894         struct ssp_ini_io_start_req ssp_cmd;
3895         u32 tag = ccb->ccb_tag;
3896         int ret;
3897         u64 phys_addr, start_addr, end_addr;
3898         u32 end_addr_high, end_addr_low;
3899         struct inbound_queue_table *circularQ;
3900         u32 q_index;
3901         u32 opc = OPC_INB_SSPINIIOSTART;
3902         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
3903         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
3904         /* data address domain added for spcv; set to 0 by host,
3905          * used internally by controller
3906          * 0 for SAS 1.1 and SAS 2.0 compatible TLR
3907          */
3908         ssp_cmd.dad_dir_m_tlr =
3909                 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
3910         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3911         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
3912         ssp_cmd.tag = cpu_to_le32(tag);
3913         if (task->ssp_task.enable_first_burst)
3914                 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
3915         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
3916         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
3917         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
3918                        task->ssp_task.cmd->cmd_len);
3919         q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
3920         circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
3921
3922         /* Check if encryption is set */
3923         if (pm8001_ha->chip->encrypt &&
3924                 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
3925                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3926                         "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
3927                         task->ssp_task.cmd->cmnd[0]));
3928                 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
3929                 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
3930                 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
3931                         ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
3932
3933                 /* fill in PRD (scatter/gather) table, if any */
3934                 if (task->num_scatter > 1) {
3935                         pm8001_chip_make_sg(task->scatter,
3936                                                 ccb->n_elem, ccb->buf_prd);
3937                         phys_addr = ccb->ccb_dma_handle +
3938                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3939                         ssp_cmd.enc_addr_low =
3940                                 cpu_to_le32(lower_32_bits(phys_addr));
3941                         ssp_cmd.enc_addr_high =
3942                                 cpu_to_le32(upper_32_bits(phys_addr));
3943                         ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
3944                 } else if (task->num_scatter == 1) {
3945                         u64 dma_addr = sg_dma_address(task->scatter);
3946                         ssp_cmd.enc_addr_low =
3947                                 cpu_to_le32(lower_32_bits(dma_addr));
3948                         ssp_cmd.enc_addr_high =
3949                                 cpu_to_le32(upper_32_bits(dma_addr));
3950                         ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3951                         ssp_cmd.enc_esgl = 0;
3952                         /* Check 4G Boundary */
3953                         start_addr = cpu_to_le64(dma_addr);
3954                         end_addr = (start_addr + ssp_cmd.enc_len) - 1;
3955                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
3956                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
3957                         if (end_addr_high != ssp_cmd.enc_addr_high) {
3958                                 PM8001_FAIL_DBG(pm8001_ha,
3959                                         pm8001_printk("The sg list address "
3960                                         "start_addr=0x%016llx data_len=0x%x "
3961                                         "end_addr_high=0x%08x end_addr_low="
3962                                         "0x%08x has crossed 4G boundary\n",
3963                                                 start_addr, ssp_cmd.enc_len,
3964                                                 end_addr_high, end_addr_low));
3965                                 pm8001_chip_make_sg(task->scatter, 1,
3966                                         ccb->buf_prd);
3967                                 phys_addr = ccb->ccb_dma_handle +
3968                                         offsetof(struct pm8001_ccb_info,
3969                                                 buf_prd[0]);
3970                                 ssp_cmd.enc_addr_low =
3971                                         cpu_to_le32(lower_32_bits(phys_addr));
3972                                 ssp_cmd.enc_addr_high =
3973                                         cpu_to_le32(upper_32_bits(phys_addr));
3974                                 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
3975                         }
3976                 } else if (task->num_scatter == 0) {
3977                         ssp_cmd.enc_addr_low = 0;
3978                         ssp_cmd.enc_addr_high = 0;
3979                         ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3980                         ssp_cmd.enc_esgl = 0;
3981                 }
3982                 /* XTS mode. All other fields are 0 */
3983                 ssp_cmd.key_cmode = 0x6 << 4;
3984                 /* set tweak values. Should be the start lba */
3985                 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
3986                                                 (task->ssp_task.cmd->cmnd[3] << 16) |
3987                                                 (task->ssp_task.cmd->cmnd[4] << 8) |
3988                                                 (task->ssp_task.cmd->cmnd[5]));
3989         } else {
3990                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3991                         "Sending Normal SAS command 0x%x inb q %x\n",
3992                         task->ssp_task.cmd->cmnd[0], q_index));
3993                 /* fill in PRD (scatter/gather) table, if any */
3994                 if (task->num_scatter > 1) {
3995                         pm8001_chip_make_sg(task->scatter, ccb->n_elem,
3996                                         ccb->buf_prd);
3997                         phys_addr = ccb->ccb_dma_handle +
3998                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3999                         ssp_cmd.addr_low =
4000                                 cpu_to_le32(lower_32_bits(phys_addr));
4001                         ssp_cmd.addr_high =
4002                                 cpu_to_le32(upper_32_bits(phys_addr));
4003                         ssp_cmd.esgl = cpu_to_le32(1<<31);
4004                 } else if (task->num_scatter == 1) {
4005                         u64 dma_addr = sg_dma_address(task->scatter);
4006                         ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4007                         ssp_cmd.addr_high =
4008                                 cpu_to_le32(upper_32_bits(dma_addr));
4009                         ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4010                         ssp_cmd.esgl = 0;
4011                         /* Check 4G Boundary */
4012                         start_addr = cpu_to_le64(dma_addr);
4013                         end_addr = (start_addr + ssp_cmd.len) - 1;
4014                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4015                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4016                         if (end_addr_high != ssp_cmd.addr_high) {
4017                                 PM8001_FAIL_DBG(pm8001_ha,
4018                                         pm8001_printk("The sg list address "
4019                                         "start_addr=0x%016llx data_len=0x%x "
4020                                         "end_addr_high=0x%08x end_addr_low="
4021                                         "0x%08x has crossed 4G boundary\n",
4022                                                  start_addr, ssp_cmd.len,
4023                                                  end_addr_high, end_addr_low));
4024                                 pm8001_chip_make_sg(task->scatter, 1,
4025                                         ccb->buf_prd);
4026                                 phys_addr = ccb->ccb_dma_handle +
4027                                         offsetof(struct pm8001_ccb_info,
4028                                                  buf_prd[0]);
4029                                 ssp_cmd.addr_low =
4030                                         cpu_to_le32(lower_32_bits(phys_addr));
4031                                 ssp_cmd.addr_high =
4032                                         cpu_to_le32(upper_32_bits(phys_addr));
4033                                 ssp_cmd.esgl = cpu_to_le32(1<<31);
4034                         }
4035                 } else if (task->num_scatter == 0) {
4036                         ssp_cmd.addr_low = 0;
4037                         ssp_cmd.addr_high = 0;
4038                         ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4039                         ssp_cmd.esgl = 0;
4040                 }
4041         }
4042         q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4043         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4044                                                 &ssp_cmd, q_index);
4045         return ret;
4046 }
4047
4048 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4049         struct pm8001_ccb_info *ccb)
4050 {
4051         struct sas_task *task = ccb->task;
4052         struct domain_device *dev = task->dev;
4053         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4054         u32 tag = ccb->ccb_tag;
4055         int ret;
4056         u32 q_index;
4057         struct sata_start_req sata_cmd;
4058         u32 hdr_tag, ncg_tag = 0;
4059         u64 phys_addr, start_addr, end_addr;
4060         u32 end_addr_high, end_addr_low;
4061         u32 ATAP = 0x0;
4062         u32 dir;
4063         struct inbound_queue_table *circularQ;
4064         unsigned long flags;
4065         u32 opc = OPC_INB_SATA_HOST_OPSTART;
4066         memset(&sata_cmd, 0, sizeof(sata_cmd));
4067         q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4068         circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4069
4070         if (task->data_dir == PCI_DMA_NONE) {
4071                 ATAP = 0x04; /* no data*/
4072                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4073         } else if (likely(!task->ata_task.device_control_reg_update)) {
4074                 if (task->ata_task.dma_xfer) {
4075                         ATAP = 0x06; /* DMA */
4076                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4077                 } else {
4078                         ATAP = 0x05; /* PIO*/
4079                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4080                 }
4081                 if (task->ata_task.use_ncq &&
4082                         dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
4083                         ATAP = 0x07; /* FPDMA */
4084                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4085                 }
4086         }
4087         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4088                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4089                 ncg_tag = hdr_tag;
4090         }
4091         dir = data_dir_flags[task->data_dir] << 8;
4092         sata_cmd.tag = cpu_to_le32(tag);
4093         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4094         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4095
4096         sata_cmd.sata_fis = task->ata_task.fis;
4097         if (likely(!task->ata_task.device_control_reg_update))
4098                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4099         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4100
4101         /* Check if encryption is set */
4102         if (pm8001_ha->chip->encrypt &&
4103                 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4104                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4105                         "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4106                         sata_cmd.sata_fis.command));
4107                 opc = OPC_INB_SATA_DIF_ENC_IO;
4108
4109                 /* set encryption bit */
4110                 sata_cmd.ncqtag_atap_dir_m_dad =
4111                         cpu_to_le32(((ncg_tag & 0xff)<<16)|
4112                                 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4113                                                         /* dad (bit 0-1) is 0 */
4114                 /* fill in PRD (scatter/gather) table, if any */
4115                 if (task->num_scatter > 1) {
4116                         pm8001_chip_make_sg(task->scatter,
4117                                                 ccb->n_elem, ccb->buf_prd);
4118                         phys_addr = ccb->ccb_dma_handle +
4119                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4120                         sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
4121                         sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
4122                         sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4123                 } else if (task->num_scatter == 1) {
4124                         u64 dma_addr = sg_dma_address(task->scatter);
4125                         sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
4126                         sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
4127                         sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4128                         sata_cmd.enc_esgl = 0;
4129                         /* Check 4G Boundary */
4130                         start_addr = cpu_to_le64(dma_addr);
4131                         end_addr = (start_addr + sata_cmd.enc_len) - 1;
4132                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4133                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4134                         if (end_addr_high != sata_cmd.enc_addr_high) {
4135                                 PM8001_FAIL_DBG(pm8001_ha,
4136                                         pm8001_printk("The sg list address "
4137                                         "start_addr=0x%016llx data_len=0x%x "
4138                                         "end_addr_high=0x%08x end_addr_low"
4139                                         "=0x%08x has crossed 4G boundary\n",
4140                                                 start_addr, sata_cmd.enc_len,
4141                                                 end_addr_high, end_addr_low));
4142                                 pm8001_chip_make_sg(task->scatter, 1,
4143                                         ccb->buf_prd);
4144                                 phys_addr = ccb->ccb_dma_handle +
4145                                                 offsetof(struct pm8001_ccb_info,
4146                                                 buf_prd[0]);
4147                                 sata_cmd.enc_addr_low =
4148                                         lower_32_bits(phys_addr);
4149                                 sata_cmd.enc_addr_high =
4150                                         upper_32_bits(phys_addr);
4151                                 sata_cmd.enc_esgl =
4152                                         cpu_to_le32(1 << 31);
4153                         }
4154                 } else if (task->num_scatter == 0) {
4155                         sata_cmd.enc_addr_low = 0;
4156                         sata_cmd.enc_addr_high = 0;
4157                         sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4158                         sata_cmd.enc_esgl = 0;
4159                 }
4160                 /* XTS mode. All other fields are 0 */
4161                 sata_cmd.key_index_mode = 0x6 << 4;
4162                 /* set tweak values. Should be the start lba */
4163                 sata_cmd.twk_val0 =
4164                         cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4165                                         (sata_cmd.sata_fis.lbah << 16) |
4166                                         (sata_cmd.sata_fis.lbam << 8) |
4167                                         (sata_cmd.sata_fis.lbal));
4168                 sata_cmd.twk_val1 =
4169                         cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4170                                          (sata_cmd.sata_fis.lbam_exp));
4171         } else {
4172                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4173                         "Sending Normal SATA command 0x%x inb %x\n",
4174                         sata_cmd.sata_fis.command, q_index));
4175                 /* dad (bit 0-1) is 0 */
4176                 sata_cmd.ncqtag_atap_dir_m_dad =
4177                         cpu_to_le32(((ncg_tag & 0xff)<<16) |
4178                                         ((ATAP & 0x3f) << 10) | dir);
4179
4180                 /* fill in PRD (scatter/gather) table, if any */
4181                 if (task->num_scatter > 1) {
4182                         pm8001_chip_make_sg(task->scatter,
4183                                         ccb->n_elem, ccb->buf_prd);
4184                         phys_addr = ccb->ccb_dma_handle +
4185                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4186                         sata_cmd.addr_low = lower_32_bits(phys_addr);
4187                         sata_cmd.addr_high = upper_32_bits(phys_addr);
4188                         sata_cmd.esgl = cpu_to_le32(1 << 31);
4189                 } else if (task->num_scatter == 1) {
4190                         u64 dma_addr = sg_dma_address(task->scatter);
4191                         sata_cmd.addr_low = lower_32_bits(dma_addr);
4192                         sata_cmd.addr_high = upper_32_bits(dma_addr);
4193                         sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4194                         sata_cmd.esgl = 0;
4195                         /* Check 4G Boundary */
4196                         start_addr = cpu_to_le64(dma_addr);
4197                         end_addr = (start_addr + sata_cmd.len) - 1;
4198                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4199                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4200                         if (end_addr_high != sata_cmd.addr_high) {
4201                                 PM8001_FAIL_DBG(pm8001_ha,
4202                                         pm8001_printk("The sg list address "
4203                                         "start_addr=0x%016llx data_len=0x%x"
4204                                         "end_addr_high=0x%08x end_addr_low="
4205                                         "0x%08x has crossed 4G boundary\n",
4206                                                 start_addr, sata_cmd.len,
4207                                                 end_addr_high, end_addr_low));
4208                                 pm8001_chip_make_sg(task->scatter, 1,
4209                                         ccb->buf_prd);
4210                                 phys_addr = ccb->ccb_dma_handle +
4211                                         offsetof(struct pm8001_ccb_info,
4212                                         buf_prd[0]);
4213                                 sata_cmd.addr_low =
4214                                         lower_32_bits(phys_addr);
4215                                 sata_cmd.addr_high =
4216                                         upper_32_bits(phys_addr);
4217                                 sata_cmd.esgl = cpu_to_le32(1 << 31);
4218                         }
4219                 } else if (task->num_scatter == 0) {
4220                         sata_cmd.addr_low = 0;
4221                         sata_cmd.addr_high = 0;
4222                         sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4223                         sata_cmd.esgl = 0;
4224                 }
4225                         /* scsi cdb */
4226                         sata_cmd.atapi_scsi_cdb[0] =
4227                                 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4228                                 (task->ata_task.atapi_packet[1] << 8) |
4229                                 (task->ata_task.atapi_packet[2] << 16) |
4230                                 (task->ata_task.atapi_packet[3] << 24)));
4231                         sata_cmd.atapi_scsi_cdb[1] =
4232                                 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4233                                 (task->ata_task.atapi_packet[5] << 8) |
4234                                 (task->ata_task.atapi_packet[6] << 16) |
4235                                 (task->ata_task.atapi_packet[7] << 24)));
4236                         sata_cmd.atapi_scsi_cdb[2] =
4237                                 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4238                                 (task->ata_task.atapi_packet[9] << 8) |
4239                                 (task->ata_task.atapi_packet[10] << 16) |
4240                                 (task->ata_task.atapi_packet[11] << 24)));
4241                         sata_cmd.atapi_scsi_cdb[3] =
4242                                 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4243                                 (task->ata_task.atapi_packet[13] << 8) |
4244                                 (task->ata_task.atapi_packet[14] << 16) |
4245                                 (task->ata_task.atapi_packet[15] << 24)));
4246         }
4247
4248         /* Check for read log for failed drive and return */
4249         if (sata_cmd.sata_fis.command == 0x2f) {
4250                 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4251                         (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4252                         (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4253                         struct task_status_struct *ts;
4254
4255                         pm8001_ha_dev->id &= 0xDFFFFFFF;
4256                         ts = &task->task_status;
4257
4258                         spin_lock_irqsave(&task->task_state_lock, flags);
4259                         ts->resp = SAS_TASK_COMPLETE;
4260                         ts->stat = SAM_STAT_GOOD;
4261                         task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4262                         task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4263                         task->task_state_flags |= SAS_TASK_STATE_DONE;
4264                         if (unlikely((task->task_state_flags &
4265                                         SAS_TASK_STATE_ABORTED))) {
4266                                 spin_unlock_irqrestore(&task->task_state_lock,
4267                                                         flags);
4268                                 PM8001_FAIL_DBG(pm8001_ha,
4269                                         pm8001_printk("task 0x%p resp 0x%x "
4270                                         " stat 0x%x but aborted by upper layer "
4271                                         "\n", task, ts->resp, ts->stat));
4272                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4273                                 return 0;
4274                         } else {
4275                                 spin_unlock_irqrestore(&task->task_state_lock,
4276                                                         flags);
4277                                 pm8001_ccb_task_free_done(pm8001_ha, task,
4278                                                                 ccb, tag);
4279                                 return 0;
4280                         }
4281                 }
4282         }
4283         q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4284         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4285                                                 &sata_cmd, q_index);
4286         return ret;
4287 }
4288
4289 /**
4290  * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4291  * @pm8001_ha: our hba card information.
4292  * @num: the inbound queue number
4293  * @phy_id: the phy id which we wanted to start up.
4294  */
4295 static int
4296 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4297 {
4298         struct phy_start_req payload;
4299         struct inbound_queue_table *circularQ;
4300         int ret;
4301         u32 tag = 0x01;
4302         u32 opcode = OPC_INB_PHYSTART;
4303         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4304         memset(&payload, 0, sizeof(payload));
4305         payload.tag = cpu_to_le32(tag);
4306
4307         PM8001_INIT_DBG(pm8001_ha,
4308                 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
4309         /*
4310          ** [0:7]       PHY Identifier
4311          ** [8:11]      link rate 1.5G, 3G, 6G
4312          ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b Auto mode
4313          ** [14]        0b disable spin up hold; 1b enable spin up hold
4314          ** [15] ob no change in current PHY analig setup 1b enable using SPAST
4315          */
4316         if (!IS_SPCV_12G(pm8001_ha->pdev))
4317                 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4318                                 LINKMODE_AUTO | LINKRATE_15 |
4319                                 LINKRATE_30 | LINKRATE_60 | phy_id);
4320         else
4321                 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4322                                 LINKMODE_AUTO | LINKRATE_15 |
4323                                 LINKRATE_30 | LINKRATE_60 | LINKRATE_120 |
4324                                 phy_id);
4325
4326         /* SSC Disable and SAS Analog ST configuration */
4327         /**
4328         payload.ase_sh_lm_slr_phyid =
4329                 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4330                 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4331                 phy_id);
4332         Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4333         **/
4334
4335         payload.sas_identify.dev_type = SAS_END_DEVICE;
4336         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4337         memcpy(payload.sas_identify.sas_addr,
4338                 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4339         payload.sas_identify.phy_id = phy_id;
4340         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4341         return ret;
4342 }
4343
4344 /**
4345  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4346  * @pm8001_ha: our hba card information.
4347  * @num: the inbound queue number
4348  * @phy_id: the phy id which we wanted to start up.
4349  */
4350 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4351         u8 phy_id)
4352 {
4353         struct phy_stop_req payload;
4354         struct inbound_queue_table *circularQ;
4355         int ret;
4356         u32 tag = 0x01;
4357         u32 opcode = OPC_INB_PHYSTOP;
4358         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4359         memset(&payload, 0, sizeof(payload));
4360         payload.tag = cpu_to_le32(tag);
4361         payload.phy_id = cpu_to_le32(phy_id);
4362         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4363         return ret;
4364 }
4365
4366 /**
4367  * see comments on pm8001_mpi_reg_resp.
4368  */
4369 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4370         struct pm8001_device *pm8001_dev, u32 flag)
4371 {
4372         struct reg_dev_req payload;
4373         u32     opc;
4374         u32 stp_sspsmp_sata = 0x4;
4375         struct inbound_queue_table *circularQ;
4376         u32 linkrate, phy_id;
4377         int rc, tag = 0xdeadbeef;
4378         struct pm8001_ccb_info *ccb;
4379         u8 retryFlag = 0x1;
4380         u16 firstBurstSize = 0;
4381         u16 ITNT = 2000;
4382         struct domain_device *dev = pm8001_dev->sas_device;
4383         struct domain_device *parent_dev = dev->parent;
4384         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4385
4386         memset(&payload, 0, sizeof(payload));
4387         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4388         if (rc)
4389                 return rc;
4390         ccb = &pm8001_ha->ccb_info[tag];
4391         ccb->device = pm8001_dev;
4392         ccb->ccb_tag = tag;
4393         payload.tag = cpu_to_le32(tag);
4394
4395         if (flag == 1) {
4396                 stp_sspsmp_sata = 0x02; /*direct attached sata */
4397         } else {
4398                 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4399                         stp_sspsmp_sata = 0x00; /* stp*/
4400                 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4401                         pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4402                         pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4403                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
4404         }
4405         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4406                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4407         else
4408                 phy_id = pm8001_dev->attached_phy;
4409
4410         opc = OPC_INB_REG_DEV;
4411
4412         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4413                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4414
4415         payload.phyid_portid =
4416                 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4417                 ((phy_id & 0xFF) << 8));
4418
4419         payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4420                 ((linkrate & 0x0F) << 24) |
4421                 ((stp_sspsmp_sata & 0x03) << 28));
4422         payload.firstburstsize_ITNexustimeout =
4423                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4424
4425         memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4426                 SAS_ADDR_SIZE);
4427
4428         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4429         if (rc)
4430                 pm8001_tag_free(pm8001_ha, tag);
4431
4432         return rc;
4433 }
4434
4435 /**
4436  * pm80xx_chip_phy_ctl_req - support the local phy operation
4437  * @pm8001_ha: our hba card information.
4438  * @num: the inbound queue number
4439  * @phy_id: the phy id which we wanted to operate
4440  * @phy_op:
4441  */
4442 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4443         u32 phyId, u32 phy_op)
4444 {
4445         struct local_phy_ctl_req payload;
4446         struct inbound_queue_table *circularQ;
4447         int ret;
4448         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4449         memset(&payload, 0, sizeof(payload));
4450         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4451         payload.tag = cpu_to_le32(1);
4452         payload.phyop_phyid =
4453                 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4454         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4455         return ret;
4456 }
4457
4458 static u32 pm80xx_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4459 {
4460         u32 value;
4461 #ifdef PM8001_USE_MSIX
4462         return 1;
4463 #endif
4464         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4465         if (value)
4466                 return 1;
4467         return 0;
4468
4469 }
4470
4471 /**
4472  * pm8001_chip_isr - PM8001 isr handler.
4473  * @pm8001_ha: our hba card information.
4474  * @irq: irq number.
4475  * @stat: stat.
4476  */
4477 static irqreturn_t
4478 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4479 {
4480         pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4481         process_oq(pm8001_ha, vec);
4482         pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4483         return IRQ_HANDLED;
4484 }
4485
4486 void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4487         u32 operation, u32 phyid, u32 length, u32 *buf)
4488 {
4489         u32 tag , i, j = 0;
4490         int rc;
4491         struct set_phy_profile_req payload;
4492         struct inbound_queue_table *circularQ;
4493         u32 opc = OPC_INB_SET_PHY_PROFILE;
4494
4495         memset(&payload, 0, sizeof(payload));
4496         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4497         if (rc)
4498                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n"));
4499         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4500         payload.tag = cpu_to_le32(tag);
4501         payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid  & 0xFF));
4502         PM8001_INIT_DBG(pm8001_ha,
4503                 pm8001_printk(" phy profile command for phy %x ,length is %d\n",
4504                         payload.ppc_phyid, length));
4505         for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
4506                 payload.reserved[j] =  cpu_to_le32(*((u32 *)buf + i));
4507                 j++;
4508         }
4509         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4510         if (rc)
4511                 pm8001_tag_free(pm8001_ha, tag);
4512 }
4513
4514 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
4515         u32 length, u8 *buf)
4516 {
4517         u32 page_code, i;
4518
4519         page_code = SAS_PHY_ANALOG_SETTINGS_PAGE;
4520         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
4521                 mpi_set_phy_profile_req(pm8001_ha,
4522                         SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
4523                 length = length + PHY_DWORD_LENGTH;
4524         }
4525         PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n"));
4526 }
4527 const struct pm8001_dispatch pm8001_80xx_dispatch = {
4528         .name                   = "pmc80xx",
4529         .chip_init              = pm80xx_chip_init,
4530         .chip_soft_rst          = pm80xx_chip_soft_rst,
4531         .chip_rst               = pm80xx_hw_chip_rst,
4532         .chip_iounmap           = pm8001_chip_iounmap,
4533         .isr                    = pm80xx_chip_isr,
4534         .is_our_interupt        = pm80xx_chip_is_our_interupt,
4535         .isr_process_oq         = process_oq,
4536         .interrupt_enable       = pm80xx_chip_interrupt_enable,
4537         .interrupt_disable      = pm80xx_chip_interrupt_disable,
4538         .make_prd               = pm8001_chip_make_sg,
4539         .smp_req                = pm80xx_chip_smp_req,
4540         .ssp_io_req             = pm80xx_chip_ssp_io_req,
4541         .sata_req               = pm80xx_chip_sata_req,
4542         .phy_start_req          = pm80xx_chip_phy_start_req,
4543         .phy_stop_req           = pm80xx_chip_phy_stop_req,
4544         .reg_dev_req            = pm80xx_chip_reg_dev_req,
4545         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
4546         .phy_ctl_req            = pm80xx_chip_phy_ctl_req,
4547         .task_abort             = pm8001_chip_abort_task,
4548         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
4549         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
4550         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
4551         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
4552         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
4553 };